WO2012074363A1 - A method of transferring silicon based layer onto polymer film - Google Patents

A method of transferring silicon based layer onto polymer film Download PDF

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Publication number
WO2012074363A1
WO2012074363A1 PCT/MY2011/000139 MY2011000139W WO2012074363A1 WO 2012074363 A1 WO2012074363 A1 WO 2012074363A1 MY 2011000139 W MY2011000139 W MY 2011000139W WO 2012074363 A1 WO2012074363 A1 WO 2012074363A1
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Prior art keywords
silicon
polymer film
layer
based layer
onto
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PCT/MY2011/000139
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French (fr)
Inventor
Bien Chia Sheng Daniel
Mohd Saman Rahimah
Buyong Muhamad Ramdzan
Mohamad Badaruddin Siti Aishah
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Mimos Berhad
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Publication of WO2012074363A1 publication Critical patent/WO2012074363A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00349—Creating layers of material on a substrate
    • B81C1/00373—Selective deposition, e.g. printing or microcontact printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035209—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions comprising a quantum structures
    • H01L31/035218—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions comprising a quantum structures the quantum structure being quantum dots
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1892—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof methods involving the use of temporary, removable substrates
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/0191—Transfer of a layer from a carrier wafer to a device wafer
    • B81C2201/0194—Transfer of a layer from a carrier wafer to a device wafer the layer being structured
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate

Definitions

  • the present invention generally relates to flexible polymer type devices and its fabrication.
  • [2] Electronic applications are emerging for devices such as displays and sensor arrays on flexible substrates, where it is desirable to be robust, light weight and deformable.
  • the main properties of these devices include their light weight, flexibility, potential low cost, and ability to enable applications such as sensors or smart skin for robotics applications, biomedical applications, smart tags and labels, wearable and mobile sensors for military and commercial use.
  • a flexible sensor device can include a flexible substrate, and at least one flexible sensor included on the flexible substrate.
  • the flexible sensor can be deposited on the flexible substrate by inkjet printing a composition that forms the flexible sensor.
  • the flexible sensor device can be configured to function when subjected to elongation, contraction, and/or distortion.
  • the prior arts of polymer devices and methods of fabrication has limitations such that their fabrication are directly on polymer substrates; therefore they are limited to the melting point of the polymer material and their structures are typically of metal or metal oxide based. To form the required structures, they rely heavily on coating of nanotube or nanowire on the polymer surface. In addition, their pattern or structural transfer relies on the use of adhesives and they are also not compatible with wafer fabrication or standard IC processing.
  • the present invention is provided a method of transferring silicon-based layer 101 onto polymer film 103 comprising the steps of: preparing an initial substrate 201; depositing the silicon-based layer on top of the initial substrates 203; etching the silicon-based layer to form desired micro-nano structure 205; depositing TiN layer by RF sputtering 207; depositing a tungsten layer 209; etching the tungsten layer 211; removing the exposed TiN off the etched planarized tungsten layer 213; coating the polymer onto a planarized surface 215; releasing the polymer film 217; and removing the tungsten plug and TiN layer 219.
  • the above provision is advantageous as it is compatible with wafer fabrication or standard integrated circuit (IC).
  • Figure 1 illustrates silicon-based layer 101 on flexible polymer 103 of the present invention.
  • Figure 2 illustrates fabrication process flow chart of the present invention.
  • Figure 3 illustrates the process of transferring of polysilicon structures 101a from silicon substrate 105a onto polyimide film 103 of the present invention.
  • Figure 4 illustrates tungsten layer 109 a) before; and b) after planarization process of the present invention.
  • Figure 5 illustrates polisilicon structures 101a after pattern transfer to polymer 103.
  • Figure 6 illustrates the process of transferring of polysilicon 101a structures from glass substrate 105b onto polyimide film 103 of the present invention.
  • Figure 7 illustrates the process of producing single crystal silicon 101b layer on silicon 105a or glass 105b substrate prior to structure formation and transfer to polymer 103.
  • the present invention relates to a method of transferring silicon structures 101
  • the proposed method utilises a combination of silicon deposition or bonding, etching, tungsten plug process and polymer coating.
  • the present invention generally comprising preparing an initial substrate 201; depositing the silicon-based layer on top of the initial substrates 203; etching the silicon-based layer to form desired micro-nano structure 205; depositing titanium nitride (TiN) layer by RF sputtering 207; depositing a tungsten layer 209; etching the tungsten layer 211; removing the exposed TiN off the etched planarized tungsten layer 213; coating the polymer onto a planarized surface 215; releasing the polymer film 217; and removing the tungsten plug and TiN layer 219.
  • TiN titanium nitride
  • the prior art of the present invention has limitations in the following areas where fabrication are done directly on the polymer substrates itself hence process methods and types of structures or materials are limited to the melting and operating point of the polymer, typically below 450 ° C. These structures are typically metal or metal oxide based because they can be deposited at much lower temperature by magnetron sputtering or evaporation. However, if they can be substituted with crystalline silicon structures, device performance in terms of sensitivity, reliability and response time can be improved. Nanotube or nanowire can also be utilised to form structures on polymer surfaces; however aligning them into a uniform and highly ordered array still proves a challenging task for large scale fabrication. They are also not compatible with standard wafer fabrication or standard IC processing which makes integration with other devices and circuitry more complicated.
  • a flexible polymer film 103 comprising silicon based structures/layer 101 as shown in Figure 1. This is achieved by utilising a novel set of fabrication steps to transfer single crystal or polycrystalline silicon (polysilicon) formed on a silicon or glass substrate onto a flexible polymer film, namely polyimide.
  • the single crystal or polysilicon structures can be doped with p- or n- type dopants to improve device conductivity or a combination of both dopant when forming a FET or p-n junction.
  • the transferred structures can be of a simple diode, field effect transistor (FET), photovoltaic cells, microfluidic devices and sensors.
  • the fabrication can be done on
  • the tungsten plug process is the core enabler to produce a planarised surface between the silicon structures.
  • tungsten is deposited by chemical vapour deposition (CVD) using tungsten hexafluoride (WF 6 ) as a precursor and etched back to be in plane with the silicon structures.
  • CVD chemical vapour deposition
  • WF 6 tungsten hexafluoride
  • the planar surface allows a uniform coating of polymer and finally releasing the polymer film by removing the silicon or glass handle substrate.
  • the fabrication flow chart is presented in Figure 2, where the tungsten plug process is the core enabler to allow successful transfer of silicon structures to flexible polymer.
  • the proposed method is compatible to standard integrated circuit (IC) processing, allowing it to be integrated on the same platform as other MEMS or IC type devices such as fluidic platfroms and electronic systems.
  • IC integrated circuit
  • a layer of oxide 107 is deposited onto the silicon substrate
  • the oxide 107 is grown thermally by silicon oxidation process or deposited by chemical vapour deposition (CVD).
  • the oxide 107 acts as a sacrificial layer or an etch stop during polysilicon and silicon substrate etching.
  • a polysilicon layer 101a is deposited on top of the oxide 107 as illustrated in Figure 3b. This is the layer to be transferred onto the flexible polymer 103.
  • Polysilicon 101a is deposited by low pressure chemical vapour deposition.
  • the next step is etching of the polysilicon layer 101a to form desired micro- or nano structures as illustrated in Figure 3c.
  • Plasma etching with Tetrafluoromethane (CF 4 ), hydrogen bromide (HBr) or sulphur hexafluoride (SF 6 ) is preferred to achieve sidewall angle closest to 90 ° .
  • the process is followed by the step of depositing a thin titanium nitride (TiN) layer 111 by RF sputtering as an adhesion layer for tungsten 109 deposition as illustrated in Figure 3d.
  • TiN titanium nitride
  • tungsten layer 109 by chemical vapour deposition (CVD) to plug the holes in the etched polysilicon layer 101a is followed ( Figure 3e).
  • Tungsten 109 is used as a sacrificial layer to produce a planarised surface for transferring the polysilicon structures 101a onto the flexible polymer 103 and will be removed at the end of the fabrication cycle.
  • the tungsten layer 109 is etched as in Figure 3f, producing a planarised surface, stopping on the underlying titanium nitride 111 layer.
  • the exposed titanium nitride layer 111 is removed from the surface.
  • a polyimide film 103 is coated onto the planarised surface.
  • the thickness of the polyimide film 103 achieved is dependent on the type of polyimide used and the coating conditions. Then, the polyimide film 103 is released by removing the silicon substrate 105a through backside etching with sulphur hexafluoride (SF 6 ) plasma; or wet etching in potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH). This step is illustrated in Figure 3i. and followed by the final step which is removing the tungsten plug 109 and titanium nitride layer 111 in wet etchant consisting hydrofluoric acid (HF) and nitric acid (HN0 3 ) leaving behind the final desired structures or devices ( Figure 3j).
  • SF 6 sulphur hexafluoride
  • TMAH tetramethylammonium hydroxide
  • Figure 4 illustrates the tungsten layer 109 with polysilicon structures 101a before and after tungsten planarization
  • Figure 5 illustrates the final structures after transferring to polyimide 103.
  • the fabrication process is largely similar to that described above when using silicon as an initial substrate, except that an initial oxide layer 107 is not required when using glass 105b and releasing of the polyimide 103 from the glass substrate 105b is done by etching in hydrofluoric acid (HF).
  • HF hydrofluoric acid
  • single crystal silicon substrate 101b is bonded to another silicon substrate 105a or glass substrate 105b and then thinned to the required structural thickness. Bonding is achieved through fusion bonding for silicon to silicon or anodic bonding for silicon to glass. Thinning of the silicon substrate can be done be either grinding-polishing technique or by inductive coupled plasma etching with sulphur hexafluoride (SF 6 ).
  • SF 6 sulphur hexafluoride

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Abstract

The present invention relates to a method of transferring a silicon based layer 101 a onto a polymer film 103 that comprises the steps of: preparing an initial substrate 105a; depositing a silicon-based layer 101 a on the initial substrate 105a; etching the silicon-based layer to form desired micro-nano structure; depositing a TiN layer 111 by RF sputtering; depositing a tungsten layer 109; etching back the tungsten layer 109 to form a planarised surface exposing the TiN layer 111 on the top of the silicon-based layer; removing the exposed portions of TiN 111 off the silicon-based layer 101a, thus forming a planarised surface comprising the silicon-based layer 101a with at least one tungsten plug 109 formed therein; coating a polymer film 103 onto the planarised surface; releasing the initial substrate 105a from the other layers; and removing the at least one tungsten plug 109 and TiN layer 111.

Description

A METHOD OF TRANSFERRING SILICON
BASED LAYER ONTO POLYMER FILM
Description
Technical Field
Technical Field
[1] The present invention generally relates to flexible polymer type devices and its fabrication.
Background Art
Background Art
[2] Electronic applications are emerging for devices such as displays and sensor arrays on flexible substrates, where it is desirable to be robust, light weight and deformable. The main properties of these devices include their light weight, flexibility, potential low cost, and ability to enable applications such as sensors or smart skin for robotics applications, biomedical applications, smart tags and labels, wearable and mobile sensors for military and commercial use.
[3] Flexible polymer type devices have many applications in the area of tagging,
biomedical and wearable sensors and devices due to its robustness and flexibility. One of the example of the device is a flexible chemical sensor, patent application number US 2010/0050793. The document relates to a flexible sensor device can include a flexible substrate, and at least one flexible sensor included on the flexible substrate. The flexible sensor can be deposited on the flexible substrate by inkjet printing a composition that forms the flexible sensor. The flexible sensor device can be configured to function when subjected to elongation, contraction, and/or distortion. Including the device, the prior arts of polymer devices and methods of fabrication has limitations such that their fabrication are directly on polymer substrates; therefore they are limited to the melting point of the polymer material and their structures are typically of metal or metal oxide based. To form the required structures, they rely heavily on coating of nanotube or nanowire on the polymer surface. In addition, their pattern or structural transfer relies on the use of adhesives and they are also not compatible with wafer fabrication or standard IC processing.
[4] Application of these devices can be wider with improved performance if it is able to incorporate silicon based structures and devices into these flexible devices.
Disclosure of Invention
Technical Problem
[5]
Technical Solution [6]
Summary of the invention
[7] According to one aspect of the present invention, the present invention is provided a method of transferring silicon-based layer 101 onto polymer film 103 comprising the steps of: preparing an initial substrate 201; depositing the silicon-based layer on top of the initial substrates 203; etching the silicon-based layer to form desired micro-nano structure 205; depositing TiN layer by RF sputtering 207; depositing a tungsten layer 209; etching the tungsten layer 211; removing the exposed TiN off the etched planarized tungsten layer 213; coating the polymer onto a planarized surface 215; releasing the polymer film 217; and removing the tungsten plug and TiN layer 219. The above provision is advantageous as it is compatible with wafer fabrication or standard integrated circuit (IC).
Description of Drawings
[8] For a fuller understanding of the nature of the present invention, reference should be made to the following detailed description taken in connection with the accompanying drawings in which:
[9] Figure 1: illustrates silicon-based layer 101 on flexible polymer 103 of the present invention.
[10] Figure 2: illustrates fabrication process flow chart of the present invention.
[11] Figure 3: illustrates the process of transferring of polysilicon structures 101a from silicon substrate 105a onto polyimide film 103 of the present invention.
[12] Figure 4: illustrates tungsten layer 109 a) before; and b) after planarization process of the present invention.
[13] Figure 5: illustrates polisilicon structures 101a after pattern transfer to polymer 103.
[14] Figure 6: illustrates the process of transferring of polysilicon 101a structures from glass substrate 105b onto polyimide film 103 of the present invention.
[15] Figure 7: illustrates the process of producing single crystal silicon 101b layer on silicon 105a or glass 105b substrate prior to structure formation and transfer to polymer 103.
[16]
[17] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[18] The present invention relates to a method of transferring silicon structures 101
(single crystal 101b or polycrystalline 101a) onto a polymer layer 103 which is compatible with wafer fabrication or CMOS type processing. The proposed method utilises a combination of silicon deposition or bonding, etching, tungsten plug process and polymer coating. The present invention generally comprising preparing an initial substrate 201; depositing the silicon-based layer on top of the initial substrates 203; etching the silicon-based layer to form desired micro-nano structure 205; depositing titanium nitride (TiN) layer by RF sputtering 207; depositing a tungsten layer 209; etching the tungsten layer 211; removing the exposed TiN off the etched planarized tungsten layer 213; coating the polymer onto a planarized surface 215; releasing the polymer film 217; and removing the tungsten plug and TiN layer 219.
[19] The prior art of the present invention has limitations in the following areas where fabrication are done directly on the polymer substrates itself hence process methods and types of structures or materials are limited to the melting and operating point of the polymer, typically below 450 ° C. These structures are typically metal or metal oxide based because they can be deposited at much lower temperature by magnetron sputtering or evaporation. However, if they can be substituted with crystalline silicon structures, device performance in terms of sensitivity, reliability and response time can be improved. Nanotube or nanowire can also be utilised to form structures on polymer surfaces; however aligning them into a uniform and highly ordered array still proves a challenging task for large scale fabrication. They are also not compatible with standard wafer fabrication or standard IC processing which makes integration with other devices and circuitry more complicated.
[20] A flexible polymer film 103 comprising silicon based structures/layer 101 as shown in Figure 1. This is achieved by utilising a novel set of fabrication steps to transfer single crystal or polycrystalline silicon (polysilicon) formed on a silicon or glass substrate onto a flexible polymer film, namely polyimide. The single crystal or polysilicon structures can be doped with p- or n- type dopants to improve device conductivity or a combination of both dopant when forming a FET or p-n junction. The transferred structures can be of a simple diode, field effect transistor (FET), photovoltaic cells, microfluidic devices and sensors.
[21] In the proposed method of the present invention, the fabrication can be done on
silicon or glass type substrates where the tungsten plug process is the core enabler to produce a planarised surface between the silicon structures. In the tungsten plug process, tungsten is deposited by chemical vapour deposition (CVD) using tungsten hexafluoride (WF6) as a precursor and etched back to be in plane with the silicon structures. The planar surface allows a uniform coating of polymer and finally releasing the polymer film by removing the silicon or glass handle substrate. The fabrication flow chart is presented in Figure 2, where the tungsten plug process is the core enabler to allow successful transfer of silicon structures to flexible polymer.
[22] The proposed method is compatible to standard integrated circuit (IC) processing, allowing it to be integrated on the same platform as other MEMS or IC type devices such as fluidic platfroms and electronic systems.
[23] The present invention will be explained in more detail through the examples below. The examples are presented only to illustrate the preferred embodiments of the present invention and not intended in any way to limit the scope of the present invention.
[24] The following section describes in more details on the fabrication process steps to transfer silicon based structures to flexible polymer from silicon or glass handle substrates as illustrated in Figure 3, 4 and 6 respectively.
[25] Example 1
[26] Transferring of polvsilicon structures from silicon substrate onto polvimide film.
[27] Referring to Figure 3a, a layer of oxide 107 is deposited onto the silicon substrate
105a. The oxide 107 is grown thermally by silicon oxidation process or deposited by chemical vapour deposition (CVD). The oxide 107 acts as a sacrificial layer or an etch stop during polysilicon and silicon substrate etching. Then, a polysilicon layer 101a is deposited on top of the oxide 107 as illustrated in Figure 3b. This is the layer to be transferred onto the flexible polymer 103. Polysilicon 101a is deposited by low pressure chemical vapour deposition.
[28] The next step is etching of the polysilicon layer 101a to form desired micro- or nano structures as illustrated in Figure 3c. Plasma etching with Tetrafluoromethane (CF4), hydrogen bromide (HBr) or sulphur hexafluoride (SF6) is preferred to achieve sidewall angle closest to 90 ° . Then the process is followed by the step of depositing a thin titanium nitride (TiN) layer 111 by RF sputtering as an adhesion layer for tungsten 109 deposition as illustrated in Figure 3d. Then, the step of depositing a tungsten layer 109 by chemical vapour deposition (CVD) to plug the holes in the etched polysilicon layer 101a is followed (Figure 3e). Tungsten 109 is used as a sacrificial layer to produce a planarised surface for transferring the polysilicon structures 101a onto the flexible polymer 103 and will be removed at the end of the fabrication cycle. Then, the tungsten layer 109 is etched as in Figure 3f, producing a planarised surface, stopping on the underlying titanium nitride 111 layer. After that, as in Figure 3g, the exposed titanium nitride layer 111 is removed from the surface. As in Figure 3h, a polyimide film 103 is coated onto the planarised surface. The thickness of the polyimide film 103 achieved is dependent on the type of polyimide used and the coating conditions. Then, the polyimide film 103 is released by removing the silicon substrate 105a through backside etching with sulphur hexafluoride (SF6) plasma; or wet etching in potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH). This step is illustrated in Figure 3i. and followed by the final step which is removing the tungsten plug 109 and titanium nitride layer 111 in wet etchant consisting hydrofluoric acid (HF) and nitric acid (HN03) leaving behind the final desired structures or devices ( Figure 3j).
[29] Figure 4 illustrates the tungsten layer 109 with polysilicon structures 101a before and after tungsten planarization, while Figure 5 illustrates the final structures after transferring to polyimide 103.
[30] Example 2
[31] Transferring of polvsilicon structures from glass substrate onto polvimide film.
[32] The fabrication process is largely similar to that described above when using silicon as an initial substrate, except that an initial oxide layer 107 is not required when using glass 105b and releasing of the polyimide 103 from the glass substrate 105b is done by etching in hydrofluoric acid (HF). The fabrication process steps are depicted in Figure 6.
[33] In addition to transferring polycrystalline silicon structures 101a, similar process steps can be extended to transfer single crystal silicon structures 101b (which are of higher quality) onto a polymer film 103. As shown in Figure 7, single crystal silicon substrate 101b is bonded to another silicon substrate 105a or glass substrate 105b and then thinned to the required structural thickness. Bonding is achieved through fusion bonding for silicon to silicon or anodic bonding for silicon to glass. Thinning of the silicon substrate can be done be either grinding-polishing technique or by inductive coupled plasma etching with sulphur hexafluoride (SF6).
[34] Although the invention has been described with reference to particular embodiment, it is to be understood that the embodiment is merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiment that other arrangements may be devised without departing from the scope of the present invention as defined by the appended claims.
Best Mode
[35]
Mode for Invention
[36]
Industrial Applicability
[37]
Sequence List Text
[38]

Claims

Claims
[Claim 1] A method of transferring silicon-based layer 101 onto polymer film 103
comprising the steps of:
preparing an initial substrate 201;
depositing the silicon-based layer on top of the initial substrates 203; etching the silicon-based layer to form desired micro-nano structure 205;
depositing TiN layer by RF sputtering 207;
depositing a tungsten layer 209;
etching the tungsten layer 211;
removing the exposed TiN off the etched planarized tungsten layer 213; coating the polymer onto a planarized surface 215;
releasing the polymer film 217; and
removing the tungsten plug and TiN layer 219.
[Claim 2] A method of transferring silicon-based layer 101 onto polymer film 103
as claimed in Claim 1, wherein the initial substrate is glass substrate 105b.
[Claim 3] A method of transferring silicon-based layer 101 onto polymer film 103
as claimed in Claim 1, wherein the initial substrate is silicon substrate 105a having an oxide layer 107 on top.
[Claim 4] A method of transferring silicon-based layer 101 onto polymer film 103
as claimed in Claim 1, wherein the step of etching the silicon-based layer 205 preferably for achieving side wall angle of closest to 90°.
[Claim 5] A method of transferring silicon-based layer 101 onto polymer film 103
as claimed in Claim 1 or Claim 4, wherein the step of etching using CF4 , HBr, or SF6.
[Claim 6] A method of transferring silicon-based layer 101 onto polymer film 103
as claimed in Claim 1, wherein the step of releasing the polymer film 217 further comprising the step of removing the silicon substrate through backside etching with SF6 plasma.
[Claim 7] A method of transferring silicon-based layer 101 onto polymer film 103
as claimed in Claim 1, wherein the step of releasing the polymer film 217 further comprising the step of wet etching in potassium hydroxide.
[Claim 8] A method of transferring silicon-based layer 101 onto polymer film 103
as claimed in Claim 1, wherein the step of releasing the polymer film 217 further comprising the step of wet etching in tetramethy- lammonium hydroxide (TMAH).
[Claim 9] A method of transferring silicon-based layer 101 onto polymer film 103 as claimed in Claim 1, wherein the tungsten plug 109 and TiN 111 in the step of removing the tungsten plug and TiN layer 219 are removed in wet etchant comprising hydrofluoric acid (HF) and nitric acid (HN03 )·
[Claim 10] A method of transferring silicon-based layer 101 onto polymer film 103
as claimed in any precedent claims, wherein the silicon based structure 101 further comprising polysilicon 101a.
[Claim 11] A method of transferring silicon-based layer 101 onto polymer film 103
as claimed in any precedent claims, wherein the silicon-based layer 101 is single silicon structure 101b.
[Claim 12] A polymer type device comprising:
a polymer film 103; and
a silicon-based layer 101 on top of the polymer film 103.
[Claim 13] A polymer type device as claimed in Claim 12, wherein the polymer film 103 further comprising polyimide.
[Claim 14] A polymer type device as claimed in Claim 12, wherein the silicon- based layer 101 further comprising polysilicon 101a.
[Claim 15] A polymer type device as claimed in Claim 12, wherein the silicon- based structure 101 is single silicon structure 101b.
PCT/MY2011/000139 2010-11-30 2011-06-23 A method of transferring silicon based layer onto polymer film WO2012074363A1 (en)

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US20100050793A1 (en) * 2008-08-28 2010-03-04 Dong June Ahn Flexible chemical sensors

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Publication number Priority date Publication date Assignee Title
US20030199127A1 (en) * 2002-04-18 2003-10-23 Tsung-Neng Liao Method of forming a thin film transistor on a plastic sheet
KR100839797B1 (en) * 2007-03-13 2008-06-19 (주) 태양기전 Color thin-film, and method for manufacturing the same
US20100050793A1 (en) * 2008-08-28 2010-03-04 Dong June Ahn Flexible chemical sensors

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* Cited by examiner, † Cited by third party
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WO2014074943A1 (en) * 2012-11-08 2014-05-15 Brewer Science Inc. Cvd-free, scalable processes for the production of silicon micro- and nanostructures
US9299778B2 (en) 2012-11-08 2016-03-29 Brewer Science Inc. CVD-free, scalable processes for the production of silicon micro- and nanostructures

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