WO2012071977A1

WO2012071977A1 - Method and device for time synchronisation on rack

Info

Publication number: WO2012071977A1
Application number: PCT/CN2011/082105
Authority: WO
Inventors: 陈晖�
Original assignee: 中兴通讯股份有限公司
Priority date: 2010-11-30
Filing date: 2011-11-11
Publication date: 2012-06-07
Also published as: CN102142954A; CN102142954B

Abstract

Disclosed are a method and a device for time synchronisation on a rack. The method includes: indicating by a transmitting side to a receiving side that a data transfer is about to begin by means of a rising edge of a synchronisation pulse on a first signal line; transferring by the transmitting side a pulse signal to the receiving side at a frequency higher than n Hz on a second signal line, with n being larger than 1; after the synchronisation pulse has reached an active state with a high level, transmitting by the transmitting side data of a time value on a third signal line when the signal on the second signal line is at a falling edge, and after having received the indication, sampling by the receiving side the data of the time value when the signal on the second signal line is at a rising edge; and after the time value has been received, correcting by the receiving side a local clock according to the received time value. The present invention has a small cumulative error, high accuracy and low requirements on hardware resources. In general, it is simple, reliable, and easy to realise.

Description

Time synchronization method and device in rack

The present invention relates to a communication device, and in particular, to a time synchronization method and device in a rack. Background technique

At present, the scale of China's 3G network construction is expanding day by day. Time synchronization is a very important technical indicator for 3G network construction, and the accuracy of time synchronization requirements is also getting higher and higher.

The time source of the network device, the master clock can be obtained from the GPS (Global Positioning System) or obtained by other means, such as obtaining through the 1588 message, and then sending other network nodes through the message, and time synchronization between the network nodes. Implemented and guaranteed by the 1588 protocol; time synchronization between the main control and the line card inside the rack, usually using the standard TOD (Time Of Day, usually translated as "year, month, day, hour, minute, second" or "current time") interface To achieve, the TOD interface is composed of lpps signal (1 Pulse per Second) and 232 serial port, which can realize one time per second. However, the disadvantage is that the positive time interval is long (1 second), which cannot meet the application of high precision applications. Summary of the invention

The technical problem solved by the present invention is to provide a time synchronization method and apparatus in a rack.

A time synchronization method in a rack is provided in the embodiment of the present invention, including:

On the first signal line, the transmitting side uses the rising edge of the synchronization pulse to indicate to the receiving side that data transmission will begin;

On the second signal line, the transmitting side transmits a pulse signal to the receiving side at a frequency greater than nHz, where n is greater than 1; On the third signal line, the transmitting side transmits the time value data when the signal on the second signal line is at the falling edge after the synchronization pulse is in the active state of the high level, and the receiving side is the second signal line after receiving the indication. Sampling time value data when the signal is at the rising edge;

After receiving the time value, the receiving side corrects the local clock according to the received time value. The time value data sent by the transmitting side is a time value indicated by the transmitting side on the first signal line plus a clock period correction value, and a line delay between the transmitting side and the receiving side, where The clock period correction value is: [(number of bits of time value / time value transmitted per cycle) - 0.5] clock cycles.

Wherein n is 2M; and/or, the time value is 80bit;

The transmitting side sends the time value data when the signal on the second signal line is at a falling edge after the synchronization pulse is in the active state of the high level:

The transmitting side transmits the lbit time value data each time the signal on the second signal line is at the falling edge after the synchronization pulse is in the active state of the high level.

Further, the method further includes:

After the receiving side receives the receiving side, the synchronizing pulse signal on the first signal line is in a low-level failure state.

After the receiving side receives the receiving side, the failure state of the synchronization pulse signal on the first signal line is at a low level:

Starting from the rising edge of the sync pulse, after [(the number of bits of the time value / time value is transmitted per cycle) -0.5] clock cycles, the sync pulse signal on the first signal line is at a low level Failure status.

The embodiment of the present invention provides a time synchronization interface device in a rack, comprising: a sending module and a receiving module, wherein the synchronous sending unit in the sending module is connected to the synchronous receiving unit in the receiving module, and the clock sending unit in the sending module Connected to a clock receiving unit in the receiving module, the data transmitting unit in the transmitting module is connected to the data receiving unit in the receiving module, and the receiving module Also included is a correction unit, wherein:

a synchronous transmitting unit, configured to indicate, by using a rising edge of the synchronization pulse, to the synchronous receiving unit to start data transmission on the first signal line;

a clock sending unit, configured to transmit a pulse signal to the clock receiving unit at a frequency greater than nHz on the second signal line, where n is greater than 1;

a data sending unit, configured to send, on the third signal line, the time value data when the signal on the second signal line is at a falling edge after the synchronous pulse sent by the synchronous transmitting unit is in an active state of a high level;

a data receiving unit, configured to: on the third signal line, sample the time value data when the signal on the second signal line is at a rising edge after the synchronization pulse received by the synchronous receiving unit is in an active state of a high level;

The correcting unit is configured to correct the local clock according to the received time value after the time value is received.

The data sending unit is further configured to determine that the sent time value data is a time value indicated by the synchronous transmitting unit on the first signal line, plus a clock period correction value, and then between the sending module and the receiving module. The line delay, where the clock period correction value is: [(number of bits of the time value / time value transmitted per cycle) - 0.5] clock cycles.

The clock sending unit is further configured to use a frequency of n being 2M; and/or, the data sending unit is further configured to determine that the sent time value is 80 bits, and each time the wrist is transmitted.

The sending module further includes:

The failing unit is configured to make the synchronous pulse signal on the first signal line in a low state after the data receiving unit receives the signal.

The failing unit is further configured to start from a rising edge of the synchronization pulse after receiving the data receiving unit, and then pass [(the bit value of the time value/time value is transmitted per cycle) Quantity) -0.5] A failure state in which the sync pulse signal on the first signal line is at a low level after one clock cycle.

The beneficial effects of the present invention are as follows:

Since the transmitting side transmits the pulse signal to the receiving side at a frequency greater than nHz, n is greater than 1; and when the falling edge is transmitting time value data, the receiving side samples the time value data while at the rising edge. When the pulse signal frequency is greater than 1 Hz, the signal period on the second signal line must be less than 1 second, that is, the time value for the synchronization correction must be less than 1 second, and the calibration time is 1 second with respect to the normal TOD interface. In terms of accuracy, the synchronization accuracy must be higher. It is also known that the technical solutions provided by the embodiments of the present invention are easily used to meet the application requirements of various communication systems after determining the time error of various communication systems. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a schematic flowchart of a method for implementing a time synchronization method in a rack according to an embodiment of the present invention; FIG. 2 is a schematic diagram of timings of signal transmission according to an embodiment of the present invention;

3 is a schematic diagram of a time synchronization implementation process of a transmitting side and a receiving side according to an embodiment of the present invention; FIG. 4 is a schematic structural diagram of a time synchronization interface device in a rack according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described with reference to the accompanying drawings.

Figure 1 is a schematic diagram of the implementation process of the time synchronization method in the rack. As shown in Figure 1, the following steps can be included:

Step 101: On the first signal line, the transmitting side uses a rising edge of the synchronization pulse to indicate to the receiving side that data transmission will start;

Step 102: On the second signal line, the transmitting side transmits a pulse signal to the receiving side at a frequency greater than n Hz, where n is greater than 1;

Step 103: On the third signal line, the transmitting side is in an active state in which the synchronization pulse is at a high level. After the signal on the second signal line is at the falling edge, the time value data is transmitted, and the receiving side samples the time value data when the signal on the second signal line is at the rising edge after receiving the indication;

Step 104: After receiving the time value, the receiving side corrects the local clock according to the received time value.

In the implementation, it may further include:

Step 105: After the receiving side receives the receiving side, the transmitting side makes the synchronous pulse signal on the first signal line in a low state.

In a specific implementation, in the time synchronization process, it may be composed of three line signals: Psync+Time_data+Time_clk. The three signal lines are a first signal line Psync (synchronous signal;), a third signal line Time_data (time data), and a second signal line Time_clk (clock). For convenience of explanation, the clock on the second signal line is used. 2MHz.

When implemented in a rack, for the master (referred to as the transmitting side in this application), the signals of the three signal lines are output signals; for the received line card (referred to as the receiving side in this application), three The signals of the signal lines are all input signals. Or, conversely, the master receives and the line card sends, and the effect is the same.

Psync is a synchronization pulse, which is used to prompt the subsequent Time_clk rising edge to start data transmission; Time_data transmits time information, which can transmit the year, month, day, hour, minute and second in sequence. In practice, it can be accurate to ns level according to needs; Time_clk is the transmission clock. The receiving side samples the data on the rising edge. Figure 2 is a schematic diagram of signal transmission timing. The timing of the three signal lines is shown in Figure 2. The transmitting side sends time information. The receiving side has a local clock module, and then adjusts and corrects according to the received time value.

From the transmitting side, after the Psync signal is active (high level), Time_data starts to transmit time information in sequence: year, month, day, hour, minute, and second (for convenience of description, a fixed 80-bit content is taken as an example), each time lbit is transmitted, The data is valid on the rising edge of Time_clk, and the accumulated transmission of 80 bits is completed, and then the Psync signal is invalidated. From the receiving side, after receiving the Psync signal pulse (sampling to the rising edge), it starts to enter the receiving program. On the rising edge of Time_clk, the data on Time_data is sampled until all 80 bits are received.

For a better understanding, the following is an example.

In the present embodiment, on the second signal line, the transmitting side transmits a pulse signal to the receiving side at a frequency of 2 MHz, and on the third signal line, the transmitting side transmits a time value of 80 bits, each time transmitting lbit.

In the implementation, the values of 2 MHz, 80 bit, etc. are only used to teach the person skilled in the art how to implement the invention, but it does not mean that only the value in the embodiment can be used. In fact, as long as the frequency is greater than 1, it is better than the present. There is a common TOD interface in the technology to correct the time in one second. Of course, in practice, the length of the actual transmitted time value must be considered to determine the specific frequency. For example, when transmitting the time value of 80 bits, the frequency is only The technical concept of the technical solution provided by the embodiment of the present invention is easy to implement by selecting the corresponding time value length and frequency. At the same time, the accuracy of the time value can be determined according to the time precision. Of course, the time value is not necessarily 80 bits. Similarly, each transmission is not limited to lbit. Therefore, it is easy for those skilled in the art to refer to the present embodiment to determine corresponding values in the implementation process in conjunction with practical needs.

FIG. 3 is a schematic diagram of a time synchronization implementation process on the transmitting side and the receiving side. As shown in FIG. 3, referring to FIG. 3, the following steps may be included:

Step 301: At the time T1, the Psync signal is valid, and the subsequent transmission time value is added to the reception delay At.

In this step, at the time T1 shown in FIG. 2, the transmitting side gives a Psync effective signal, which changes from low to high. The receiving side is notified to prepare for the receiving time value. The time value to be transmitted is not the time value at time T1, but the fixed delay At from transmission to reception needs to be added. When Time_clk temporarily selects 2M clock in this embodiment, A t is 79.5 Time_clk clock cycles. (3975ns) + line delay. If the Time_clk frequency changes, the A t value also changes accordingly. For the same For each system, the line delay is basically fixed, and the specific value (ns level) can be obtained by measurement. Step 302: Time_data sends data, sends data on the falling edge of Time_clk, and the receiving side samples on the rising edge.

In this step, on the transmitting side, after the falling edge of Time_clk, the time value is sent on Time_data, and sequentially transmitted in the order of year, month, day, hour, minute, and second, until the 80-bit transmission is completed. On the receiving side, on the rising edge of Time_clk, the data on the Time_data line is sampled.

Step 303: It is judged whether the 80 bit transmission is finished, if yes, the process proceeds to step 304, otherwise, the process proceeds to step 302.

In this step, the transmitting side determines whether the 80 bit transmission is completed, and if it is not finished, returns to step 302. If the 80bit transmission is completed, go to step 304. On the receiving side, if the 80bit is not received, continue to wait for the following data bits until the 80bit reception is completed.

Step 304: The transmitting side waits for a half Time_clk period after the T2 time to invalidate the Psync signal.

In this step, the transmitting side waits for half of the Time_clk period after the time T2 shown in FIG. 2, and disables the Psync signal from high to low. The receiving side performs sampling and correction of all clock values substantially at time T2.

In other implementations, in other cases, the processing of the failure may also be: after the receiving side receives the receiving side, the synchronization pulse signal on the first signal line is low after [1/2] clock cycles. The flat failure state, or, at the time T1 as shown in Fig. 2, passes through [(the number of bits of the time value/time value is transmitted per cycle) - 0.5] clock cycles to make the first signal line The sync pulse signal is in a low state of failure.

In this way, synchronization between the transmitting side and the receiving side of the rack can be achieved.

Based on the same inventive concept, the time synchronization interface device in the rack is also provided in the embodiment of the present invention. Since the principle of solving the problem is similar to the time synchronization method in the rack, the implementation of the device can refer to the implementation of the method. The repetitions are not repeated here. Figure 4 is a schematic structural diagram of a time synchronization interface device in a rack. As shown in the figure, the interface device may include:

Transmitting module 401 and receiving module 402;

The synchronous transmitting unit 4011 in the transmitting module 401 is connected to the synchronous receiving unit 4021 in the receiving module 402, the clock transmitting unit 4012 in the transmitting module 401 is connected to the clock receiving unit 4022 in the receiving module 402, and the data transmitting unit in the transmitting module 401 4013 is connected to the data receiving unit 4023 in the receiving module 402. The receiving module 402 further includes a correcting unit 4024, where:

The synchronous transmitting unit 4011 is configured to, on the first signal line, indicate to the synchronization receiving unit 4021 that the data transmission will be started by using the rising edge of the synchronization pulse;

The clock sending unit 4012 is configured to transmit a pulse signal to the clock receiving unit 4022 at a frequency greater than n Hz on the second signal line, where n is greater than 1;

The data sending unit 4013 is configured to send, on the third signal line, the time value data when the synchronization pulse sent by the synchronous transmitting unit 4011 is in an active state of a high level, and when the signal on the second signal line is at a falling edge;

The data receiving unit 4023 is configured to, on the third signal line, sample the time value data when the signal on the second signal line is at a rising edge after the synchronization pulse received by the synchronization receiving unit 4021 is in an active state of a high level;

The correcting unit 4024 is configured to correct the local clock according to the received time value after the time value is received.

In the implementation, the data sending unit 4013 may further be configured to determine that the time value of the sending is the time value indicated by the synchronous transmitting unit 4011 on the first signal line plus the clock period correction value, and then the sending module 401 and the receiving module. Line delay between 402, where the clock period correction value is: [(number of bit values of time value / time value transmitted per cycle) -0.5] clock cycles, or, [(bit value bit bit) The number is -0.5] clock cycles per clock cycle. In an implementation, the clock sending unit 4012 may further be configured to adopt a frequency where n is 2Μ; and/or, the data transmitting unit 4013 may be further configured to determine that the transmitted time value is 80 bits, and each time the bit is transmitted.

In the implementation, the sending module 401 may further include:

The failing unit 4014 is configured to enable the synchronization pulse signal on the first signal line to be in a low state after the data receiving unit 4023 receives the completion.

In the implementation, the failing unit 4014 may further be configured to enable the synchronization pulse signal on the first signal line to be in a low state after [1/2] clock cycles after the data receiving unit 4023 is received, or As shown in Fig. 2 at time T1, after [(the number of bits of the time value/time value is transmitted per cycle) -0.5] clock cycles, the synchronization pulse signal on the first signal line is at a low level. Failure status.

For convenience of description, the various parts of the above described devices are described separately by function into various modules or units. Of course, in implementing the present invention, the functions of the modules or units can be implemented in the same software or hardware, for example, by using the CPU 10 or the programmable device 10 pins.

Ordinary TOD interface usually sends a TOD message once every second, and the receiving side checks for one time. If the master receives time information from the 1588 packet mode, the master clock frequency differs from the 1588 master by 1 PPM (this should be the case;), because the 1 second interval is too long, 1 second response on the line card The time error is lus. After the multi-level time node is transmitted, the error accumulation is larger, which also leads to the inability to meet the application requirements. For example, TD-SCDMA (Time Division Synchronized Code Division Multiple Access) is required to meet the application requirements of time difference between base stations within 1.5 us, and cannot satisfy CDMA (Code Division Multiple Access). Address access requirements are application requirements within 3us.

However, by adopting the technical solution provided in the embodiment of the invention, the method of improving the time proofing frequency is used to compensate for the above defects, for example, it can be increased to 490 times per second, which is obviously greatly reduced. Short adjustment time interval. In the specific implementation, it is only necessary to set the number of times per second to be sent by software.

In the technical solution provided by the embodiment of the invention, the internal time synchronization of the rack can be realized by using only the three-wire interface, and the positive time interval can be modified by software, and the accumulated error is small, and the precision is high (the inside of the rack is nanoseconds) Level error), the implementation of the CPU 10 or programmable device 10 feet can be achieved, do not need to use a dedicated 232 serial port, the hardware resources are not high. It is simple, reliable and easy to implement.

Those skilled in the art will appreciate that embodiments of the present invention can be provided as a method, system, or computer program product. Thus, the present invention can take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart and/or block diagrams, and combinations of flows and/or blocks in the flowcharts and/or block diagrams can be implemented by computer program instructions. These computer program instructions may be provided to a general purpose computer, a special machine, such that instructions executed by a processor of a computer or other programmable data processing device are used to implement a block or a block and/or block diagram of a flowchart or A device that has multiple functions specified in the box.

The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart. These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

While the preferred embodiment of the invention has been described, the subject matter Therefore, it is intended that the appended claims be interpreted as including

It is apparent that those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. Thus, it is intended that the present invention cover the modifications and modifications of the invention

Claims

Claim

A time synchronization method in a rack, the method comprising: transmitting, on a first signal line, a rising edge of a synchronization pulse on a transmitting side to a receiving side to start data transmission;

On the second signal line, the transmitting side transmits a pulse signal to the receiving side at a frequency greater than n Hz, where n is greater than 1;

On the third signal line, the transmitting side transmits the time value data when the signal on the second signal line is at the falling edge after the synchronization pulse is in the active state of the high level, and the receiving side is the second signal line after receiving the indication. Sampling time value data when the signal is at the rising edge;

After receiving the time value, the receiving side corrects the local clock according to the received time value.

2. The method according to claim 1, wherein the time value data sent by the transmitting side is a time value indicated by the transmitting side on the first signal line plus a clock period correction value, and then sent The line delay between the side and the receiving side, where the clock period correction value is: [(number of bits of the time value / time value transmitted per cycle) - 0.5] clock cycles.

3. The method according to claim 2, wherein the n is 2M; and/or, the time value is 80 bits;

The method according to any one of claims 1 to 3, wherein the method further comprises:

5. The method according to claim 4, wherein the transmitting side receives on the receiving side After the completion, the failure state of the synchronization pulse signal on the first signal line is at a low level: starting from the rising edge of the synchronization pulse, and then passing [(the number of bits of the time value/time value is transmitted per cycle) -0.5] A fail state in which the sync pulse signal on the first signal line is at a low level after one clock cycle.

A time synchronization interface device in a rack, the device comprising: a sending module and a receiving module, wherein the synchronous sending unit in the sending module is connected to the synchronous receiving unit in the receiving module, and the clock in the sending module The sending unit is connected to the clock receiving unit in the receiving module, and the data sending unit in the sending module is connected to the data receiving unit in the receiving module, and the receiving module further comprises a correcting unit, wherein:

a clock sending unit, configured to transmit a pulse signal to the clock receiving unit at a frequency greater than n Hz on the second signal line, where n is greater than 1;

The device according to claim 6, wherein the data transmitting unit adds a time period value to the clock period correction value, and further adds a line delay between the transmitting module and the receiving module, wherein The clock period correction value is: [ (the bit value of the time value / time value is transmitted per cycle) The number) -0.5] clock cycles.

8. The device according to claim 7, wherein the clock transmitting unit is further used to adopt a frequency of n of 2M;

And / or, the data sending unit is further configured to determine that the time value sent is 80 bits, each time transmitting lbito

The device according to any one of claims 6 to 8, wherein the sending module further comprises:

The device according to claim 9, wherein the failing unit is further configured to start from a rising edge of the synchronization pulse after receiving the data receiving unit, and then pass [(bit value bit number/ The time value is transmitted per cycle) -0.5] After the clock cycle, the sync pulse signal on the first signal line is in a low state.