WO2012070551A1 - Device for manufacturing and method for manufacturing memory element - Google Patents

Device for manufacturing and method for manufacturing memory element Download PDF

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Publication number
WO2012070551A1
WO2012070551A1 PCT/JP2011/076851 JP2011076851W WO2012070551A1 WO 2012070551 A1 WO2012070551 A1 WO 2012070551A1 JP 2011076851 W JP2011076851 W JP 2011076851W WO 2012070551 A1 WO2012070551 A1 WO 2012070551A1
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Prior art keywords
etching
metal oxide
manufacturing
oxide layer
chamber
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PCT/JP2011/076851
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French (fr)
Japanese (ja)
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善明 吉田
小風　豊
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株式会社アルバック
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Priority to JP2012528170A priority Critical patent/JP5437492B2/en
Publication of WO2012070551A1 publication Critical patent/WO2012070551A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

Definitions

  • the present invention relates to a memory device manufacturing apparatus and manufacturing method, and more particularly to a memory device manufacturing apparatus and manufacturing method having a transition metal oxide layer.
  • ReRAM Resistance Random Access Memory
  • the single cell structure of ReRAM is a simple capacitor structure in which a transition metal oxide exhibiting an insulator or semiconductor electrical property is sandwiched between metal electrodes, and can generate a huge resistance change by applying a pulse voltage. it can.
  • the ReRAM has a feature that a minimum cell area of 4F 2 (F is a minimum processing dimension in a manufacturing process of a memory cell, so-called design rule) is possible, and multi-value can be made.
  • F is a minimum processing dimension in a manufacturing process of a memory cell, so-called design rule
  • the bit cost can be reduced by high integration, and it is expected as a universal memory that replaces and integrates DRAM and Flash memory.
  • Transition metals such as Co and Ni are used for the resistance change film used in ReRAM, and the vapor pressure of fluorides and chlorides of these materials is low, which is known as a difficult etching material.
  • the etching product easily adheres to the side wall of the element pattern, and in the prior art, this product remains and becomes dust and contaminates the apparatus in the next process or the next process. There is a risk of disconnection or insulation failure in the wiring formation process.
  • FIGS. 2A to 2C a conventional metal oxide pattern forming method will be described.
  • a processing target in which an insulating layer 112, a lower electrode 113, a metal oxide layer 114, and first and second metal layers 116 and 117 are laminated in this order on a substrate 111.
  • a mask 120 having a predetermined pattern is formed on the second metal layer 117 of the object.
  • the first and second metal layers 116 and 117 constitute the upper electrode 118.
  • the object to be processed is transferred to an etching chamber and etched with a chlorine-based gas such as Cl 2 or BCl 3 until the lower electrode 113 is exposed.
  • the etching product 125 adheres to the etched side wall portion of the object to be processed.
  • the object to be processed is carried into an ashing chamber while maintaining a vacuum atmosphere, and plasma ashing is performed using O 2 gas to remove the mask 120. After ashing, a residue 126 is seen on the side wall of the object to be processed. The residue 126 cannot be removed in the subsequent steps and remains.
  • the present invention was created to solve the above-mentioned disadvantages of the prior art, and its purpose is to remove etching products generated in reactive ion etching to form a pattern on a metal oxide satisfactorily. I will provide a.
  • the inventors examined the residue and found that the residue was an oxide of Co or Ni. Since the etching product is a chloride of Co or Ni, it is considered that the oxide is formed by oxidizing the chloride generated during the etching during the ashing. The oxide could not be removed in a later step, but the chloride could be dissolved by washing with water, thus completing the present invention.
  • a metal oxide layer is disposed between the upper electrode and the lower electrode and a DC voltage is applied between the upper electrode and the lower electrode, the DC voltage is reduced.
  • information can be stored by entering one of a high resistance state and a low resistance state, a sense current is passed in the film thickness direction, a resistance value is measured, and the high resistance state and the An apparatus for manufacturing a memory element capable of reading information by determining a low resistance state, an etching chamber having a gas supply unit for supplying an etching gas, and a plasma generating unit for converting the etching gas into a plasma
  • the memory device manufacturing apparatus is configured to expose the lower electrode by etching, and the cleaning chamber is configured to contact a cleaning liquid with the etched surface of the processing object.
  • the present invention is a memory device manufacturing apparatus, wherein the metal oxide layer is selected from the group consisting of Al 2 O 3 , Y 2 O 5 , HfO 2 , TiO 2 , CoO, and NiO. This is an apparatus for manufacturing a memory element made of one metal oxide.
  • the present invention is an apparatus for manufacturing a memory element, wherein the etching gas is one of a gas selected from the group consisting of Cl 2 , BCl 3 , and SiCl 4 , or a mixed gas of two or more. It is a manufacturing device.
  • the present invention when a metal oxide is disposed between the upper electrode and the lower electrode, and a DC voltage is applied between the upper electrode and the lower electrode, a high resistance state and a low resistance are generated according to the polarity of the DC voltage.
  • Information can be recorded by entering one of the resistance states, and a sense current is passed in the film thickness direction, and the resistance value is measured to discriminate between the high resistance state and the low resistance state.
  • An apparatus for manufacturing a memory element that can be read wherein the upper electrode is exposed on a processing object in which the lower electrode, the metal oxide layer, and the upper electrode are stacked in this order on a substrate.
  • a cleaning liquid is brought into contact with the etched surface of the processing object, a method of manufacturing a memory device having a cleaning process for removing metal chlorides generated in the etching step.
  • the present invention is a method of manufacturing a memory device, wherein the metal oxide layer is selected from the group consisting of Al 2 O 3 , Y 2 O 5 , HfO 2 , TiO 2 , CoO, and NiO.
  • 1 is a method of manufacturing a memory element made of one metal oxide.
  • the present invention is a method of manufacturing a memory device, wherein the etching gas used for etching the metal oxide layer is one gas selected from the group consisting of Cl 2 , BCl 3 , and SiCl 4 , or two or more. Is a method for manufacturing a memory element containing a mixed gas of
  • the etching product can be removed, the yield of ReRAM manufacturing can be improved without contaminating the devices after the next step or causing disconnection or insulation failure in the next wiring formation step. Since the transition metal oxide can be stably patterned by reactive ion etching, high integration of ReRAM becomes possible.
  • FIG. 1E shows the structure of the memory element 5 formed according to the present invention
  • FIG. 4 shows a schematic diagram of the memory device 1 having a plurality of memory elements 5.
  • the storage device 1 includes a storage unit 6 and a control unit 7.
  • a plurality of memory elements 5 are arranged in the storage unit 6.
  • the memory element 5 has a lower electrode 13, a metal oxide layer 14, and first and second metal layers 16 and 17, and the layers 13, 14, 16, and 17 are insulated. They are stacked on the substrate 11 in this order via the layer 12.
  • the first and second metal layers 16 and 17 constitute the upper electrode 18. That is, the metal oxide layer 14 is disposed between the upper electrode 18 and the lower electrode 13.
  • the substrate 11 is made of a semiconductor or the like, and Si is used here, and the insulating layer 12 is made of an insulator, and here is SiO 2 .
  • the lower electrode 13 and the first and second metal layers 16 and 17 are made of a conductive material.
  • a TiN film is used for the lower electrode 13 and the second metal layer 17, and the first metal layer 16 is an Al film.
  • the metal oxide layer 14 is made of one metal oxide selected from the group consisting of Al 2 O 3 , Y 2 O 5 , HfO 2 , TiO 2 , CoO, and NiO.
  • the memory element 5 When a DC voltage is applied between the upper electrode 18 and the lower electrode 13, the memory element 5 is either in a high resistance state or a low resistance state having a resistance value lower than that in the high resistance state depending on the polarity of the DC voltage. It comes to be in one state.
  • the memory element 5 when a positive pulse voltage is applied with the upper electrode 18 as an anode and the lower electrode 13 as a cathode, the memory element 5 is in a low resistance state, and a negative pulse voltage is applied.
  • it is configured to be in a high resistance state, it is configured to be in a high resistance state when a pulsed positive voltage is applied, and to be in a low resistance state when a pulsed negative voltage is applied. May be.
  • first and second connection terminals are electrically connected to the second metal layer 17 and the lower electrode 13, respectively.
  • Reference numerals 71a and 71b in FIG. 4 indicate first and second connection terminals.
  • the one memory element 5 When a DC voltage is applied from the control unit 7 to the first and second connection terminals 71a and 71b of the one memory element 5, the one memory element 5 has a high resistance state and a low resistance depending on the polarity of the DC voltage. One of the resistance states is entered. By associating the low resistance state and the high resistance state with 1 and 0, respectively, 1/0 information can be recorded.
  • a sense current is passed from the control unit 7 in the film thickness direction of the one memory element 5 via the first and second connection terminals 71a and 71b, and the resistance value of the one memory element 5 is measured. By discriminating between the high resistance state and the low resistance state, the information stored in the one memory element 5 can be read out.
  • FIG. 3 shows a memory device manufacturing apparatus 50 according to the present invention.
  • the memory element manufacturing apparatus 50 includes an etching chamber 30 that forms a predetermined pattern on a processing target, a cleaning chamber 52 that removes etching products, and a transfer chamber that transfers the processing target from the etching chamber 30 to the cleaning chamber 52. 51.
  • the etching chamber 30 includes a vacuum chamber 39, a gas supply unit 31 that supplies an etching gas into the vacuum chamber 39, a plasma generation unit 42 that converts the supplied etching gas into plasma, and a vacuum that evacuates the vacuum chamber 39.
  • positioned in the vacuum layer 39 are provided.
  • a stage 36 for placing a processing object is provided inside the vacuum chamber 39.
  • the temperature control unit 38 is connected to the stage 36, and can control the temperature of the processing object placed on the stage 36 by flowing a temperature-controlled heat medium through a cooling pipe (not shown) provided on the stage 36, for example. Has been.
  • the plasma generation unit 42 includes an RF antenna 33, a plasma matching box 37a, and a plasma high-frequency power source 34.
  • the RF antenna 33 is installed above the vacuum chamber 39 and is electrically connected to the plasma high frequency power supply 34 via the plasma matching box 37a.
  • a high frequency voltage is applied from the plasma high frequency power supply 34 to the RF antenna 33,
  • the etching gas supplied into the vacuum chamber 39 can be converted into plasma by inductive coupling.
  • a high frequency power supply 35 for bias is electrically connected to the stage 36 via a bias matching box 37b.
  • a high frequency voltage is applied to the stage 36 from the high frequency power supply 35 for bias, an electric field is formed on the stage 36.
  • ions in the plasma are drawn toward the stage 36 and collide with the object to be processed, so that the object to be processed can be anisotropically etched.
  • the gas supply unit 31 is installed outside the vacuum chamber 39 and is connected to the inside of the vacuum chamber 39 so that an etching gas can be supplied into the vacuum chamber 39.
  • the evacuation unit 32 is installed outside the vacuum chamber 39 and connected to the inside of the vacuum chamber 39 so that the inside of the vacuum chamber 39 can be evacuated.
  • the transfer chamber 51 is hermetically connected to the vacuum chamber 39 of the etching chamber 30 via the first gate valve 55a, and the cleaning chamber 52 is hermetically connected to the transfer chamber 51 via the second gate valve 55b. Yes.
  • the transfer chamber 51 has an evacuation unit (not shown), and is configured so that the transfer chamber 51 can be evacuated while the first and second gate valves 55a and 55b are closed.
  • the first and second gate valves 55a and 55b are closed, and the inside of the vacuum chamber 39 and the transfer chamber 51 of the etching chamber 30 are evacuated in advance to maintain a vacuum atmosphere. Further, an inert gas not containing oxygen is introduced into the cleaning chamber 52 to keep the atmospheric pressure.
  • FIG. 1A a processing target in which an insulating layer 12, a lower electrode 13, a metal oxide layer 14, and first and second metal layers 16 and 17 are stacked in this order on a substrate 11.
  • a photoresist is applied on the second metal layer 17, a predetermined pattern is exposed and developed, and a mask 20 having an opening is formed.
  • the second metal layer 17 is exposed on the bottom surface of the opening of the mask 20.
  • an imprint resist is applied onto the second metal layer 17 and an original plate having irregularities of a predetermined pattern is pressed to form a mask 20 having an opening, and the second metal layer 17 is formed on the bottom surface of the opening. It may be exposed.
  • the object to be processed 10 is carried into the vacuum chamber 39 of the etching chamber 30 while maintaining the vacuum atmosphere with reference to FIG. 36.
  • the temperature control unit 38 is operated, a temperature-controlled heat medium is passed through a cooling pipe (not shown) of the stage 36, and the temperature of the processing object 10 during etching is maintained in the range of 20 ° C to 80 ° C.
  • a first etching gas is supplied from the gas supply unit 31, and the inside of the vacuum chamber 39 is maintained at a pressure of 0.1 Pa to 2.0 Pa.
  • a gas containing chlorine in the chemical structure is used as the first etching gas, for example, a gas containing one gas or a mixed gas of two or more selected from the group consisting of Cl 2 , BCl 3 , and SiCl 4. is there.
  • a rare gas He, Ne, Ar, Kr, Xe
  • the high frequency power supply for plasma 34 is activated, an alternating current is passed through the RF antenna 33, radio waves are emitted from the RF antenna 33 into the vacuum chamber 39, the first etching gas is excited and turned into plasma, and chlorine ions and chlorine radicals are produced. And so on.
  • the bias high-frequency power source 35 is activated, a bias voltage is applied to the object 10 to be processed, and the generated chlorine ions are incident on the object 10 to perform an anisotropic etching process.
  • the supply of the second etching gas from the gas supply unit 31 is started.
  • the inside of the vacuum chamber 39 is maintained at a pressure of 0.1 Pa to 10 Pa according to the selection ratio with the resist (mask 20).
  • a gas containing chlorine to the composition in the chemical structure in the second etching gas for example, Cl 2, and BCl 3
  • the gas containing one gas or more of the mixed gas selected from the group of SiCl 4 It is.
  • a rare gas He, Ne, Ar, Kr, Xe
  • a rare gas He, Ne, Ar, Kr, Xe
  • the high frequency power source for plasma 34 and the high frequency power source for bias 35 are operated, and the exposed metal oxide layer 14 is reacted with the second etching gas by chlorine ions in the plasma to generate a chloride gas. Then, anisotropic etching is performed by removing chloride gas by evacuation.
  • an etching product 25 made of a metal chloride contained in the metal oxide layer 14 adheres and remains on the etched side wall portion of the processing object 10. This is because the metal chloride contained in the metal oxide layer 14 generally has a high melting point and boiling point and a low vapor pressure at the temperature during etching.
  • a transfer robot 65 is provided in the transfer chamber 51. After the transfer chamber 51 is evacuated and the pressure in the vacuum chamber 39 decreases, the first gate valve 55a is opened to move the processing object 10 from the vacuum chamber 39 into the transfer chamber 51, and One gate valve 55a is closed. Next, an inert gas not containing oxygen is introduced into the transfer chamber 51 to raise the pressure in the transfer chamber 51 to atmospheric pressure.
  • a cleaning stage 61 on which a processing target can be placed and a shower nozzle 62 for injecting a cleaning liquid onto the processing target placed on the cleaning stage 61 are arranged.
  • the second gate valve 55 b is opened, the processing object 10 is carried into the cleaning chamber 52 from the transfer chamber 51, and placed on the cleaning stage 61.
  • a cleaning liquid is sprayed from the shower nozzle 62 onto the etched surface of the processing object 10, and the etching surface of the processing object 10 is brought into contact with the cleaning liquid to perform a cleaning process.
  • the shower method is described as the cleaning method, but the present invention is not limited to this, and the cleaning process is performed by bringing the etched surface of the processing object 10 into contact with the cleaning liquid by another cleaning method such as an ultrasonic dip method. May be.
  • the cleaning liquid one kind or a mixture of two or more kinds of water such as pure water, ion exchange water, micro / nano bubble water, and organic solvents such as ethanol, methanol, acetone, isopropyl alcohol, and ethyl ether are used.
  • the etching product 25 is, for example, a water-soluble and alcohol-soluble metal chloride such as CoCl 2 or NiCl 2. As shown in FIG. 1D, the etching product 25 is dissolved in the cleaning liquid by the cleaning process using the cleaning liquid. And removed.
  • the time required from the time when the processing object 10 is brought into contact with the atmosphere in the transfer chamber 51 to the start of the cleaning in the cleaning chamber 52 is within 5 minutes. This is because when the object to be treated 10 is put into the atmosphere, chlorine remaining on the surface of the object to be treated 10 reacts with moisture in the atmosphere to form HCl. This is because if a material (for example, Al) that is corroded by HCl is used for the object 10 to be processed, corrosion (corrosion) may occur there.
  • a material for example, Al
  • the object to be processed is dried by centrifugal force drying or high-temperature gas blowing, and then the object to be processed is carried into an ashing chamber (not shown), and plasma ashing is performed using O 2 gas.
  • O 2 gas oxygen ions and oxygen radicals generated from the excited O 2 gas oxidize and decompose the mask 20 to remove the mask 20.
  • the etching product 25 on the side wall portion of the object to be processed is removed before ashing, and no oxide residue remains on the side wall portion after ashing.
  • the memory element 5 in which the pattern is formed on the metal oxide layer 14 as shown in FIG. 1E is obtained.

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Abstract

Provided are a device for manufacturing and a method for manufacturing a memory element having a metal oxide layer with etching resistance. Anisotropic etching is performed by the metal oxide layer (14) reacting with etching gas containing chlorine in the chemical structure thereof and generating a chloride gas, which is eliminated by vacuum exhausting. Etching products (25) adhere to the side wall parts that have been etched and remain because the vapor pressure is low at the temperature during etching. These etching products (25) are water soluble; therefore, directly after etching, the etched surfaces are brought into contact with a washing fluid and the etching products (25) are eliminated by dissolution. Thus, a memory element (5) for which a pattern is formed by the metal oxide layer (14) can be obtained.

Description

メモリ素子の製造装置及び製造方法Memory device manufacturing apparatus and manufacturing method
　本発明は、メモリ素子の製造装置及び製造方法に関し、特に、遷移金属酸化物層を有するメモリ素子の製造装置及び製造方法に関する。 The present invention relates to a memory device manufacturing apparatus and manufacturing method, and more particularly to a memory device manufacturing apparatus and manufacturing method having a transition metal oxide layer.
　近年、遷移金属酸化物を用いた新しい不揮発性メモリとして抵抗変化メモリ（Ｒｅｓｉｓｔａｎｃｅ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ、ＲｅＲＡＭ）が注目されている。ＲｅＲＡＭの単一セル構造は、絶縁体または半導体的な電気特性を示す遷移金属酸化物を金属電極で挟んだ単純キャパシタ構造であり、パルス電圧を印加することにより巨大な抵抗変化を発生させることができる。 In recent years, a resistance change memory (Resistance Random Access Memory, ReRAM) has attracted attention as a new nonvolatile memory using a transition metal oxide. The single cell structure of ReRAM is a simple capacitor structure in which a transition metal oxide exhibiting an insulator or semiconductor electrical property is sandwiched between metal electrodes, and can generate a huge resistance change by applying a pulse voltage. it can.
　ＲｅＲＡＭは、４Ｆ2（Ｆはメモリセルの製造プロセスにおける最小加工寸法、いわゆる設計ルール）の最小セル面積が可能であり、また多値化が可能である等の特徴をもつ。またＲｅＲＡＭ製造プロセスはＣＭＯＳプロセスとの整合性が良いことから、高集積化によるビットコスト低減が可能であり、ＤＲＡＭやＦｌａｓｈメモリを代替・統合するユニバーサルメモリとして期待されている。 The ReRAM has a feature that a minimum cell area of 4F 2 (F is a minimum processing dimension in a manufacturing process of a memory cell, so-called design rule) is possible, and multi-value can be made. In addition, since the ReRAM manufacturing process has good consistency with the CMOS process, the bit cost can be reduced by high integration, and it is expected as a universal memory that replaces and integrates DRAM and Flash memory.
　メモリの大容量化のためには微細なメモリセルを制御性よく加工する必要があり、またＣＭＯＳプロセスとの親和性の観点から、半導体分野で広く用いられている反応性イオンエッチング（Ｒｅａｃｔｉｖｅ　Ｉｏｎ　Ｅｔｃｈｉｎｇ、ＲＩＥ）による加工プロセスの開発が求められている。 In order to increase the memory capacity, it is necessary to process fine memory cells with good controllability, and from the viewpoint of compatibility with CMOS processes, reactive ion etching (Reactive Ion Etching) widely used in the semiconductor field , RIE) is required to develop a machining process.
　ＲｅＲＡＭで使われている抵抗変化膜にはＣｏやＮｉ等の遷移金属が用いられており、これらの材料のフッ化物や塩化物の蒸気圧は低く、難エッチング材料として知られている。このような材料をエッチングした場合、エッチング生成物が素子パターンの側壁に付着しやすく、従来技術ではこの生成物が残留し、ゴミとなって次工程以降の装置を汚染したり、次工程である配線形成工程において断線もしくは絶縁不良の原因となる虞があった。 Transition metals such as Co and Ni are used for the resistance change film used in ReRAM, and the vapor pressure of fluorides and chlorides of these materials is low, which is known as a difficult etching material. When such a material is etched, the etching product easily adheres to the side wall of the element pattern, and in the prior art, this product remains and becomes dust and contaminates the apparatus in the next process or the next process. There is a risk of disconnection or insulation failure in the wiring formation process.
　図２（ａ）～（ｃ）を参照し、従来技術による金属酸化物のパターン形成方法を説明する。
　まず、図２（ａ）に示すように、基板１１１上に絶縁層１１２と下部電極１１３と金属酸化物層１１４と第一、第二の金属層１１６、１１７とがこの順に積層された処理対象物の第二の金属層１１７上に、所定のパターンのマスク１２０を形成する。ここでは第一、第二の金属層１１６、１１７が上部電極１１８を構成している。 With reference to FIGS. 2A to 2C, a conventional metal oxide pattern forming method will be described.
First, as shown in FIG. 2A, a processing target in which an insulating layer 112, a lower electrode 113, a metal oxide layer 114, and first and second metal layers 116 and 117 are laminated in this order on a substrate 111. A mask 120 having a predetermined pattern is formed on the second metal layer 117 of the object. Here, the first and second metal layers 116 and 117 constitute the upper electrode 118.
　次いで図２（ｂ）に示すように、この処理対象物をエッチング室に搬送し、Ｃｌ2やＢＣｌ3等の塩素系ガスにて下部電極１１３が露出するまでエッチングする。このとき処理対象物のエッチングされた側壁部分にはエッチング生成物１２５が付着する。
　次いで図２（ｃ）に示すように、処理対象物を真空雰囲気に維持したまま、アッシング室に搬入し、Ｏ2ガスを用いてプラズマアッシングを行い、マスク１２０を除去する。アッシング後には処理対象物の側壁部分に残留物１２６が見られる。残留物１２６は後工程以降で除去できず、残留することになる。 Next, as shown in FIG. 2B, the object to be processed is transferred to an etching chamber and etched with a chlorine-based gas such as Cl 2 or BCl 3 until the lower electrode 113 is exposed. At this time, the etching product 125 adheres to the etched side wall portion of the object to be processed.
Next, as shown in FIG. 2C, the object to be processed is carried into an ashing chamber while maintaining a vacuum atmosphere, and plasma ashing is performed using O 2 gas to remove the mask 120. After ashing, a residue 126 is seen on the side wall of the object to be processed. The residue 126 cannot be removed in the subsequent steps and remains.
再公表特許２００４／００８５３５号公報Republished Patent 2004/008535
　本発明は上記従来技術の不都合を解決するために創作されたものであり、その目的は、反応性イオンエッチングにおいて発生するエッチング生成物を除去して、金属酸化物にパターンを良好に形成する技術を提供する。 The present invention was created to solve the above-mentioned disadvantages of the prior art, and its purpose is to remove etching products generated in reactive ion etching to form a pattern on a metal oxide satisfactorily. I will provide a.
　本発明者らは残留物を検討したところ、残留物はＣｏやＮｉの酸化物であることが分かった。エッチング生成物がＣｏやＮｉの塩化物であることから、酸化物はエッチングの際に生成された塩化物がアッシングの際に酸化されて形成されると考えられる。酸化物は後工程で除去できないが、塩化物は水洗することで溶解できることから本発明を完成させた。 The inventors examined the residue and found that the residue was an oxide of Co or Ni. Since the etching product is a chloride of Co or Ni, it is considered that the oxide is formed by oxidizing the chloride generated during the etching during the ashing. The oxide could not be removed in a later step, but the chloride could be dissolved by washing with water, thus completing the present invention.
　係る知見に基づいて成された本発明は、上部電極と下部電極との間に金属酸化物層が配置され、前記上部電極と前記下部電極との間に直流電圧を印加すると、前記直流電圧の極性に応じて高抵抗状態と低抵抗状態のいずれか一方の状態になることにより情報を記憶することができ、膜厚方向にセンス電流を流し、抵抗値を測定して前記高抵抗状態と前記低抵抗状態とを判別することにより情報を読み出すことができるメモリ素子の製造装置であって、エッチングガスを供給するガス供給部と、前記エッチングガスをプラズマ化するプラズマ生成部とを有するエッチング室と、前記エッチング室に接続して配置された洗浄室と、処理対象物を前記エッチング室から前記洗浄室に搬送する搬送室と、を有し、前記エッチング室は、基板上に前記下部電極と前記金属酸化物層と前記上部電極とがこの順に積層された処理対象物が搬入されると、化学構造中に塩素を含むエッチングガスをプラズマ化し、前記上部電極と前記金属酸化物層をエッチングして、前記下部電極を露出させるように構成され、前記洗浄室は、前記処理対象物のエッチングした表面に洗浄液を接触させるように構成されたメモリ素子の製造装置である。
　本発明はメモリ素子の製造装置であって、前記金属酸化物層は、Ａｌ2Ｏ3と、Ｙ2Ｏ5と、ＨｆＯ2と、ＴｉＯ2と、ＣｏＯと、ＮｉＯとからなる群より選択される一の金属酸化物からなるメモリ素子の製造装置である。
　本発明はメモリ素子の製造装置であって、前記エッチングガスは、Ｃｌ2と、ＢＣｌ3と、ＳｉＣｌ4とからなる群より選択される一のガス又は二以上の混合ガスを含有するメモリ素子の製造装置である。
　本発明は、上部電極と下部電極との間に金属酸化物が配置され、前記上部電極と前記下部電極との間に直流電圧を印加すると、前記直流電圧の極性に応じて高抵抗状態と低抵抗状態のいずれか一方の状態になることにより情報を記録することができ、膜厚方向にセンス電流を流し、抵抗値を測定して高抵抗状態と低抵抗状態とを判別することにより情報を読み出すことができるメモリ素子の製造装置であって、基板上に前記下部電極と前記金属酸化物層と前記上部電極とがこの順に積層された処理対象物上に、前記上部電極が露出するような開口を有する所定のパターンのマスクを配置するマスク工程と、化学構造中に塩素を含むエッチングガスをプラズマ化し、前記上部電極と前記金属酸化物層をエッチングして、前記下部電極を露出させるエッチング工程と、前記処理対象物のエッチングした表面に洗浄液を接触させ、前記エッチング工程で生成された金属の塩化物を除去する洗浄工程とを有するメモリ素子の製造方法である。
　本発明はメモリ素子の製造方法であって、前記金属酸化物層は、Ａｌ2Ｏ3と、Ｙ2Ｏ5と、ＨｆＯ2と、ＴｉＯ2と、ＣｏＯと、ＮｉＯとからなる群より選択される一の金属酸化物からなるメモリ素子の製造方法である。
　本発明はメモリ素子の製造方法であって、前記金属酸化物層のエッチングに用いる前記エッチングガスは、Ｃｌ2と、ＢＣｌ3と、ＳｉＣｌ4とからなる群より選択される一のガス又は二以上の混合ガスを含有するメモリ素子の製造方法である。 In the present invention based on such knowledge, when a metal oxide layer is disposed between the upper electrode and the lower electrode and a DC voltage is applied between the upper electrode and the lower electrode, the DC voltage is reduced. Depending on the polarity, information can be stored by entering one of a high resistance state and a low resistance state, a sense current is passed in the film thickness direction, a resistance value is measured, and the high resistance state and the An apparatus for manufacturing a memory element capable of reading information by determining a low resistance state, an etching chamber having a gas supply unit for supplying an etching gas, and a plasma generating unit for converting the etching gas into a plasma A cleaning chamber connected to the etching chamber, and a transfer chamber for transferring an object to be processed from the etching chamber to the cleaning chamber, the etching chamber on the substrate. When a processing object in which an electrode, the metal oxide layer, and the upper electrode are stacked in this order is carried in, an etching gas containing chlorine in the chemical structure is turned into plasma, and the upper electrode and the metal oxide layer are The memory device manufacturing apparatus is configured to expose the lower electrode by etching, and the cleaning chamber is configured to contact a cleaning liquid with the etched surface of the processing object.
The present invention is a memory device manufacturing apparatus, wherein the metal oxide layer is selected from the group consisting of Al 2 O 3 , Y 2 O 5 , HfO 2 , TiO 2 , CoO, and NiO. This is an apparatus for manufacturing a memory element made of one metal oxide.
The present invention is an apparatus for manufacturing a memory element, wherein the etching gas is one of a gas selected from the group consisting of Cl 2 , BCl 3 , and SiCl 4 , or a mixed gas of two or more. It is a manufacturing device.
According to the present invention, when a metal oxide is disposed between the upper electrode and the lower electrode, and a DC voltage is applied between the upper electrode and the lower electrode, a high resistance state and a low resistance are generated according to the polarity of the DC voltage. Information can be recorded by entering one of the resistance states, and a sense current is passed in the film thickness direction, and the resistance value is measured to discriminate between the high resistance state and the low resistance state. An apparatus for manufacturing a memory element that can be read, wherein the upper electrode is exposed on a processing object in which the lower electrode, the metal oxide layer, and the upper electrode are stacked in this order on a substrate. A mask process for disposing a mask having a predetermined pattern having an opening, and plasma etching of an etching gas containing chlorine in the chemical structure, etching the upper electrode and the metal oxide layer to expose the lower electrode And an etching step, a cleaning liquid is brought into contact with the etched surface of the processing object, a method of manufacturing a memory device having a cleaning process for removing metal chlorides generated in the etching step.
The present invention is a method of manufacturing a memory device, wherein the metal oxide layer is selected from the group consisting of Al 2 O 3 , Y 2 O 5 , HfO 2 , TiO 2 , CoO, and NiO. 1 is a method of manufacturing a memory element made of one metal oxide.
The present invention is a method of manufacturing a memory device, wherein the etching gas used for etching the metal oxide layer is one gas selected from the group consisting of Cl 2 , BCl 3 , and SiCl 4 , or two or more. Is a method for manufacturing a memory element containing a mixed gas of
　エッチング生成物を除去できるので、次工程以降の装置を汚染したり、次工程である配線形成工程において断線もしくは絶縁不良を起こしたりせず、ＲｅＲＡＭ製造の歩留まりが向上する。
　遷移金属酸化物を反応性イオンエッチングで安定してパターン形成できるので、ＲｅＲＡＭの高集積化が可能となる。 Since the etching product can be removed, the yield of ReRAM manufacturing can be improved without contaminating the devices after the next step or causing disconnection or insulation failure in the next wiring formation step.
Since the transition metal oxide can be stably patterned by reactive ion etching, high integration of ReRAM becomes possible.
（ａ）～（ｅ）：本発明のメモリ素子の製造方法を説明する図(A)-(e): The figure explaining the manufacturing method of the memory element of this invention （ａ）～（ｃ）：従来技術による金属酸化物のパターン形成方法を説明する図(A)-(c): The figure explaining the metal oxide pattern formation method by a prior art 本発明のメモリ素子の製造装置の内部構成図The internal block diagram of the memory device manufacturing apparatus of this invention 本発明で形成されたメモリ素子を有する記憶装置の模式図Schematic diagram of a memory device having a memory element formed in the present invention
　図１（ｅ）に本発明で形成されるメモリ素子５の構造を示し、図４にこのメモリ素子５を複数有する記憶装置１の模式図を示す。
　図４に示すように、記憶装置１は記憶部６と制御部７とを有している。記憶部６には複数のメモリ素子５が配置されている。 FIG. 1E shows the structure of the memory element 5 formed according to the present invention, and FIG. 4 shows a schematic diagram of the memory device 1 having a plurality of memory elements 5.
As illustrated in FIG. 4, the storage device 1 includes a storage unit 6 and a control unit 7. A plurality of memory elements 5 are arranged in the storage unit 6.
　図１（ｅ）に示すように、メモリ素子５は下部電極１３と金属酸化物層１４と第一、第二の金属層１６、１７とを有し、各層１３、１４、１６、１７は絶縁層１２を介して基板１１上にこの順に積層されて配置されている。第一、第二の金属層１６、１７とが上部電極１８を構成している。すなわち、上部電極１８と下部電極１３との間に金属酸化物層１４が配置されている。 As shown in FIG. 1E, the memory element 5 has a lower electrode 13, a metal oxide layer 14, and first and second metal layers 16 and 17, and the layers 13, 14, 16, and 17 are insulated. They are stacked on the substrate 11 in this order via the layer 12. The first and second metal layers 16 and 17 constitute the upper electrode 18. That is, the metal oxide layer 14 is disposed between the upper electrode 18 and the lower electrode 13.
　基板１１は半導体等から成り、ここではＳｉが用いられており、絶縁層１２は絶縁物から成り、ここではＳｉＯ2である。また下部電極１３と第一、第二の金属層１６、１７は導電性物質から成り、ここでは下部電極１３と第二の金属層１７にはＴｉＮ膜が用いられており、第一の金属層１６にはＡｌ膜が用いられている。
　金属酸化物層１４は、Ａｌ2Ｏ3と、Ｙ2Ｏ5と、ＨｆＯ2と、ＴｉＯ2と、ＣｏＯと、ＮｉＯとからなる群より選択される一の金属酸化物からなる。 The substrate 11 is made of a semiconductor or the like, and Si is used here, and the insulating layer 12 is made of an insulator, and here is SiO 2 . The lower electrode 13 and the first and second metal layers 16 and 17 are made of a conductive material. Here, a TiN film is used for the lower electrode 13 and the second metal layer 17, and the first metal layer 16 is an Al film.
The metal oxide layer 14 is made of one metal oxide selected from the group consisting of Al 2 O 3 , Y 2 O 5 , HfO 2 , TiO 2 , CoO, and NiO.
　上部電極１８と下部電極１３との間に直流電圧が印加されると、メモリ素子５は、直流電圧の極性に応じて高抵抗状態と、高抵抗状態より抵抗値の低い低抵抗状態のいずれか一方の状態になるようになっている。
　本実施例では、上部電極１８を陽極とし、下部電極１３を陰極として、パルス状の正電圧が印加されると、メモリ素子５は低抵抗状態になり、パルス状の負電圧が印加されると、高抵抗状態になるように構成されているが、パルス状の正電圧が印加されると、高抵抗状態になり、パルス状の負電圧が印加されると、低抵抗状態になるように構成されていてもよい。 When a DC voltage is applied between the upper electrode 18 and the lower electrode 13, the memory element 5 is either in a high resistance state or a low resistance state having a resistance value lower than that in the high resistance state depending on the polarity of the DC voltage. It comes to be in one state.
In this embodiment, when a positive pulse voltage is applied with the upper electrode 18 as an anode and the lower electrode 13 as a cathode, the memory element 5 is in a low resistance state, and a negative pulse voltage is applied. Although it is configured to be in a high resistance state, it is configured to be in a high resistance state when a pulsed positive voltage is applied, and to be in a low resistance state when a pulsed negative voltage is applied. May be.
　下部電極１３の表面は部分的に露出され、第二の金属層１７と下部電極１３にはそれぞれ第一、第二の接続端子が電気的に接続されている。
　図４の符号７１ａ、７１ｂは第一、第二の接続端子を示している。 The surface of the lower electrode 13 is partially exposed, and first and second connection terminals are electrically connected to the second metal layer 17 and the lower electrode 13, respectively.
Reference numerals 71a and 71b in FIG. 4 indicate first and second connection terminals.
　制御部７から一のメモリ素子５の第一、第二の接続端子７１ａ、７１ｂの間に直流電圧を印加すると、直流電圧の極性に応じて、この一のメモリ素子５は高抵抗状態と低抵抗状態のいずれか一方の状態になる。低抵抗状態と高抵抗状態とをそれぞれ１と０に対応づけることにより、１／０の情報を記録することができる。 When a DC voltage is applied from the control unit 7 to the first and second connection terminals 71a and 71b of the one memory element 5, the one memory element 5 has a high resistance state and a low resistance depending on the polarity of the DC voltage. One of the resistance states is entered. By associating the low resistance state and the high resistance state with 1 and 0, respectively, 1/0 information can be recorded.
　また制御部７から第一、第二の接続端子７１ａ、７１ｂを介して一のメモリ素子５の膜厚方向にセンス電流を流し、この一のメモリ素子５の抵抗値を測定して、測定値を高抵抗状態と低抵抗状態に判別することにより、この一のメモリ素子５に記憶された情報を読み出すことができる。 In addition, a sense current is passed from the control unit 7 in the film thickness direction of the one memory element 5 via the first and second connection terminals 71a and 71b, and the resistance value of the one memory element 5 is measured. By discriminating between the high resistance state and the low resistance state, the information stored in the one memory element 5 can be read out.
　図３に本発明であるメモリ素子の製造装置５０を示す。
　メモリ素子の製造装置５０は、処理対象物に所定のパターンを形成するエッチング室３０と、エッチング生成物を除去する洗浄室５２と、処理対象物をエッチング室３０から洗浄室５２に搬送する搬送室５１とを有している。 FIG. 3 shows a memory device manufacturing apparatus 50 according to the present invention.
The memory element manufacturing apparatus 50 includes an etching chamber 30 that forms a predetermined pattern on a processing target, a cleaning chamber 52 that removes etching products, and a transfer chamber that transfers the processing target from the etching chamber 30 to the cleaning chamber 52. 51.
　エッチング室３０は、真空槽３９と、真空槽３９内にエッチングガスを供給するガス供給部３１と、供給されたエッチングガスをプラズマ化するプラズマ生成部４２と、真空槽３９内を真空排気する真空排気部３２と、真空層３９内に配置された処理対象物の温度を制御する温度制御部３８とを有している。 The etching chamber 30 includes a vacuum chamber 39, a gas supply unit 31 that supplies an etching gas into the vacuum chamber 39, a plasma generation unit 42 that converts the supplied etching gas into plasma, and a vacuum that evacuates the vacuum chamber 39. The exhaust part 32 and the temperature control part 38 which controls the temperature of the process target object arrange | positioned in the vacuum layer 39 are provided.
　真空槽３９の内部には処理対象物を載置するためのステージ３６が設けられている。
　温度制御部３８はステージ３６に接続され、例えばステージ３６に設けられた不図示の冷却パイプに温度制御した熱媒体を流すことにより、ステージ３６上に載置される処理対象物の温度を制御できるようにされている。 Inside the vacuum chamber 39, a stage 36 for placing a processing object is provided.
The temperature control unit 38 is connected to the stage 36, and can control the temperature of the processing object placed on the stage 36 by flowing a temperature-controlled heat medium through a cooling pipe (not shown) provided on the stage 36, for example. Has been.
　プラズマ生成部４２はＲＦアンテナ３３とプラズマ用マッチングボックス３７ａとプラズマ用高周波電源３４とを有している。ＲＦアンテナ３３は真空槽３９の上方に設置され、プラズマ用マッチングボックス３７ａを介してプラズマ用高周波電源３４に電気的に接続されており、プラズマ用高周波電源３４からＲＦアンテナ３３に高周波電圧を印加すると、誘導結合により、真空槽３９内に供給されたエッチングガスをプラズマ化できるようにされている。 The plasma generation unit 42 includes an RF antenna 33, a plasma matching box 37a, and a plasma high-frequency power source 34. The RF antenna 33 is installed above the vacuum chamber 39 and is electrically connected to the plasma high frequency power supply 34 via the plasma matching box 37a. When a high frequency voltage is applied from the plasma high frequency power supply 34 to the RF antenna 33, The etching gas supplied into the vacuum chamber 39 can be converted into plasma by inductive coupling.
　またステージ３６にはバイアス用マッチングボックス３７ｂを介してバイアス用高周波電源３５が電気的に接続されており、バイアス用高周波電源３５からステージ３６に高周波電圧を印加すると、ステージ３６上に電場を形成して、プラズマ中のイオンをステージ３６側に引き込んで処理対象物に衝突させ、処理対象物を異方性エッチングできるようにされている。 A high frequency power supply 35 for bias is electrically connected to the stage 36 via a bias matching box 37b. When a high frequency voltage is applied to the stage 36 from the high frequency power supply 35 for bias, an electric field is formed on the stage 36. Thus, ions in the plasma are drawn toward the stage 36 and collide with the object to be processed, so that the object to be processed can be anisotropically etched.
　ガス供給部３１は、真空槽３９の外部に設置されて、真空槽３９内部に接続され、真空槽３９内にエッチングガスを供給可能にされている。
　真空排気部３２は、真空槽３９の外部に設置されて、真空槽３９内部に接続され、真空槽３９内を真空排気可能にされている。 The gas supply unit 31 is installed outside the vacuum chamber 39 and is connected to the inside of the vacuum chamber 39 so that an etching gas can be supplied into the vacuum chamber 39.
The evacuation unit 32 is installed outside the vacuum chamber 39 and connected to the inside of the vacuum chamber 39 so that the inside of the vacuum chamber 39 can be evacuated.
　搬送室５１は、エッチング室３０の真空槽３９に第一のゲートバルブ５５ａを介して気密に接続され、洗浄室５２は、搬送室５１に第二のゲートバルブ５５ｂを介して気密に接続されている。
　搬送室５１は不図示の真空排気手段を有し、第一、第二のゲートバルブ５５ａ、５５ｂを閉じた状態で、搬送室５１内を真空排気できるように構成されている。 The transfer chamber 51 is hermetically connected to the vacuum chamber 39 of the etching chamber 30 via the first gate valve 55a, and the cleaning chamber 52 is hermetically connected to the transfer chamber 51 via the second gate valve 55b. Yes.
The transfer chamber 51 has an evacuation unit (not shown), and is configured so that the transfer chamber 51 can be evacuated while the first and second gate valves 55a and 55b are closed.
　本発明であるメモリ素子の製造方法を説明する。
　第一、第二のゲートバルブ５５ａ、５５ｂを閉じて、エッチング室３０の真空槽３９内と搬送室５１内をあらかじめ真空排気して真空雰囲気に維持しておく。また洗浄室５２内に酸素を含有しない不活性ガスを導入して、大気圧にしておく。 A method for manufacturing a memory element according to the present invention will be described.
The first and second gate valves 55a and 55b are closed, and the inside of the vacuum chamber 39 and the transfer chamber 51 of the etching chamber 30 are evacuated in advance to maintain a vacuum atmosphere. Further, an inert gas not containing oxygen is introduced into the cleaning chamber 52 to keep the atmospheric pressure.
　図１（ａ）に示すように、基板１１上に、絶縁層１２と下部電極１３と金属酸化物層１４と第一、第二の金属層１６、１７とがこの順序で積層された処理対象物を用いる。
　まずマスク工程として、図１（ｂ）に示すように、第二の金属層１７上に、フォトレジストを塗布し、所定のパターンを露光し、現像して、開口を有するマスク２０を形成する。マスク２０の開口部の底面には第二の金属層１７が露出する。 As shown in FIG. 1A, a processing target in which an insulating layer 12, a lower electrode 13, a metal oxide layer 14, and first and second metal layers 16 and 17 are stacked in this order on a substrate 11. Use things.
First, as a mask process, as shown in FIG. 1B, a photoresist is applied on the second metal layer 17, a predetermined pattern is exposed and developed, and a mask 20 having an opening is formed. The second metal layer 17 is exposed on the bottom surface of the opening of the mask 20.
　あるいは、第二の金属層１７上にインプリントレジストを塗布し、所定のパターンの凹凸を有する原板を押し当てて、開口を有するマスク２０を形成し、開口の底面に第二の金属層１７を露出させてもよい。
　次いで、エッチング工程として、この処理対象物１０を、図３を参照し、エッチング室３０の真空槽３９内に真空雰囲気を維持しながら搬入し、マスク２０側の表面が露出するような向きでステージ３６上に載置する。 Alternatively, an imprint resist is applied onto the second metal layer 17 and an original plate having irregularities of a predetermined pattern is pressed to form a mask 20 having an opening, and the second metal layer 17 is formed on the bottom surface of the opening. It may be exposed.
Next, as an etching process, the object to be processed 10 is carried into the vacuum chamber 39 of the etching chamber 30 while maintaining the vacuum atmosphere with reference to FIG. 36.
　温度制御部３８を動作させ、ステージ３６の不図示の冷却パイプに温度制御した熱媒体を流し、エッチング中の処理対象物１０の温度を２０℃～８０℃の範囲に保持する。
　ガス供給部３１から第一のエッチングガスを供給し、真空槽３９内を０．１Ｐａ～２．０Ｐａの圧力に保持する。第一のエッチングガスには化学構造中に塩素を含有するガスを用い、例えばＣｌ2と、ＢＣｌ3と、ＳｉＣｌ4の群から選択される一のガス又は二以上の混合ガスを含有するガスである。ＢＣｌ3を使用する場合には、重合性を希釈するため、希ガス（Ｈｅ、Ｎｅ、Ａｒ、Ｋｒ、Ｘｅ）を添加してもよい。 The temperature control unit 38 is operated, a temperature-controlled heat medium is passed through a cooling pipe (not shown) of the stage 36, and the temperature of the processing object 10 during etching is maintained in the range of 20 ° C to 80 ° C.
A first etching gas is supplied from the gas supply unit 31, and the inside of the vacuum chamber 39 is maintained at a pressure of 0.1 Pa to 2.0 Pa. A gas containing chlorine in the chemical structure is used as the first etching gas, for example, a gas containing one gas or a mixed gas of two or more selected from the group consisting of Cl 2 , BCl 3 , and SiCl 4. is there. When BCl 3 is used, a rare gas (He, Ne, Ar, Kr, Xe) may be added to dilute the polymerizability.
　プラズマ用高周波電源３４を起動し、ＲＦアンテナ３３に交流電流を流し、ＲＦアンテナ３３から真空槽３９内に電波を放射させ、第一のエッチングガスを励起して、プラズマ化し、塩素イオンや塩素ラジカル等の活性種を生成する。またバイアス用高周波電源３５を起動し、処理対象物１０にバイアス電圧を印加して、生成された塩素イオンを処理対象物１０に入射させ、異方性のエッチング処理を行う。 The high frequency power supply for plasma 34 is activated, an alternating current is passed through the RF antenna 33, radio waves are emitted from the RF antenna 33 into the vacuum chamber 39, the first etching gas is excited and turned into plasma, and chlorine ions and chlorine radicals are produced. And so on. In addition, the bias high-frequency power source 35 is activated, a bias voltage is applied to the object 10 to be processed, and the generated chlorine ions are incident on the object 10 to perform an anisotropic etching process.
　ここでは、ステージ３６を囲むようにシールド４１が設けられており、エッチング生成物の真空槽３９の内壁への付着が防止されている。
　異方性のエッチング処理により金属酸化物層１４が露出したら、プラズマ用高周波電源３４とバイアス用高周波電源３５の動作をそれぞれ停止し、かつガス供給部３１からの第一のエッチングガスの供給を停止する。 Here, a shield 41 is provided so as to surround the stage 36, and adhesion of etching products to the inner wall of the vacuum chamber 39 is prevented.
When the metal oxide layer 14 is exposed by the anisotropic etching process, the operations of the plasma high-frequency power source 34 and the bias high-frequency power source 35 are stopped, and the supply of the first etching gas from the gas supply unit 31 is stopped. To do.
　第一のエッチングガスを真空排気し、真空槽３９内の圧力が低下した後、ガス供給部３１から第二のエッチングガスの供給を開始する。真空槽３９内はレジスト（マスク２０）との選択比に応じて０．１Ｐａ～１０Ｐａの圧力に保持する。第二のエッチングガスには化学構造中に塩素を組成に含むガスを用い、例えばＣｌ2と、ＢＣｌ3と、ＳｉＣｌ4の群から選択される一のガス又は二以上の混合ガスを含有するガスである。ＢＣｌ3を使用する場合には、重合性を希釈するため、希ガス（Ｈｅ、Ｎｅ、Ａｒ、Ｋｒ、Ｘｅ）を添加してもよい。 After the first etching gas is evacuated and the pressure in the vacuum chamber 39 decreases, the supply of the second etching gas from the gas supply unit 31 is started. The inside of the vacuum chamber 39 is maintained at a pressure of 0.1 Pa to 10 Pa according to the selection ratio with the resist (mask 20). Using a gas containing chlorine to the composition in the chemical structure in the second etching gas, for example, Cl 2, and BCl 3, the gas containing one gas or more of the mixed gas selected from the group of SiCl 4 It is. When BCl 3 is used, a rare gas (He, Ne, Ar, Kr, Xe) may be added to dilute the polymerizability.
　次いで、プラズマ用高周波電源３４とバイアス用高周波電源３５を動作させ、プラズマ中の塩素イオンにより、露出している金属酸化物層１４を第二のエッチングガスと反応させ、塩化物ガスを生成して、真空排気によって塩化物ガスを除去することで、異方性エッチングする。 Next, the high frequency power source for plasma 34 and the high frequency power source for bias 35 are operated, and the exposed metal oxide layer 14 is reacted with the second etching gas by chlorine ions in the plasma to generate a chloride gas. Then, anisotropic etching is performed by removing chloride gas by evacuation.
　このとき図１（ｃ）に示すように、処理対象物１０のエッチングされた側壁部分には金属酸化物層１４に含まれる金属の塩化物からなるエッチング生成物２５が付着し、残留する。これは一般に、金属酸化物層１４に含まれる金属の塩化物は融点、沸点が高く、エッチング中の温度では蒸気圧が低いためである。 At this time, as shown in FIG. 1C, an etching product 25 made of a metal chloride contained in the metal oxide layer 14 adheres and remains on the etched side wall portion of the processing object 10. This is because the metal chloride contained in the metal oxide layer 14 generally has a high melting point and boiling point and a low vapor pressure at the temperature during etching.
　下部電極１３が露出したら、プラズマ用高周波電源３４とバイアス用高周波電源３５の動作をそれぞれ停止し、かつガス供給部３１からの第二のエッチングガスの供給を停止する。
　搬送室５１にはここでは搬送用のロボット６５が設けられている。搬送室５１を真空排気しておき、真空槽３９内の圧力が低下した後、第一のゲートバルブ５５ａを開いて、真空槽３９内から搬送室５１内に処理対象物１０を移動させ、第一のゲートバルブ５５ａを閉じる。次いで、搬送室５１内に酸素を含有しない不活性ガスを導入して、搬送室５１内の圧力を大気圧まで上げる。 When the lower electrode 13 is exposed, the operations of the plasma high-frequency power source 34 and the bias high-frequency power source 35 are stopped, and the supply of the second etching gas from the gas supply unit 31 is stopped.
Here, a transfer robot 65 is provided in the transfer chamber 51. After the transfer chamber 51 is evacuated and the pressure in the vacuum chamber 39 decreases, the first gate valve 55a is opened to move the processing object 10 from the vacuum chamber 39 into the transfer chamber 51, and One gate valve 55a is closed. Next, an inert gas not containing oxygen is introduced into the transfer chamber 51 to raise the pressure in the transfer chamber 51 to atmospheric pressure.
　洗浄室５２内には、処理対象物を載置できる洗浄ステージ６１と、洗浄ステージ６１に載置された処理対象物に洗浄液を噴射するシャワーノズル６２とが配置されている。
　第二のゲートバルブ５５ｂを開き、処理対象物１０を搬送室５１から洗浄室５２に搬入し、洗浄ステージ６１上に置く。 In the cleaning chamber 52, a cleaning stage 61 on which a processing target can be placed and a shower nozzle 62 for injecting a cleaning liquid onto the processing target placed on the cleaning stage 61 are arranged.
The second gate valve 55 b is opened, the processing object 10 is carried into the cleaning chamber 52 from the transfer chamber 51, and placed on the cleaning stage 61.
　次いで洗浄工程として、処理対象物１０のエッチングした表面にシャワーノズル６２から洗浄液を噴霧して、処理対象物１０のエッチングした表面を洗浄液と接触させて洗浄処理を行う。
　ここでは洗浄方法としてシャワー式を説明したが、本発明はこれに限定されず、超音波ディップ式等の他の洗浄方法で処理対象物１０のエッチングした表面を洗浄液と接触させて洗浄処理をしても良い。 Next, as a cleaning process, a cleaning liquid is sprayed from the shower nozzle 62 onto the etched surface of the processing object 10, and the etching surface of the processing object 10 is brought into contact with the cleaning liquid to perform a cleaning process.
Here, the shower method is described as the cleaning method, but the present invention is not limited to this, and the cleaning process is performed by bringing the etched surface of the processing object 10 into contact with the cleaning liquid by another cleaning method such as an ultrasonic dip method. May be.
　洗浄液としては、純水、イオン交換水、マイクロ・ナノバブル水などの水や、エタノール、メタノール、アセトン、イソプロピルアルコール、エチルエーテルなどの有機溶媒のうち一種類又は二種類以上の混合物を用いる。
　エッチング生成物２５は、例えばＣｏＣｌ2やＮｉＣｌ2等の水溶性及びアルコール可溶性の金属の塩化物であり、図１（ｄ）に示すように、洗浄液による洗浄処理によりエッチング生成物２５は洗浄液に溶解して、除去される。 As the cleaning liquid, one kind or a mixture of two or more kinds of water such as pure water, ion exchange water, micro / nano bubble water, and organic solvents such as ethanol, methanol, acetone, isopropyl alcohol, and ethyl ether are used.
The etching product 25 is, for example, a water-soluble and alcohol-soluble metal chloride such as CoCl 2 or NiCl 2. As shown in FIG. 1D, the etching product 25 is dissolved in the cleaning liquid by the cleaning process using the cleaning liquid. And removed.
　ここで、搬送室５１にて処理対象物１０を大気に接触させてからから洗浄室５２にて洗浄を開始するまでに要する時間は５分以内が望ましい。なぜならば、処理対象物１０を大気に出すと、処理対象物１０の表面に残留していた塩素が大気中の水分と反応しＨＣｌを形成する。処理対象物１０にＨＣｌにて腐食される材料（例えばＡｌ）を使っていると、そこに腐食（コロージョン）が発生する虞があるからである。 Here, it is desirable that the time required from the time when the processing object 10 is brought into contact with the atmosphere in the transfer chamber 51 to the start of the cleaning in the cleaning chamber 52 is within 5 minutes. This is because when the object to be treated 10 is put into the atmosphere, chlorine remaining on the surface of the object to be treated 10 reacts with moisture in the atmosphere to form HCl. This is because if a material (for example, Al) that is corroded by HCl is used for the object 10 to be processed, corrosion (corrosion) may occur there.
　洗浄処理を終えた後、遠心力による乾燥や、高温気体の吹き付けなどによって処理対象物を乾燥させ、次いで、不図示のアッシング室に処理対象物を搬入し、Ｏ2ガスを用いてプラズマアッシングを行う。励起したＯ2ガスから生じた酸素イオンや酸素ラジカルがマスク２０を酸化、分解させて、マスク２０が除去される。
　処理対象物の側壁部分のエッチング生成物２５はアッシング前に除去されており、アッシング後に側壁部分に酸化物から成る残留物が残留することはない。
　このようにして図１（ｅ）に示すように金属酸化物層１４にパターン形成が成されたメモリ素子５が得られる。 After the cleaning process is completed, the object to be processed is dried by centrifugal force drying or high-temperature gas blowing, and then the object to be processed is carried into an ashing chamber (not shown), and plasma ashing is performed using O 2 gas. Do. Oxygen ions and oxygen radicals generated from the excited O 2 gas oxidize and decompose the mask 20 to remove the mask 20.
The etching product 25 on the side wall portion of the object to be processed is removed before ashing, and no oxide residue remains on the side wall portion after ashing.
Thus, the memory element 5 in which the pattern is formed on the metal oxide layer 14 as shown in FIG. 1E is obtained.
　５……メモリ素子
　１３……下部電極
　１４……金属酸化物層
　１８……上部電極
　２０……マスク
　３０……エッチング室
　３１……ガス供給部
　４２……プラズマ生成部
　５０……メモリ素子の製造装置
　５１……搬送室
　５２……洗浄室
  5 ... Memory element 13 ... Lower electrode 14 ... Metal oxide layer 18 ... Upper electrode 20 ... Mask 30 ... Etching chamber 31 ... Gas supply part 42 ... Plasma generation part 50 ... Manufacturing of memory element Equipment 51 …… Transport chamber 52 …… Cleaning chamber

Claims (6)

  1. 　上部電極と下部電極との間に金属酸化物層が配置され、前記上部電極と前記下部電極との間に直流電圧を印加すると、前記直流電圧の極性に応じて高抵抗状態と低抵抗状態のいずれか一方の状態になることにより情報を記憶することができ、膜厚方向にセンス電流を流し、抵抗値を測定して前記高抵抗状態と前記低抵抗状態とを判別することにより情報を読み出すことができるメモリ素子の製造装置であって、
    　エッチングガスを供給するガス供給部と、前記エッチングガスをプラズマ化するプラズマ生成部とを有するエッチング室と、
    　前記エッチング室に接続して配置された洗浄室と、
    　処理対象物を前記エッチング室から前記洗浄室に搬送する搬送室と、
    　を有し、
    　前記エッチング室は、基板上に前記下部電極と前記金属酸化物層と前記上部電極とがこの順に積層された処理対象物が搬入されると、化学構造中に塩素を含むエッチングガスをプラズマ化し、前記金属酸化物層をエッチングして、前記下部電極を露出させるように構成され、
    　前記洗浄室は、前記処理対象物のエッチングした表面に洗浄液を接触させるように構成されたメモリ素子の製造装置。     When a metal oxide layer is disposed between the upper electrode and the lower electrode, and a DC voltage is applied between the upper electrode and the lower electrode, the high resistance state and the low resistance state are changed according to the polarity of the DC voltage. Information can be stored by entering either state, and information is read by flowing a sense current in the film thickness direction and measuring the resistance value to distinguish between the high resistance state and the low resistance state An apparatus for manufacturing a memory device,
    An etching chamber having a gas supply section for supplying an etching gas, and a plasma generation section for converting the etching gas into a plasma;
    A cleaning chamber disposed in connection with the etching chamber;
    A transfer chamber for transferring a processing object from the etching chamber to the cleaning chamber;
    Have
    When the processing object in which the lower electrode, the metal oxide layer, and the upper electrode are stacked in this order is loaded on the substrate, the etching chamber converts the etching gas containing chlorine into plasma into plasma, Etching the metal oxide layer to expose the lower electrode;
    The apparatus for manufacturing a memory element, wherein the cleaning chamber is configured to bring a cleaning liquid into contact with an etched surface of the processing object.
  2. 　前記金属酸化物層は、Ａｌ2Ｏ3と、Ｙ2Ｏ5と、ＨｆＯ2と、ＴｉＯ2と、ＣｏＯと、ＮｉＯとからなる群より選択される一の金属酸化物からなる請求項１記載のメモリ素子の製造装置。 The metal oxide layer, Al 2 O 3, and Y 2 O 5, and HfO 2, and TiO 2, and CoO, consists of a metal oxide selected from the group consisting of NiO claim 1, wherein Memory device manufacturing apparatus.
  3. 　前記エッチングガスは、Ｃｌ2と、ＢＣｌ3と、ＳｉＣｌ4とからなる群より選択される一のガス又は二以上の混合ガスを含有する請求項１又は請求項２のいずれか１項記載のメモリ素子の製造装置。 3. The memory according to claim 1, wherein the etching gas contains one gas or two or more mixed gases selected from the group consisting of Cl 2 , BCl 3 , and SiCl 4. Device manufacturing equipment.
  4. 　上部電極と下部電極との間に金属酸化物が配置され、前記上部電極と前記下部電極との間に直流電圧を印加すると、前記直流電圧の極性に応じて高抵抗状態と低抵抗状態のいずれか一方の状態になることにより情報を記録することができ、膜厚方向にセンス電流を流し、抵抗値を測定して高抵抗状態と低抵抗状態とを判別することにより情報を読み出すことができるメモリ素子の製造装置であって、
    　基板上に前記下部電極と前記金属酸化物層と前記上部電極とがこの順に積層された処理対象物上に、前記上部電極が露出するような開口を有する所定のパターンのマスクを配置するマスク工程と、
    　化学構造中に塩素を含むエッチングガスをプラズマ化し、前記上部電極と前記金属酸化物層をエッチングして、前記下部電極を露出させるエッチング工程と、
    　前記処理対象物のエッチングした表面に洗浄液を接触させ、前記エッチング工程で生成された金属の塩化物を除去する洗浄工程とを有するメモリ素子の製造方法。     When a metal oxide is disposed between the upper electrode and the lower electrode and a DC voltage is applied between the upper electrode and the lower electrode, either a high resistance state or a low resistance state is selected depending on the polarity of the DC voltage. Information can be recorded by entering one of the states, and information can be read by flowing a sense current in the film thickness direction and measuring the resistance value to distinguish between a high resistance state and a low resistance state. A device for manufacturing a memory element,
    A mask process of disposing a mask having a predetermined pattern having an opening exposing the upper electrode on a processing object in which the lower electrode, the metal oxide layer, and the upper electrode are laminated in this order on a substrate. When,
    An etching process that plasmaizes an etching gas containing chlorine in a chemical structure, etches the upper electrode and the metal oxide layer, and exposes the lower electrode;
    A method of manufacturing a memory device, comprising: a cleaning step of bringing a cleaning liquid into contact with an etched surface of the object to be processed to remove a metal chloride generated in the etching step.
  5. 　前記金属酸化物層は、Ａｌ2Ｏ3と、Ｙ2Ｏ5と、ＨｆＯ2と、ＴｉＯ2と、ＣｏＯと、ＮｉＯとからなる群より選択される一の金属酸化物からなる請求項４記載のメモリ素子の製造方法。 The metal oxide layer is made of one metal oxide selected from the group consisting of Al 2 O 3 , Y 2 O 5 , HfO 2 , TiO 2 , CoO, and NiO. Method for manufacturing the memory element.
  6. 　前記金属酸化物層のエッチングに用いる前記エッチングガスは、Ｃｌ2と、ＢＣｌ3と、ＳｉＣｌ4とからなる群より選択される一のガス又は二以上の混合ガスを含有する請求項４又は請求項５のいずれか１項記載のメモリ素子の製造方法。
          The etching gas used for etching of the metal oxide layer, and Cl 2, and BCl 3, claim 4 or claim containing one gas or more of the mixed gas selected from the group consisting of SiCl 4 Metropolitan 6. A method for manufacturing a memory element according to any one of items 5 to 6.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022039950A1 (en) * 2020-08-21 2022-02-24 Tokyo Electron Limited Methods for resistive ram (reram) performance stabilization via dry etch clean treatment
WO2023067786A1 (en) * 2021-10-22 2023-04-27 株式会社日立ハイテク Plasma processing method

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102692978B1 (en) 2017-12-14 2024-08-06 어플라이드 머티어리얼스, 인코포레이티드 Methods of etching metal oxides with less etch residue
CN111653477A (en) * 2020-05-09 2020-09-11 中国科学院微电子研究所 Method and system for forming yttrium oxide film

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001347236A (en) * 2000-06-06 2001-12-18 Anelva Corp Substrate treatment apparatus
JP2010226058A (en) * 2009-03-25 2010-10-07 Toshiba Corp Non-volatile storage device and manufacturing method of the same
JP2010232213A (en) * 2009-03-25 2010-10-14 Toshiba Corp Method for manufacturing nonvolatile memory device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001347236A (en) * 2000-06-06 2001-12-18 Anelva Corp Substrate treatment apparatus
JP2010226058A (en) * 2009-03-25 2010-10-07 Toshiba Corp Non-volatile storage device and manufacturing method of the same
JP2010232213A (en) * 2009-03-25 2010-10-14 Toshiba Corp Method for manufacturing nonvolatile memory device

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