WO2012070551A1 - Device for manufacturing and method for manufacturing memory element - Google Patents

Device for manufacturing and method for manufacturing memory element Download PDF

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Publication number
WO2012070551A1
WO2012070551A1 PCT/JP2011/076851 JP2011076851W WO2012070551A1 WO 2012070551 A1 WO2012070551 A1 WO 2012070551A1 JP 2011076851 W JP2011076851 W JP 2011076851W WO 2012070551 A1 WO2012070551 A1 WO 2012070551A1
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etching
metal oxide
manufacturing
oxide layer
chamber
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PCT/JP2011/076851
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French (fr)
Japanese (ja)
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善明 吉田
小風 豊
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株式会社アルバック
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Priority to JP2012528170A priority Critical patent/JP5437492B2/en
Publication of WO2012070551A1 publication Critical patent/WO2012070551A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/0206Cleaning during device manufacture during, before or after processing of insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/101Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011Manufacture or treatment of multistable switching devices
    • H10N70/021Formation of the switching material, e.g. layer deposition
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011Manufacture or treatment of multistable switching devices
    • H10N70/061Patterning of the switching material
    • H10N70/063Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20Multistable switching devices, e.g. memristors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801Constructional details of multistable switching devices
    • H10N70/881Switching materials
    • H10N70/883Oxides or nitrides
    • H10N70/8833Binary metal oxides, e.g. TaOx

Definitions

  • the present invention relates to a memory device manufacturing apparatus and manufacturing method, and more particularly to a memory device manufacturing apparatus and manufacturing method having a transition metal oxide layer.
  • ReRAM Resistance Random Access Memory
  • the single cell structure of ReRAM is a simple capacitor structure in which a transition metal oxide exhibiting an insulator or semiconductor electrical property is sandwiched between metal electrodes, and can generate a huge resistance change by applying a pulse voltage. it can.
  • the ReRAM has a feature that a minimum cell area of 4F 2 (F is a minimum processing dimension in a manufacturing process of a memory cell, so-called design rule) is possible, and multi-value can be made.
  • F is a minimum processing dimension in a manufacturing process of a memory cell, so-called design rule
  • the bit cost can be reduced by high integration, and it is expected as a universal memory that replaces and integrates DRAM and Flash memory.
  • Transition metals such as Co and Ni are used for the resistance change film used in ReRAM, and the vapor pressure of fluorides and chlorides of these materials is low, which is known as a difficult etching material.
  • the etching product easily adheres to the side wall of the element pattern, and in the prior art, this product remains and becomes dust and contaminates the apparatus in the next process or the next process. There is a risk of disconnection or insulation failure in the wiring formation process.
  • FIGS. 2A to 2C a conventional metal oxide pattern forming method will be described.
  • a processing target in which an insulating layer 112, a lower electrode 113, a metal oxide layer 114, and first and second metal layers 116 and 117 are laminated in this order on a substrate 111.
  • a mask 120 having a predetermined pattern is formed on the second metal layer 117 of the object.
  • the first and second metal layers 116 and 117 constitute the upper electrode 118.
  • the object to be processed is transferred to an etching chamber and etched with a chlorine-based gas such as Cl 2 or BCl 3 until the lower electrode 113 is exposed.
  • the etching product 125 adheres to the etched side wall portion of the object to be processed.
  • the object to be processed is carried into an ashing chamber while maintaining a vacuum atmosphere, and plasma ashing is performed using O 2 gas to remove the mask 120. After ashing, a residue 126 is seen on the side wall of the object to be processed. The residue 126 cannot be removed in the subsequent steps and remains.
  • the present invention was created to solve the above-mentioned disadvantages of the prior art, and its purpose is to remove etching products generated in reactive ion etching to form a pattern on a metal oxide satisfactorily. I will provide a.
  • the inventors examined the residue and found that the residue was an oxide of Co or Ni. Since the etching product is a chloride of Co or Ni, it is considered that the oxide is formed by oxidizing the chloride generated during the etching during the ashing. The oxide could not be removed in a later step, but the chloride could be dissolved by washing with water, thus completing the present invention.
  • a metal oxide layer is disposed between the upper electrode and the lower electrode and a DC voltage is applied between the upper electrode and the lower electrode, the DC voltage is reduced.
  • information can be stored by entering one of a high resistance state and a low resistance state, a sense current is passed in the film thickness direction, a resistance value is measured, and the high resistance state and the An apparatus for manufacturing a memory element capable of reading information by determining a low resistance state, an etching chamber having a gas supply unit for supplying an etching gas, and a plasma generating unit for converting the etching gas into a plasma
  • the memory device manufacturing apparatus is configured to expose the lower electrode by etching, and the cleaning chamber is configured to contact a cleaning liquid with the etched surface of the processing object.
  • the present invention is a memory device manufacturing apparatus, wherein the metal oxide layer is selected from the group consisting of Al 2 O 3 , Y 2 O 5 , HfO 2 , TiO 2 , CoO, and NiO. This is an apparatus for manufacturing a memory element made of one metal oxide.
  • the present invention is an apparatus for manufacturing a memory element, wherein the etching gas is one of a gas selected from the group consisting of Cl 2 , BCl 3 , and SiCl 4 , or a mixed gas of two or more. It is a manufacturing device.
  • the present invention when a metal oxide is disposed between the upper electrode and the lower electrode, and a DC voltage is applied between the upper electrode and the lower electrode, a high resistance state and a low resistance are generated according to the polarity of the DC voltage.
  • Information can be recorded by entering one of the resistance states, and a sense current is passed in the film thickness direction, and the resistance value is measured to discriminate between the high resistance state and the low resistance state.
  • An apparatus for manufacturing a memory element that can be read wherein the upper electrode is exposed on a processing object in which the lower electrode, the metal oxide layer, and the upper electrode are stacked in this order on a substrate.
  • a cleaning liquid is brought into contact with the etched surface of the processing object, a method of manufacturing a memory device having a cleaning process for removing metal chlorides generated in the etching step.
  • the present invention is a method of manufacturing a memory device, wherein the metal oxide layer is selected from the group consisting of Al 2 O 3 , Y 2 O 5 , HfO 2 , TiO 2 , CoO, and NiO.
  • 1 is a method of manufacturing a memory element made of one metal oxide.
  • the present invention is a method of manufacturing a memory device, wherein the etching gas used for etching the metal oxide layer is one gas selected from the group consisting of Cl 2 , BCl 3 , and SiCl 4 , or two or more. Is a method for manufacturing a memory element containing a mixed gas of
  • the etching product can be removed, the yield of ReRAM manufacturing can be improved without contaminating the devices after the next step or causing disconnection or insulation failure in the next wiring formation step. Since the transition metal oxide can be stably patterned by reactive ion etching, high integration of ReRAM becomes possible.
  • FIG. 1E shows the structure of the memory element 5 formed according to the present invention
  • FIG. 4 shows a schematic diagram of the memory device 1 having a plurality of memory elements 5.
  • the storage device 1 includes a storage unit 6 and a control unit 7.
  • a plurality of memory elements 5 are arranged in the storage unit 6.
  • the memory element 5 has a lower electrode 13, a metal oxide layer 14, and first and second metal layers 16 and 17, and the layers 13, 14, 16, and 17 are insulated. They are stacked on the substrate 11 in this order via the layer 12.
  • the first and second metal layers 16 and 17 constitute the upper electrode 18. That is, the metal oxide layer 14 is disposed between the upper electrode 18 and the lower electrode 13.
  • the substrate 11 is made of a semiconductor or the like, and Si is used here, and the insulating layer 12 is made of an insulator, and here is SiO 2 .
  • the lower electrode 13 and the first and second metal layers 16 and 17 are made of a conductive material.
  • a TiN film is used for the lower electrode 13 and the second metal layer 17, and the first metal layer 16 is an Al film.
  • the metal oxide layer 14 is made of one metal oxide selected from the group consisting of Al 2 O 3 , Y 2 O 5 , HfO 2 , TiO 2 , CoO, and NiO.
  • the memory element 5 When a DC voltage is applied between the upper electrode 18 and the lower electrode 13, the memory element 5 is either in a high resistance state or a low resistance state having a resistance value lower than that in the high resistance state depending on the polarity of the DC voltage. It comes to be in one state.
  • the memory element 5 when a positive pulse voltage is applied with the upper electrode 18 as an anode and the lower electrode 13 as a cathode, the memory element 5 is in a low resistance state, and a negative pulse voltage is applied.
  • it is configured to be in a high resistance state, it is configured to be in a high resistance state when a pulsed positive voltage is applied, and to be in a low resistance state when a pulsed negative voltage is applied. May be.
  • first and second connection terminals are electrically connected to the second metal layer 17 and the lower electrode 13, respectively.
  • Reference numerals 71a and 71b in FIG. 4 indicate first and second connection terminals.
  • the one memory element 5 When a DC voltage is applied from the control unit 7 to the first and second connection terminals 71a and 71b of the one memory element 5, the one memory element 5 has a high resistance state and a low resistance depending on the polarity of the DC voltage. One of the resistance states is entered. By associating the low resistance state and the high resistance state with 1 and 0, respectively, 1/0 information can be recorded.
  • a sense current is passed from the control unit 7 in the film thickness direction of the one memory element 5 via the first and second connection terminals 71a and 71b, and the resistance value of the one memory element 5 is measured. By discriminating between the high resistance state and the low resistance state, the information stored in the one memory element 5 can be read out.
  • FIG. 3 shows a memory device manufacturing apparatus 50 according to the present invention.
  • the memory element manufacturing apparatus 50 includes an etching chamber 30 that forms a predetermined pattern on a processing target, a cleaning chamber 52 that removes etching products, and a transfer chamber that transfers the processing target from the etching chamber 30 to the cleaning chamber 52. 51.
  • the etching chamber 30 includes a vacuum chamber 39, a gas supply unit 31 that supplies an etching gas into the vacuum chamber 39, a plasma generation unit 42 that converts the supplied etching gas into plasma, and a vacuum that evacuates the vacuum chamber 39.
  • positioned in the vacuum layer 39 are provided.
  • a stage 36 for placing a processing object is provided inside the vacuum chamber 39.
  • the temperature control unit 38 is connected to the stage 36, and can control the temperature of the processing object placed on the stage 36 by flowing a temperature-controlled heat medium through a cooling pipe (not shown) provided on the stage 36, for example. Has been.
  • the plasma generation unit 42 includes an RF antenna 33, a plasma matching box 37a, and a plasma high-frequency power source 34.
  • the RF antenna 33 is installed above the vacuum chamber 39 and is electrically connected to the plasma high frequency power supply 34 via the plasma matching box 37a.
  • a high frequency voltage is applied from the plasma high frequency power supply 34 to the RF antenna 33,
  • the etching gas supplied into the vacuum chamber 39 can be converted into plasma by inductive coupling.
  • a high frequency power supply 35 for bias is electrically connected to the stage 36 via a bias matching box 37b.
  • a high frequency voltage is applied to the stage 36 from the high frequency power supply 35 for bias, an electric field is formed on the stage 36.
  • ions in the plasma are drawn toward the stage 36 and collide with the object to be processed, so that the object to be processed can be anisotropically etched.
  • the gas supply unit 31 is installed outside the vacuum chamber 39 and is connected to the inside of the vacuum chamber 39 so that an etching gas can be supplied into the vacuum chamber 39.
  • the evacuation unit 32 is installed outside the vacuum chamber 39 and connected to the inside of the vacuum chamber 39 so that the inside of the vacuum chamber 39 can be evacuated.
  • the transfer chamber 51 is hermetically connected to the vacuum chamber 39 of the etching chamber 30 via the first gate valve 55a, and the cleaning chamber 52 is hermetically connected to the transfer chamber 51 via the second gate valve 55b. Yes.
  • the transfer chamber 51 has an evacuation unit (not shown), and is configured so that the transfer chamber 51 can be evacuated while the first and second gate valves 55a and 55b are closed.
  • the first and second gate valves 55a and 55b are closed, and the inside of the vacuum chamber 39 and the transfer chamber 51 of the etching chamber 30 are evacuated in advance to maintain a vacuum atmosphere. Further, an inert gas not containing oxygen is introduced into the cleaning chamber 52 to keep the atmospheric pressure.
  • FIG. 1A a processing target in which an insulating layer 12, a lower electrode 13, a metal oxide layer 14, and first and second metal layers 16 and 17 are stacked in this order on a substrate 11.
  • a photoresist is applied on the second metal layer 17, a predetermined pattern is exposed and developed, and a mask 20 having an opening is formed.
  • the second metal layer 17 is exposed on the bottom surface of the opening of the mask 20.
  • an imprint resist is applied onto the second metal layer 17 and an original plate having irregularities of a predetermined pattern is pressed to form a mask 20 having an opening, and the second metal layer 17 is formed on the bottom surface of the opening. It may be exposed.
  • the object to be processed 10 is carried into the vacuum chamber 39 of the etching chamber 30 while maintaining the vacuum atmosphere with reference to FIG. 36.
  • the temperature control unit 38 is operated, a temperature-controlled heat medium is passed through a cooling pipe (not shown) of the stage 36, and the temperature of the processing object 10 during etching is maintained in the range of 20 ° C to 80 ° C.
  • a first etching gas is supplied from the gas supply unit 31, and the inside of the vacuum chamber 39 is maintained at a pressure of 0.1 Pa to 2.0 Pa.
  • a gas containing chlorine in the chemical structure is used as the first etching gas, for example, a gas containing one gas or a mixed gas of two or more selected from the group consisting of Cl 2 , BCl 3 , and SiCl 4. is there.
  • a rare gas He, Ne, Ar, Kr, Xe
  • the high frequency power supply for plasma 34 is activated, an alternating current is passed through the RF antenna 33, radio waves are emitted from the RF antenna 33 into the vacuum chamber 39, the first etching gas is excited and turned into plasma, and chlorine ions and chlorine radicals are produced. And so on.
  • the bias high-frequency power source 35 is activated, a bias voltage is applied to the object 10 to be processed, and the generated chlorine ions are incident on the object 10 to perform an anisotropic etching process.
  • the supply of the second etching gas from the gas supply unit 31 is started.
  • the inside of the vacuum chamber 39 is maintained at a pressure of 0.1 Pa to 10 Pa according to the selection ratio with the resist (mask 20).
  • a gas containing chlorine to the composition in the chemical structure in the second etching gas for example, Cl 2, and BCl 3
  • the gas containing one gas or more of the mixed gas selected from the group of SiCl 4 It is.
  • a rare gas He, Ne, Ar, Kr, Xe
  • a rare gas He, Ne, Ar, Kr, Xe
  • the high frequency power source for plasma 34 and the high frequency power source for bias 35 are operated, and the exposed metal oxide layer 14 is reacted with the second etching gas by chlorine ions in the plasma to generate a chloride gas. Then, anisotropic etching is performed by removing chloride gas by evacuation.
  • an etching product 25 made of a metal chloride contained in the metal oxide layer 14 adheres and remains on the etched side wall portion of the processing object 10. This is because the metal chloride contained in the metal oxide layer 14 generally has a high melting point and boiling point and a low vapor pressure at the temperature during etching.
  • a transfer robot 65 is provided in the transfer chamber 51. After the transfer chamber 51 is evacuated and the pressure in the vacuum chamber 39 decreases, the first gate valve 55a is opened to move the processing object 10 from the vacuum chamber 39 into the transfer chamber 51, and One gate valve 55a is closed. Next, an inert gas not containing oxygen is introduced into the transfer chamber 51 to raise the pressure in the transfer chamber 51 to atmospheric pressure.
  • a cleaning stage 61 on which a processing target can be placed and a shower nozzle 62 for injecting a cleaning liquid onto the processing target placed on the cleaning stage 61 are arranged.
  • the second gate valve 55 b is opened, the processing object 10 is carried into the cleaning chamber 52 from the transfer chamber 51, and placed on the cleaning stage 61.
  • a cleaning liquid is sprayed from the shower nozzle 62 onto the etched surface of the processing object 10, and the etching surface of the processing object 10 is brought into contact with the cleaning liquid to perform a cleaning process.
  • the shower method is described as the cleaning method, but the present invention is not limited to this, and the cleaning process is performed by bringing the etched surface of the processing object 10 into contact with the cleaning liquid by another cleaning method such as an ultrasonic dip method. May be.
  • the cleaning liquid one kind or a mixture of two or more kinds of water such as pure water, ion exchange water, micro / nano bubble water, and organic solvents such as ethanol, methanol, acetone, isopropyl alcohol, and ethyl ether are used.
  • the etching product 25 is, for example, a water-soluble and alcohol-soluble metal chloride such as CoCl 2 or NiCl 2. As shown in FIG. 1D, the etching product 25 is dissolved in the cleaning liquid by the cleaning process using the cleaning liquid. And removed.
  • the time required from the time when the processing object 10 is brought into contact with the atmosphere in the transfer chamber 51 to the start of the cleaning in the cleaning chamber 52 is within 5 minutes. This is because when the object to be treated 10 is put into the atmosphere, chlorine remaining on the surface of the object to be treated 10 reacts with moisture in the atmosphere to form HCl. This is because if a material (for example, Al) that is corroded by HCl is used for the object 10 to be processed, corrosion (corrosion) may occur there.
  • a material for example, Al
  • the object to be processed is dried by centrifugal force drying or high-temperature gas blowing, and then the object to be processed is carried into an ashing chamber (not shown), and plasma ashing is performed using O 2 gas.
  • O 2 gas oxygen ions and oxygen radicals generated from the excited O 2 gas oxidize and decompose the mask 20 to remove the mask 20.
  • the etching product 25 on the side wall portion of the object to be processed is removed before ashing, and no oxide residue remains on the side wall portion after ashing.
  • the memory element 5 in which the pattern is formed on the metal oxide layer 14 as shown in FIG. 1E is obtained.

Abstract

Provided are a device for manufacturing and a method for manufacturing a memory element having a metal oxide layer with etching resistance. Anisotropic etching is performed by the metal oxide layer (14) reacting with etching gas containing chlorine in the chemical structure thereof and generating a chloride gas, which is eliminated by vacuum exhausting. Etching products (25) adhere to the side wall parts that have been etched and remain because the vapor pressure is low at the temperature during etching. These etching products (25) are water soluble; therefore, directly after etching, the etched surfaces are brought into contact with a washing fluid and the etching products (25) are eliminated by dissolution. Thus, a memory element (5) for which a pattern is formed by the metal oxide layer (14) can be obtained.

Description

メモリ素子の製造装置及び製造方法Memory device manufacturing apparatus and manufacturing method
 本発明は、メモリ素子の製造装置及び製造方法に関し、特に、遷移金属酸化物層を有するメモリ素子の製造装置及び製造方法に関する。 The present invention relates to a memory device manufacturing apparatus and manufacturing method, and more particularly to a memory device manufacturing apparatus and manufacturing method having a transition metal oxide layer.
 近年、遷移金属酸化物を用いた新しい不揮発性メモリとして抵抗変化メモリ(Resistance Random Access Memory、ReRAM)が注目されている。ReRAMの単一セル構造は、絶縁体または半導体的な電気特性を示す遷移金属酸化物を金属電極で挟んだ単純キャパシタ構造であり、パルス電圧を印加することにより巨大な抵抗変化を発生させることができる。 In recent years, a resistance change memory (Resistance Random Access Memory, ReRAM) has attracted attention as a new nonvolatile memory using a transition metal oxide. The single cell structure of ReRAM is a simple capacitor structure in which a transition metal oxide exhibiting an insulator or semiconductor electrical property is sandwiched between metal electrodes, and can generate a huge resistance change by applying a pulse voltage. it can.
 ReRAMは、4F2(Fはメモリセルの製造プロセスにおける最小加工寸法、いわゆる設計ルール)の最小セル面積が可能であり、また多値化が可能である等の特徴をもつ。またReRAM製造プロセスはCMOSプロセスとの整合性が良いことから、高集積化によるビットコスト低減が可能であり、DRAMやFlashメモリを代替・統合するユニバーサルメモリとして期待されている。 The ReRAM has a feature that a minimum cell area of 4F 2 (F is a minimum processing dimension in a manufacturing process of a memory cell, so-called design rule) is possible, and multi-value can be made. In addition, since the ReRAM manufacturing process has good consistency with the CMOS process, the bit cost can be reduced by high integration, and it is expected as a universal memory that replaces and integrates DRAM and Flash memory.
 メモリの大容量化のためには微細なメモリセルを制御性よく加工する必要があり、またCMOSプロセスとの親和性の観点から、半導体分野で広く用いられている反応性イオンエッチング(Reactive Ion Etching、RIE)による加工プロセスの開発が求められている。 In order to increase the memory capacity, it is necessary to process fine memory cells with good controllability, and from the viewpoint of compatibility with CMOS processes, reactive ion etching (Reactive Ion Etching) widely used in the semiconductor field , RIE) is required to develop a machining process.
 ReRAMで使われている抵抗変化膜にはCoやNi等の遷移金属が用いられており、これらの材料のフッ化物や塩化物の蒸気圧は低く、難エッチング材料として知られている。このような材料をエッチングした場合、エッチング生成物が素子パターンの側壁に付着しやすく、従来技術ではこの生成物が残留し、ゴミとなって次工程以降の装置を汚染したり、次工程である配線形成工程において断線もしくは絶縁不良の原因となる虞があった。 Transition metals such as Co and Ni are used for the resistance change film used in ReRAM, and the vapor pressure of fluorides and chlorides of these materials is low, which is known as a difficult etching material. When such a material is etched, the etching product easily adheres to the side wall of the element pattern, and in the prior art, this product remains and becomes dust and contaminates the apparatus in the next process or the next process. There is a risk of disconnection or insulation failure in the wiring formation process.
 図2(a)~(c)を参照し、従来技術による金属酸化物のパターン形成方法を説明する。
 まず、図2(a)に示すように、基板111上に絶縁層112と下部電極113と金属酸化物層114と第一、第二の金属層116、117とがこの順に積層された処理対象物の第二の金属層117上に、所定のパターンのマスク120を形成する。ここでは第一、第二の金属層116、117が上部電極118を構成している。
With reference to FIGS. 2A to 2C, a conventional metal oxide pattern forming method will be described.
First, as shown in FIG. 2A, a processing target in which an insulating layer 112, a lower electrode 113, a metal oxide layer 114, and first and second metal layers 116 and 117 are laminated in this order on a substrate 111. A mask 120 having a predetermined pattern is formed on the second metal layer 117 of the object. Here, the first and second metal layers 116 and 117 constitute the upper electrode 118.
 次いで図2(b)に示すように、この処理対象物をエッチング室に搬送し、Cl2やBCl3等の塩素系ガスにて下部電極113が露出するまでエッチングする。このとき処理対象物のエッチングされた側壁部分にはエッチング生成物125が付着する。
 次いで図2(c)に示すように、処理対象物を真空雰囲気に維持したまま、アッシング室に搬入し、O2ガスを用いてプラズマアッシングを行い、マスク120を除去する。アッシング後には処理対象物の側壁部分に残留物126が見られる。残留物126は後工程以降で除去できず、残留することになる。
Next, as shown in FIG. 2B, the object to be processed is transferred to an etching chamber and etched with a chlorine-based gas such as Cl 2 or BCl 3 until the lower electrode 113 is exposed. At this time, the etching product 125 adheres to the etched side wall portion of the object to be processed.
Next, as shown in FIG. 2C, the object to be processed is carried into an ashing chamber while maintaining a vacuum atmosphere, and plasma ashing is performed using O 2 gas to remove the mask 120. After ashing, a residue 126 is seen on the side wall of the object to be processed. The residue 126 cannot be removed in the subsequent steps and remains.
再公表特許2004/008535号公報Republished Patent 2004/008535
 本発明は上記従来技術の不都合を解決するために創作されたものであり、その目的は、反応性イオンエッチングにおいて発生するエッチング生成物を除去して、金属酸化物にパターンを良好に形成する技術を提供する。 The present invention was created to solve the above-mentioned disadvantages of the prior art, and its purpose is to remove etching products generated in reactive ion etching to form a pattern on a metal oxide satisfactorily. I will provide a.
 本発明者らは残留物を検討したところ、残留物はCoやNiの酸化物であることが分かった。エッチング生成物がCoやNiの塩化物であることから、酸化物はエッチングの際に生成された塩化物がアッシングの際に酸化されて形成されると考えられる。酸化物は後工程で除去できないが、塩化物は水洗することで溶解できることから本発明を完成させた。 The inventors examined the residue and found that the residue was an oxide of Co or Ni. Since the etching product is a chloride of Co or Ni, it is considered that the oxide is formed by oxidizing the chloride generated during the etching during the ashing. The oxide could not be removed in a later step, but the chloride could be dissolved by washing with water, thus completing the present invention.
 係る知見に基づいて成された本発明は、上部電極と下部電極との間に金属酸化物層が配置され、前記上部電極と前記下部電極との間に直流電圧を印加すると、前記直流電圧の極性に応じて高抵抗状態と低抵抗状態のいずれか一方の状態になることにより情報を記憶することができ、膜厚方向にセンス電流を流し、抵抗値を測定して前記高抵抗状態と前記低抵抗状態とを判別することにより情報を読み出すことができるメモリ素子の製造装置であって、エッチングガスを供給するガス供給部と、前記エッチングガスをプラズマ化するプラズマ生成部とを有するエッチング室と、前記エッチング室に接続して配置された洗浄室と、処理対象物を前記エッチング室から前記洗浄室に搬送する搬送室と、を有し、前記エッチング室は、基板上に前記下部電極と前記金属酸化物層と前記上部電極とがこの順に積層された処理対象物が搬入されると、化学構造中に塩素を含むエッチングガスをプラズマ化し、前記上部電極と前記金属酸化物層をエッチングして、前記下部電極を露出させるように構成され、前記洗浄室は、前記処理対象物のエッチングした表面に洗浄液を接触させるように構成されたメモリ素子の製造装置である。
 本発明はメモリ素子の製造装置であって、前記金属酸化物層は、Al23と、Y25と、HfO2と、TiO2と、CoOと、NiOとからなる群より選択される一の金属酸化物からなるメモリ素子の製造装置である。
 本発明はメモリ素子の製造装置であって、前記エッチングガスは、Cl2と、BCl3と、SiCl4とからなる群より選択される一のガス又は二以上の混合ガスを含有するメモリ素子の製造装置である。
 本発明は、上部電極と下部電極との間に金属酸化物が配置され、前記上部電極と前記下部電極との間に直流電圧を印加すると、前記直流電圧の極性に応じて高抵抗状態と低抵抗状態のいずれか一方の状態になることにより情報を記録することができ、膜厚方向にセンス電流を流し、抵抗値を測定して高抵抗状態と低抵抗状態とを判別することにより情報を読み出すことができるメモリ素子の製造装置であって、基板上に前記下部電極と前記金属酸化物層と前記上部電極とがこの順に積層された処理対象物上に、前記上部電極が露出するような開口を有する所定のパターンのマスクを配置するマスク工程と、化学構造中に塩素を含むエッチングガスをプラズマ化し、前記上部電極と前記金属酸化物層をエッチングして、前記下部電極を露出させるエッチング工程と、前記処理対象物のエッチングした表面に洗浄液を接触させ、前記エッチング工程で生成された金属の塩化物を除去する洗浄工程とを有するメモリ素子の製造方法である。
 本発明はメモリ素子の製造方法であって、前記金属酸化物層は、Al23と、Y25と、HfO2と、TiO2と、CoOと、NiOとからなる群より選択される一の金属酸化物からなるメモリ素子の製造方法である。
 本発明はメモリ素子の製造方法であって、前記金属酸化物層のエッチングに用いる前記エッチングガスは、Cl2と、BCl3と、SiCl4とからなる群より選択される一のガス又は二以上の混合ガスを含有するメモリ素子の製造方法である。
In the present invention based on such knowledge, when a metal oxide layer is disposed between the upper electrode and the lower electrode and a DC voltage is applied between the upper electrode and the lower electrode, the DC voltage is reduced. Depending on the polarity, information can be stored by entering one of a high resistance state and a low resistance state, a sense current is passed in the film thickness direction, a resistance value is measured, and the high resistance state and the An apparatus for manufacturing a memory element capable of reading information by determining a low resistance state, an etching chamber having a gas supply unit for supplying an etching gas, and a plasma generating unit for converting the etching gas into a plasma A cleaning chamber connected to the etching chamber, and a transfer chamber for transferring an object to be processed from the etching chamber to the cleaning chamber, the etching chamber on the substrate. When a processing object in which an electrode, the metal oxide layer, and the upper electrode are stacked in this order is carried in, an etching gas containing chlorine in the chemical structure is turned into plasma, and the upper electrode and the metal oxide layer are The memory device manufacturing apparatus is configured to expose the lower electrode by etching, and the cleaning chamber is configured to contact a cleaning liquid with the etched surface of the processing object.
The present invention is a memory device manufacturing apparatus, wherein the metal oxide layer is selected from the group consisting of Al 2 O 3 , Y 2 O 5 , HfO 2 , TiO 2 , CoO, and NiO. This is an apparatus for manufacturing a memory element made of one metal oxide.
The present invention is an apparatus for manufacturing a memory element, wherein the etching gas is one of a gas selected from the group consisting of Cl 2 , BCl 3 , and SiCl 4 , or a mixed gas of two or more. It is a manufacturing device.
According to the present invention, when a metal oxide is disposed between the upper electrode and the lower electrode, and a DC voltage is applied between the upper electrode and the lower electrode, a high resistance state and a low resistance are generated according to the polarity of the DC voltage. Information can be recorded by entering one of the resistance states, and a sense current is passed in the film thickness direction, and the resistance value is measured to discriminate between the high resistance state and the low resistance state. An apparatus for manufacturing a memory element that can be read, wherein the upper electrode is exposed on a processing object in which the lower electrode, the metal oxide layer, and the upper electrode are stacked in this order on a substrate. A mask process for disposing a mask having a predetermined pattern having an opening, and plasma etching of an etching gas containing chlorine in the chemical structure, etching the upper electrode and the metal oxide layer to expose the lower electrode And an etching step, a cleaning liquid is brought into contact with the etched surface of the processing object, a method of manufacturing a memory device having a cleaning process for removing metal chlorides generated in the etching step.
The present invention is a method of manufacturing a memory device, wherein the metal oxide layer is selected from the group consisting of Al 2 O 3 , Y 2 O 5 , HfO 2 , TiO 2 , CoO, and NiO. 1 is a method of manufacturing a memory element made of one metal oxide.
The present invention is a method of manufacturing a memory device, wherein the etching gas used for etching the metal oxide layer is one gas selected from the group consisting of Cl 2 , BCl 3 , and SiCl 4 , or two or more. Is a method for manufacturing a memory element containing a mixed gas of
 エッチング生成物を除去できるので、次工程以降の装置を汚染したり、次工程である配線形成工程において断線もしくは絶縁不良を起こしたりせず、ReRAM製造の歩留まりが向上する。
 遷移金属酸化物を反応性イオンエッチングで安定してパターン形成できるので、ReRAMの高集積化が可能となる。
Since the etching product can be removed, the yield of ReRAM manufacturing can be improved without contaminating the devices after the next step or causing disconnection or insulation failure in the next wiring formation step.
Since the transition metal oxide can be stably patterned by reactive ion etching, high integration of ReRAM becomes possible.
(a)~(e):本発明のメモリ素子の製造方法を説明する図(A)-(e): The figure explaining the manufacturing method of the memory element of this invention (a)~(c):従来技術による金属酸化物のパターン形成方法を説明する図(A)-(c): The figure explaining the metal oxide pattern formation method by a prior art 本発明のメモリ素子の製造装置の内部構成図The internal block diagram of the memory device manufacturing apparatus of this invention 本発明で形成されたメモリ素子を有する記憶装置の模式図Schematic diagram of a memory device having a memory element formed in the present invention
 図1(e)に本発明で形成されるメモリ素子5の構造を示し、図4にこのメモリ素子5を複数有する記憶装置1の模式図を示す。
 図4に示すように、記憶装置1は記憶部6と制御部7とを有している。記憶部6には複数のメモリ素子5が配置されている。
FIG. 1E shows the structure of the memory element 5 formed according to the present invention, and FIG. 4 shows a schematic diagram of the memory device 1 having a plurality of memory elements 5.
As illustrated in FIG. 4, the storage device 1 includes a storage unit 6 and a control unit 7. A plurality of memory elements 5 are arranged in the storage unit 6.
 図1(e)に示すように、メモリ素子5は下部電極13と金属酸化物層14と第一、第二の金属層16、17とを有し、各層13、14、16、17は絶縁層12を介して基板11上にこの順に積層されて配置されている。第一、第二の金属層16、17とが上部電極18を構成している。すなわち、上部電極18と下部電極13との間に金属酸化物層14が配置されている。 As shown in FIG. 1E, the memory element 5 has a lower electrode 13, a metal oxide layer 14, and first and second metal layers 16 and 17, and the layers 13, 14, 16, and 17 are insulated. They are stacked on the substrate 11 in this order via the layer 12. The first and second metal layers 16 and 17 constitute the upper electrode 18. That is, the metal oxide layer 14 is disposed between the upper electrode 18 and the lower electrode 13.
 基板11は半導体等から成り、ここではSiが用いられており、絶縁層12は絶縁物から成り、ここではSiO2である。また下部電極13と第一、第二の金属層16、17は導電性物質から成り、ここでは下部電極13と第二の金属層17にはTiN膜が用いられており、第一の金属層16にはAl膜が用いられている。
 金属酸化物層14は、Al23と、Y25と、HfO2と、TiO2と、CoOと、NiOとからなる群より選択される一の金属酸化物からなる。
The substrate 11 is made of a semiconductor or the like, and Si is used here, and the insulating layer 12 is made of an insulator, and here is SiO 2 . The lower electrode 13 and the first and second metal layers 16 and 17 are made of a conductive material. Here, a TiN film is used for the lower electrode 13 and the second metal layer 17, and the first metal layer 16 is an Al film.
The metal oxide layer 14 is made of one metal oxide selected from the group consisting of Al 2 O 3 , Y 2 O 5 , HfO 2 , TiO 2 , CoO, and NiO.
 上部電極18と下部電極13との間に直流電圧が印加されると、メモリ素子5は、直流電圧の極性に応じて高抵抗状態と、高抵抗状態より抵抗値の低い低抵抗状態のいずれか一方の状態になるようになっている。
 本実施例では、上部電極18を陽極とし、下部電極13を陰極として、パルス状の正電圧が印加されると、メモリ素子5は低抵抗状態になり、パルス状の負電圧が印加されると、高抵抗状態になるように構成されているが、パルス状の正電圧が印加されると、高抵抗状態になり、パルス状の負電圧が印加されると、低抵抗状態になるように構成されていてもよい。
When a DC voltage is applied between the upper electrode 18 and the lower electrode 13, the memory element 5 is either in a high resistance state or a low resistance state having a resistance value lower than that in the high resistance state depending on the polarity of the DC voltage. It comes to be in one state.
In this embodiment, when a positive pulse voltage is applied with the upper electrode 18 as an anode and the lower electrode 13 as a cathode, the memory element 5 is in a low resistance state, and a negative pulse voltage is applied. Although it is configured to be in a high resistance state, it is configured to be in a high resistance state when a pulsed positive voltage is applied, and to be in a low resistance state when a pulsed negative voltage is applied. May be.
 下部電極13の表面は部分的に露出され、第二の金属層17と下部電極13にはそれぞれ第一、第二の接続端子が電気的に接続されている。
 図4の符号71a、71bは第一、第二の接続端子を示している。
The surface of the lower electrode 13 is partially exposed, and first and second connection terminals are electrically connected to the second metal layer 17 and the lower electrode 13, respectively.
Reference numerals 71a and 71b in FIG. 4 indicate first and second connection terminals.
 制御部7から一のメモリ素子5の第一、第二の接続端子71a、71bの間に直流電圧を印加すると、直流電圧の極性に応じて、この一のメモリ素子5は高抵抗状態と低抵抗状態のいずれか一方の状態になる。低抵抗状態と高抵抗状態とをそれぞれ1と0に対応づけることにより、1/0の情報を記録することができる。 When a DC voltage is applied from the control unit 7 to the first and second connection terminals 71a and 71b of the one memory element 5, the one memory element 5 has a high resistance state and a low resistance depending on the polarity of the DC voltage. One of the resistance states is entered. By associating the low resistance state and the high resistance state with 1 and 0, respectively, 1/0 information can be recorded.
 また制御部7から第一、第二の接続端子71a、71bを介して一のメモリ素子5の膜厚方向にセンス電流を流し、この一のメモリ素子5の抵抗値を測定して、測定値を高抵抗状態と低抵抗状態に判別することにより、この一のメモリ素子5に記憶された情報を読み出すことができる。 In addition, a sense current is passed from the control unit 7 in the film thickness direction of the one memory element 5 via the first and second connection terminals 71a and 71b, and the resistance value of the one memory element 5 is measured. By discriminating between the high resistance state and the low resistance state, the information stored in the one memory element 5 can be read out.
 図3に本発明であるメモリ素子の製造装置50を示す。
 メモリ素子の製造装置50は、処理対象物に所定のパターンを形成するエッチング室30と、エッチング生成物を除去する洗浄室52と、処理対象物をエッチング室30から洗浄室52に搬送する搬送室51とを有している。
FIG. 3 shows a memory device manufacturing apparatus 50 according to the present invention.
The memory element manufacturing apparatus 50 includes an etching chamber 30 that forms a predetermined pattern on a processing target, a cleaning chamber 52 that removes etching products, and a transfer chamber that transfers the processing target from the etching chamber 30 to the cleaning chamber 52. 51.
 エッチング室30は、真空槽39と、真空槽39内にエッチングガスを供給するガス供給部31と、供給されたエッチングガスをプラズマ化するプラズマ生成部42と、真空槽39内を真空排気する真空排気部32と、真空層39内に配置された処理対象物の温度を制御する温度制御部38とを有している。 The etching chamber 30 includes a vacuum chamber 39, a gas supply unit 31 that supplies an etching gas into the vacuum chamber 39, a plasma generation unit 42 that converts the supplied etching gas into plasma, and a vacuum that evacuates the vacuum chamber 39. The exhaust part 32 and the temperature control part 38 which controls the temperature of the process target object arrange | positioned in the vacuum layer 39 are provided.
 真空槽39の内部には処理対象物を載置するためのステージ36が設けられている。
 温度制御部38はステージ36に接続され、例えばステージ36に設けられた不図示の冷却パイプに温度制御した熱媒体を流すことにより、ステージ36上に載置される処理対象物の温度を制御できるようにされている。
Inside the vacuum chamber 39, a stage 36 for placing a processing object is provided.
The temperature control unit 38 is connected to the stage 36, and can control the temperature of the processing object placed on the stage 36 by flowing a temperature-controlled heat medium through a cooling pipe (not shown) provided on the stage 36, for example. Has been.
 プラズマ生成部42はRFアンテナ33とプラズマ用マッチングボックス37aとプラズマ用高周波電源34とを有している。RFアンテナ33は真空槽39の上方に設置され、プラズマ用マッチングボックス37aを介してプラズマ用高周波電源34に電気的に接続されており、プラズマ用高周波電源34からRFアンテナ33に高周波電圧を印加すると、誘導結合により、真空槽39内に供給されたエッチングガスをプラズマ化できるようにされている。 The plasma generation unit 42 includes an RF antenna 33, a plasma matching box 37a, and a plasma high-frequency power source 34. The RF antenna 33 is installed above the vacuum chamber 39 and is electrically connected to the plasma high frequency power supply 34 via the plasma matching box 37a. When a high frequency voltage is applied from the plasma high frequency power supply 34 to the RF antenna 33, The etching gas supplied into the vacuum chamber 39 can be converted into plasma by inductive coupling.
 またステージ36にはバイアス用マッチングボックス37bを介してバイアス用高周波電源35が電気的に接続されており、バイアス用高周波電源35からステージ36に高周波電圧を印加すると、ステージ36上に電場を形成して、プラズマ中のイオンをステージ36側に引き込んで処理対象物に衝突させ、処理対象物を異方性エッチングできるようにされている。 A high frequency power supply 35 for bias is electrically connected to the stage 36 via a bias matching box 37b. When a high frequency voltage is applied to the stage 36 from the high frequency power supply 35 for bias, an electric field is formed on the stage 36. Thus, ions in the plasma are drawn toward the stage 36 and collide with the object to be processed, so that the object to be processed can be anisotropically etched.
 ガス供給部31は、真空槽39の外部に設置されて、真空槽39内部に接続され、真空槽39内にエッチングガスを供給可能にされている。
 真空排気部32は、真空槽39の外部に設置されて、真空槽39内部に接続され、真空槽39内を真空排気可能にされている。
The gas supply unit 31 is installed outside the vacuum chamber 39 and is connected to the inside of the vacuum chamber 39 so that an etching gas can be supplied into the vacuum chamber 39.
The evacuation unit 32 is installed outside the vacuum chamber 39 and connected to the inside of the vacuum chamber 39 so that the inside of the vacuum chamber 39 can be evacuated.
 搬送室51は、エッチング室30の真空槽39に第一のゲートバルブ55aを介して気密に接続され、洗浄室52は、搬送室51に第二のゲートバルブ55bを介して気密に接続されている。
 搬送室51は不図示の真空排気手段を有し、第一、第二のゲートバルブ55a、55bを閉じた状態で、搬送室51内を真空排気できるように構成されている。
The transfer chamber 51 is hermetically connected to the vacuum chamber 39 of the etching chamber 30 via the first gate valve 55a, and the cleaning chamber 52 is hermetically connected to the transfer chamber 51 via the second gate valve 55b. Yes.
The transfer chamber 51 has an evacuation unit (not shown), and is configured so that the transfer chamber 51 can be evacuated while the first and second gate valves 55a and 55b are closed.
 本発明であるメモリ素子の製造方法を説明する。
 第一、第二のゲートバルブ55a、55bを閉じて、エッチング室30の真空槽39内と搬送室51内をあらかじめ真空排気して真空雰囲気に維持しておく。また洗浄室52内に酸素を含有しない不活性ガスを導入して、大気圧にしておく。
A method for manufacturing a memory element according to the present invention will be described.
The first and second gate valves 55a and 55b are closed, and the inside of the vacuum chamber 39 and the transfer chamber 51 of the etching chamber 30 are evacuated in advance to maintain a vacuum atmosphere. Further, an inert gas not containing oxygen is introduced into the cleaning chamber 52 to keep the atmospheric pressure.
 図1(a)に示すように、基板11上に、絶縁層12と下部電極13と金属酸化物層14と第一、第二の金属層16、17とがこの順序で積層された処理対象物を用いる。
 まずマスク工程として、図1(b)に示すように、第二の金属層17上に、フォトレジストを塗布し、所定のパターンを露光し、現像して、開口を有するマスク20を形成する。マスク20の開口部の底面には第二の金属層17が露出する。
As shown in FIG. 1A, a processing target in which an insulating layer 12, a lower electrode 13, a metal oxide layer 14, and first and second metal layers 16 and 17 are stacked in this order on a substrate 11. Use things.
First, as a mask process, as shown in FIG. 1B, a photoresist is applied on the second metal layer 17, a predetermined pattern is exposed and developed, and a mask 20 having an opening is formed. The second metal layer 17 is exposed on the bottom surface of the opening of the mask 20.
 あるいは、第二の金属層17上にインプリントレジストを塗布し、所定のパターンの凹凸を有する原板を押し当てて、開口を有するマスク20を形成し、開口の底面に第二の金属層17を露出させてもよい。
 次いで、エッチング工程として、この処理対象物10を、図3を参照し、エッチング室30の真空槽39内に真空雰囲気を維持しながら搬入し、マスク20側の表面が露出するような向きでステージ36上に載置する。
Alternatively, an imprint resist is applied onto the second metal layer 17 and an original plate having irregularities of a predetermined pattern is pressed to form a mask 20 having an opening, and the second metal layer 17 is formed on the bottom surface of the opening. It may be exposed.
Next, as an etching process, the object to be processed 10 is carried into the vacuum chamber 39 of the etching chamber 30 while maintaining the vacuum atmosphere with reference to FIG. 36.
 温度制御部38を動作させ、ステージ36の不図示の冷却パイプに温度制御した熱媒体を流し、エッチング中の処理対象物10の温度を20℃~80℃の範囲に保持する。
 ガス供給部31から第一のエッチングガスを供給し、真空槽39内を0.1Pa~2.0Paの圧力に保持する。第一のエッチングガスには化学構造中に塩素を含有するガスを用い、例えばCl2と、BCl3と、SiCl4の群から選択される一のガス又は二以上の混合ガスを含有するガスである。BCl3を使用する場合には、重合性を希釈するため、希ガス(He、Ne、Ar、Kr、Xe)を添加してもよい。
The temperature control unit 38 is operated, a temperature-controlled heat medium is passed through a cooling pipe (not shown) of the stage 36, and the temperature of the processing object 10 during etching is maintained in the range of 20 ° C to 80 ° C.
A first etching gas is supplied from the gas supply unit 31, and the inside of the vacuum chamber 39 is maintained at a pressure of 0.1 Pa to 2.0 Pa. A gas containing chlorine in the chemical structure is used as the first etching gas, for example, a gas containing one gas or a mixed gas of two or more selected from the group consisting of Cl 2 , BCl 3 , and SiCl 4. is there. When BCl 3 is used, a rare gas (He, Ne, Ar, Kr, Xe) may be added to dilute the polymerizability.
 プラズマ用高周波電源34を起動し、RFアンテナ33に交流電流を流し、RFアンテナ33から真空槽39内に電波を放射させ、第一のエッチングガスを励起して、プラズマ化し、塩素イオンや塩素ラジカル等の活性種を生成する。またバイアス用高周波電源35を起動し、処理対象物10にバイアス電圧を印加して、生成された塩素イオンを処理対象物10に入射させ、異方性のエッチング処理を行う。 The high frequency power supply for plasma 34 is activated, an alternating current is passed through the RF antenna 33, radio waves are emitted from the RF antenna 33 into the vacuum chamber 39, the first etching gas is excited and turned into plasma, and chlorine ions and chlorine radicals are produced. And so on. In addition, the bias high-frequency power source 35 is activated, a bias voltage is applied to the object 10 to be processed, and the generated chlorine ions are incident on the object 10 to perform an anisotropic etching process.
 ここでは、ステージ36を囲むようにシールド41が設けられており、エッチング生成物の真空槽39の内壁への付着が防止されている。
 異方性のエッチング処理により金属酸化物層14が露出したら、プラズマ用高周波電源34とバイアス用高周波電源35の動作をそれぞれ停止し、かつガス供給部31からの第一のエッチングガスの供給を停止する。
Here, a shield 41 is provided so as to surround the stage 36, and adhesion of etching products to the inner wall of the vacuum chamber 39 is prevented.
When the metal oxide layer 14 is exposed by the anisotropic etching process, the operations of the plasma high-frequency power source 34 and the bias high-frequency power source 35 are stopped, and the supply of the first etching gas from the gas supply unit 31 is stopped. To do.
 第一のエッチングガスを真空排気し、真空槽39内の圧力が低下した後、ガス供給部31から第二のエッチングガスの供給を開始する。真空槽39内はレジスト(マスク20)との選択比に応じて0.1Pa~10Paの圧力に保持する。第二のエッチングガスには化学構造中に塩素を組成に含むガスを用い、例えばCl2と、BCl3と、SiCl4の群から選択される一のガス又は二以上の混合ガスを含有するガスである。BCl3を使用する場合には、重合性を希釈するため、希ガス(He、Ne、Ar、Kr、Xe)を添加してもよい。 After the first etching gas is evacuated and the pressure in the vacuum chamber 39 decreases, the supply of the second etching gas from the gas supply unit 31 is started. The inside of the vacuum chamber 39 is maintained at a pressure of 0.1 Pa to 10 Pa according to the selection ratio with the resist (mask 20). Using a gas containing chlorine to the composition in the chemical structure in the second etching gas, for example, Cl 2, and BCl 3, the gas containing one gas or more of the mixed gas selected from the group of SiCl 4 It is. When BCl 3 is used, a rare gas (He, Ne, Ar, Kr, Xe) may be added to dilute the polymerizability.
 次いで、プラズマ用高周波電源34とバイアス用高周波電源35を動作させ、プラズマ中の塩素イオンにより、露出している金属酸化物層14を第二のエッチングガスと反応させ、塩化物ガスを生成して、真空排気によって塩化物ガスを除去することで、異方性エッチングする。 Next, the high frequency power source for plasma 34 and the high frequency power source for bias 35 are operated, and the exposed metal oxide layer 14 is reacted with the second etching gas by chlorine ions in the plasma to generate a chloride gas. Then, anisotropic etching is performed by removing chloride gas by evacuation.
 このとき図1(c)に示すように、処理対象物10のエッチングされた側壁部分には金属酸化物層14に含まれる金属の塩化物からなるエッチング生成物25が付着し、残留する。これは一般に、金属酸化物層14に含まれる金属の塩化物は融点、沸点が高く、エッチング中の温度では蒸気圧が低いためである。 At this time, as shown in FIG. 1C, an etching product 25 made of a metal chloride contained in the metal oxide layer 14 adheres and remains on the etched side wall portion of the processing object 10. This is because the metal chloride contained in the metal oxide layer 14 generally has a high melting point and boiling point and a low vapor pressure at the temperature during etching.
 下部電極13が露出したら、プラズマ用高周波電源34とバイアス用高周波電源35の動作をそれぞれ停止し、かつガス供給部31からの第二のエッチングガスの供給を停止する。
 搬送室51にはここでは搬送用のロボット65が設けられている。搬送室51を真空排気しておき、真空槽39内の圧力が低下した後、第一のゲートバルブ55aを開いて、真空槽39内から搬送室51内に処理対象物10を移動させ、第一のゲートバルブ55aを閉じる。次いで、搬送室51内に酸素を含有しない不活性ガスを導入して、搬送室51内の圧力を大気圧まで上げる。
When the lower electrode 13 is exposed, the operations of the plasma high-frequency power source 34 and the bias high-frequency power source 35 are stopped, and the supply of the second etching gas from the gas supply unit 31 is stopped.
Here, a transfer robot 65 is provided in the transfer chamber 51. After the transfer chamber 51 is evacuated and the pressure in the vacuum chamber 39 decreases, the first gate valve 55a is opened to move the processing object 10 from the vacuum chamber 39 into the transfer chamber 51, and One gate valve 55a is closed. Next, an inert gas not containing oxygen is introduced into the transfer chamber 51 to raise the pressure in the transfer chamber 51 to atmospheric pressure.
 洗浄室52内には、処理対象物を載置できる洗浄ステージ61と、洗浄ステージ61に載置された処理対象物に洗浄液を噴射するシャワーノズル62とが配置されている。
 第二のゲートバルブ55bを開き、処理対象物10を搬送室51から洗浄室52に搬入し、洗浄ステージ61上に置く。
In the cleaning chamber 52, a cleaning stage 61 on which a processing target can be placed and a shower nozzle 62 for injecting a cleaning liquid onto the processing target placed on the cleaning stage 61 are arranged.
The second gate valve 55 b is opened, the processing object 10 is carried into the cleaning chamber 52 from the transfer chamber 51, and placed on the cleaning stage 61.
 次いで洗浄工程として、処理対象物10のエッチングした表面にシャワーノズル62から洗浄液を噴霧して、処理対象物10のエッチングした表面を洗浄液と接触させて洗浄処理を行う。
 ここでは洗浄方法としてシャワー式を説明したが、本発明はこれに限定されず、超音波ディップ式等の他の洗浄方法で処理対象物10のエッチングした表面を洗浄液と接触させて洗浄処理をしても良い。
Next, as a cleaning process, a cleaning liquid is sprayed from the shower nozzle 62 onto the etched surface of the processing object 10, and the etching surface of the processing object 10 is brought into contact with the cleaning liquid to perform a cleaning process.
Here, the shower method is described as the cleaning method, but the present invention is not limited to this, and the cleaning process is performed by bringing the etched surface of the processing object 10 into contact with the cleaning liquid by another cleaning method such as an ultrasonic dip method. May be.
 洗浄液としては、純水、イオン交換水、マイクロ・ナノバブル水などの水や、エタノール、メタノール、アセトン、イソプロピルアルコール、エチルエーテルなどの有機溶媒のうち一種類又は二種類以上の混合物を用いる。
 エッチング生成物25は、例えばCoCl2やNiCl2等の水溶性及びアルコール可溶性の金属の塩化物であり、図1(d)に示すように、洗浄液による洗浄処理によりエッチング生成物25は洗浄液に溶解して、除去される。
As the cleaning liquid, one kind or a mixture of two or more kinds of water such as pure water, ion exchange water, micro / nano bubble water, and organic solvents such as ethanol, methanol, acetone, isopropyl alcohol, and ethyl ether are used.
The etching product 25 is, for example, a water-soluble and alcohol-soluble metal chloride such as CoCl 2 or NiCl 2. As shown in FIG. 1D, the etching product 25 is dissolved in the cleaning liquid by the cleaning process using the cleaning liquid. And removed.
 ここで、搬送室51にて処理対象物10を大気に接触させてからから洗浄室52にて洗浄を開始するまでに要する時間は5分以内が望ましい。なぜならば、処理対象物10を大気に出すと、処理対象物10の表面に残留していた塩素が大気中の水分と反応しHClを形成する。処理対象物10にHClにて腐食される材料(例えばAl)を使っていると、そこに腐食(コロージョン)が発生する虞があるからである。 Here, it is desirable that the time required from the time when the processing object 10 is brought into contact with the atmosphere in the transfer chamber 51 to the start of the cleaning in the cleaning chamber 52 is within 5 minutes. This is because when the object to be treated 10 is put into the atmosphere, chlorine remaining on the surface of the object to be treated 10 reacts with moisture in the atmosphere to form HCl. This is because if a material (for example, Al) that is corroded by HCl is used for the object 10 to be processed, corrosion (corrosion) may occur there.
 洗浄処理を終えた後、遠心力による乾燥や、高温気体の吹き付けなどによって処理対象物を乾燥させ、次いで、不図示のアッシング室に処理対象物を搬入し、O2ガスを用いてプラズマアッシングを行う。励起したO2ガスから生じた酸素イオンや酸素ラジカルがマスク20を酸化、分解させて、マスク20が除去される。
 処理対象物の側壁部分のエッチング生成物25はアッシング前に除去されており、アッシング後に側壁部分に酸化物から成る残留物が残留することはない。
 このようにして図1(e)に示すように金属酸化物層14にパターン形成が成されたメモリ素子5が得られる。
After the cleaning process is completed, the object to be processed is dried by centrifugal force drying or high-temperature gas blowing, and then the object to be processed is carried into an ashing chamber (not shown), and plasma ashing is performed using O 2 gas. Do. Oxygen ions and oxygen radicals generated from the excited O 2 gas oxidize and decompose the mask 20 to remove the mask 20.
The etching product 25 on the side wall portion of the object to be processed is removed before ashing, and no oxide residue remains on the side wall portion after ashing.
Thus, the memory element 5 in which the pattern is formed on the metal oxide layer 14 as shown in FIG. 1E is obtained.
 5……メモリ素子
 13……下部電極
 14……金属酸化物層
 18……上部電極
 20……マスク
 30……エッチング室
 31……ガス供給部
 42……プラズマ生成部
 50……メモリ素子の製造装置
 51……搬送室
 52……洗浄室
 
5 ... Memory element 13 ... Lower electrode 14 ... Metal oxide layer 18 ... Upper electrode 20 ... Mask 30 ... Etching chamber 31 ... Gas supply part 42 ... Plasma generation part 50 ... Manufacturing of memory element Equipment 51 …… Transport chamber 52 …… Cleaning chamber

Claims (6)

  1.  上部電極と下部電極との間に金属酸化物層が配置され、前記上部電極と前記下部電極との間に直流電圧を印加すると、前記直流電圧の極性に応じて高抵抗状態と低抵抗状態のいずれか一方の状態になることにより情報を記憶することができ、膜厚方向にセンス電流を流し、抵抗値を測定して前記高抵抗状態と前記低抵抗状態とを判別することにより情報を読み出すことができるメモリ素子の製造装置であって、
     エッチングガスを供給するガス供給部と、前記エッチングガスをプラズマ化するプラズマ生成部とを有するエッチング室と、
     前記エッチング室に接続して配置された洗浄室と、
     処理対象物を前記エッチング室から前記洗浄室に搬送する搬送室と、
     を有し、
     前記エッチング室は、基板上に前記下部電極と前記金属酸化物層と前記上部電極とがこの順に積層された処理対象物が搬入されると、化学構造中に塩素を含むエッチングガスをプラズマ化し、前記金属酸化物層をエッチングして、前記下部電極を露出させるように構成され、
     前記洗浄室は、前記処理対象物のエッチングした表面に洗浄液を接触させるように構成されたメモリ素子の製造装置。
    When a metal oxide layer is disposed between the upper electrode and the lower electrode, and a DC voltage is applied between the upper electrode and the lower electrode, the high resistance state and the low resistance state are changed according to the polarity of the DC voltage. Information can be stored by entering either state, and information is read by flowing a sense current in the film thickness direction and measuring the resistance value to distinguish between the high resistance state and the low resistance state An apparatus for manufacturing a memory device,
    An etching chamber having a gas supply section for supplying an etching gas, and a plasma generation section for converting the etching gas into a plasma;
    A cleaning chamber disposed in connection with the etching chamber;
    A transfer chamber for transferring a processing object from the etching chamber to the cleaning chamber;
    Have
    When the processing object in which the lower electrode, the metal oxide layer, and the upper electrode are stacked in this order is loaded on the substrate, the etching chamber converts the etching gas containing chlorine into plasma into plasma, Etching the metal oxide layer to expose the lower electrode;
    The apparatus for manufacturing a memory element, wherein the cleaning chamber is configured to bring a cleaning liquid into contact with an etched surface of the processing object.
  2.  前記金属酸化物層は、Al23と、Y25と、HfO2と、TiO2と、CoOと、NiOとからなる群より選択される一の金属酸化物からなる請求項1記載のメモリ素子の製造装置。 The metal oxide layer, Al 2 O 3, and Y 2 O 5, and HfO 2, and TiO 2, and CoO, consists of a metal oxide selected from the group consisting of NiO claim 1, wherein Memory device manufacturing apparatus.
  3.  前記エッチングガスは、Cl2と、BCl3と、SiCl4とからなる群より選択される一のガス又は二以上の混合ガスを含有する請求項1又は請求項2のいずれか1項記載のメモリ素子の製造装置。 3. The memory according to claim 1, wherein the etching gas contains one gas or two or more mixed gases selected from the group consisting of Cl 2 , BCl 3 , and SiCl 4. Device manufacturing equipment.
  4.  上部電極と下部電極との間に金属酸化物が配置され、前記上部電極と前記下部電極との間に直流電圧を印加すると、前記直流電圧の極性に応じて高抵抗状態と低抵抗状態のいずれか一方の状態になることにより情報を記録することができ、膜厚方向にセンス電流を流し、抵抗値を測定して高抵抗状態と低抵抗状態とを判別することにより情報を読み出すことができるメモリ素子の製造装置であって、
     基板上に前記下部電極と前記金属酸化物層と前記上部電極とがこの順に積層された処理対象物上に、前記上部電極が露出するような開口を有する所定のパターンのマスクを配置するマスク工程と、
     化学構造中に塩素を含むエッチングガスをプラズマ化し、前記上部電極と前記金属酸化物層をエッチングして、前記下部電極を露出させるエッチング工程と、
     前記処理対象物のエッチングした表面に洗浄液を接触させ、前記エッチング工程で生成された金属の塩化物を除去する洗浄工程とを有するメモリ素子の製造方法。
    When a metal oxide is disposed between the upper electrode and the lower electrode and a DC voltage is applied between the upper electrode and the lower electrode, either a high resistance state or a low resistance state is selected depending on the polarity of the DC voltage. Information can be recorded by entering one of the states, and information can be read by flowing a sense current in the film thickness direction and measuring the resistance value to distinguish between a high resistance state and a low resistance state. A device for manufacturing a memory element,
    A mask process of disposing a mask having a predetermined pattern having an opening exposing the upper electrode on a processing object in which the lower electrode, the metal oxide layer, and the upper electrode are laminated in this order on a substrate. When,
    An etching process that plasmaizes an etching gas containing chlorine in a chemical structure, etches the upper electrode and the metal oxide layer, and exposes the lower electrode;
    A method of manufacturing a memory device, comprising: a cleaning step of bringing a cleaning liquid into contact with an etched surface of the object to be processed to remove a metal chloride generated in the etching step.
  5.  前記金属酸化物層は、Al23と、Y25と、HfO2と、TiO2と、CoOと、NiOとからなる群より選択される一の金属酸化物からなる請求項4記載のメモリ素子の製造方法。 The metal oxide layer is made of one metal oxide selected from the group consisting of Al 2 O 3 , Y 2 O 5 , HfO 2 , TiO 2 , CoO, and NiO. Method for manufacturing the memory element.
  6.  前記金属酸化物層のエッチングに用いる前記エッチングガスは、Cl2と、BCl3と、SiCl4とからなる群より選択される一のガス又は二以上の混合ガスを含有する請求項4又は請求項5のいずれか1項記載のメモリ素子の製造方法。
     
    The etching gas used for etching of the metal oxide layer, and Cl 2, and BCl 3, claim 4 or claim containing one gas or more of the mixed gas selected from the group consisting of SiCl 4 Metropolitan 6. A method for manufacturing a memory element according to any one of items 5 to 6.
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