WO2012067409A2 - Thin film transistor substrate having hybrid cmos structure and optical sensor array using the substrate - Google Patents

Thin film transistor substrate having hybrid cmos structure and optical sensor array using the substrate Download PDF

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Publication number
WO2012067409A2
WO2012067409A2 PCT/KR2011/008721 KR2011008721W WO2012067409A2 WO 2012067409 A2 WO2012067409 A2 WO 2012067409A2 KR 2011008721 W KR2011008721 W KR 2011008721W WO 2012067409 A2 WO2012067409 A2 WO 2012067409A2
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thin film
film transistor
silicon thin
substrate
polycrystalline silicon
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PCT/KR2011/008721
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French (fr)
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WO2012067409A3 (en
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Moon Hyo Kang
Ji Ho Hur
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Silicon Display Co., Ltd.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14692—Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon

Definitions

  • the present invention relates to a thin film transistor substrate, and, more particularly, to a substrate acquired by configuring a complementary metal-oxide semiconductor (CMOS) within one thin film transistor by manufacturing a P-type polycrystalline silicon thin film transistor and an N-type amorphous silicon thin film transistor on the same substrate, and an optical sensor array using the substrate.
  • CMOS complementary metal-oxide semiconductor
  • CMOS structure in which both an nMOS (n-channel MOSFET) and a pMOS (p-channel MOSFET) exist is used in a display or a sensor array, a characteristic of the device can be improved and applicability thereof can be increased.
  • the polycrystalline silicon thin film transistor and the amorphous thin film transistor have different manufacturing processes, and different structures, and, as a result, it is not easy to manufacture the polycrystalline silicon thin film transistor and the amorphous thin film transistor on the same substrate.
  • a gate insulating layer of a general polycrystalline silicon thin film transistor is made of SiO 2 (silicon dioxide) and a gate insulating layer of the amorphous silicon thin film transistor is made of SiNx (silicon nitride).
  • the polycrystalline thin film transistor generally uses a coplanar structure and the amorphous silicon thin film transistor generally uses an inverted staggered structure, such that the structure and the manufacturing process are complicated in order to manufacture two types of thin film transistors on the same substrate.
  • optical sensor array devices having light sensitivity needs to be incorporated in each pixel for optical sensing, and optical sensor arrays in the related art include the three types described below.
  • an embedded driving circuit is configured by the amorphous silicon thin film transistor and an amorphous silicon photosensor is included, second, the embedded driving circuit is configured by the polycrystalline silicon thin film transistor and a polycrystalline silicon photosensor is included, and, third, the embedded driving circuit is configured by the polycrystalline silicon thin film transistor and the amorphous silicon photosensor is included.
  • the amorphous silicon thin film transistor has a lower field effect mobility than the polycrystalline silicon thin film transistor, it is difficult to configure the driving circuit.
  • the polycrystalline silicon thin film transistors are used for the transistors constituting the embedded driving circuit, and amorphous PIN photodiodes are used for the photosensors included in each pixel of the array.
  • the present invention has been made in an effort to provide a thin film transistor substrate having a hybrid CMOS structure of which a manufacturing process is simplified by forming an insulating interlayer of a polycrystalline silicon thin film transistor and a gate insulating layer of an amorphous silicon thin film transistor as the same layer.
  • the present invention has been made in an effort to provide an optical sensor array capable of reducing a process cost and a process time by using the hybrid CMOS structure.
  • CMOS structure having a hybrid CMOS structure and an optical sensor array using the substrate.
  • a polycrystalline silicon thin film transistor having a coplanar structure with an insulating interlayer and an amorphous silicon thin film transistor having an inverted staggered structure with a gate insulating layer are formed on one substrate and the insulating interlayer and the gate insulating layer are formed as the same layer.
  • the polycrystalline silicon thin film transistor may be a P-type transistor and the amorphous silicon transistor may be an N-type transistor.
  • a gate of the polycrystalline silicon thin film transistor and a gate of the amorphous silicon thin film transistor may be formed as the same layer, and a source and a drain of the polycrystalline silicon thin film transistor and a source and a drain of the amorphous silicon thin film transistor may be formed as the same layer.
  • the insulating interlayer and the gate insulating layer may adopt a silicon nitride layer.
  • the gate insulating layer, amorphous silicon, and N+ silicon may be consecutively deposited.
  • the substrate may be made of glass or metal.
  • an optical sensor array using a thin film transistor substrate having a hybrid CMOS structure in which a polycrystalline silicon thin film transistor having a coplanar structure with an insulating interlayer and an amorphous silicon thin film transistor having an inverted staggered structure with a gate insulating layer are formed on one substrate and the insulating interlayer and the gate insulating layer are formed as the same layer, wherein a driving circuit is configured by the polycrystalline silicon thin film transistor and a photosensor is configured by the amorphous silicon thin film transistor.
  • the one polycrystalline silicon thin film transistor and the one amorphous silicon thin film transistor may be configured in each pixel.
  • the three polycrystalline silicon thin film transistors and the one amorphous silicon thin film transistor may be configured in each pixel.
  • an inorganic electroluminescence (EL) or an organic light-emitting diode (OLED) may be used as a light source of the photosensor.
  • the optical sensor array may be used as a fingerprint recognition sensor by using inorganic EL.
  • the manufacturing process is simplified and the characteristic of the amorphous silicon thin film transistor and the characteristic of the polycrystalline silicon thin film transistor can be simultaneously used on one substrate, and, as a result, the applicability of the thin film transistor is increased.
  • the CMOS inverter can be configured by using the hybrid CMOS structure and the CMOS circuit can be incorporated in the display substrate or the sensor array.
  • the polycrystalline silicon thin film transistor can be used and as the photosensor, the amorphous silicon thin film transistor can be used, and, as a result, the circuit can be incorporated in the substrate by using the high photo current property of the amorphous silicon thin film transistor and the high field effect mobility of the polycrystalline silicon thin film transistor.
  • the process cost and the process time can be reduced through the hybrid CMOS structure.
  • FIG. 1 is a longitudinal cross-sectional view of a thin film transistor substrate having a hybrid CMOS structure according to an exemplary embodiment of the present invention
  • FIG. 2 is a longitudinal cross-sectional view for specifically describing each layer of the thin film transistor substrate 11 having the hybrid CMOS structure according to the exemplary embodiment of the present invention
  • FIG. 3 is a longitudinal cross-sectional view of a thin film transistor substrate having a hybrid CMOS structure used as an optical sensor according to an exemplary embodiment of the present invention.
  • FIGS. 4 and 5 are circuit diagrams showing a passive type and an active type as an optical sensor array using the thin film transistor having the hybrid CMOS structure according to the exemplary embodiment of the present invention.
  • FIG. 1 is a longitudinal cross-sectional view of a thin film transistor substrate having a hybrid CMOS structure according to an exemplary embodiment of the present invention.
  • a polycrystalline silicon thin film transistor 5 having a coplanar structure and an amorphous silicon thin film transistor 10 having an inverted staggered structure are implemented on the same substrate 11.
  • the substrate 11 may be metal or glass.
  • metal having a high melting point and a small thermal expansion coefficient such as molybdenum (Mo), tungsten (W), a molybdenum alloy, a tungsten alloy, and the like may be formed in a sheet form.
  • FIG. 2 is a longitudinal cross-sectional view for specifically describing each layer of the thin film transistor substrate 11 having the hybrid CMOS structure according to the exemplary embodiment of the present invention.
  • buffer layers 12 of the polycrystalline silicon thin film transistor 5 having the coplanar structure and the amorphous silicon thin film transistor 10 having the inverted staggered structure are formed by depositing a silicon oxide layer or a silicon nitride layer on the entire surface of the metallic substrate 11 through a deposition method such as plasma enhanced chemical vapor deposition (PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • a polycrystalline silicon layer 13 is formed on the buffer layer12.
  • the polycrystalline silicon layer 13 is formed through crystallization of amorphous silicon, or is deposited at 600 to 1200 °C or higher using deposition methods such as low pressure chemical vapor deposition (LPCVD), the PECVD, and the like.
  • LPCVD low pressure chemical vapor deposition
  • PECVD PECVD
  • the polycrystalline silicon layer 13 acts as an active layer.
  • a gate insulating layer 15 of the polycrystalline silicon thin film transistor 5 having the coplanar structure is formed on the polycrystalline silicon layer 13.
  • a gate 16 of the polycrystalline silicon thin film transistor 5 having the coplanar structure is formed on the gate insulating layer 15. Thereafter, boron is doped to form a p+ polycrystalline silicon layer 14.
  • the gate insulating layer 15 of the polycrystalline silicon thin film transistor 5 having the coplanar structure is formed by depositing an inorganic insulating material such as SiO 2 through the deposition method such as the PECVD.
  • the gate 16 of the polycrystalline silicon thin film transistor 5 having the coplanar structure is processed at the same time as a gate 17 of the amorphous silicon thin film transistor 10 having the inverter staggered structure for simplicity.
  • an insulating interlayer 18 is formed on the gate insulating layer 15 in which the gate 16 of the polycrystalline silicon thin film transistor 5 having the coplanar structure is formed. Then, holes are formed to penetrate through the insulating interlayer 18 and the gate insulating layer 15, and the source and drain 22 of the polycrystalline silicon thin film transistor 5 are then formed through the holes. Therefore, the source and drain 22 of the polycrystalline silicon thin film transistor 5 having the coplanar structure are connected to the p+ polycrystalline silicon layer 14.
  • the source and drain 22 of the polycrystalline silicon thin film transistor 5 having the coplanar structure is formed at the same time as the source and drain 21 of the amorphous silicon thin film transistor 10, which makes the fabrication process simplified.
  • the insulating interlayer 18 of the polycrystalline silicon thin film transistor 5 having the coplanar structure is used as the gate insulating layer of the amorphous silicon thin film transistor 10 having the inverted staggered structure to simplify the process, thereby implementing the hybrid CMOS structure.
  • SiNx is deposited separately twice. That is, a first SiNx thin film is deposited and thereafter, the polycrystalline silicon thin film transistor 5 is heat-treated. Thereafter, three thin films of a second SiNx thin film, amorphous silicon 19, and n+ amorphous silicon 20 are consecutively deposited thereon to secure a stable interface characteristics and process convenience.
  • the amorphous silicon 19 is formed on the gate insulating layer of the amorphous silicon thin film transistor 10 having the inverted staggered structure and the n+ amorphous silicon 20.
  • the source and drain 21 of the amorphous silicon thin film transistor 10 is processed at the same time as the source and drain 22 of the polycrystalline silicon thin film transistor 5 having the coplanar structure.
  • a passivation layer 23 is formed on uppermost layers of the polycrystalline silicon thin film transistor 5 having the coplanar structure and the amorphous silicon thin film transistor 10 having the inverted staggered structure.
  • a CMOS inverter may be configured by using the hybrid CMOS structure and a CMOS circuit may be incorporated in a display substrate or a sensor array.
  • FIG. 3 is a longitudinal cross-sectional view of a thin film transistor substrate having a hybrid CMOS structure used as an optical sensor according to an exemplary embodiment of the present invention.
  • a light source 31 may be an inorganic EL. Furthermore, the light source 31 may be an organic light-emitting diode (OLED). That is, the inorganic EL and the optical sensor array according to the exemplary embodiment of the present invention may be used as a fingerprint recognition sensor.
  • OLED organic light-emitting diode
  • FIGS. 4 and 5 are circuit diagrams showing a passive type and an active type as an optical sensor array using the thin film transistor having the hybrid CMOS structure according to the exemplary embodiment of the present invention.
  • an amorphous silicon thin film transistor T P1 serves as the photosensor and the polycrystalline silicon thin film transistor 5 T S1 serves as a switching transistor.
  • the voltage of a gate 17 of the photosensor T P1 which is the amorphous silicon thin film transistor is set as the voltage of a common terminal V com of -5 V at all times.
  • photo current generated due to light in the photosensor T P1 which is the amorphous silicon thin film transistor causes electric charges stored in the storage capacitor C to be leaked and, therefore, the volatage of the storage capacitor C is decreased.
  • the gate 16 of a driving transistor T S2 which is the polycrystalline silicon thin film transistor 5
  • the gate of the switching transistor T S3 which is the polycrystalline silicon thin film transistor 5
  • current flows from VDD through a data bus line since the amount of current that flows is determined according to the gate voltage of the driving transistor T S2 , the gate voltage of the driving transistor T S2 depends on the amount of photo current of the photosensor T P1 .
  • the photo current of the amorphous silicon thin film transistor is sensed, and the sensed signal is then transmitted to a data read-out line through the polycrystalline silicon thin film transistor.
  • a reset transistor T S1 which is the polycrystalline silicon thin film transistor 5 is selected and operated to initialize the voltage of the storage capacitor C.
  • Scan signals Scan n+1 and Scan n are sequentially supplied to the reset transistor T S1 and the switching transistor T S3 .
  • the thin film transistor substrate having the hybrid CMOS structure according to the exemplary embodiment of the present invention when used, as the transistors constituting the embedded circuit, the polycrystalline silicon thin film transistor 5 is used and the amorphous silicon thin film transistor may be used as the photosensor.
  • the present invention is advantageous in that both of a driving circuit and a photosensor can be incorporated in a substrate using a high photo current property of the amorphous silicon thin film transistor and high field effect mobility of the polycrystalline silicon thin film transistor 5. Further, the CMOS circuit can be incorporated by using two types of pMOS and nMOS.
  • the process cost and the process time can be reduced through the hybrid CMOS structure.

Abstract

The present invention relates to a thin film transistor substrate in which a polycrystalline silicon thin film transistor having a coplanar structure with an insulating interlayer and an amorphous silicon thin film transistor having an inverted staggered structure with a gate insulating layer are formed on one substrate and the insulating interlayer and the gate insulating layer are formed as the same layer. When a hybrid CMOS structure is used, the manufacturing process is simplified and a characteristic of the amorphous silicon thin film transistor and the characteristic of the polycrystalline silicon thin film transistor can be simultaneously obtained with one substrate, and, as a result, the applicability of the thin film transistor is increased.

Description

THIN FILM TRANSISTOR SUBSTRATE HAVING HYBRID CMOS STRUCTURE AND OPTICAL SENSOR ARRAY USING THE SUBSTRATE
The present invention relates to a thin film transistor substrate, and, more particularly, to a substrate acquired by configuring a complementary metal-oxide semiconductor (CMOS) within one thin film transistor by manufacturing a P-type polycrystalline silicon thin film transistor and an N-type amorphous silicon thin film transistor on the same substrate, and an optical sensor array using the substrate.
In general, when a CMOS structure in which both an nMOS (n-channel MOSFET) and a pMOS (p-channel MOSFET) exist is used in a display or a sensor array, a characteristic of the device can be improved and applicability thereof can be increased.
However, the polycrystalline silicon thin film transistor and the amorphous thin film transistor have different manufacturing processes, and different structures, and, as a result, it is not easy to manufacture the polycrystalline silicon thin film transistor and the amorphous thin film transistor on the same substrate.
That is, a gate insulating layer of a general polycrystalline silicon thin film transistor is made of SiO2 (silicon dioxide) and a gate insulating layer of the amorphous silicon thin film transistor is made of SiNx (silicon nitride). The polycrystalline thin film transistor generally uses a coplanar structure and the amorphous silicon thin film transistor generally uses an inverted staggered structure, such that the structure and the manufacturing process are complicated in order to manufacture two types of thin film transistors on the same substrate.
Meanwhile, in the optical sensor array, devices having light sensitivity needs to be incorporated in each pixel for optical sensing, and optical sensor arrays in the related art include the three types described below.
First, an embedded driving circuit is configured by the amorphous silicon thin film transistor and an amorphous silicon photosensor is included, second, the embedded driving circuit is configured by the polycrystalline silicon thin film transistor and a polycrystalline silicon photosensor is included, and, third, the embedded driving circuit is configured by the polycrystalline silicon thin film transistor and the amorphous silicon photosensor is included.
In the first case, since the amorphous silicon thin film transistor has a lower field effect mobility than the polycrystalline silicon thin film transistor, it is difficult to configure the driving circuit.
In the second case, since the photosensing effect of the polycrystalline silicon photosensor is lower than the photosensing effect of the amorphous silicon thin film transistor, it is disadvantageous in optical sensing.
In the third case, the polycrystalline silicon thin film transistors are used for the transistors constituting the embedded driving circuit, and amorphous PIN photodiodes are used for the photosensors included in each pixel of the array. In this case, it is advantageous in circuit configuration or sensing, but significant costs are required and the process time is increased because the process of the polycrystalline silicon thin film transistor is completed and the amorphous PIN photodiode should be processed thereon again.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
The present invention has been made in an effort to provide a thin film transistor substrate having a hybrid CMOS structure of which a manufacturing process is simplified by forming an insulating interlayer of a polycrystalline silicon thin film transistor and a gate insulating layer of an amorphous silicon thin film transistor as the same layer.
Further, the present invention has been made in an effort to provide an optical sensor array capable of reducing a process cost and a process time by using the hybrid CMOS structure.
There are provided a thin film transistor substrate having a hybrid CMOS structure and an optical sensor array using the substrate.
In the thin film transistor substrate having a hybrid CMOS structure, a polycrystalline silicon thin film transistor having a coplanar structure with an insulating interlayer and an amorphous silicon thin film transistor having an inverted staggered structure with a gate insulating layer are formed on one substrate and the insulating interlayer and the gate insulating layer are formed as the same layer.
Herein, the polycrystalline silicon thin film transistor may be a P-type transistor and the amorphous silicon transistor may be an N-type transistor.
Further, a gate of the polycrystalline silicon thin film transistor and a gate of the amorphous silicon thin film transistor may be formed as the same layer, and a source and a drain of the polycrystalline silicon thin film transistor and a source and a drain of the amorphous silicon thin film transistor may be formed as the same layer.
Herein, the insulating interlayer and the gate insulating layer may adopt a silicon nitride layer.
Meanwhile, in the amorphous silicon thin film transistor, the gate insulating layer, amorphous silicon, and N+ silicon may be consecutively deposited.
Further, the substrate may be made of glass or metal.
Meanwhile, in an optical sensor array using a thin film transistor substrate having a hybrid CMOS structure in which a polycrystalline silicon thin film transistor having a coplanar structure with an insulating interlayer and an amorphous silicon thin film transistor having an inverted staggered structure with a gate insulating layer are formed on one substrate and the insulating interlayer and the gate insulating layer are formed as the same layer, wherein a driving circuit is configured by the polycrystalline silicon thin film transistor and a photosensor is configured by the amorphous silicon thin film transistor.
Herein, in the passive optical sensor array, the one polycrystalline silicon thin film transistor and the one amorphous silicon thin film transistor may be configured in each pixel.
Further, in the active optical sensor array, the three polycrystalline silicon thin film transistors and the one amorphous silicon thin film transistor may be configured in each pixel.
Further, as a light source of the photosensor, an inorganic electroluminescence (EL) or an organic light-emitting diode (OLED) may be used. Furthermore, the optical sensor array may be used as a fingerprint recognition sensor by using inorganic EL.
According to the exemplary embodiments of the present invention, when the hybrid CMOS structure is used, the manufacturing process is simplified and the characteristic of the amorphous silicon thin film transistor and the characteristic of the polycrystalline silicon thin film transistor can be simultaneously used on one substrate, and, as a result, the applicability of the thin film transistor is increased.
Further, since the polycrystalline silicon thin film transistor prepared on one substrate is the pMOS and the amorphous silicon thin film transistor is the nMOS, the CMOS inverter can be configured by using the hybrid CMOS structure and the CMOS circuit can be incorporated in the display substrate or the sensor array.
Further, as the transistors constituting the embedded circuit, the polycrystalline silicon thin film transistor can be used and as the photosensor, the amorphous silicon thin film transistor can be used, and, as a result, the circuit can be incorporated in the substrate by using the high photo current property of the amorphous silicon thin film transistor and the high field effect mobility of the polycrystalline silicon thin film transistor.
Furthermore, the process cost and the process time can be reduced through the hybrid CMOS structure.
The above and other features of the present invention will now be described in detail with reference to certain exemplary embodiments thereof illustrated the accompanying drawings which are given hereinafter by way of illustration only, and thus are not limitative of the present invention, and wherein:
FIG. 1 is a longitudinal cross-sectional view of a thin film transistor substrate having a hybrid CMOS structure according to an exemplary embodiment of the present invention;
FIG. 2 is a longitudinal cross-sectional view for specifically describing each layer of the thin film transistor substrate 11 having the hybrid CMOS structure according to the exemplary embodiment of the present invention;
FIG. 3 is a longitudinal cross-sectional view of a thin film transistor substrate having a hybrid CMOS structure used as an optical sensor according to an exemplary embodiment of the present invention; and
FIGS. 4 and 5 are circuit diagrams showing a passive type and an active type as an optical sensor array using the thin film transistor having the hybrid CMOS structure according to the exemplary embodiment of the present invention.
It should be understood that the appended drawings are not necessarily to scale, presenting a somewhat simplified representation of various preferred features illustrative of the basic principles of the invention. The specific design features of the present invention as disclosed herein, including, for example, specific dimensions, orientations, locations, and shapes will be determined in part by the particular intended application and use environment.
In the figures, reference numbers refer to the same or equivalent parts of the present invention throughout the several figures of the drawing.
Hereinafter reference will now be made in detail to various embodiments of the present invention, examples of which are illustrated in the accompanying drawings and described below. While the invention will be described in conjunction with exemplary embodiments, it will be understood that the present description is not intended to limit the invention to those exemplary embodiments. On the contrary, the invention is intended to cover not only the exemplary embodiments, but also various alternatives, modifications, equivalents and other embodiments, which may be included within the spirit and scope of the invention as defined by the appended claims.
FIG. 1 is a longitudinal cross-sectional view of a thin film transistor substrate having a hybrid CMOS structure according to an exemplary embodiment of the present invention.
As shown in FIG. 1, a polycrystalline silicon thin film transistor 5 having a coplanar structure and an amorphous silicon thin film transistor 10 having an inverted staggered structure are implemented on the same substrate 11.
Herein, the substrate 11 may be metal or glass. In the case of the metal, metal having a high melting point and a small thermal expansion coefficient such as molybdenum (Mo), tungsten (W), a molybdenum alloy, a tungsten alloy, and the like may be formed in a sheet form.
FIG. 2 is a longitudinal cross-sectional view for specifically describing each layer of the thin film transistor substrate 11 having the hybrid CMOS structure according to the exemplary embodiment of the present invention.
As shown in FIG. 2, buffer layers 12 of the polycrystalline silicon thin film transistor 5 having the coplanar structure and the amorphous silicon thin film transistor 10 having the inverted staggered structure are formed by depositing a silicon oxide layer or a silicon nitride layer on the entire surface of the metallic substrate 11 through a deposition method such as plasma enhanced chemical vapor deposition (PECVD).
Meanwhile, a polycrystalline silicon layer 13 is formed on the buffer layer12. In this case, the polycrystalline silicon layer 13 is formed through crystallization of amorphous silicon, or is deposited at 600 to 1200 ℃ or higher using deposition methods such as low pressure chemical vapor deposition (LPCVD), the PECVD, and the like. The polycrystalline silicon layer 13 acts as an active layer.
Further, a gate insulating layer 15 of the polycrystalline silicon thin film transistor 5 having the coplanar structure is formed on the polycrystalline silicon layer 13. In addition, a gate 16 of the polycrystalline silicon thin film transistor 5 having the coplanar structure is formed on the gate insulating layer 15. Thereafter, boron is doped to form a p+ polycrystalline silicon layer 14.
Specifically, the gate insulating layer 15 of the polycrystalline silicon thin film transistor 5 having the coplanar structure is formed by depositing an inorganic insulating material such as SiO2 through the deposition method such as the PECVD.
Herein, the gate 16 of the polycrystalline silicon thin film transistor 5 having the coplanar structure is processed at the same time as a gate 17 of the amorphous silicon thin film transistor 10 having the inverter staggered structure for simplicity.
In addition, an insulating interlayer 18 is formed on the gate insulating layer 15 in which the gate 16 of the polycrystalline silicon thin film transistor 5 having the coplanar structure is formed. Then, holes are formed to penetrate through the insulating interlayer 18 and the gate insulating layer 15, and the source and drain 22 of the polycrystalline silicon thin film transistor 5 are then formed through the holes. Therefore, the source and drain 22 of the polycrystalline silicon thin film transistor 5 having the coplanar structure are connected to the p+ polycrystalline silicon layer 14.
Herein, the source and drain 22 of the polycrystalline silicon thin film transistor 5 having the coplanar structure is formed at the same time as the source and drain 21 of the amorphous silicon thin film transistor 10, which makes the fabrication process simplified.
In addition, the insulating interlayer 18 of the polycrystalline silicon thin film transistor 5 having the coplanar structure is used as the gate insulating layer of the amorphous silicon thin film transistor 10 having the inverted staggered structure to simplify the process, thereby implementing the hybrid CMOS structure.
Herein, in order to use the insulating interlayer 18 as the gate insulating layer of the amorphous silicon thin film transistor 10, SiNx is deposited separately twice. That is, a first SiNx thin film is deposited and thereafter, the polycrystalline silicon thin film transistor 5 is heat-treated. Thereafter, three thin films of a second SiNx thin film, amorphous silicon 19, and n+ amorphous silicon 20 are consecutively deposited thereon to secure a stable interface characteristics and process convenience.
Meanwhile, the amorphous silicon 19 is formed on the gate insulating layer of the amorphous silicon thin film transistor 10 having the inverted staggered structure and the n+ amorphous silicon 20. Next, the source and drain 21 of the amorphous silicon thin film transistor 10 is processed at the same time as the source and drain 22 of the polycrystalline silicon thin film transistor 5 having the coplanar structure.
In addition, lastly, a passivation layer 23 is formed on uppermost layers of the polycrystalline silicon thin film transistor 5 having the coplanar structure and the amorphous silicon thin film transistor 10 having the inverted staggered structure.
Accordingly, in the hybrid structure, since the polycrystalline silicon thin film transistor 5 prepared on one substrate 11 is the pMOS and the amorphous silicon thin film transistor 10 is the nMOS, a CMOS inverter may be configured by using the hybrid CMOS structure and a CMOS circuit may be incorporated in a display substrate or a sensor array.
FIG. 3 is a longitudinal cross-sectional view of a thin film transistor substrate having a hybrid CMOS structure used as an optical sensor according to an exemplary embodiment of the present invention.
In FIG. 3, a light source 31 may be an inorganic EL. Furthermore, the light source 31 may be an organic light-emitting diode (OLED). That is, the inorganic EL and the optical sensor array according to the exemplary embodiment of the present invention may be used as a fingerprint recognition sensor.
FIGS. 4 and 5 are circuit diagrams showing a passive type and an active type as an optical sensor array using the thin film transistor having the hybrid CMOS structure according to the exemplary embodiment of the present invention.
As shown in FIG. 4, an amorphous silicon thin film transistor TP1 serves as the photosensor and the polycrystalline silicon thin film transistor 5 TS1 serves as a switching transistor.
That is, current generated from the photo sensor TP1 by light is stored in a storage capacitor C during one frame and when the selection switching transistor TS1 is selected, the current is transferred through data read-out.
Further, as shown in FIG. 5, the voltage of a gate 17 of the photosensor TP1 which is the amorphous silicon thin film transistor is set as the voltage of a common terminal Vcom of -5 V at all times.
In FIG. 5, photo current generated due to light in the photosensor TP1 which is the amorphous silicon thin film transistor causes electric charges stored in the storage capacitor C to be leaked and, therefore, the volatage of the storage capacitor C is decreased. When the voltage is applied to a gate 16 of a driving transistor TS2, which is the polycrystalline silicon thin film transistor 5, the gate of the switching transistor TS3, which is the polycrystalline silicon thin film transistor 5 is selected, and current flows from VDD through a data bus line. In this case, since the amount of current that flows is determined according to the gate voltage of the driving transistor TS2, the gate voltage of the driving transistor TS2 depends on the amount of photo current of the photosensor TP1. In other words, the photo current of the amorphous silicon thin film transistor is sensed, and the sensed signal is then transmitted to a data read-out line through the polycrystalline silicon thin film transistor. Further, a reset transistor TS1 which is the polycrystalline silicon thin film transistor 5 is selected and operated to initialize the voltage of the storage capacitor C. Scan signals Scan n+1 and Scan n are sequentially supplied to the reset transistor TS1 and the switching transistor TS3.
As seen in FIGS. 4 and 5, when the thin film transistor substrate having the hybrid CMOS structure according to the exemplary embodiment of the present invention is used, as the transistors constituting the embedded circuit, the polycrystalline silicon thin film transistor 5 is used and the amorphous silicon thin film transistor may be used as the photosensor.
Accordingly, the present invention is advantageous in that both of a driving circuit and a photosensor can be incorporated in a substrate using a high photo current property of the amorphous silicon thin film transistor and high field effect mobility of the polycrystalline silicon thin film transistor 5. Further, the CMOS circuit can be incorporated by using two types of pMOS and nMOS.
Furthermore, the process cost and the process time can be reduced through the hybrid CMOS structure.
The invention has been described in detail with reference to preferred embodiments thereof. However, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (11)

  1. A thin film transistor substrate having a hybrid CMOS structure, wherein:
    a polycrystalline silicon thin film transistor having a coplanar structure with an insulating interlayer and an amorphous silicon thin film transistor having an inverted staggered structure with a gate insulating layer are formed on one substrate, and
    the insulating interlayer and the gate insulating layer are formed as the same layer.
  2. The thin film transistor substrate having a hybrid CMOS structure of claim 1, wherein the polycrystalline silicon thin film transistor is a P-type transistor and the amorphous silicon transistor is an N-type transistor.
  3. The thin film transistor substrate having a hybrid CMOS structure of claim 1 or 2, wherein:
    a gate of the polycrystalline silicon thin film transistor and a gate of the amorphous silicon thin film transistor are formed as the same layer, and
    a source and a drain of the polycrystalline silicon thin film transistor and a source and a drain of the amorphous silicon thin film transistor are formed as the same layer.
  4. The thin film transistor substrate having a hybrid CMOS structure of claim 1 or 2, wherein the insulating interlayer and the gate insulating layer adopt a silicon nitride layer.
  5. The thin film transistor substrate having a hybrid CMOS structure of claim 1 or 2, wherein in the amorphous silicon thin film transistor, the gate insulating layer, amorphous silicon, and N+ silicon are consecutively deposited.
  6. The thin film transistor substrate having a hybrid CMOS structure of claim 1 or 2, wherein the substrate is made of glass or metal.
  7. The thin film transistor substrate having a hybrid CMOS structure of claim 1 or 2, wherein in the insulating interlayer, SiNx is deposited separately twice, that is, a first SiNx thin film is deposited and thereafter, the polycrystalline silicon thin film transistor is heat-treated and a second SiNx thin film is deposited thereon.
  8. An optical sensor array using a thin film transistor substrate having a hybrid CMOS structure in which a polycrystalline silicon thin film transistor having a coplanar structure with an insulating interlayer and an amorphous silicon thin film transistor having an inverted staggered structure with a gate insulating layer are formed on one substrate and the insulating interlayer and the gate insulating layer are formed as the same layer, wherein a driving circuit is configured by the polycrystalline silicon thin film transistor and a photosensor is configured by the amorphous silicon thin film transistor.
  9. The passive optical sensor array of claim 8, wherein the one polycrystalline silicon thin film transistor and the one amorphous silicon thin film transistor are configured in each pixel.
  10. The active optical sensor array of claim 8, wherein the three polycrystalline silicon thin film transistors and the one amorphous silicon thin film transistor are configured in each pixel.
  11. The optical sensor array of any one of claims 8 to 10, wherein as a light source of the photosensor, an inorganic electroluminescence (EL) or an organic light-emitting diode (OLED) is used.
PCT/KR2011/008721 2010-11-15 2011-11-15 Thin film transistor substrate having hybrid cmos structure and optical sensor array using the substrate WO2012067409A2 (en)

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