WO2012060839A1

WO2012060839A1 - Advanced transistors with structured low dopant channels

Info

Publication number: WO2012060839A1
Application number: PCT/US2010/055560
Authority: WO
Inventors: Pushkar Ranade; Lucian Shifren
Original assignee: Suvolta, Inc.
Priority date: 2010-11-05
Filing date: 2010-11-05
Publication date: 2012-05-10
Also published as: KR20120060777A; KR101178016B1

Abstract

A field effect transistor structure and method includes a well doped to have a first concentration of a dopant and a lightly or substantially undoped channel region. A highly doped screening region is positioned between the well and a gate. A threshold voltage set region can be formed at least in part by dopant implant after dummy gate removal. This allows for low power and good performance transistors capable of being manufactured by widely available planar CMOS processes.

Description

Advanced Transistors with Structured Low Dopant Channels

Field of the Invention:

This disclosure relates to structures and processes for forming advanced transistors with improved operational characteristics, including low doped channels and processing that includes gate removal.

Background of the Invention:

Fitting more transistors onto a single die is desirable to reduce cost of electronics and improve their functional capability. A common strategy employed by semiconductor manufacturers is to simply reduce gate size of a field effect transistor (FET), and proportionally shrink area of the transistor source, drain, and required interconnects between transistors. However, a simple proportional shrink is not always possible, in part because of what are known as "short channel effects". Short channel effects are particularly acute when channel length under a transistor gate is comparable in magnitude to depletion depth of an operating transistor, and include reduction in threshold voltage, severe surface scattering, drain induced barrier lowering (DIBL), source-drain punch through, and electron mobility issues. To try to continue downward scaling, semiconductor manufacturers have investigated high channel doping, retrograde doping, steep retrograde doping, and other advanced techniques, but making commercially practical transistor devices with gate length under 100 nanometers (nanoscale) is becoming increasingly difficult.

Many semiconductor manufacturers have attempted to avoid certain adverse short channel effects in transistors with nanoscale gate transistor sizes by employing new transistor types, including fully or partially depleted silicon on insulator (SOI) transistors. SOI transistors are built on a thin layer of silicon that overlies an insulator layer, and generally require VT setting channel implants or halo implants for operation. Unfortunately, creating a suitable insulator layer is expensive and difficult to accomplish. Early SOI devices were built on insulative sapphire wafers instead of silicon wafers, and are typically only used in specialty applications (e.g. military avionics or satellite) because of the high costs. Modern SOI technology can use silicon wafers, but require expensive and time consuming additional wafer processing steps to make an insulative silicon oxide layer that extends across the entire wafer below a surface layer of device-quality single-crystal silicon.

One common approach to making such a silicon oxide layer on a silicon wafer requires

high dose ion implantation of oxygen and high temperature annealing to form a buried oxide (BOX) layer in a bulk silicon wafer. Alternatively, SOI wafers can be fabricated by bonding a silicon wafer to another silicon wafer (a "handle" wafer) that has an oxide layer on its surface. The pair of wafers are split apart, using a process that leaves a thin

transistor quality layer of single crystal silicon on top of the BOX layer on the handle wafer. This is called the "layer transfer" technique, because it transfers a thin layer of silicon onto a thermally grown oxide layer of the handle wafer.

As would be expected, both BOX formation or layer transfer are costly manufacturing techniques with a relatively high failure rate. Accordingly, manufacture of SOI transistors is not an economically attractive solution for many leading manufacturers. When cost of transistor redesign to cope with "floating body" effects, the need to develop new SOI specific transistor processes, and other circuit changes is added to SOI wafer costs, it is clear that other solutions are needed.

Another possible advanced transistor that has been investigated uses multiple gate transistors that, like SOI transistors, minimize adverse scaling and short channel effects by having little or no doping in the channel. Commonly known as a finFET (due to a fin-like shaped channel partially surrounded by gates), use of finFET transistors has been proposed for transistors having 28 nanometer or lower transistor gate size. But again, like SOI transistors, while moving to a radically new transistor architecture solves some scaling, Vj, set point, and short channel effect issues, it creates others, requiring even more significant transistor layout redesign than SOI. Considering the likely need for complex non-planar transistor manufacturing techniques to make a finFET, and the unknown difficulty in creating a new process flow for finFET, manufacturers have been reluctant to invest in semiconductor fabrication facilities capable of making finFETs. Brief Description of the Drawings:

Fig. 1 illustrates a transistor with an improved dopant structure;

Fig. 2 is a flow diagram of a process for forming the transistor with improved dopant structure; and

Figs. 3-6 schematically illustrate a portion of the process flow. Detailed Description:

Nanoscale bulk CMOS transistors (those typically having a gate length less than 100 nanometers) are increasingly difficult to manufacture in part because VT scaling does not match VDD scaling. Normally, for transistors having a gate size greater than 100 nanometers, reduction in gate length of a transistor included a roughly proportional reduction in operating voltage VDD, which together ensured a roughly equivalent electrical field and operating characteristics. The ability to reduce the operating voltage VDD, depends in part on being able to accurately set the threshold voltage VT, but that has become increasingly difficult as transistor dimensions decrease because of a variety of factors, including, for example, Random Dopant Fluctuation (RDF). For transistors made using bulk CMOS processes, the primary parameter that sets the threshold voltage VT is the amount of dopants in the channel. In theory, this can be done precisely, such that the same transistors on the same chip will have the same V , but in reality the threshold voltages can vary significantly. This means that these transistors will not all switch on at the same time in response to the same gate voltage, and some may never switch on. For nanoscale transistors having a gate and channel length of 100 nm or less, RDF is a major determinant of variations in V_T, typically referred to as sigmaV_T or aVr, and the amount of oYy caused by RDF only increases as channel length decreases. An improved transistor manufacturable on bulk CMOS substrates using conventional planar CMOS processes is seen in Fig. 1 . A Field Effect Transistor (FET) 100 is configured to have greatly reduced short channel effects, along with an ability to precisely set threshold voltage Vt according to certain described embodiments. The FET 100 includes a gate electrode 102, source 104, drain 106, and a gate dielectric 108 positioned over a channel 1 10. In operation, the channel 1 10 is deeply depleted, forming what can be described as deeply depleted channel (DDC) as compared to conventional transistors, with depletion depth set in part by a highly doped screening region 1 12. While the channel 1 10 is substantially undoped, and positioned as illustrated above a highly doped screening region 1 12, it may include simple or complex layering with different dopant concentrations. This doped layering can include a threshold voltage set region 1 1 1 with a dopant concentration less than screening region 1 12, optionally positioned between the gate dielectric 108 and the screening region 1 12 in the channel 1 10. A threshold voltage set region 1 1 1 permits small adjustments in operational threshold voltage of the FET 100, while leaving the bulk of the channel 1 10 substantially undoped. In particular, that portion of the channel 1 10 adjacent to the gate dielectric 108 should remain undoped. Additionally, a punch through suppression region 1 13 is formed beneath the screening region 1 12. Like the threshold voltage set region 1 1 1 , the punch through suppression region 1 13 has a dopant concentration less than screening region 1 12, while being higher than the overall dopant concentration of a lightly doped P-well substrate 1 14.

In operation, a bias voltage 122 VBS may be applied to source 104 to further modify operational threshold voltage, and P+ terminal 126 can be connected to P-well 1 14 at connection 124 to close the circuit. The gate stack includes a gate electrode 102, gate contact 1 18 and a gate dielectric 108. Gate spacers 130 are included to separate the gate from the source and drain, and optional Source/Drain Extensions (SDE) 132, or "tips" extend the source and drain under the gate spacers and gate dielectric 108, somewhat reducing the gate length and improving electrical characteristics of FET 100. In this exemplary embodiment, the FET 100 is shown as an N-channel transistor having a source and drain made of N-type dopant material, formed upon a substrate as P-type doped silicon substrate providing a P-well 1 14 formed on a substrate 1 16. However, it will be understood that, with appropriate change to substrate or dopant material, a non-silicon P-type semiconductor transistor formed from other suitable substrates such as Gallium Arsenide based materials may be substituted. The source 104 and drain 106 can be formed using conventional dopant implant processes and materials, and may include, for example, modifications such as stress inducing source/drain structures, raised and/or recessed source/drains, asymmetrically doped, counter-doped or crystal structure modified source/drains, or implant doping of source/drain extension regions according to LDD (low doped drain) techniques. Various other techniques to modify source/drain operational characteristics can also be used, including, in certain embodiments, use of heterogeneous dopant materials as compensation dopants to modify electrical characteristics.

The gate electrode 102 can be formed from conventional materials, preferably including, but not limited to, metals, metal alloys, metal nitrides and metal silicides, as well as laminates thereof and composites thereof. In certain embodiments the gate electrode 102 may also be formed from polysilicon, including, for example, highly doped polysilicon and polysilicon-germanium alloy. Metals or metal alloys may include those containing aluminum, titanium, tantalum, or nitrides thereof, including titanium containing compounds such as titanium nitride. Formation of the gate electrode 102 can include silicide methods, chemical vapor deposition methods and physical vapor deposition methods, such as, but not limited to, evaporative methods and sputtering methods. Typically, the gate electrode 102 has an overall thickness from about 1 to about 500 nanometers.

The gate dielectric 108 may include conventional dielectric materials such as oxides, nitrides and oxynitrides. Alternatively, the gate dielectric 108 may include generally higher dielectric constant dielectric materials including, but not limited to hafnium oxides, hafnium silicates, zirconium oxides, lanthanum oxides, titanium oxides, barium-strontium-titanates and lead-zirconate-titanates, metal based dielectric materials, and other materials having dielectric properties. Preferred hafnium- containing oxides include Hf0₂, HfZrO_x, HfSiO_x, HfTiO_x, HfA10_x, and the like. Depending on composition and available deposition processing equipment, the gate dielectric 108 may be formed by such methods as thermal or plasma oxidation, nitridation methods, chemical vapor deposition methods (including atomic layer deposition methods) and physical vapor deposition methods. In some embodiments, multiple or composite layers, laminates, and compositional mixtures of dielectric materials can be used. For example, a gate dielectric can be formed from a Si0₂- based insulator having a thickness between about 0.3 and 1 nm and the hafnium oxide based insulator having a thickness between 0.5 and 4nm. Typically, the gate dielectric 108 has an overall thickness from about 0.5 to about 5 nanometers.

The channel 110 is formed below the gate dielectric 108 and above the highly doped screening region 1 12. The channel 1 10 also contacts and extends between, the source 104 and the drain 106. Preferably, the channel region includes substantially undoped silicon having a dopant concentration less than 5 x 10 dopant atoms per cm adjacent or near the gate dielectric 108. Channel thickness can typically range from 5 to 50 nanometers. In certain embodiments the channel 1 10 is formed by epitaxial growth of pure or substantially pure silicon on the screening region. As disclosed, the threshold voltage set region 1 1 1 is positioned above screening region 1 12, and is typically formed as a thin doped region or layer. In certain embodiments, delta doping, controlled in-situ deposition, or atomic layer deposition can be used to form at least one dopant plane that is substantially parallel and vertically offset with respect to the screening region 1 12. Suitably varying dopant concentration, thickness, and separation from the gate dielectric and the screening region allows for controlled slight adjustments of threshold voltage in the operating FET 100. In certain embodiments, the threshold voltage set region 1 1 1 is doped to have a concentration between about 1 x 10¹⁸ dopant atoms per cm³ and about 1 x 10¹⁹ dopant atoms per cm³. In certain embodiments, the threshold voltage set region 111 is formed at a depth of 5 nanometers or greater from the gate dielectric 108, providing a high mobility channel with little or no dopant scattering centers. The threshold voltage set region 1 1 1 can be formed by several different processes, including 1) in- situ epitaxial doping, 2) epitaxial growth of a thin layer of silicon followed by a tightly controlled dopant implant (e.g. delta doping), 3) epitaxial growth of a thin layer of silicon followed by dopant diffusion of atoms from the screening region 112, 4) post-dummy gate removal and precision implants, 5) by any combination of these processes (e.g. epitaxial growth of silicon followed by both dopant implant and diffusion from the screening layer 1 12, or delta doping followed by precision implants after dummy gate removal) .

Position of a highly doped screening region 1 12 typically sets depth of the depletion zone of an operating FET 100. Advantageously, the screening region 1 12 (and associated depletion depth) are set at a depth that ranges from one comparable to the gate length (Lg/1) to a depth that is a large fraction of the gate length (Lg/5). In preferred embodiments, the typical range is between Lg/3 to Lg/1.5. Devices having an Lg/2 or greater are preferred for extremely low power operation, while digital or analog devices operating at higher voltages can often be formed with a screening region between Lg/5 and Lg/2. For example, a transistor having a gate length of 32 nanometers could be formed to have a screening region that has a peak dopant density at a depth below the gate dielectric of about 16 nanometers (Lg/2), along with a voltage threshold set at peak dopant density at a depth of 8 nanometers (Lg/4).

In certain embodiments, a screening region and /or layer 112 is doped to have a concentration between about 5 x 10 dopant atoms per cm and about 1 x 10 dopant atoms per cm³, significantly more than the dopant concentration of the undoped channel, and at least slightly greater than the dopant concentration of the optional voltage threshold set region 11 1. As will be appreciated, exact dopant concentrations and screening region depths can be modified to improve desired operating characteristics of FET 100, or to take in to account available transistor manufacturing processes and process conditions. To help control leakage, the punch through suppression region 1 13 is formed beneath the screening region 112. Typically, the punch through suppression region 1 13 is formed by direct implant into a lightly doped well, but it can be formed by out diffusion from the screening region, in-situ growth, or other known process. Like the threshold voltage set region 1 1 1, the punch through suppression region 1 13 has a dopant concentration less than the screening region 112, typically set between about 1 x 10¹⁸ dopant atoms per cm³ and about 1 x 10¹⁹ dopant atoms per cm³. In addition, the punch through suppression region 1 13 dopant concentration is set higher than the overall dopant concentration of the well substrate. As will be appreciated, exact dopant concentrations and depths can be modified to improve desired operating characteristics of FET 100, or to take in to account available transistor manufacturing processes and process conditions.

Together, the structures and the methods of making the structures allow for FET transistors having both a low operating voltage and a low threshold voltage as compared to conventional nanoscale devices. Furthermore, DDC transistors can be configured to allow for the threshold voltage to be statically set with the aid of a voltage body bias generator. In some embodiments the threshold voltage can even be dynamically controlled, allowing the transistor leakage currents to be greatly reduced (by setting the voltage bias to upwardly adjust the T for low leakage, low speed operation), or increased (by downwardly adjusting the VT for high leakage, high speed operation). Ultimately, these structures and the methods of making structures provide for designing integrated circuits having FET devices that can be dynamically adjusted while the circuit is in operation. Thus, transistors in an integrated circuit can be designed with nominally identical structure, and can be controlled, modulated or programmed to operate at different operating voltages in response to different bias voltages, or to operate in different operating modes in response to different bias voltages and operating voltages. In addition, these can be configured post-fabrication for different applications within a circuit.

As will be appreciated, concentrations of atoms implanted or otherwise present in a substrate or crystalline layers of a semiconductor to modify physical and electrical characteristics of a semiconductor are be described in terms of physical and functional regions or layers. These may be understood by those skilled in the art as three- dimensional masses of material that have particular averages of concentrations. Or, they may be understood as sub-regions or sub-layers with different or spatially varying concentrations. They may also exist as small groups of dopant atoms, regions of substantially similar dopant atoms or the like, or other physical embodiments. Descriptions of the regions based on these properties are not intended to limit the shape, exact location or orientation. They are also not intended to limit these regions or layers to any particular type or number of process steps, type or numbers of layers (e.g., composite or unitary), semiconductor deposition, etch techniques, or growth techniques utilized. These processes may include epitaxially formed regions or atomic layer deposition, dopant implant methodologies or particular vertical or lateral dopant profiles, including linear, monotonically increasing, retrograde, or other suitable spatially varying dopant concentration. To ensure that desired dopant concentrations are maintained, various dopant anti-migration techniques, are contemplated, including low temperature processing, carbon doping, in-situ dopant deposition, and advanced flash or other annealing techniques. The resultant dopant profile may have one or more regions or layers with different dopant concentrations, and the variations in concentrations and how the regions or layers are defined, regardless of process, may or may not be detectable via techniques including infrared spectroscopy, Rutherford Back Scattering (RBS), Secondary Ion Mass Spectroscopy (SIMS), or other dopant analysis tools using different qualitative or quantitative dopant concentration determination methodologies.

Forming such a FET 100 is relatively simple compared to SOI or finFET transistors, since planar CMOS processing techniques can be readily adapted. However, maintaining a desired dopant profile can present challenges, since high temperatures during processing can promote movement of interstitially deposited dopants, and even relatively low temperatures, if maintained for an extended time, can promote diffusion of dopants from a screening region, for example, into the channel. Processes that delay some or all dopant implant to later stages in the transistor manufacture process, which typically have lower temperature, are helpful for limiting dopant migration that can adversely affect transistor operation. Further related technical details are discussed in US Patent Application No.12/708,497, titled "Electronic Devices and Systems, and Methods for Making and Using the Same", filed February 18, 2010, the disclosure of which is incorporated by reference herein.

Fig. 2 is a process flow diagram 300 illustrating one exemplary process for forming a transistor that reduces dopant migration by using a sacrificial dummy gate and a screening region suitable for different types of FET structures, including both analog and digital transistors. The process illustrated here is intended to be general and broad in its description in order not to obscure the inventive concepts, and more detailed embodiments and examples as set forth below. These along with other process steps allow for the processing and manufacture of integrated circuits that include DDC structured devices together with legacy devices, allowing for designs to cover a full range of analog and digital devices with improved performance and lower power. In Step 302, the process begins at the well formation, which may be one of many different processes according to different embodiments and examples. As indicated in 303, the well formation may be before or after STI (shallow trench isolation) formation 304, depending on the application and results desired. Boron (B), indium (I) or other P-type materials may be used for P-type implants, and arsenic (As) or phosphorous (P) and other N-type materials may be used for N-type implants. For the PMOS well implants, the P+ implant may be implanted within a range from 10 to 80keV, and at concentrations from 1 x 10 to 8 x 10 /cm . As+ may be implanted within a range of 5 to 60keV, and at concentrations from 1 x 10 to 8 x 10 /cm . For NMOS well implants, the boron implant B+ implant may be within a range of 0.5 to 5keV, and within a concentration range of 1 x 10 to 8 x 10 /cm . A germanium implant Ge+, may be performed within a range of 10 to 60keV, and at a concentration of 1 x 10¹⁴ to 5x10¹⁴ /cm². To reduce dopant migration, a carbon implant, C+ may be performed at a range of 0.5 to 5keV, and at a concentration of 1 x 10 to 8 x 10 /cm . Well implants may include sequential implant, and/or epitaxial growth and implant, of punch through suppression regions, with the screen regions having a higher dopant density than the punch through suppression region. In some embodiments the well formation 302 may include a beam line implant of Ge/B (N), As (P), followed by an epitaxial (EPI) pre-clean process, and followed finally non-selective blanket EPI deposition, as shown in 302A. Alternatively, the well may be formed using a plasma implant of B (N), As (P), followed by an EPI pre- clean, then finally a non-selective (blanket) EPI deposition, 302B. The well formation may alternatively include a solid-source diffusion of B(N), As(P), followed by an EPI pre-clean, and followed finally by a non-selective (blanket) EPI deposition, 302C. As yet another alternative, well formation may simply include deep well implants, followed by in-situ doped selective EPI of B (N), P (P). In other embodiments, only a punch through suppression region is deposited, or only a punch through suppression region and a screening region, with the threshold voltage set region being later implanted (after dummy gate removal). Embodiments described herein allow for any one of a number of devices configured on a common substrate with different well structures and according to different parameters.

Shallow trench isolation (STI) formation 304, which, again, may occur before or after well formation 302, may include a low temperature trench sacrificial oxide (TSOX) liner at a temperature lower than 900°C. The gate stack 306 is typically formed using polysilicon, polysilicon, amorphous silicon, or other suitable material capable of deposited, photo lithographically defined, etched, and/or removed and acts as a dummy gate that later in the process is removed and replaced with an alternative gate material.

Next, in step 308, Source/Drain tips may be implanted, or optionally may not be implanted depending on the application. The dimensions of the tips can be varied as required, and will depend in part on whether gate spacers (SPCR) are used. In one option, there may be no tip implant in 308 A. Next, in optional steps 310 and 312, PMOS or NMOS EPI layers may be formed in the source and drain regions as performance enhancers for creating strained channels. A gate-last module 314 allows for dummy gate removal, implants deep into the channel, and build-up of a new gate, typically a band edge metal or metal alloy. Gate last module processing begins with removal of polysilicon or other material forming the gate. This is better illustrated by Figs. 3-6, which show a pair of transistors 400, including a PMOS transistor 402 and an NMOS transistor 404 that have been formed by a process such as disclosed with respect to Fig. 2 and are ready for dummy gate removal in the gate last module processing step. In this example embodiment, the transistors 402 and 404 are formed on a P-type silicon substrate 406, and support a P-well 408 and N-well 410. While not required for all transistors, isolation and ability to bias selected wells is improved by provision on shallow N-well 412 and shallow P-well 414. Transistor isolation is provided in part by shallow trench isolation structures 416.

As seen in Figure 3, source and drains of the transistors 402 are formed from differentially doped multilayers 418 and 420. Transistor 402 also has channel tip structures 422, and a dummy gate 426 with sidewall spacers 424. Similarly, transistor 404 has differentially doped multilayers 428 and 430 to form sources and drain, along with channel tip structures 432, and a dummy gate 436 with sidewall spacers 434.

As seen in Figures 4-6, dummy gates 426 and 436 can be simultaneously removed, leaving respective gate regions 425 and 435. With the dummy gates removed, channels 427 and 437 can be deeply implanted with dopants, creating or augmenting a threshold voltage setting region, a screening region, or even a punch through suppression region. Dopant introduction must be carefully done to leave a substantially undoped region in contact with the gate, as previously described in connection with Fig. 1.

Preferred dopant implant processes include plasma doping, which is capable of providing tightly defined dopant profiles, while minimizing crystallographic damage. Plasma doping creates a pulse or "package" of dopants that is delivered to the silicon substrate within a narrowly defined energy range and time. Short pulse lengths and short plasma life time combine to minimize both particle nucleation and the risk of etching of pre-existing surface films. The plasma process can include long relaxation times after each pulse to allow stored charges to effectively drain away and reduce risk of dielectric damage. Alternatively, solid state doping or other advanced doping technique capable of maintaining low dopant concentration in the channel near the gate dielectric. After carefully controlled dopant implant, new gate stacks 460 and 464 can fill in the gate regions 425 and 435. In certain embodiments a high-k dielectric can be formed on the surface of the channel, along with a gate liner 458 and 462. Metal or metal alloy gates are preferred. Care is taken during these gate formation steps to maintain as low as temperature as feasible, which helps prevent channel dopant migration. Low temperature anneals can be used to activate dopants and remedy (by annealing) damage to the crystal structure caused by dummy gate removal and dopant implant.

While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific constructions and arrangements shown and described, since various other modifications may occur to those ordinarily skilled in the art. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

Claims:

1. A field effect transistor structure, comprising

a well doped to have a first concentration of a dopant,

a screening region positioned between the well and a gate and having a second concentration of dopant greater than 5 10 dopant atoms per cm , and

a threshold voltage set region formed at least in part by dopant implant after dummy gate removal.

2. The field effect transistor structure of claim 1, wherein dopants defining the threshold voltage set region is deposited by plasma doping.

3. The field effect transistor structure of claim 1 , wherein the threshold voltage set region is positioned in a channel defined between a source and a drain at a depth greater than 5 nanometers from a gate.

4. The field effect transistor structure of claim 1, wherein dopants are implanted between a source and a drain, and below a gate, both before dummy gate removal and after dummy gate removal.

5. The field effect transistor structure of claim 1, further comprising a channel doped to have a density less than about 5 x 10¹⁷ dopant atoms per cm³ adjacent to a gate dielectric.

6. A field effect transistor structure, comprising

a well doped to have a first concentration of a dopant,

a screening region positioned between the well and a gate and having a second concentration of dopant greater than 5 x 10¹⁸ dopant atoms per cm³ formed at least in part by dopant implant after dummy gate removal.

7. The field effect transistor structure of claim 6, further comprising a threshold voltage set region deposited between the screening region and the gate.

8. The field effect transistor structure of claim 6, further comprising a threshold voltage set region deposited between the screening region and the gate, wherein the threshold voltage set region is doped to have less than 5 x 10 dopant atoms per cm and positioned in a channel defined between a source and a drain at a depth greater than 5 nanometers from a gate.

9. A method for forming a field effect transistor structure, comprising the steps of forming a well doped to have a first concentration of a dopant,

removing a dummy gate

implanting a screening region into the well having a dopant concentration dopant of greater than 5 x 10¹⁸ dopant atoms per cm³ , and

reforming a gate having gate length Lg between a source and a drain, and above the screening region.

10. The method of claim 9 for forming a field effect transistor structure, wherein the screening region is implanted at a depth below the gate selected to be between about Lg/5 and about Lg/1.

1 1. The method of claim 9 for forming a field effect transistor structure, further comprising the step of forming a threshold voltage set region positioned in a channel defined between the source and the drain at a depth greater than 5 nanometers from a gate.

12. The method of claim 9 for forming a field effect transistor structure, wherein dopants are implanted between a source and a drain, and below a gate, both before dummy gate removal and after dummy gate removal.

13. The method of claim 9 for forming a field effect transistor structure wherein a channel defined between the source and the drain has a dopant density less than about 5 x 10¹⁷ dopant atoms per cm³ adjacent to a gate dielectric.

14. The method of claim 9 wherein the reformed gate is metal.