KR101178016B1 - Advanced transistors with structured low dopant channels - Google Patents

Abstract

Field effect transistors and methods include wells doped with a first concentration of dopant, and weakly or substantially undoped channel regions. Highly doped screening regions are located between the wells and the gates. The threshold voltage setting region may be formed at least in part by dopant implantation after removing the dummy gate. This allows for low power and good performance transistors that can be fabricated by widely available planar CMOS processes.

Description

ADVANCED TRANSISTORS WITH STRUCTURED LOW DOPANT CHANNELS

This disclosure relates to structures and processes for forming advanced transistors with improved operating characteristics, including processing including lightly doped channels, and gate removal.

It is desirable to fit more transistors on one die to reduce the cost of electronic devices and improve their functional capabilities. A common strategy used by semiconductor manufacturers is to simply reduce the gate size of field effect transistors (FETs) and proportionately reduce the area of transistor sources, drains, and interconnections needed between transistors. However, simple proportional reduction is not always possible due in part to what is known as the "short channel effect". The short channel effect is particularly severe when the channel length below the transistor gate is similar in size and depth to the depletion of the transistor in operation, reducing threshold voltages, severe surface scattering, drain induced barrier lowering, and source- Drain punch through, and electron mobility problems. To continue proportional reduction, semiconductor manufacturers have studied high-density channel doping, retrograde doping, steep regression doping, and other advanced techniques, but commercially with gate lengths of less than 100 nanometers (nanoscale). It is becoming more difficult to manufacture practical transistor devices.

Many semiconductor manufacturers have attempted to prevent certain negative short channel effects in transistors with nanoscale gate transistor size by using new transistor types, including completely or partially depleted silicon on insulator (SOI) transistors. SOI transistors require a channel set V _T injection or halo implant to a thin layer, typically operate are built on top of the silicon in the upper insulating layer. Unfortunately, creating a suitable insulating layer is expensive and difficult to complete. Early SOI devices were built on insulating sapphire wafers instead of silicon wafers and are typically only used in specialized applications (eg, military avionics or satellites) because of their high cost. Modern SOI techniques can use silicon wafers, but require expensive and time-consuming additional wafer processing steps to fabricate an insulating silicon oxide layer across the wafer under the surface layer of device quality single crystal silicon.

One common approach to fabricating such silicon oxide layers on silicon wafers requires high capacity ion implantation and high temperature annealing of oxygen to form an oxide (BOX) layer buried in the bulk silicon wafer. Shall be. Alternatively, SOI wafers can be fabricated by bonding the silicon wafer to another silicon wafer (“handle” wafer) having an oxide layer on its surface. The pairs of wafers are separated using a process that leaves a thin transistor quality layer of monocrystalline silicon over the BOX layer on the handle wafer. This is called a "layer transfer" technique because it transfers a thin layer of silicon over the thermally grown oxide layer of the handle wafer.

As can be expected, both BOX formation or layer transfer are expensive manufacturing techniques with relatively high failure rates. Thus, for many major manufacturers, the manufacture of SOI transistors is not an economically attractive solution. If the cost of redesigning the transistor to address the "floating body" effect, the need to develop new SOI specific transistor processes, and other circuit modifications added to the SOI wafer cost, it is clear that other solutions are needed.

Other possible advanced transistors that have been studied use multiple gate transistors, similar to SOI transistors, with minimal or no doping in the channel, thereby minimizing adverse scaling and short channel effects. In general, the use of finFET transistors, known as finFETs (due to fin shaped channels partially surrounded by gates), have been proposed for transistors having transistor gate sizes of 28 nanometers or less. However, similar to SOI transistors, moving to a fundamentally new transistor architecture solves some scaling, V _T , set point, and short channel effect problems, but it causes other problems that make the transistor more prominent than SOI. Requires layout redesign. Given the need for complex non-planar transistor fabrication techniques to fabricate finFETs and the unknown difficulties in creating new process flows for finFETs, manufacturers are looking to invest in semiconductor manufacturing facilities that can fabricate finFETs. Hesitate.

1 shows a transistor having an improved dopant structure.
2 is a flow chart of a process for forming a transistor having an improved dopant structure.
3 through 6 schematically illustrate portions of a process flow.

Nanoscale bulk CMOS transistors (typically with gate lengths less than 100 nanometers) are increasingly difficult to fabricate, in part because V _T scaling does not match V _DD scaling. Typically, for transistors with a gate size greater than 100 nanometers, the reduction in the gate length of the transistor included a roughly proportional reduction in the operating voltage V _DD , which together ensures approximately the same electric field and operating characteristics. The ability to reduce the operating voltage V _DD depends in part on being able to accurately set the threshold voltage V _T , but as transistor size decreases, it becomes more difficult because of various factors, including, for example, RDF (Random Dopant Fluctuation). For transistors fabricated using bulk CMOS processes, the main parameter that sets the threshold voltage V _T is the amount of dopant in the channel. In theory, this can be done exactly so that the same transistors on the same chip have the same V _T , but in reality the threshold voltage can vary significantly. This means that these transistors are not all on at the same time in response to the same gate voltage, and some transistors may never be on. For the nano-scale transistor having a gate and a channel length of no more than 100 nm, RDF is typically Sigma V _T or σV and _T important determinant of change of V _T that are named, in the σV _T caused by the RDF amount of channel length Only increases with decrease.

An improved transistor manufacturable on bulk CMOS substrates using conventional planar CMOS processes is shown in FIG. 1. The field effect transistor (FET) 100 is configured to have the ability to accurately set the threshold voltage V _T in accordance with certain described embodiments, with greatly reduced short channel effects. FET 100 includes a gate electrode 102, a source 104, a drain 106, and a gate dielectric 108 positioned over the channel 110. In operation, channel 110 is deeply depleted and forms what can be described as a deeply depleted channel (DDC) compared to conventional transistors, the depletion depth being partially doped screening region ( 112). Channel 110 is substantially non-doped and is positioned above highly doped screening region 112 as illustrated, but it may comprise simple or complex layering with different dopant concentrations. This doped stack includes a threshold voltage setting region 111 having a lower dopant concentration than the screening region 112 (optionally located between the screening region 112 and the gate dielectric 108 in the channel 110). can do. Threshold voltage setting region 111 allows small adjustments to the operating threshold voltage of FET 100 while leaving the bulk of channel 110 substantially undoped. In particular, that portion adjacent to the gate dielectric 108 of the channel 110 should remain undoped. In addition, a punch through suppression region 113 is formed just below the screening region 112. Similar to the threshold voltage setting region 111, the punch through suppression region 113 has a dopant concentration that is higher than the overall dopant concentration of the slightly doped P-well substrate 114 but lower than the screening region 112.

In operation, a bias voltage 122 V _BS may be applied to the source 104 to further modify the operating threshold voltage, and a P + terminal 126 may be applied to the P-well 114 at the connection 124 to close the circuit. Can be connected. The gate stack includes a gate electrode 102, a gate contact 118 and a gate dielectric 108. Gate spacers 130 are included to separate the gate from the source and drain, and optional source / drain extensions (SDE) 132, or “tips”, source below the gate spacers and gate dielectric 108. And extending the drain to slightly reduce the gate length and improve the electrical characteristics of the FET 100.

In this exemplary embodiment, the FET 100 has an N channel having a source and a drain made of N type dopant material formed over the substrate as a P type doped silicon substrate providing a P-well 114 formed over the substrate 116. It is shown as a transistor. However, it will be appreciated that a non-silicon P type semiconductor transistor formed from other suitable substrates, such as gallium arsenide based materials, with suitable modifications to the substrate or dopant material may be substituted. Source 104 and drain 106 may be formed using conventional dopant implantation processes and materials, such as, for example, stress-induced source / drain structures, raised or recessed source / It may include changes such as draining, asymmetrically doped, counter doped, or modified source / drain crystal structures, or implantation doping of source / drain extension regions according to low doped drain (LDD) techniques. In certain embodiments, other various techniques for modifying source / drain operating characteristics may also be used, including the use of heterogeneous dopant materials as compensation dopants for modifying electrical characteristics.

Gate electrode 102 may be formed from conventional materials, including but not limited to metals, metal alloys, metal nitrides, and metal silicides, as well as stacks and mixtures thereof. In certain embodiments, gate electrode 102 may also be formed from polysilicon including, for example, heavily doped polysilicon and polysilicon-germanium alloys. Metals or metal alloys may include aluminum, titanium, tantalum, or those containing their nitrides, which include compounds containing titanium such as titanium nitride. Formation of the gate electrode 102 may include physical vapor deposition methods such as, but not limited to, silicide methods, chemical vapor deposition methods, and evaporation methods and sputtering methods. Typically, gate electrode 102 has a total thickness of about 1 to about 500 nanometers.

Gate dielectric 108 may include conventional dielectric materials such as oxides, nitrides, and oxynitrides. Alternatively, gate dielectric 108 may be hafnium oxide, hafnium silicide, zirconium oxide, lanthanum oxide, titanium oxide, barium-strontium-titanate and lead-zirconate-titanate, metal based dielectric materials, and dielectric It may include dielectric materials having generally higher dielectric constants, including but not limited to other materials having properties. Preferred hafnium containing oxides include HfO ₂ , HfZrO _x , HfSiO _x , HfTiO _x , HfAlO _x , and the like. Depending on the composition, and available deposition processing equipment, the gate dielectric 108 may be subjected to methods such as thermal or plasma oxidation, nitriding methods, chemical vapor deposition methods (including atomic layer deposition method), and physical vapor deposition methods. It can be formed by. In some embodiments, composition mixtures of multiple or composite layers, laminates, and dielectric materials may be used. For example, the gate dielectric may be formed from a SiO ₂ based insulator having a thickness between about 0.3 and 1 nm and a hafnium oxide based insulator having a thickness between 0.5 and 4 nm. Typically, gate dielectric 108 has a total thickness of about 0.5 to about 5 nanometers. Channel 110 is formed below gate dielectric 108 and above heavily doped screening region 112. Channel 110 also abuts and extends between source 104 and drain 106. Preferably, the channel region comprises substantially undoped silicon having a dopant concentration lower than 5 × 10 ¹⁷ dopant atoms / cm ³ , adjacent or near the gate dielectric 108. Channel thicknesses can typically range from 5 to 50 nanometers. In certain embodiments, channel 110 is formed by epitaxial growth of pure or substantially pure silicon over the screening area.

As disclosed, the threshold voltage setting region 111 is located above the screening region 112 and is typically formed as a thin doped region or layer. In certain embodiments, delta doping, controlled in-situ deposition, or atomic layer deposition to form at least one dopant face that is substantially parallel and vertically offset relative to screening region 112. This can be used. Appropriately varying dopant concentrations, thicknesses, and separations from the gate dielectric and screening regions allow controlled slight adjustment of the threshold voltage at the FET 100 in operation. In certain embodiments, the threshold voltage setting region 111 is doped to have a concentration between about 1 × 10 ¹⁸ dopant atoms / cm ³ and about 1 × 10 ¹⁹ dopant atoms / cm ³ . In certain embodiments, the threshold voltage setting region 111 is formed at a depth of at least 5 nanometers from the gate dielectric 108 to provide a high mobility channel with little or no dopant scattering centers. Threshold voltage setting region 111 includes 1) in-situ epitaxial doping, 2) epitaxial growth of a thin layer of silicon followed by strictly controlled dopant implantation (e.g., delta doping), 3) epitaxial thin layer of silicon. Dopant diffusion of atoms from the screening region 112 following tactical growth, 4) precision implantation after dummy gate removal, 5) any combination of these processes (e.g., dopant implantation and screening layer 112 following epitaxial growth of silicon) Diffusion), or precision implantation after delta doping followed by dummy gate removal).

The location of the heavily doped screening region 112 typically sets the depth of the depletion region of the FET 100 in operation. Advantageously, the screening area 112 (and associated depletion depth) is set at a depth ranging from a depth comparable to the gate length Lg / 1 to a depth that is a large fraction Lg / 5 of the gate length. In preferred embodiments, a typical range is between Lg / 3 and Lg / 1.5. Devices with Lg / 2 or higher are desirable for extremely low power operation, and digital or analog devices operating at higher voltages can often be formed with screening areas between Lg / 5 and Lg / 2. For example, a transistor with a gate length of 32 nanometers has a maximum at a depth of 8 nanometers (Lg / 4), with a screening area having a maximum dopant density at a depth of about 16 nanometers (Lg / 2) below the gate dielectric. It may be formed to have a threshold voltage set at the dopant density.

In certain embodiments, the screening region and / or layer 112 may have a concentration between about 5 × 10 ¹⁸ dopant atoms / cm ³ and about 1 × 10 ²⁰ dopant atoms / cm ³ (significantly greater than the dopant concentration of the undoped channel). High and doped to have an optional threshold voltage setting region 111 at least slightly larger than the dopant concentration. As will be appreciated, the correct dopant concentration and screening area depth can be modified to improve the desired operating characteristics of the FET 100 or to account for available transistor fabrication processes and process conditions.

To aid in control leakage, a punch through suppression region 113 is formed below the screening region 112. Typically, the punch through suppression region 113 is formed by direct injection into a lightly doped well, but it may be formed by diffusion from the screening region, in-situ growth, or other known process. Similar to the threshold voltage setting region 111, the punch through suppression region 113 has a lower dopant concentration than the screening region 112, and typically has about 1 × 10 ¹⁸ dopant atoms / cm ³ and about 1 × 10 ¹⁹ dopant Is set between atoms / cm ³ . In addition, the punch through suppression region 113 dopant concentration is set higher than the total dopant concentration of the well substrate. As will be appreciated, the correct dopant concentration and depth can be modified to improve the desired operating characteristics of the FET 100 or to account for available transistor fabrication processes and process conditions.

The structures and methods for fabricating the structures together allow for FET transistors having lower operating voltage and lower threshold voltage compared to conventional nanoscale devices. Moreover, DDC transistors can be configured to allow the threshold voltage to be set statistically with the help of a voltage body bias generator. In some embodiments, the threshold voltage may be dynamically controlled and the transistor leakage current is greatly reduced (by setting the voltage bias to adjust V _T upward for low leakage, low speed operation) or increased (high leakage). , By adjusting V _T downward for high speed operation). Ultimately, these structures and methods for fabricating them provide for designing integrated circuits with FET devices that can be dynamically adjusted while the circuit is operating. Thus, transistors in an integrated circuit can be designed with nominally the same structure, operating at different operating voltages in response to different bias voltages, or different operating modes in response to different bias voltages and operating voltages. It can be controlled, adjusted, or programmed to operate at. In addition, they can be configured after manufacture for other applications in the circuit.

As will be appreciated, the concentration of atoms injected or otherwise present in the substrate or crystal layers of the semiconductor to modify the physical and electronic properties of the semiconductor is described with respect to the physical and functional regions or layers. These can be understood by those skilled in the art as three-dimensional chunks of material with specific concentration averages. Or they can be understood as sub-regions or sub-layers having different or spatially varying concentrations. They may also exist as small groups of dopant atoms, regions of substantially similar dopant atoms or the like, or other physical embodiments. The description of the regions based on these characteristics is not intended to limit the shape, exact position or orientation. They are also intended to limit these areas or layers to any particular kind or number of process steps, kind or number of layers (eg complex or unit), semiconductor deposition, etch techniques, or growth techniques used. It doesn't work. Such processes may include epitaxially formed regions or atomic layer deposition, dopant implantation methods or a particular vertical or horizontal dopant profile (including linear, monotonically increasing, degenerating, or other suitable spatially varying dopant concentrations). Can be. To ensure that the desired dopant concentration is maintained, various anti-migration techniques are anticipated, including low temperature processing, carbon doping, in-situ dopant deposition, and advanced flash or other annealing techniques. The resulting dopant profile may have one or more regions or layers with different dopant concentrations, and the change in concentration and how the regions or layers are defined, regardless of process, infrared spectroscopy, RBS (Rutherford) It may or may not be detectable using Back Scattering, Secondary Ion Mass Spectroscopy (SIMS), or other dopant analysis means using other qualitative or quantitative dopant concentration determination methods.

Forming such FET 100 is relatively simple compared to SOI or finFET transistors because planar CMOS processing techniques can be easily adapted. However, high temperatures during processing may facilitate the movement of deposited dopants between gratings and, if even relatively low temperatures are maintained for extended periods of time, may promote the diffusion of dopants from the screening region, for example into the channel. However, maintaining the desired dopant profile can present a challenging challenge. Processes that defer some or all of the dopant implantation into later steps (typically having a lower temperature) of the transistor fabrication process are useful to limit dopant migration that may adversely affect transistor operation. Related technical details are discussed in US Patent Application No. 12 / 708,497, "Electronic Devices and Systems, and Methods for Making and Using the Same," filed February 18, 2010, the disclosure of which is incorporated herein by reference.

2 is a process flow diagram 300 illustrating one exemplary process for forming a transistor that reduces dopant movement by using a screening region and a sacrificial dummy gate suitable for several types of FET structures, including both analog and digital transistors. )to be. In order not to obscure the inventive concepts and more detailed embodiments and examples as set forth below, the process shown herein is intended to be generic and broad in its description. Together with other process steps, these allow for the processing and fabrication of integrated circuits including DDC structure devices along with legacy devices, which covers a full range of analog and digital devices with improved performance and lower power. Allow designs.

In step 302, the process begins with well formation, which may be one of many different processes in accordance with different embodiments and examples. As shown at 303, well formation may be before or after shallow trench isolation (STI) formation 304, depending on the application and desired results. Boron (B), indium (I) or other P type materials may be used for P type implantation, and arsenic (As) or phosphorus (P) and other N type materials may be used for N type implantation. For PMOS well implantation, P + implantation can be implanted in the range of 10 to 80 keV, and in the concentration range of 1 × 10 ¹³ to 8 × 10 ¹³ / cm ² . As + may be injected in the range of 5 to 60 keV and in the concentration range of 1 × 10 ¹³ to 8 × 10 ¹³ / cm ² . For NMOS well implantation, boron implantation B + may be in the range of 0.5 to 5 keV, and in the concentration range of 1 × 10 ¹³ to 8 × 10 ¹³ / cm ² . Germanium implantation Ge + may be carried out in the range of 10 to 60 keV, and at a concentration of 1 × 10 ¹⁴ to 5 × 10 ¹⁴ / cm ² . To reduce dopant migration, carbon injection, C +, can be performed in the range of 0.5 to 5 keV, and in the concentration range of 1 × 10 ¹³ to 8 × 10 ¹³ / cm ² . Well implantation may include sequential implantation of punch through suppression regions, and / or epitaxial growth and implantation, where the screen regions have a higher dopant density than the punch through suppression region.

In some embodiments, as shown in 302A, the well formation 302 may be an epitaxial (EPI) pre-clean process following beam line injection of Ge / B (N), As (P), And finally non-selective blanket EPI deposition. Alternatively, the wells may be formed using plasma injection of B (N), As (P) followed by EPI preclean and then finally non-selective (blanket) EPI deposition (302B). Well formation may alternatively include solid source diffusion of B (N), As (P) followed by EPI preclean, and finally non-selective (blanket) EPI deposition (302C). As another alternative, well formation may simply comprise doped phosphorus selective EPI of B (N), P (P) followed by deep well implantation. In other embodiments, only punch through suppression regions are deposited, or only punch through suppression regions and screening regions are deposited, and threshold voltage setting regions are subsequently implanted (after dummy gate removal). Embodiments described herein allow any one of a number of devices configured on a common substrate with different well structures according to different parameters.

Shallow trench isolation (STI) formation 304, which may occur before or after well formation 302, may include a low temperature trench sacrificial oxide (TSOX) liner at a temperature lower than 900 ° C. Typically, gate stack 306 is formed using polysilicon, amorphous silicon, or other suitable material that can be deposited, photolithographically defined, etched, and / or removed, and later removed in the process to provide alternatives. It acts as a dummy gate that is replaced with a conventional gate material.

Next, in step 308, the source / drain tips may be injected, or optionally not depending on the application. The size of the tips may vary as required and will depend in part on whether a gate spacer (SPCR) is used. In one option, there may be no tip injection in 308A. Next, in optional steps 310 and 312, PMOS or NMOS EPI layers may be formed in the source and drain regions as a performance enhancing material for creating the strained channel. Gate-last module 314 allows for dummy gate removal, deep implantation in the channel, and construction of new gates (typically band edge metal or metal alloys).

Gate last module processing begins with the removal of polysilicon or other material forming the gate. This is better illustrated in Figures 3-6, which are formed by a process such as that described with respect to Figure 2, which includes a PMOS transistor 402 and an NMOS transistor 404 prepared for dummy gate removal in the gate last module processing step. A pair of transistors 400 is shown. In this embodiment, transistors 402 and 404 are formed over P type silicon substrate 406 and support P well 408 and N well 410. Although not required for all transistors, the ability to isolate and bias selected wells is improved by providing a shallow N well 412 and a shallow P well 414. Transistor isolation is provided in part by shallow trench isolation (STI) structures 416.

As shown in FIG. 3, the source and drain of transistor 402 are formed from differently doped multilayers 418 and 420. Transistor 402 also has a dummy gate 426 having channel tip structures 422, and sidewall spacers 424. Similarly, transistor 404 has a dummy gate 436 having channel tip structures 432 and sidewall spacers 434 along with differently doped multilayers 428 and 430 to form a source and a drain. Has

As shown in FIGS. 4-6, dummy gates 426 and 436 may be removed at the same time, leaving corresponding gate regions 425 and 435. As the dummy gates are removed, the channels 427 and 437 can be deeply implanted with dopants, creating or increasing even a threshold voltage setting region, a screening region, or a punch through suppression region. As previously described with respect to FIG. 1, dopant introduction must be carefully implemented to leave a substantially undoped region in contact with the gate.

Preferred dopant implant processes include plasma doping, which can provide a strictly defined dopant profile while minimizing crystallographic damage. Plasma doping produces a pulse or "package" of dopants applied to the silicon substrate within a narrowly defined energy range and time. The short pulse length and short plasma lifetime combine to minimize particle nucleation and the risk of etching existing surface films. The plasma process may include a long relaxation time after each pulse to allow the stored charges to be effectively released and reduce the risk of dielectric damage. Alternatively, solid state doping or other advanced doping techniques capable of maintaining low dopant concentrations in channels close to the gate dielectric.

After carefully controlled dopant implantation, new gate stacks 460 and 464 can fill the gate regions 425 and 435. In certain embodiments, a high-k dielectric may be formed over the surface of the channel with gate liners 458 and 462. Metal or metal alloy gates are preferred. Care is taken to keep the temperature as low as possible during these gate forming steps, which helps to prevent channel dopant movement. Low temperature annealing may be used to activate the dopants and to remove (by annealing) damage to the crystal structure caused by dummy gate removal and dopant implantation.

While specific representative embodiments have been described and illustrated in the accompanying drawings, the embodiments are merely illustrative and not restrictive to the broad invention, as various other modifications will occur to those skilled in the art. It will be understood that it is not limited to the specific structures and arrangements shown and described. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims (14)

As a method for forming a field effect transistor structure,
Forming a well doped with a first concentration of dopant,
Removing the dummy gate,
Implanting a screening region into the well having a second dopant concentration of greater than 5 x 10 ¹⁸ dopant atoms / cm ³ , wherein the screening region sets the depth of a depletion region for the transistor structure; and
Reforming a gate having a gate length Lg between a source and a drain and over the screening region
Field effect transistor structure forming method comprising a. The method of claim 1,
And wherein said screening region is implanted below said gate at a depth selected to be between Lg / 5 and Lg / 1. The method of claim 1,
Forming a separate threshold voltage setting region over the screening region between the source and the drain at a depth of at least 5 nanometers from a gate. The method of claim 3,
And the threshold voltage setting region has a lower dopant concentration than the screening region. The method of claim 1,
A method of forming a field effect transistor structure before and after dummy gate removal, dopants are implanted between the source and drain and below the gate. The method of claim 1,
And a channel defined between the source and the drain has a dopant density of less than 5 x 10 ¹⁷ dopant atoms / cm ³ adjacent a gate dielectric. The method of claim 1,
And wherein the re-formed gate is a metal. The method of claim 1,
Forming a undoped epitaxial channel layer over the screening region, wherein the gate is formed again on the undoped epitaxial channel layer. The method of claim 1,
Forming a punch through suppression region in the well, wherein the punch through suppression region is located below the screening region, and the screening region is higher dopant than the punch through suppression region. A method of forming a field effect transistor structure having a concentration. 10. The method of claim 9,
And wherein said punch through suppression region has a higher dopant concentration than said well. delete delete delete delete

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