WO2012039174A1 - Gate drive circuit of semiconductor switching device - Google Patents

Gate drive circuit of semiconductor switching device Download PDF

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Publication number
WO2012039174A1
WO2012039174A1 PCT/JP2011/064916 JP2011064916W WO2012039174A1 WO 2012039174 A1 WO2012039174 A1 WO 2012039174A1 JP 2011064916 W JP2011064916 W JP 2011064916W WO 2012039174 A1 WO2012039174 A1 WO 2012039174A1
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Prior art keywords
negative bias
mosfet
semiconductor switching
channel mosfet
switching element
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PCT/JP2011/064916
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French (fr)
Japanese (ja)
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達也 北村
中武　浩
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三菱電機株式会社
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Priority to JP2012534951A priority Critical patent/JP5400968B2/en
Publication of WO2012039174A1 publication Critical patent/WO2012039174A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H03K2017/066—Maximizing the OFF-resistance instead of minimizing the ON-resistance
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K2017/6875—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors using self-conductive, depletion FETs

Definitions

  • the present invention relates to a gate driving circuit for driving a semiconductor switching element, and more particularly to a gate driving circuit for a semiconductor switching element capable of switching the semiconductor switching element with high reliability.
  • a semiconductor switching element MOSFET Metal-Oxide-Semiconductor, Field-Effect Transistor
  • IGBT Insulated Gate Bipolar Transistor
  • the conventional gate drive circuit includes a negative bias circuit including a capacitor connected to the gate terminal of the low-voltage side arm switch, and is generated in the negative bias circuit capacitor when the low-voltage side arm switch is turned on.
  • a technique is shown in which a voltage is applied as a negative bias when a low-voltage side arm switch is turned off (for example, Patent Document 1).
  • Patent Document 2 a gate drive circuit provided with a negative bias circuit so as to avoid an increase in loss of an arm switch due to a change in power supply or a decrease in gate voltage is disclosed (for example, Patent Document 2).
  • Patent Document 2 when a MOSFET is used as an arm switch, the negative bias applied by the capacitor gradually decreases due to discharge and approaches the source potential of the driving MOSFET. Since there is no means for recovering the negative bias amount such as recharging the capacitor during the off-period of the driving MOSFET, it is likely to be erroneously turned on when noise is mixed when the negative bias is reduced. In particular, when a SiC-MOSFET having a low gate-source threshold voltage is used as the driving MOSFET, there is a problem that the possibility of erroneous turn-on due to noise is further increased because of its characteristics as compared with the conventional Si-MOSFET. there were.
  • the charging time of the capacitor also increases.Therefore, when switching at a high frequency, the charging time tends to be insufficient, and a sufficient amount of negative bias is applied. It becomes difficult to obtain.
  • the present invention solves the above-described problems, further improves the technique of Patent Document 2, has a function of quickly recovering a decrease in negative bias due to capacitor discharge, and a Si-MOSFET as a semiconductor switching element.
  • Another object of the present invention is to obtain a gate drive circuit of a semiconductor switching element that can perform high-frequency switching in a SiC-MOSFET and can prevent gate malfunction due to noise.
  • a gate driving circuit for a semiconductor switching element includes a buffer provided with an ON drive switch and an OFF drive switch for driving the semiconductor switching element, a negative bias generation unit, and a negative bias generation unit control circuit.
  • the negative bias generator is provided with two or more switching / charging circuits that are connected to the buffer OFF drive switch and generate a negative bias to be applied to the semiconductor switching element.
  • the generation unit applies a continuous negative bias to the semiconductor switching element by switching the system of two or more switching / charging circuits at least once by the negative bias generation unit control circuit during a period when the semiconductor switching element is OFF. Is.
  • the gate driving circuit of the semiconductor switching element according to the present invention adopts the above-described configuration, when the semiconductor switching element is OFF, two or more switching / charging circuit systems are continuously switched, and the semiconductor switching circuit is switched. A continuous and sufficient negative bias is applied to the element, and malfunction due to noise or the like can be prevented.
  • FIG. 3 is a diagram illustrating a gate drive circuit of the semiconductor switching element according to the first embodiment.
  • FIG. 4 is a diagram illustrating an example of a transient waveform of each part of the gate drive circuit of the semiconductor switching element according to the first embodiment. It is a schematic block diagram which shows the conventional gate drive circuit. It is a figure which shows the example of the transient waveform of each part of the conventional gate drive circuit.
  • FIG. 3 is a schematic configuration diagram showing the gate drive circuit of Patent Document 2 described above.
  • the gate drive circuit 100 a has a P-channel MOSFET 5 connected in series, a buffer 7 composed of an N-channel MOSFET 6, an anode connected to the source of the N-channel MOSFET 6, and a cathode connected to the source potential of the drive MOSFET 3.
  • the drive MOSFET 3 when the drive MOSFET 3 is turned off, the P-channel MOSFET 5 is turned off, the N-channel MOSFET 6 is turned on, and the N-channel MOSFET 17 is turned on, and the source potential of the drive MOSFET 3 (hereinafter referred to as Vs) is lowered by the charging voltage of the capacitor 16.
  • Vs the source potential of the drive MOSFET 3
  • Vgs the gate-source voltage
  • FIG. 4 shows an example of a transient waveform of the gate drive circuit 100a.
  • S1 is a switch state of the driving MOSFET 3
  • V1 is a drain potential of the N-channel MOSFET 17
  • V2 is a source potential of the N-channel MOSFET 6.
  • the driving MOSFET 3 is in the ON state
  • V1 is Vcc ⁇ Vzd.
  • V2 is Vf.
  • the capacitor 16 is charged with Vcc ⁇ Vzd ⁇ Vf.
  • Vgs is equal to Vcc.
  • Vgs obtains a negative bias of Vs ⁇ (Vcc ⁇ Vzd ⁇ Vf), which is a potential difference between V2 and Vs.
  • current flows through the path of the gate-source capacitance of the driving MOSFET 3, the gate resistor 9, the N-channel MOSFET 6, the capacitor 16, and the N-channel MOSFET 17, so that Vgs gradually increases.
  • the driving MOSFET 3 is in the ON state and the N-channel MOSFET 17 is turned off again, so that V1 rises and becomes Vcc ⁇ Vzd. V2 also becomes Vf again.
  • the negative bias applied when the drive MOSFET 3 is OFF gradually decreases as shown by the curve of Vgs in the period t2 in FIG. Since it becomes difficult to more reliably suppress the occurrence of malfunctions by increasing the length, a negative bias generation function that enables this is required.
  • FIG. 1 is a schematic configuration diagram showing a gate drive circuit 100 according to the first embodiment.
  • a gate drive circuit 100 includes a P-channel MOSFET 5 of an ON drive switch and an N-channel MOSFET 6 of an OFF drive switch connected in series via a gate resistor 8 when ON and a gate resistor 9 when OFF.
  • a negative bias generator 50 connected between the control power supply 11 and the source potential of the driving MOSFET 3 which is a semiconductor switching element.
  • the negative bias generator 50 includes a first switching / charging circuit 51 formed of a resistor 20, a P-channel MOSFET 21, an N-channel MOSFET 22, a resistor 23, and a capacitor 30, which are one system for generating a negative bias, and a negative bias.
  • a second switching and charging circuit 52 formed of a resistor 24, a P-channel MOSFET 25, an N-channel MOSFET 26, a resistor 27, and a capacitor 31 as a second system to be generated, and an anode at the source of the N-channel MOSFET 6 of the buffer 7
  • a diode 28 and a diode 29 to be connected are provided.
  • the capacitor 30 is connected between the drain of the N-channel MOSFET 22 and the cathode of the diode 28, and the capacitor 31 is connected between the drain of the N-channel MOSFET 26 and the cathode of the diode 29.
  • the anode of the diode 32 is connected to the cathode of the diode 28, and the cathode of the diode 32 is connected to the source potential of the driving MOSFET 3.
  • the anode of the diode 33 is connected to the cathode of the diode 29, and the cathode of the diode 33 is connected to the source potential of the drive MOSFET 3.
  • a control signal is given to the P-channel MOSFET 21 and the N-channel MOSFET 22 of the first switching / charging circuit 51 and the P-channel MOSFET 25 and the N-channel MOSFET 26 of the second switching / charging circuit 52, so that the capacitors 30 and 31
  • a negative bias generator control circuit 34 for controlling charging / discharging is provided.
  • a drive control circuit 10 is provided for driving the drive MOSFET 3 by supplying a control signal to the buffer 7.
  • the driving MOSFET 3 when the driving MOSFET 3 is turned on, the P-channel MOSFET 5 of the buffer 7 is turned on and the N-channel MOSFET 6 is turned off.
  • the P-channel MOSFET 21 of the first switching / charging circuit 51 and the P-channel MOSFET 25 of the second switching / charging circuit 52 of the negative bias generator 50 are turned on, the N-channel MOSFET 22 and the N-channel MOSFET 26 are turned off, and the capacitor 30
  • the capacitor 31 is charged by the potential difference between the forward voltage of Vcc and the diode 32 and the forward voltage of Vcc and the diode 33, respectively. If the characteristics of the diode 28, the diode 29, the diode 32, and the diode 33 are the same and the forward voltage is Vf, then Vcc ⁇ Vf.
  • the drive MOSFET 3 when the drive MOSFET 3 is turned off, the P-channel MOSFET 5 is turned off and the N-channel MOSFET 6 is turned on.
  • the source potential Vs of the driving MOSFET 3 is lowered by the charging voltage of the capacitor 30.
  • Vs is lowered by the charging voltage of the capacitor 31.
  • the capacitor 30 is charged by the control power supply 11.
  • FIG. 2 shows a transient waveform example of each part of the gate drive circuit 100.
  • S1 is a driving MOSFET 3
  • S2 is an N-channel MOSFET 22 and a P-channel MOSFET 25
  • S3 is a switch state of the P-channel MOSFET 21 and the N-channel MOSFET 26, and is ON at a high level.
  • Vc1 is the drain potential of the N-channel MOSFET 22
  • Vc2 is the drain potential of the N-channel MOSFET 26
  • V3 is the source potential of the N-channel MOSFET 6.
  • the driving MOSFET 3 In the period t4, the driving MOSFET 3 is in the ON state, and Vc1 and Vc2 are Vcc. V3 is 2Vf. In the period t4, the capacitor 30 and the capacitor 31 are charged with Vcc ⁇ Vf. Vgs is equal to Vcc.
  • Vc1 becomes Vs.
  • Vgs obtains a negative bias of Vs ⁇ (Vcc ⁇ 2Vf) which is the potential difference between V3 and Vs at the maximum.
  • the N-channel MOSFET 26 is turned on instead of the N-channel MOSFET 22, so that Vc2 becomes Vs.
  • Vgs obtains a negative bias of Vs ⁇ (Vcc ⁇ 2Vf) which is the potential difference between V3 and Vs at the maximum.
  • Vcc ⁇ 2Vf Vs ⁇ (Vcc ⁇ 2Vf) which is the potential difference between V3 and Vs at the maximum.
  • the driving MOSFET 3 is in the ON state, and the N-channel MOSFET 22 and the N-channel MOSFET 26 are turned off again, so that both Vc1 and Vc2 become Vcc. V3 also becomes 2Vf again.
  • the first switching / charging circuit 51 and the second switching / charging circuit 52 provided in the negative bias generation unit 50 are switched during the period (t5 to t7) when the driving MOSFET 3 is OFF.
  • the source potential of the drive MOSFET 3 can be continuously lowered twice to bring the Vgs of the drive MOSFET 3 into a negative bias state. That is, two systems of the first switching / charging circuit 51 and the second switching / charging circuit 52 for generating a negative bias are provided, and the first switching / charging circuit 51 of the first system By switching to the switching / charging circuit 52 of FIG.
  • MOSFET was used as an example for the switching element of the circuit configuration, it is needless to say that the present invention is not limited to this and a switching element such as a transistor can be used. Needless to say, the switching element to be driven is not limited to the MOSFET but can be applied to an IGBT or the like.
  • the present invention is not limited to this, and switching may be performed twice or more.
  • the example of 2 systems was shown, it is not limited to 2 systems, It is a switching and charging circuit of 3 systems or more, and the switching may be performed at least once.
  • the discharge pattern of the capacitors 30 and 31 is not limited to the first embodiment.
  • FIG. 2 a case where a MOSFET formed of a wide band gap semiconductor is used as the driving MOSFET 3 will be described.
  • a wide band gap semiconductor is a wide band gap semiconductor having a larger band gap than silicon.
  • Examples of the wide band gap semiconductor include silicon carbide, a gallium nitride-based material, and diamond.
  • Switching elements and diode elements formed by such wide band gap semiconductors have high voltage resistance and high allowable current density, so that switching elements and diode elements can be miniaturized. By using elements and diode elements, it is possible to reduce the size of a semiconductor module incorporating these elements.
  • the heat resistance is high, the heat dissipating fins of the heat sink can be downsized and the water cooling section can be air cooled, so that the semiconductor module can be further downsized. Furthermore, since the power loss is low, it is possible to increase the efficiency of the switching element and the diode element, and further increase the efficiency of the semiconductor module.
  • the drive MOSFET 3 formed of a wide band gap semiconductor tends to be lower in Vth than the Si-MOSFET, there is a possibility that it may be erroneously turned on even with smaller noise.
  • it is possible to apply a negative bias of a certain level or more continuously, so that it is possible to prevent erroneous turn-on even when noise is applied.

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Abstract

A negative bias generation unit (50) controlled by a negative bias generation unit control circuit (34) connected to a buffer (7) comprising an ON driving switch (5) and an OFF driving switch (6) of a semiconductor switching device (3) constituting an arm switch of an inverter is provided with at least two systems, switching charging circuits (51, 52), and switching of the systems is performed at least once and a negative bias is applied to the semiconductor switching device (3) when the semiconductor switching device (3) is in an OFF period, thereby preventing the semiconductor switching device (3) from accidentally turning on due to noise contamination when the amount of negative bias decreases due to discharge.

Description

半導体スイッチング素子のゲート駆動回路Semiconductor switching element gate drive circuit
　この発明は、半導体スイッチング素子を駆動するゲート駆動回路に関するものであり、特に半導体スイッチング素子を高信頼にスイッチングできる半導体スイッチング素子のゲート駆動回路に関する。 The present invention relates to a gate driving circuit for driving a semiconductor switching element, and more particularly to a gate driving circuit for a semiconductor switching element capable of switching the semiconductor switching element with high reliability.
　高電圧側アームと低電圧側アームで構成されるハーフブリッジまたはフルブリッジからなるインバータでは、アームスイッチとして半導体スイッチング素子であるＭＯＳＦＥＴ（Ｍｅｔａｌ－Ｏｘｉｄｅ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ－Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）やＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）等が用いられている。ここで、例えば高電圧側アームスイッチをターンオン、低電圧側アームスイッチをターンオフしたときに、低電圧側アームスイッチのドレイン－ソース間電圧が上昇することでゲート電圧が持ち上がり、ターンオフしている低電圧側アームスイッチがターンオンしてしまう誤動作を起こすという不具合を生じる。 In an inverter consisting of a high-voltage side arm and a low-voltage side arm and consisting of a half-bridge or a full-bridge, a semiconductor switching element MOSFET (Metal-Oxide-Semiconductor, Field-Effect Transistor) or IGBT (Insulated Gate Bipolar Transistor) is used as an arm switch. ) Etc. are used. Here, for example, when the high voltage side arm switch is turned on and the low voltage side arm switch is turned off, the gate voltage rises due to the rise of the drain-source voltage of the low voltage side arm switch, and the low voltage is turned off. This causes a malfunction of causing the side arm switch to turn on and malfunction.
　その対策のため、従来からゲート駆動回路には様々な対策が施されてきた。例えば、従来例のゲート駆動回路では、低電圧側アームスイッチのゲート端子に接続されたコンデンサなどからなる負バイアス回路を備え、低電圧側アームスイッチがターンオンするときに負バイアス回路内コンデンサに発生する電圧を、低電圧側アームスイッチがターンオフするときに負バイアスとして印加している技術が示されている（例えば、特許文献１）。 For this purpose, various measures have been taken for gate drive circuits. For example, the conventional gate drive circuit includes a negative bias circuit including a capacitor connected to the gate terminal of the low-voltage side arm switch, and is generated in the negative bias circuit capacitor when the low-voltage side arm switch is turned on. A technique is shown in which a voltage is applied as a negative bias when a low-voltage side arm switch is turned off (for example, Patent Document 1).
　ここで、特許文献１の技術では、スイッチングの高速化により半導体スイッチング素子のゲート－ソース間に印加されるノイズが大きくなった場合に負バイアス電圧を大きく取ろうとするとゲート駆動回路の電源電圧を変更もしくは追加しなければならず、また、ゲート駆動回路の電源電圧を従来のままとするならばアームスイッチのゲート電圧を小さくする必要がある。 Here, in the technique of Patent Document 1, when the noise applied between the gate and the source of the semiconductor switching element becomes large due to the high speed switching, the power supply voltage of the gate drive circuit is changed to increase the negative bias voltage. Alternatively, the gate voltage of the arm switch needs to be reduced if the power supply voltage of the gate driving circuit remains the same.
　これを改善した従来例として電源の変更やゲート電圧低下に伴うアームスイッチの損失増加を回避するように負バイアス回路を設けたゲート駆動回路が示されている（例えば、特許文献２）。 As a conventional example that improves this, a gate drive circuit provided with a negative bias circuit so as to avoid an increase in loss of an arm switch due to a change in power supply or a decrease in gate voltage is disclosed (for example, Patent Document 2).
特開平０８－１４９７９６号公報Japanese Patent Application Laid-Open No. 08-149796 特許第４１００１３４号公報Japanese Patent No. 4100134
　しかしながら、特許文献２に示された技術は、例えばアームスイッチとしてＭＯＳＦＥＴを用いたとき、コンデンサによって与えられる負バイアスは、放電によって徐々にその負バイアス量が減少し駆動ＭＯＳＦＥＴのソース電位に近づくが、駆動ＭＯＳＦＥＴがオフ期間中にコンデンサを再充電するなどの負バイアス量回復のための手段が無いため、負バイアスが小さくなったときにノイズが混入した場合などに誤オンしやすくなる。特に、駆動ＭＯＳＦＥＴとしてゲート－ソース間閾値電圧が低いＳｉＣ－ＭＯＳＦＥＴを用いた場合には、その特性から従来のＳｉ－ＭＯＳＦＥＴと比較してノイズで誤オンする可能性が更に高くなってしまう問題があった。また、負バイアスを大きく且つ継続して得るためにコンデンサの容量を大きくするとコンデンサの充電時間も増加するため、高周波でスイッチングする場合には充電時間が不足しがちになり充分な量の負バイアスを得ることが難しくなる。 However, in the technique shown in Patent Document 2, for example, when a MOSFET is used as an arm switch, the negative bias applied by the capacitor gradually decreases due to discharge and approaches the source potential of the driving MOSFET. Since there is no means for recovering the negative bias amount such as recharging the capacitor during the off-period of the driving MOSFET, it is likely to be erroneously turned on when noise is mixed when the negative bias is reduced. In particular, when a SiC-MOSFET having a low gate-source threshold voltage is used as the driving MOSFET, there is a problem that the possibility of erroneous turn-on due to noise is further increased because of its characteristics as compared with the conventional Si-MOSFET. there were. In addition, if the capacitor capacity is increased to increase the negative bias continuously, the charging time of the capacitor also increases.Therefore, when switching at a high frequency, the charging time tends to be insufficient, and a sufficient amount of negative bias is applied. It becomes difficult to obtain.
　本発明は、上記のような課題を解決するもので、特許文献２の技術をさらに改善し、コンデンサ放電による負バイアスの減少を速やかに回復させる機能を持たせ、半導体スイッチング素子としてのＳｉ－ＭＯＳＦＥＴやＳｉＣ－ＭＯＳＦＥＴにおいて高周波スイッチングが可能で、かつノイズによるゲート誤動作を防止可能な半導体スイッチング素子のゲート駆動回路を得ることを目的としている。 The present invention solves the above-described problems, further improves the technique of Patent Document 2, has a function of quickly recovering a decrease in negative bias due to capacitor discharge, and a Si-MOSFET as a semiconductor switching element. Another object of the present invention is to obtain a gate drive circuit of a semiconductor switching element that can perform high-frequency switching in a SiC-MOSFET and can prevent gate malfunction due to noise.
　この発明に係る半導体スイッチング素子のゲート駆動回路は、半導体スイッチング素子を駆動するＯＮ駆動用スイッチおよびＯＦＦ駆動用スイッチとが設けられたバッファと、負バイアス生成部と、負バイアス生成部制御回路とが設けられており、負バイアス生成部には、バッファのＯＦＦ駆動用スイッチに接続され、半導体スイッチング素子に印加する負バイアスを生成する２系統以上のスイッチング・充電回路が設けられているとともに、負バイアス生成部は、半導体スイッチング素子がＯＦＦの期間に、負バイアス生成部制御回路によって２系統以上のスイッチング・充電回路の系統切り替えを１回以上行って、半導体スイッチング素子に連続的な負バイアスを印加するものである。 A gate driving circuit for a semiconductor switching element according to the present invention includes a buffer provided with an ON drive switch and an OFF drive switch for driving the semiconductor switching element, a negative bias generation unit, and a negative bias generation unit control circuit. The negative bias generator is provided with two or more switching / charging circuits that are connected to the buffer OFF drive switch and generate a negative bias to be applied to the semiconductor switching element. The generation unit applies a continuous negative bias to the semiconductor switching element by switching the system of two or more switching / charging circuits at least once by the negative bias generation unit control circuit during a period when the semiconductor switching element is OFF. Is.
　この発明による半導体スイッチング素子のゲート駆動回路は上記のような構成を採用しているので、半導体スイッチング素子がＯＦＦの時に、２系統以上のスイッチング・充電回路の系統が連続的に切り替えられ、半導体スイッチング素子に対して連続的かつ充分な負バイアスが印加され、ノイズなどによる誤動作を防止することが可能となる。 Since the gate driving circuit of the semiconductor switching element according to the present invention adopts the above-described configuration, when the semiconductor switching element is OFF, two or more switching / charging circuit systems are continuously switched, and the semiconductor switching circuit is switched. A continuous and sufficient negative bias is applied to the element, and malfunction due to noise or the like can be prevented.
実施の形態１の半導体スイッチング素子のゲート駆動回路を示す図である。FIG. 3 is a diagram illustrating a gate drive circuit of the semiconductor switching element according to the first embodiment. 実施の形態１の半導体スイッチング素子のゲート駆動回路の各部の過渡波形の例を示す図である。FIG. 4 is a diagram illustrating an example of a transient waveform of each part of the gate drive circuit of the semiconductor switching element according to the first embodiment. 従来のゲート駆動回路を示す概略構成図である。It is a schematic block diagram which shows the conventional gate drive circuit. 従来のゲート駆動回路の各部の過渡波形の例を示す図である。It is a figure which shows the example of the transient waveform of each part of the conventional gate drive circuit.
　ここで本願発明をより理解し易くするため、従来例の特許文献２におけるゲート駆動回路の動作について、図３、図４を用いて説明する。 Here, in order to make the present invention easier to understand, the operation of the conventional gate drive circuit in Patent Document 2 will be described with reference to FIGS.
　図３は、上記特許文献２のゲート駆動回路を示した概略の構成図である。図３において、ゲート駆動回路１００ａは、直列に接続されたＰチャネルＭＯＳＦＥＴ５と、ＮチャネルＭＯＳＦＥＴ６からなるバッファ７と、ＮチャネルＭＯＳＦＥＴ６のソースにアノードを接続し、駆動ＭＯＳＦＥＴ３のソース電位にカソードを接続するダイオード１３と、抵抗１４を介して制御電源１１にカソードを接続するツェナーダイオード１５と、ツェナーダイオード１５のアノードと、ダイオード１３のアノードとの間に接続する負バイアス用のコンデンサ１６と、ツェナーダイオード１５のアノードにドレインを接続し、ダイオード１３のカソードにソースを接続する負バイアス発生用ＮチャネルＭＯＳＦＥＴ１７と、ＯＮ時のゲート抵抗８と、ＯＦＦ時のゲート抵抗９と、バッファ７の駆動を行う駆動制御回路１０と、負バイアス発生用のＮチャネルＭＯＳＦＥＴ１７の駆動を行う負バイアス制御回路１８を備えている。 FIG. 3 is a schematic configuration diagram showing the gate drive circuit of Patent Document 2 described above. In FIG. 3, the gate drive circuit 100 a has a P-channel MOSFET 5 connected in series, a buffer 7 composed of an N-channel MOSFET 6, an anode connected to the source of the N-channel MOSFET 6, and a cathode connected to the source potential of the drive MOSFET 3. A diode 13, a Zener diode 15 having a cathode connected to the control power supply 11 via a resistor 14, a negative bias capacitor 16 connected between the anode of the Zener diode 15 and the anode of the diode 13, and a Zener diode 15 Drive control for driving the negative bias generating N-channel MOSFET 17 having the drain connected to the anode and the source connected to the cathode of the diode 13, the gate resistance 8 when ON, the gate resistance 9 when OFF, and the buffer 7. Circuit 10 and negative And a negative bias control circuit 18 for driving the N-channel MOSFET17 of bias for generation.
　このような構成において、駆動ＭＯＳＦＥＴ３がＯＮ状態のときにＰチャネルＭＯＳＦＥＴ５がＯＮ、ＮチャネルＭＯＳＦＥＴ６がＯＦＦ、ＮチャネルＭＯＳＦＥＴ１７がＯＦＦとなり、負バイアス生成回路のコンデンサ１６は制御電源１１の電圧（以下、Ｖｃｃと表記）とツェナーダイオード１５のツェナー電圧（以下、Ｖｚｄと表記）とダイオード１３の順方向電圧（以下、Ｖｆと表記）との電位差（Ｖｃｃ－Ｖｚｄ－Ｖｆ）で充電される。 In such a configuration, when the drive MOSFET 3 is in the ON state, the P-channel MOSFET 5 is turned on, the N-channel MOSFET 6 is turned off, the N-channel MOSFET 17 is turned off, and the capacitor 16 of the negative bias generation circuit is connected to the voltage of the control power supply 11 (hereinafter referred to as Vcc). And a Zener voltage of the Zener diode 15 (hereinafter referred to as Vzd) and a forward voltage of the diode 13 (hereinafter referred to as Vf) (Vcc−Vzd−Vf).
　一方、駆動ＭＯＳＦＥＴ３がＯＦＦするときには、ＰチャネルＭＯＳＦＥＴ５がＯＦＦ、ＮチャネルＭＯＳＦＥＴ６がＯＮ、ＮチャネルＭＯＳＦＥＴ１７がＯＮとなり、駆動ＭＯＳＦＥＴ３のソース電位（以下、Ｖｓと表記）はコンデンサ１６の充電電圧だけ引き下げられる。これにより駆動ＭＯＳＦＥＴ３がＯＦＦの状態においては駆動ＭＯＳＦＥＴ３のゲート－ソース間電圧（以下、Ｖｇｓと表記）は負バイアス状態となりノイズによる誤動作の防止が図られている。ここで、ノイズによる誤動作の防止の観点から負バイアスは出来る限り大きく継続することが望ましい。 On the other hand, when the drive MOSFET 3 is turned off, the P-channel MOSFET 5 is turned off, the N-channel MOSFET 6 is turned on, and the N-channel MOSFET 17 is turned on, and the source potential of the drive MOSFET 3 (hereinafter referred to as Vs) is lowered by the charging voltage of the capacitor 16. As a result, when the drive MOSFET 3 is in an OFF state, the gate-source voltage (hereinafter referred to as Vgs) of the drive MOSFET 3 is in a negative bias state to prevent malfunction due to noise. Here, it is desirable to continue the negative bias as much as possible from the viewpoint of preventing malfunction due to noise.
　図４に、ゲート駆動回路１００ａの過渡波形例を示す。Ｓ１は駆動ＭＯＳＦＥＴ３のスイッチ状態、Ｖ１はＮチャネルＭＯＳＦＥＴ１７のドレイン電位、Ｖ２はＮチャネルＭＯＳＦＥＴ６のソース電位である。期間ｔ１において、駆動ＭＯＳＦＥＴ３はＯＮ状態でありＶ１はＶｃｃ－Ｖｚｄである。また、Ｖ２はＶｆである。期間ｔ１ではコンデンサ１６はＶｃｃ－Ｖｚｄ－Ｖｆで充電される。ＶｇｓはＶｃｃに等しい。 FIG. 4 shows an example of a transient waveform of the gate drive circuit 100a. S1 is a switch state of the driving MOSFET 3, V1 is a drain potential of the N-channel MOSFET 17, and V2 is a source potential of the N-channel MOSFET 6. In the period t1, the driving MOSFET 3 is in the ON state, and V1 is Vcc−Vzd. V2 is Vf. In the period t1, the capacitor 16 is charged with Vcc−Vzd−Vf. Vgs is equal to Vcc.
　期間ｔ２において、駆動ＭＯＳＦＥＴ３はＯＦＦ状態であり、ＮチャネルＭＯＳＦＥＴ１７がＯＮするためＶ１はＶｓになる。これによりＶｇｓはＶ２とＶｓの電位差であるＶｓ－（Ｖｃｃ－Ｖｚｄ－Ｖｆ）の負バイアスを得る。その後、駆動ＭＯＳＦＥＴ３のゲート－ソース間容量、ゲート抵抗９、ＮチャネルＭＯＳＦＥＴ６、コンデンサ１６、ＮチャネルＭＯＳＦＥＴ１７の経路で電流が流れるためＶｇｓは徐々に上昇していく。 During the period t2, the driving MOSFET 3 is in an OFF state, and the N-channel MOSFET 17 is turned on, so that V1 becomes Vs. As a result, Vgs obtains a negative bias of Vs− (Vcc−Vzd−Vf), which is a potential difference between V2 and Vs. Thereafter, current flows through the path of the gate-source capacitance of the driving MOSFET 3, the gate resistor 9, the N-channel MOSFET 6, the capacitor 16, and the N-channel MOSFET 17, so that Vgs gradually increases.
　期間ｔ３において、駆動ＭＯＳＦＥＴ３はＯＮ状態であり、ＮチャネルＭＯＳＦＥＴ１７は再びＯＦＦとなるためＶ１は上昇しＶｃｃ－Ｖｚｄとなる。Ｖ２も再びＶｆとなる。
　このように、従来の負バイアス生成機能では駆動ＭＯＳＦＥＴ３がＯＦＦ時に与えられる負バイアスは、図４のｔ２の期間におけるＶｇｓの曲線に示すように徐々に小さくなっていくことから、負バイアスが大きい期間を長くすることで誤動作の発生をより確実に抑えることが難しくなるため、これを可能とする負バイアス生成機能が求められていた。 In the period t3, the driving MOSFET 3 is in the ON state and the N-channel MOSFET 17 is turned off again, so that V1 rises and becomes Vcc−Vzd. V2 also becomes Vf again.
Thus, in the conventional negative bias generation function, the negative bias applied when the drive MOSFET 3 is OFF gradually decreases as shown by the curve of Vgs in the period t2 in FIG. Since it becomes difficult to more reliably suppress the occurrence of malfunctions by increasing the length, a negative bias generation function that enables this is required.
　本発明は、このような従来の負バイアス生成機能を備えたゲート駆動回路に対する要求を満たすものである。以下、実施の形態を図面に基づき詳細に説明する。 The present invention satisfies the requirements for such a conventional gate drive circuit having a negative bias generation function. Hereinafter, embodiments will be described in detail with reference to the drawings.
実施の形態１．
　図１は、実施の形態１によるゲート駆動回路１００を示した概略の構成図である。図１において、ゲート駆動回路１００は、ＯＮ時のゲート抵抗８とＯＦＦ時のゲート抵抗９を介して、直列接続されたＯＮ駆動用スイッチのＰチャネルＭＯＳＦＥＴ５と、ＯＦＦ駆動用スイッチのＮチャネルＭＯＳＦＥＴ６からなるバッファ７と、制御電源１１と半導体スイッチング素子である駆動ＭＯＳＦＥＴ３のソース電位との間に接続された負バイアス生成部５０が設けられている。 Embodiment 1 FIG.
FIG. 1 is a schematic configuration diagram showing a gate drive circuit 100 according to the first embodiment. In FIG. 1, a gate drive circuit 100 includes a P-channel MOSFET 5 of an ON drive switch and an N-channel MOSFET 6 of an OFF drive switch connected in series via a gate resistor 8 when ON and a gate resistor 9 when OFF. And a negative bias generator 50 connected between the control power supply 11 and the source potential of the driving MOSFET 3 which is a semiconductor switching element.
　この負バイアス生成部５０は、負バイアスを生成する１系統である抵抗２０、ＰチャネルＭＯＳＦＥＴ２１、ＮチャネルＭＯＳＦＥＴ２２、抵抗２３およびコンデンサ３０で形成される第１のスイッチング・充電回路５１と、負バイアスを生成する第２の系統である抵抗２４、ＰチャネルＭＯＳＦＥＴ２５、ＮチャネルＭＯＳＦＥＴ２６、抵抗２７およびコンデンサ３１で形成される第２のスイッチング・充電回路５２と、前記バッファ７のＮチャネルＭＯＳＦＥＴ６のソースにアノードを接続するダイオード２８、およびダイオード２９が設けられている。 The negative bias generator 50 includes a first switching / charging circuit 51 formed of a resistor 20, a P-channel MOSFET 21, an N-channel MOSFET 22, a resistor 23, and a capacitor 30, which are one system for generating a negative bias, and a negative bias. A second switching and charging circuit 52 formed of a resistor 24, a P-channel MOSFET 25, an N-channel MOSFET 26, a resistor 27, and a capacitor 31 as a second system to be generated, and an anode at the source of the N-channel MOSFET 6 of the buffer 7 A diode 28 and a diode 29 to be connected are provided.
　なお、前記コンデンサ３０は、ＮチャネルＭＯＳＦＥＴ２２のドレインとダイオード２８のカソード間に接続され、コンデンサ３１はＮチャネルＭＯＳＦＥＴ２６のドレインとダイオード２９のカソード間に接続されている。 The capacitor 30 is connected between the drain of the N-channel MOSFET 22 and the cathode of the diode 28, and the capacitor 31 is connected between the drain of the N-channel MOSFET 26 and the cathode of the diode 29.
　またダイオード３２のアノードは前記ダイオード２８のカソードに、ダイオード３２のカソードが前記駆動ＭＯＳＦＥＴ３のソース電位に接続されている。またダイオード３３のアノードは前記ダイオード２９のカソードに、ダイオード３３のカソードが前記駆動ＭＯＳＦＥＴ３のソース電位に接続されている。 The anode of the diode 32 is connected to the cathode of the diode 28, and the cathode of the diode 32 is connected to the source potential of the driving MOSFET 3. The anode of the diode 33 is connected to the cathode of the diode 29, and the cathode of the diode 33 is connected to the source potential of the drive MOSFET 3.
　さらに、前記第１のスイッチング・充電回路５１のＰチャネルＭＯＳＦＥＴ２１とＮチャネルＭＯＳＦＥＴ２２、および前記第２のスイッチング・充電回路５２のＰチャネルＭＯＳＦＥＴ２５とＮチャネルＭＯＳＦＥＴ２６に制御信号を与えてコンデンサ３０、コンデンサ３１の充放電を制御する負バイアス生成部制御回路３４が設けられている。
　また、前記バッファ７に制御信号を与えて駆動ＭＯＳＦＥＴ３を駆動する駆動制御回路１０が設けられている。 Further, a control signal is given to the P-channel MOSFET 21 and the N-channel MOSFET 22 of the first switching / charging circuit 51 and the P-channel MOSFET 25 and the N-channel MOSFET 26 of the second switching / charging circuit 52, so that the capacitors 30 and 31 A negative bias generator control circuit 34 for controlling charging / discharging is provided.
Further, a drive control circuit 10 is provided for driving the drive MOSFET 3 by supplying a control signal to the buffer 7.
　このような構成において、駆動ＭＯＳＦＥＴ３がＯＮするときには、バッファ７のＰチャネルＭＯＳＦＥＴ５がＯＮ、ＮチャネルＭＯＳＦＥＴ６がＯＦＦする。また、負バイアス生成部５０の第１のスイッチング・充電回路５１のＰチャネルＭＯＳＦＥＴ２１と第２のスイッチング・充電回路５２のＰチャネルＭＯＳＦＥＴ２５がＯＮ、ＮチャネルＭＯＳＦＥＴ２２とＮチャネルＭＯＳＦＥＴ２６がＯＦＦとなり、コンデンサ３０とコンデンサ３１はＶｃｃとダイオード３２の順方向電圧、Ｖｃｃとダイオード３３の順方向電圧の電位差でそれぞれ充電される。ダイオード２８、ダイオード２９、ダイオード３２、ダイオード３３の特性を同一として順方向電圧をＶｆとすればＶｃｃ－Ｖｆである。 In such a configuration, when the driving MOSFET 3 is turned on, the P-channel MOSFET 5 of the buffer 7 is turned on and the N-channel MOSFET 6 is turned off. In addition, the P-channel MOSFET 21 of the first switching / charging circuit 51 and the P-channel MOSFET 25 of the second switching / charging circuit 52 of the negative bias generator 50 are turned on, the N-channel MOSFET 22 and the N-channel MOSFET 26 are turned off, and the capacitor 30 The capacitor 31 is charged by the potential difference between the forward voltage of Vcc and the diode 32 and the forward voltage of Vcc and the diode 33, respectively. If the characteristics of the diode 28, the diode 29, the diode 32, and the diode 33 are the same and the forward voltage is Vf, then Vcc−Vf.
　一方、駆動ＭＯＳＦＥＴ３がＯＦＦするときには、ＰチャネルＭＯＳＦＥＴ５がＯＦＦ、ＮチャネルＭＯＳＦＥＴ６がＯＮする。そして、まず、ＰチャネルＭＯＳＦＥＴ２１がＯＦＦしてＮチャネルＭＯＳＦＥＴ２２がＯＮすると、コンデンサ３０の充電電圧だけ駆動ＭＯＳＦＥＴ３のソース電位Ｖｓを引き下げる。次に、ＮチャネルＭＯＳＦＥＴ２２とＰチャネルＭＯＳＦＥＴ２５をＯＦＦ、ＮチャネルＭＯＳＦＥＴ２６とＰチャネルＭＯＳＦＥＴ２１をＯＮするとコンデンサ３１の充電電圧だけＶｓを引き下げる。このときコンデンサ３０は制御電源１１により充電が行われる。次に、ＮチャネルＭＯＳＦＥＴ２６とＰチャネルＭＯＳＦＥＴ２１をＯＦＦ、ＮチャネルＭＯＳＦＥＴ２２とＰチャネルＭＯＳＦＥＴ２５をＯＮするとコンデンサ３０の充電電圧だけＶｓを引き下げる。再度、駆動ＭＯＳＦＥＴ３がＯＦＦするときは前述の通りコンデンサ３０とコンデンサ３１は両方とも放電が停止され充電される。 On the other hand, when the drive MOSFET 3 is turned off, the P-channel MOSFET 5 is turned off and the N-channel MOSFET 6 is turned on. First, when the P-channel MOSFET 21 is turned off and the N-channel MOSFET 22 is turned on, the source potential Vs of the driving MOSFET 3 is lowered by the charging voltage of the capacitor 30. Next, when the N-channel MOSFET 22 and the P-channel MOSFET 25 are turned off and the N-channel MOSFET 26 and the P-channel MOSFET 21 are turned on, Vs is lowered by the charging voltage of the capacitor 31. At this time, the capacitor 30 is charged by the control power supply 11. Next, when the N-channel MOSFET 26 and the P-channel MOSFET 21 are turned off and the N-channel MOSFET 22 and the P-channel MOSFET 25 are turned on, Vs is lowered by the charging voltage of the capacitor 30. When the driving MOSFET 3 is turned off again, the capacitor 30 and the capacitor 31 are both discharged and charged as described above.
　図２に、ゲート駆動回路１００の各部の過渡波形例を示す。Ｓ１は駆動ＭＯＳＦＥＴ３、Ｓ２はＮチャネルＭＯＳＦＥＴ２２とＰチャネルＭＯＳＦＥＴ２５、Ｓ３はＰチャネルＭＯＳＦＥＴ２１とＮチャネルＭＯＳＦＥＴ２６のスイッチ状態を示し、ハイレベルでＯＮを示す。Ｖｃ１はＮチャネルＭＯＳＦＥＴ２２のドレイン電位、Ｖｃ２はＮチャネルＭＯＳＦＥＴ２６のドレイン電位、Ｖ３はＮチャネルＭＯＳＦＥＴ６のソース電位である。 FIG. 2 shows a transient waveform example of each part of the gate drive circuit 100. S1 is a driving MOSFET 3, S2 is an N-channel MOSFET 22 and a P-channel MOSFET 25, S3 is a switch state of the P-channel MOSFET 21 and the N-channel MOSFET 26, and is ON at a high level. Vc1 is the drain potential of the N-channel MOSFET 22, Vc2 is the drain potential of the N-channel MOSFET 26, and V3 is the source potential of the N-channel MOSFET 6.
　期間ｔ４において、駆動ＭＯＳＦＥＴ３はＯＮ状態でありＶｃ１とＶｃ２はＶｃｃである。また、Ｖ３は２Ｖｆである。期間ｔ４ではコンデンサ３０とコンデンサ３１はＶｃｃ－Ｖｆで充電される。ＶｇｓはＶｃｃに等しい。 In the period t4, the driving MOSFET 3 is in the ON state, and Vc1 and Vc2 are Vcc. V3 is 2Vf. In the period t4, the capacitor 30 and the capacitor 31 are charged with Vcc−Vf. Vgs is equal to Vcc.
　期間ｔ５において、駆動ＭＯＳＦＥＴ３はＯＦＦ状態であり、ＮチャネルＭＯＳＦＥＴ２２がＯＮするためＶｃ１はＶｓになる。これによりＶｇｓは最大でＶ３とＶｓの電位差であるＶｓ－（Ｖｃｃ－２Ｖｆ）の負バイアスを得る。その後、駆動ＭＯＳＦＥＴ３のゲート－ソース間容量、ゲート抵抗９、ＮチャネルＭＯＳＦＥＴ６、ダイオード２８、コンデンサ３０、ＮチャネルＭＯＳＦＥＴ２２、抵抗２３の経路で電流が流れるためＶ３は徐々に上昇していく。 During the period t5, the driving MOSFET 3 is in an OFF state, and the N-channel MOSFET 22 is turned ON, so that Vc1 becomes Vs. As a result, Vgs obtains a negative bias of Vs− (Vcc−2Vf) which is the potential difference between V3 and Vs at the maximum. After that, since current flows through the path between the gate-source capacitance of the driving MOSFET 3, the gate resistor 9, the N-channel MOSFET 6, the diode 28, the capacitor 30, the N-channel MOSFET 22, and the resistor 23, V3 gradually increases.
　期間ｔ６において、ＮチャネルＭＯＳＦＥＴ２２に代わってＮチャネルＭＯＳＦＥＴ２６がＯＮするためＶｃ２はＶｓになる。これによりＶｇｓは最大でＶ３とＶｓの電位差であるＶｓ－（Ｖｃｃ－２Ｖｆ）の負バイアスを得る。その後、駆動ＭＯＳＦＥＴ３のゲート－ソース間容量、ゲート抵抗９、ＮチャネルＭＯＳＦＥＴ６、ダイオード２９、コンデンサ３１、ＮチャネルＭＯＳＦＥＴ２６、抵抗２７の経路で電流が流れるためＶ３は徐々に上昇していく。ＰチャネルＭＯＳＦＥＴ２１はＯＮしているためＶｃ１は再びＶｃｃとなりコンデンサ３０は充電される。 In the period t6, the N-channel MOSFET 26 is turned on instead of the N-channel MOSFET 22, so that Vc2 becomes Vs. As a result, Vgs obtains a negative bias of Vs− (Vcc−2Vf) which is the potential difference between V3 and Vs at the maximum. Thereafter, since current flows through the path of the gate-source capacitance of the drive MOSFET 3, the gate resistor 9, the N-channel MOSFET 6, the diode 29, the capacitor 31, the N-channel MOSFET 26, and the resistor 27, V3 gradually increases. Since the P-channel MOSFET 21 is ON, Vc1 becomes Vcc again, and the capacitor 30 is charged.
　期間ｔ７において、再びＮチャネルＭＯＳＦＥＴ２２がＯＮするためＶｃ１はＶｓになる。これによりＶｇｓは最大でＶ３とＶｓの電位差であるＶｓ－（Ｖｃｃ－２Ｖｆ）の負バイアスを得る。その後、駆動ＭＯＳＦＥＴ３のゲート－ソース間容量、ゲート抵抗９、ＮチャネルＭＯＳＦＥＴ６、ダイオード２８、コンデンサ３０、ＮチャネルＭＯＳＦＥＴ２２、抵抗２３の経路で電流が流れるためＶ３は徐々に上昇していく。ＰチャネルＭＯＳＦＥＴ２５はＯＮしているためＶｃ２は再びＶｃｃとなりコンデンサ３１は充電される。 In the period t7, the N-channel MOSFET 22 is turned on again, so that Vc1 becomes Vs. As a result, Vgs obtains a negative bias of Vs− (Vcc−2Vf) which is the potential difference between V3 and Vs at the maximum. After that, since current flows through the path between the gate-source capacitance of the driving MOSFET 3, the gate resistor 9, the N-channel MOSFET 6, the diode 28, the capacitor 30, the N-channel MOSFET 22, and the resistor 23, V3 gradually increases. Since the P-channel MOSFET 25 is ON, Vc2 becomes Vcc again, and the capacitor 31 is charged.
　期間ｔ８において、駆動ＭＯＳＦＥＴ３はＯＮ状態であり、ＮチャネルＭＯＳＦＥＴ２２とＮチャネルＭＯＳＦＥＴ２６は再びＯＦＦとなるためＶｃ１とＶｃ２はともにＶｃｃとなる。Ｖ３も再び２Ｖｆとなる。 During the period t8, the driving MOSFET 3 is in the ON state, and the N-channel MOSFET 22 and the N-channel MOSFET 26 are turned off again, so that both Vc1 and Vc2 become Vcc. V3 also becomes 2Vf again.
　このように、駆動ＭＯＳＦＥＴ３がＯＦＦしている期間（ｔ５～ｔ７）に負バイアス生成部５０に設けられた第１のスイッチング・充電回路５１と、第２のスイッチング・充電回路５２がスイッチングすることで、駆動ＭＯＳＦＥＴ３のソース電位を２度にわたって継続的に引き下げて駆動ＭＯＳＦＥＴ３のＶｇｓを負バイアス状態にすることができる。すなわち、負バイアスを生成する第１のスイッチング・充電回路５１、第２のスイッチング・充電回路５２を２系統設け、第１の系統の第１のスイッチング・充電回路５１から、第２の系統の第２のスイッチング・充電回路５２に切り替えを行うことにより連続的に一定以上の負バイアスを駆動ＭＯＳＦＥＴ３に対して印加可能となり、コンデンサの容量を増大することなく高速スイッチング可能でノイズによる誤動作を防止し、ひいてはエネルギー消費量を削減した半導体スイッチング素子のゲート駆動回路１００を得ることができる。 In this way, the first switching / charging circuit 51 and the second switching / charging circuit 52 provided in the negative bias generation unit 50 are switched during the period (t5 to t7) when the driving MOSFET 3 is OFF. The source potential of the drive MOSFET 3 can be continuously lowered twice to bring the Vgs of the drive MOSFET 3 into a negative bias state. That is, two systems of the first switching / charging circuit 51 and the second switching / charging circuit 52 for generating a negative bias are provided, and the first switching / charging circuit 51 of the first system By switching to the switching / charging circuit 52 of FIG. 2, it becomes possible to apply a negative bias of a certain level or more to the driving MOSFET 3 continuously, enabling high-speed switching without increasing the capacity of the capacitor, and preventing malfunction due to noise. As a result, the gate drive circuit 100 of the semiconductor switching element with reduced energy consumption can be obtained.
　なお、回路構成のスイッチング素子にＭＯＳＦＥＴを例に用いて説明したが、これに限定するものではなく、トランジスタなどのスイッチング素子などを用いることができることは言うまでもない。また、駆動対象のスイッチング素子もＭＯＳＦＥＴに限定せずＩＧＢＴなどに対しても適用可能であることは言うまでもない。 In addition, although MOSFET was used as an example for the switching element of the circuit configuration, it is needless to say that the present invention is not limited to this and a switching element such as a transistor can be used. Needless to say, the switching element to be driven is not limited to the MOSFET but can be applied to an IGBT or the like.
　また、第１のスイッチング・充電回路５１から第２のスイッチング・充電回路５２への系統切り替えを１回行う例を示したが、これに限定されず２回以上の切り替えであってもよい。さらにまた２系統の例を示したが２系統に限定されず、３系統以上のスイッチング・充電回路であり、かつ少なくとも１回以上の切り替えが行われるものであってもよい。さらにコンデンサ３０、３１の放電パターンはこの実施の形態１に限定されるものではない。 In addition, although an example in which the system switching from the first switching / charging circuit 51 to the second switching / charging circuit 52 is performed once is shown, the present invention is not limited to this, and switching may be performed twice or more. Furthermore, although the example of 2 systems was shown, it is not limited to 2 systems, It is a switching and charging circuit of 3 systems or more, and the switching may be performed at least once. Furthermore, the discharge pattern of the capacitors 30 and 31 is not limited to the first embodiment.
実施の形態２．
　この実施の形態２では、駆動ＭＯＳＦＥＴ３として、ワイドバンドギャップ半導体で形成したＭＯＳＦＥＴを用いた場合について説明する。ワイドバンドギャップ半導体は、珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体である。ワイドバンドギャップ半導体としては、例えば、炭化珪素、窒化ガリウム系材料又はダイヤモンドがある。このようなワイドバンドギャップ半導体によって形成されたスイッチング素子やダイオード素子は、耐電圧性が高く、許容電流密度も高いため、スイッチング素子やダイオード素子の小型化が可能であり、これら小型化されたスイッチング素子やダイオード素子を用いることにより、これらの素子を組み込んだ半導体モジュールの小型化が可能となる。また、耐熱性も高いため、ヒートシンクの放熱フィンの小型化や、水冷部の空冷化が可能であるので、半導体モジュールの一層の小型化が可能になる。更に、電力損失が低いため、スイッチング素子やダイオード素子の高効率化が可能であり、延いては半導体モジュールの高効率化が可能になる。 Embodiment 2. FIG.
In the second embodiment, a case where a MOSFET formed of a wide band gap semiconductor is used as the driving MOSFET 3 will be described. A wide band gap semiconductor is a wide band gap semiconductor having a larger band gap than silicon. Examples of the wide band gap semiconductor include silicon carbide, a gallium nitride-based material, and diamond. Switching elements and diode elements formed by such wide band gap semiconductors have high voltage resistance and high allowable current density, so that switching elements and diode elements can be miniaturized. By using elements and diode elements, it is possible to reduce the size of a semiconductor module incorporating these elements. In addition, since the heat resistance is high, the heat dissipating fins of the heat sink can be downsized and the water cooling section can be air cooled, so that the semiconductor module can be further downsized. Furthermore, since the power loss is low, it is possible to increase the efficiency of the switching element and the diode element, and further increase the efficiency of the semiconductor module.
　ワイドバンドギャップ半導体によって形成された駆動ＭＯＳＦＥＴ３はＳｉ－ＭＯＳＦＥＴと比較してＶｔｈが低い傾向にあるためより小さなノイズでも誤オンする可能性があるが、この実施の形態２のようなゲート駆動回路を用いることによって、連続的で一定以上の負バイアスを印加することができるので、ノイズが印加されても誤オンしてしまうことを防止することができる。 Since the drive MOSFET 3 formed of a wide band gap semiconductor tends to be lower in Vth than the Si-MOSFET, there is a possibility that it may be erroneously turned on even with smaller noise. By using it, it is possible to apply a negative bias of a certain level or more continuously, so that it is possible to prevent erroneous turn-on even when noise is applied.

Claims (3)

  1. 半導体スイッチング素子のゲート駆動回路であって、
    前記ゲート駆動回路は、前記半導体スイッチング素子を駆動するＯＮ駆動用スイッチおよびＯＦＦ駆動用スイッチが設けられたバッファと、負バイアス生成部と、負バイアス生成部制御回路とが設けられており、
    前記負バイアス生成部には、前記バッファのＯＦＦ駆動用スイッチに接続され、前記半導体スイッチング素子に印加する負バイアスを生成する２系統以上のスイッチング・充電回路が設けられているとともに、前記負バイアス生成部は、前記半導体スイッチング素子がＯＦＦの期間に、前記負バイアス生成部制御回路によって前記２系統以上のスイッチング・充電回路の系統切り替えを１回以上行って、前記半導体スイッチング素子に連続的な負バイアスを印加する半導体スイッチング素子のゲート駆動回路。     A gate driving circuit for a semiconductor switching element,
    The gate drive circuit is provided with a buffer provided with an ON drive switch and an OFF drive switch for driving the semiconductor switching element, a negative bias generation unit, and a negative bias generation unit control circuit,
    The negative bias generation unit includes two or more switching / charging circuits that are connected to an OFF drive switch of the buffer and generate a negative bias to be applied to the semiconductor switching element. The switching unit performs switching of the two or more switching / charging circuits at least once by the negative bias generation unit control circuit during a period in which the semiconductor switching element is OFF, so that a continuous negative bias is applied to the semiconductor switching element. The gate drive circuit of the semiconductor switching element which applies.
  2. 前記半導体スイッチング素子は、ワイドバンドギャップ半導体によって形成されている請求項１に記載の半導体スイッチング素子のゲート駆動回路。 The semiconductor switching element gate drive circuit according to claim 1, wherein the semiconductor switching element is formed of a wide band gap semiconductor.
  3. 前記ワイドバンドギャップ半導体は、炭化珪素、窒化ガリウム系材料またはダイヤモンドである請求項２に記載の半導体スイッチング素子のゲート駆動回路。 The gate driving circuit of the semiconductor switching element according to claim 2, wherein the wide band gap semiconductor is silicon carbide, a gallium nitride-based material, or diamond.
PCT/JP2011/064916 2010-09-21 2011-06-29 Gate drive circuit of semiconductor switching device WO2012039174A1 (en)

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JPH06140900A (en) * 1992-10-28 1994-05-20 Fuji Electric Co Ltd Gate driving circuit of gto
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JPS5360156A (en) * 1976-11-10 1978-05-30 Toshiba Corp Gate control system for gate turn-off thyristor
JPH06140900A (en) * 1992-10-28 1994-05-20 Fuji Electric Co Ltd Gate driving circuit of gto
JP2010035387A (en) * 2008-07-31 2010-02-12 Daikin Ind Ltd Gate drive device for voltage-type drive element

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