WO2012037936A1

WO2012037936A1 - Superconducting structures on circuits or circuit elements, production of these structures and use thereof

Info

Publication number: WO2012037936A1
Application number: PCT/DE2011/075202
Authority: WO
Inventors: Richard Skrotzki; Viton Heera; Thomas HERRMANNSDÖRFER; Jan Fiedler; Bernd Schmidt; Manfred Helm
Original assignee: Helmholtz-Zentrum Dresden-Rossendorf E. V.
Priority date: 2010-08-27
Filing date: 2011-08-29
Publication date: 2012-03-29
Also published as: DE102010039911A1; WO2012037936A9

Abstract

The invention describes the production of integrated superconducting structures in circuits and circuit elements on the basis of silicon or germanium wafers by implementing precipitations, new chemical compounds or doping via ion implantation and subsequent short-time annealing. An advantage of these structures is the low-cost production and the higher power density of these circuits in comparison with transistor circuits. These structures make it possible to control quantum-mechanical interference phenomena with the aid of an external magnetic field or a magnetic field produced on the chip. A further possibility is to use them for logic circuits for quantum computing.

Description

description

Superconducting structures on circuits or circuit elements, production of these structures and their use

Technical area

The invention describes microelectronic circuits with novel integrated superconducting structures, their production and the

Use.

State of the art

As a result of the constant miniaturization of microelectronic components

These have today dimensions of a few nanometers. Therefore, in the complementary next generation metal - oxide semiconductor (CMOS) devices, very high doping concentrations and low film resistivities must be achieved in the n + and p + regions. [TANAKA, Hiroaki, et al. Low Contact Resistivity with Low

Silicides / p + -Silicon Schottky Barrier for High-Performance P-Channel Metal-Oxide-Silicon Field Effect Transistors. Jpn. j. appl. phys. 2010, Vol. 49, p. 04DA03. Integrated devices (also referred to as circuit or circuit elements) are formed on wafers by various methods of semiconductor technology, such as epitaxial deposition, sputtering, vapor deposition, chemical deposition, layer removal, and

Patterning (photolithography) produced, often also in connection with doping method for changing material properties.

Superconducting systems are distinguished into two types, which differ in their production.

In the single-layer process, only a complex compound as

Layers applied to the wafer. Subsequently, the layer is structured, for example, with the aid of particle radiation. investigated

Compounds for the production of high-temperature superconductor layers are YBaCuO or MgB2. Compounds where only the

Applying a single-coat process generally achieves higher critical temperatures. Thus, the finished circuit elements can be operated at higher operating temperatures. [PORTESI, C, et al. Fabrication of superconducting MgB2 nanostructures by an electron beam. J. appl. Phys. 2006, Volume 99, p. 0661 15, TLNCHEVT, SS.

Investigation of RF SQUIDS made from epitaxial YBCO films.

Superconductor Science and Technology. 1990, Vol. 3, No. 10, pp. 500-503.]

Multilayer systems have the advantage that superconducting structures, in addition to normal conducting or insulating structures can be applied to the substrate, the arrangement alternately as

Interlayers is performed. Electron beam lithography is used for microstructuring. Possible tunneling barriers are made of oxides such as Al2O3 or metals such as HfTi. Important in the arrangement of these layers is a good affinity of the layers

to each other. [FLOKSTRA, J., et al. Josephson junctions and DC SQUIDS based on Nb / Al technology. Clinical Physics and Physiological

Measurements. 1991, Vol. 12, p. 59-67. , Kim, Yun Won, et al.

Fabrication of MgB2 / Au / Nb and MgB2 / Nb Josephson junctions. Physica C: Superconductivity and its Applications. 2007, Vol. 460-462, p.1466-1467.]

Brief description of the invention

Task is a manufacturing method for integrated circuits

superconducting structures in silicon or germanium wafers

specify.

The production of the structures of the integrated circuits takes place in

Wafers with or without oxidic cover layer by the implantation of chemical elements, resulting in a subsequent

Short-term annealing either be eliminated, enter into a new chemical compound with the wafer or achieve the effect of doping.

By the use of silicon or germanium wafers is the

Circuit element manufacturing simplified. In microelectronics silicon wafers are usually used, so that thus a quick transfer of the resulting circuit elements is made possible in production. The fabrication of superconducting structures on these wafers is less expensive than the use of other wafers. First Studies show that the invention

Structures have little or no signs of aging.

[0009]

Short description of the drawing figures

Fig. 1 shows a schematic representation of a typical

Circuit element on the example of a double superconducting

Tunnelskontaktes (so-called SQUID) 1, consisting of the substrate (wafer) 2, the applied thick oxide layer 3, the optional thin oxide layer 4, the implanted layer 5, the contacts 6 and the tunnel beam produced with a focused ion beam tunneling 7 in the right image ,

[001 1] The following figures show test results using the example of a silicon wafer with a prepared gallium layer after the

Implantation and healing. Fig. 2 shows the dependency of the temperature-dependent sheet resistance. Figs. 5 and 6 show two cross-section transmission electron micrographs (XTEM images) and Figs. 3 and 4 indicate the composition of the areas marked in Fig. 6 energy dispersive X-ray spectroscopy (EDX) were determined.

Description of the embodiments

The starting point is an Si wafer or Ge wafer. In order to avoid the outdiffusion of already implanted ions from the solid and the sputtering of surface atoms during implantation, passivation layers, such as oxide layers, preferably silicon dioxide, can be applied to the wafer. As a result of the implantation impact cascades occur in the oxide layer and it takes place at the

Interface a mixing of materials. Depending on the substance to be implanted, a thick oxide layer greater than 100 nm is applied to the wafer, advantageously S1O 2 is used for this purpose, and advantageously the oxide layer is 200 to 300 nm thick. The

Oxide layer is selectively etched for microstructuring, advantageously with an etch-resistive negative mask representing the desired superconducting structure. In the oxide-etched area becomes the desired Layer implemented. By using the thick cover layer, the ions can not enter the implant during implantation

Neighboring areas penetrate into the depth of silicon or germanium. On the area of the applied structure, it is possible and depending on the implanted substance necessary to leave a thin oxide layer, this is true for the reasons mentioned above in the

Implantation and thus the substance during subsequent annealing does not diffuse out of the wafer.

With increasing dose during implantation and thus increasing defect density, the defects begin to overlap and form Defektagg lomerate or locally amorphous areas to amorphous layers. The thickness of the amorphous layer increases with increasing ion energy and dose. Furthermore, the maximum concentration of implanted ions in the layer is dependent on the ion dose. In the subsequent annealing, the layer is recrystallized, and depending on the target for the system to be prepared (see below), the

imbedded atoms are incorporated in the lattice (doping) or precipitated within the wafer (precipitation formation). Alternatively, the annealing should lead to a synthesis of new chemical compounds. When curing, it is important to avoid leakage of the implanted atoms. Therefore, short term annealing methods such as rapid thermal annealing (RTA), flash lamp annealing (FLA) and / or ultra short laser annealing (USLA) are used. The backside of the wafers can be additionally heated to keep the temperature gradient in the sample small. If the

Temperature differences in the wafer become too large, which initially leads to an inhomogeneous healing. It may, however, due to

mechanical stresses that are caused by temperature gradients, also come to destroy the wafer.

After annealing, contacts to the prepared structures

sputtered or vapor-deposited, advantageously off

metallic substances. For the examined highly doped layers is making contacts, even at low temperatures

show ohmic behavior, relatively difficult. In the marginal areas of the circuits gold contacts are sputtered or vapor-deposited. If an optional thin oxide layer has been used, it may need to be removed in small areas by selective etching. The use of gold proves to be an option for that

Establishing stable contacts. Thin silver wires can then be glued to the gold using silver conductive paint. These are electrically connected to the corresponding measuring electronics (for example via soldering).

With a focused ion beam (focussed ion beam - abbreviated FIB) can also be placed particularly narrow sections, which serve as electronic tunneling barriers.

In a preferred embodiment (precipitation formation) arise after implantation superconducting structures from the implanted into the wafer chemical elements. As such, Ga, Nb and / or V come into question. The corresponding parameters in the production of the individual substances are given in Tab. The reached

Transition temperature T _c in the implantation of (amorphous) Ga in silicon is, for example, 7 K.

In a further preferred embodiment, in the

The new non-equilibrium conditions for implantation and annealing may also favor the formation of metastable phases (also applicable to precipitation formation). Promising compounds are NbsSi (T _c 19K), NbsGe (T _c 21 K), V ₃ Si (T _c 17, 1 K) and V ₃ Ge (T _c 8.01 K).

Another embodiment is created by the implantation of

doping ions. In this way, Ge: Ga (T _c = 0.5 to 1, 4 K and 43 K, respectively), Ge: B and Si: B were prepared.

[0019]

Tab. 1

Substrate (with oxidic implanted substance with healing method with protective layer) Dose parameters

Si wafer or Ge wafer Ga RTA Substrate (with oxidic implanted material with annealing method with

Protective layer) dose parameter

with 20 to 50 nm dose for about 1 min

oxidizing 10 ¹⁶ to 10 ¹⁷ cm ² at 600 to 700 ° C.

Protective layer (Si wafer) or

at 800 to 1000 ° C

(Ge-wafer)

Si wafers or Ge wafers Nb, V RTA

with 20 to 50 nm dose about 1 to 100 s oxidic protective layer 10 ¹⁴ to 5 x 10 ¹⁷ cnr ² at 600 to 1200 ° C.

or

FLA

for 0.1 to 20 ms about 10 to 100 Jcnr ²

(T = 600 to 1500 ° C) or

USLA

for 1 to 100 ns,

T = 900 to 1500 ° C

(- 0.1 to 10 Jcnr ² )

Si wafer or Ge wafer binary or ternary RTA

with optional 20 to 50 compound from about 1 to 100 s nm of oxidic implanted elements at 600 to 1200 ° C

Protective layer and substrate material or

NbsGe, NbsSi, V ₃ Si or FLA

V ₃ Ge for 0.1 to 20 ms

Dose: about 10 to 100 Jcnr ²

10 ¹⁵ to 5 x 10 ¹⁷ cnr ² (T = 600 to 1500 ° C) or

USLA

1 to 100 ns,

T = 900 to 1500 ° C

(- 0.1 to 10 Jcnr ² ) Substrate (with oxidic implanted material with annealing method with

Protective layer) dose parameter

Si wafers or doped ions are in the FTA

Germanium wafer substrate dissolved 40 to 80 s

with 20 to 50 nm Ge: Ga at 800 to 950 ° C oxidizing dose: 2 to 6 x 10 ¹⁶ cm ² or

Protective layer FLA

for 2 to 5 ms

at 40 to 80 Jcnrr ² or

USLA

1 to 100 ns,

T = 900 to 1500 ° C

(- 0.1 to 10 cm ² )

Si wafer or Si: B, Ge: B RLA

Germanium-wafer Dose: 2 to 6 x 10 ¹⁶ cm- ² 1 to 100 sec

with 20 to 50 nm at 600 to 1200 ° C oxide protective layer or

FLA

for 0.1 to 20 ms at 10 to 100 Jcm- ²

(T = 600 to 1500 ° C) or

USLA

1 to 100 ns,

T = 900 to 1500 ° C

(- 0.1 to 10 cm ² )

When annealing with USLA, the laser pulses with the in Tab 1

Times are repeated up to 1000 times with 1 to 10 Hz repetition rates.

Furthermore, it makes sense to allow the sample to flow around during the annealing of a gaseous substance (for example Ar). The advantages achieved of the superconducting structures thus produced on the components are described using the example of implanted with gallium silicon wafer.

[0023] Fig. 5 shows the XTEM- on if one of them cm- with 4 x 10 ¹⁶ ² gallium

implanted and not healed sample. The approximately 100 nm wide amorphous layer 13 is clearly visible. Fig. 6 shows the XTEM micrograph of an implanted with 4 x 10 ¹⁶ cm- ² gallium and annealed at 650 ° C sample. In this photograph, the amorphous layer of Fig. 5 is now polycrystalline 14 and precipitates 18 are clearly visible. The heavily damaged transition region 12 between the polycrystalline layer 14 and the monocrystalline substrate 1 1 is present unchanged.

Furthermore, there is a high density of the precipitates 18 at the interface with the oxide layer 15 (here S1O2). The precipitation density decreases behind the boundary surface, and precipitates 18 which are randomly distributed and sometimes several nm in size are visible in deeper areas. The precipitates 18 visible in Fig. 6 show no crystalline

Structures and are therefore amorphous. To shed light on the

To obtain composition of these areas, EDX analyzes were performed on the 21 and 22 labeled areas. The resulting spectra are shown in Fig. 3 (point 21) and 4 (point 22).

Fig. 2 shows the temperature-dependent sheet resistance of

4x10 ¹⁶ cnr ² Gallium implanted and between 550 ° C and 900 ° C healed samples of a gallium implanted Si wafer. A drop in resistance of 5.3 kQ / sq. at 6K to 550 Ω / sq. at 2.5 K can be seen in the healed at 600 ° C sample. Even below 7 K, the resistance of the samples heated at 650 ° C and 700 ° C respectively has dropped to a non-measurable value with the devices used here.

[0025]

Industrial Applicability

The structures according to the invention, in addition to the known applications of microelectronic circuit element, the control of quantum mechanical interference phenomena with the help of a external magnetic field or a magnetic field generated on the chip. Another application is provided by logic circuits for quantum computing.

[0027]

List of reference numbers

[0028]

Tab 2: List of Reference Signs

1 circuit element

2 wafers

3 thick oxide layer

4 optional thin oxide layer

5 implanted layer

6 contacts

7 FIB - section

1 1 crystalline substrate

12 severely damaged area

13 amorphous layer

14 polycrystalline layer

15 oxide layer

16 glue

17 holes

18 excretions

it EDX analyzed areas

Claims

claims

1. Superconducting structure in microelectronic circuits or

Circuit elements, characterized in that the superconducting structure

a) implanted chemical elements (Ga, Nb or V) or

b) chemical compounds (NbsSi, NbsGe, V3S1 or VsGe) or

c) doped ions (Ge: Ga, Ge: B or Si: B) and

the structure is processed in silicon or germanium.

2. Process for the preparation of the superconducting structure specified in claim 1, characterized

a thick oxidic protective layer is applied to the wafer, followed by microstructuring and possibly a thin oxidic protective layer on the microstructured areas

is applied, or is left in the microstructuring on the wafer, then that the implantation of the substance takes place and

then the wafer is treated by means of short term annealing.

3. The method according to claim 2, characterized in that as

Short-term annealing RTA (rapid thermal annealing), FLA (flash lamp annealing) or USLA (ultra short laser annealing) takes place.

4. The method according to claim 2, characterized in that the thin

oxidizing protective layer 15 is between 20 and 50 nm thick.

5. The method according to claim 2, characterized in that the thin

oxidizing protective layer does not have to be applied to superconducting structures made of chemical compounds.

6. The method of claim 3 in the USLA annealing method, the laser pulses can be repeated up to 1000 times at 1 to 10 Hz repetition rates.

7. The method according to claim 2, that the sample when annealing with a

gaseous material is flowed around, preferably Ar.

8. Use of microelectronic circuit elements with superconducting

Structures according to claim 1.

9. Use according to claim 8 in the control of quantum mechanical Interferrenzerscheinungen using an external magnetic field or a magnetic element integrated on the circuit element.

Use according to claim 8, in the construction of logic circuits for quantum computing.