WO2012032583A1

WO2012032583A1 - Method of forming image data, method of writing image data, and image data processing circuit

Info

Publication number: WO2012032583A1
Application number: PCT/JP2010/005543
Authority: WO
Inventors: 康洲鎌
Original assignee: 富士通株式会社
Priority date: 2010-09-10
Filing date: 2010-09-10
Publication date: 2012-03-15
Also published as: JP5708653B2; JPWO2012032583A1

Abstract

Provided is a method of writing image data whereby the number of times an external memory is written to is reduced for the image data and for a method of forming image data that reduces the amount of image data used for anti-aliasing. The method of forming image data comprising: a step wherein a three dimensional graphics image is segmented into pixel blocks; a step wherein with respect to all pixels for each pixel block, using a coverage mask, if there is a solid fill of the same color, a flag with a first logic is generated, and if one portion of the pixel has a solid fill of a different color, or, if there is no fill, a flag with a second logic is generated; a step wherein within a pixel block having the flag with the first logic a single pixel value is selected from among the pixel values and is defined as a first pixel value; a step wherein within a pixel block having the flag with the second logic all pixel values are defined as a second pixel value; a step wherein image data is generated on the bases of the first pixel value, the second pixel value, and the flags with first and second logic.

Description

Image data forming method, image data writing method, and image data processing circuit

The present invention relates to a method for forming image data associated with anti-aliasing, a method for writing the formed image data, and an image data processing circuit, which are performed in the rendering processing of three-dimensional graphics.

Anti-aliasing is performed to reduce jaggy (shaking of the outline) that occurs when drawing a three-dimensional graphics image having image data in the depth (depth) direction.
As general anti-aliasing processing, super sampling anti-aliasing (SSAA) processing and multi-sample anti-aliasing (MSAA) processing are mainly used (Patent Document 1).
Here, SSAA is a technique for rendering a rendering target at a resolution higher than the display resolution, and reducing the resolution of the resulting image to obtain a display image. MSAA is similar to SSAA in that it renders a rendering target at a resolution higher than the display resolution and reduces the resolution of the obtained image to obtain display pixels, but the pixel colors are all the same. This is a different technique in that the rendering process is simplified. However, also in MSAA, image data in the depth direction is handled in the same manner as SSAA.

However, in MSAA, although anti-aliasing can be reduced, the amount of image data handled in anti-aliasing cannot be reduced. Therefore, if the method or apparatus for processing the image data is the same, the access amount to the memory for storing the image data is the same in the SSAA process and the MSAA process.
Then, the performance requirements for the external memory for storing image data are the same in the SSAA process and the MSAA process.

Therefore, since image data for an image tends to increase, there is a tendency that an increase in clock frequency used for accessing an external memory related to anti-aliasing or an increase in bus width of the bus cannot be avoided.

JP 2002-63597 A

An image data forming method for reducing the amount of image data used for anti-aliasing processing and a writing method for reducing the number of times of writing the formed image data to an external memory are provided.

According to the first aspect of the present invention, the following image data forming method is provided. The image data forming method includes a step of dividing pixels arranged in a matrix included in a three-dimensional graphics image into pixel blocks including the pixels of K rows and L columns, and for each pixel block, Using the coverage indicating the color fill state, if the same color fill is performed for all the included pixels, a flag having the first logic is generated, and some of the included pixels are filled with different colors or not filled. In this case, in the step of generating a flag having the second logic and the pixel block having the flag having the first logic, one pixel value is selected from the pixel values of the included pixels, and is set as the first pixel value. And a step of setting all of the pixel values of the pixels included in the pixel block having a flag having the second logic to a second pixel value; Generating the image data of the three-dimensional graphics image based on a flag including the first pixel value, the second pixel value, and the first and second logics. This is an image data forming method.
According to the second aspect of the present invention, the following image data writing method is provided. The image data forming method is a method of writing image data including the first pixel value or the first depth value of the first pixel included in the three-dimensional graphics image after the drawing process, and the three-dimensional graphic after the drawing process. Dividing the first pixels arranged in a matrix form included in the scan image into first pixel blocks composed of the first pixels of K rows and L columns, and for each first pixel block, When the same color is applied to all the first pixels included using the coverage indicating the color fill state, a first flag of the first logic is generated, and some of the included first pixels have different colors. If there is no fill or no fill, the step of generating the first flag of the second logic and the first image of the first pixel included for the first pixel block having the first flag of the first logic. A step of selecting one first pixel value from among the prime values to obtain a third pixel value, and a drawing stored in the external memory for the first pixel block having the first flag of the second logic A step of reading the corresponding second pixel block and second flag included in the three-dimensional graphics image before processing, and a part of the second pixel including the logic of the second flag are filled with different colors or without filling. When indicating that there is a third pixel value, the step of setting the first pixel value of all the first pixels included in the first pixel block having the first flag of the second logic to the third pixel value; In the case of indicating the same color fill, the first pixel value of the first pixel having coverage indicating the color fill state among the first pixels of the first pixel block and the cover indicating the color unfilled state. Instead of the first pixel value of the first pixel having the first pixel value, the second pixel value of the second pixel block is set to the third pixel value, and the third pixel value, the first logic, and the second logic And a step of writing pixel data comprising a first flag to an external memory.

According to the present invention, it is possible to provide a method for forming image data for reducing the amount of image data used for anti-aliasing processing, and a writing method for reducing the number of times the formed image data is written to an external memory. .

FIG. 1 shows a semiconductor device including a drawing circuit 10, an image data processing circuit 20, and an external memory 30. FIG. 2 shows 8 × 8 pixels divided into 2 × 2 pixel blocks. FIG. 3 is a diagram showing the relationship between the flag and the pixel value stored in the external memory 30 for 8 × 8 pixels divided into 2 × 2 pixel blocks. FIG. 4 is a diagram for explaining the depth value, the flag related to the depth value, and the X and Y increment values related to the depth value. FIG. 5 is a diagram for explaining the operation of the pixel access unit 50 and the pixel access unit 50. 6A and 6B show specific circuit examples of the flag generation unit 51 and the pixel writing unit 52. FIG. FIG. 6C shows a specific circuit example of the pixel readout unit 53. FIG. 7 is a diagram for explaining the operation of the pixel access unit 50. FIG. 8 is a flowchart for explaining the entire writing operation of the pixel access unit 50. FIG. 9 is a flowchart for explaining the entire reading operation of the pixel access unit 50. FIG. 10 is a diagram for explaining the operation of the depth access unit 60 and the depth access unit 60. 11A and 11B show specific circuit examples of the flag generation unit 61 and the depth writing unit 62. FIG. FIG. 11C shows a specific circuit example of the depth reading unit 63. FIG. 12 is a diagram for explaining the operation of the depth access unit 60. FIG. 13 is a flowchart for explaining the entire writing operation of the depth access unit 60. FIG. 14 is a flowchart for explaining the entire reading operation of the depth access unit 60.

The present invention includes the embodiments described below that have been modified by the design that can be conceived by those skilled in the art, and those in which the components shown in the embodiments have been recombined. Further, the present invention includes those in which the constituent elements are replaced with other constituent elements having the same operational effects, and are not limited to the following embodiments.

FIG. 1 shows a semiconductor device including a drawing circuit 10, an image data processing circuit 20, and an external memory 30.
The drawing circuit 10 is a circuit that forms a three-dimensional graphics image to be drawn by rendering processing from a three-dimensional model and an original image. Here, the rendering process includes, for example, a projection process, a rasterization process, a hidden surface removal process, and a shooting / effect applying process.

The image data processing circuit 20 includes a pixel access unit 50 and a depth access unit 60.
The pixel access unit 50 performs data processing on the pixel values and coverage of pixels constituting the three-dimensional graphics image after the drawing processing by the drawing circuit 10, and selects the flag generated by the data processing and the data processing. This is a circuit for storing the pixel value of the selected pixel in the external memory 30.
The pixel access unit 50 is a circuit that develops a pixel value and coverage before drawing processing from a flag received from the external memory 30 and a selected pixel value.
The depth access unit 60 performs data processing on the depth value and coverage of the pixels constituting the three-dimensional graphics image after the rendering processing by the rendering circuit 10, and generates a flag generated by the data processing and the data processing. This is a circuit for storing in the external memory 30 the X and Y increment values and the selected depth value generated by the data processing.
The depth access unit 60 is a circuit that expands the flag received from the external memory 30, the X and Y increment values, and the selected depth value into the depth value before the drawing process and the coverage.

FIG. 2 shows 8 × 8 pixels divided into 2 × 2 pixel blocks. The pixel block coverage will be described with reference to FIG.
For each pixel, a coverage indicating a color fill state is assigned, and when there is a color fill, a logic “1” is assigned to the coverage, and when there is no color fill, a logic “0” is assigned to the coverage. Therefore, coverage refers to a logical value assigned to each pixel block expressed as a binary number arranged in the order of upper left, upper right, lower left, and lower right.
In FIG. 2, vertical 8 × horizontal 8 pixels are shown. However, the present invention is not limited to this, and generally the coverage of vertical M × horizontal N pixels (M and N are arbitrary positive integers) is also included. It is expressed similarly. In addition, the pixel block is composed of 2 × vertical pixels in the above, but may be composed of pixels of vertical L × horizontal K (K and L are arbitrary positive integers).

FIG. 3 is a diagram showing the relationship between the flag and the pixel value stored in the external memory 30 for 8 × 8 pixels divided into 2 × 2 pixel blocks.
In the upper left of FIG. 3, pixels whose coverage logic is “1” are represented by vertical stripes.
Next, in the upper right of FIG. 3, pixel blocks that are to be color-filled are extracted from all the pixels constituting the 2 × 2 pixel block, and are represented by horizontal stripes.
Here, the flag is a logical value. In each pixel block, when all the pixels belonging to the pixel block are color-filled, the logic is “1”. Otherwise, the logic is “0”. Become.
Therefore, the lower left of FIG. 3 shows the logical value of the flag in each pixel block. Next, in the lower right of FIG. 3, among the respective pixel blocks, those in which the pixel values are stored in the external memory 30 are represented by vertical stripes, and those not stored are diagonal stripes. When the flag logic is “1”, only the upper left pixel value of the pixel block is stored in the external memory 30. On the other hand, when the flag logic is “0”, only the pixel value of the pixel to be color-filled is stored in the external memory 30.

FIG. 4 is a diagram for explaining the depth value, the flag related to the depth value, and the X and Y increment values related to the depth value.
The upper part of FIG. 4 is a diagram illustrating the state of the flag of the image block included in the three-dimensional graphics image to be handled. If all pixels in the image block are filled, the flag logic is “1”; otherwise, the flag logic is “0”. Therefore, the logic of the flags of the second and third pixel blocks in the first column is “1”. The logic of all flags of the pixel blocks in the second column is “1”. The logic of the flags of the second, third, and fourth pixel blocks of the pixel blocks in the third column is “1”. The logic of the flag of the third pixel block of the pixel blocks in the fourth column is “1”. The logic of other pixel block flags is “0”.
The lower diagram in FIG. 4 shows that when the logic of the pixel block flag is “1”, the depth value of the upper right pixel, the depth value of the lower left pixel, and the depth of the lower right pixel are based on the depth value of the upper left pixel. It indicates that a numerical value represented by an X, Y increment value from the reference value is set in the pixel block. Further, when the logic of the flag of the pixel block is “0”, it indicates that each depth value belonging to the pixel is set in the pixel block. Therefore, the external memory 30 stores the depth value or depth value and X and Y increment values set for each pixel block.

FIG. 5 is a diagram for explaining the operation of the pixel access unit 50 and the pixel access unit 50.
The pixel access unit 50 includes a flag generation unit 51, a pixel writing unit 52, and a pixel reading unit 53.
The pixel access unit 50 creates a flag from the coverage of each pixel for each pixel block composed of 2 × 2 pixels when the 3D graphics image includes M × N pixels. It has a function of storing in the external memory 30. In addition, it has a function of changing the pixel value of the external memory 30 for the pixel block in which the logical value of the flag is “0” when the drawing process is performed on the vertical M × N horizontal pixels. Hereinafter, functions of each circuit unit included in the pixel access unit 50 in order to provide the above functions will be described.
The flag generation unit 51 is a circuit that generates a flag from the coverage received from the drawing circuit 10.
The pixel writing unit 52 receives the pixel value from the writing request from the drawing circuit 30 and outputs the pixel value to the external memory 30 together with the writing request. The pixel writing unit 52 receives the flag and the coverage from the flag generation unit 51. When the pixel writing unit 52 receives a writing request from the drawing circuit, it issues a reading request to the pixel reading unit 53 and receives a flag and a pixel value.
The pixel reading unit 53 receives a pixel value from the drawing circuit 10 together with a read request. The pixel reading unit 53 sends a read request to the external memory 30 and receives a flag and a pixel value. The pixel reading unit 53 outputs a flag and a pixel value when receiving a reading request from the pixel writing unit 52.

6A, 6B, and 6C show specific circuit examples of the flag generation unit 51, the pixel writing unit 52, and the pixel reading unit 53. FIG.
Referring to FIG. 6A, the flag generation unit 51 according to the first embodiment is a 4-input AND, and when a 4-bit coverage is input, a 1-bit flag is generated. The coverage is a flag attached to each pixel and indicating whether the pixel is drawn (filled) or not drawn (not filled) after the rendering process. That is, it is 0 when not painted, and 1 when painted. Here, when MSAA is executed using four times the number of pixels, a 4-bit coverage consisting of 2 columns × 2 rows is handled. In that case, the flag generation unit 51 becomes a 4-input AND as shown in FIG. 6A.

Then, if all four pixels do not have the same color, in other words, if the four pixels to be drawn are not filled, the flag is 0. On the other hand, if all the colors are the same, the flag is 1.

Continuing the description with reference to FIG. 6B, the pixel writing unit 52 in the first embodiment includes a comparison circuit 52a, a 2-bit counter 52b, an AND 52c, and a selector 52d.
When the flag indicating the logic “0” is received from the flag generation unit 51, the pixel writing unit 52 indicates that the logic of the read request to the pixel reading unit 53 and the write request to the external memory 30 is “0”. Accordingly, reading from the pixel reading unit 53 to the pixel writing unit 52 and writing to the external memory 30 from the pixel writing unit 52 are not performed.

When a flag representing logic 7 “1” is received from the flag generation unit 51, the read request logic to the pixel reading unit 53 is “1”, so that the read request from the pixel writing unit 52 to the pixel reading unit 53 is performed. Is done. The flag of logic “1” is input to the 2-bit counter 52b, and the 2-bit counter 52b is counted up. The comparison circuit 52a displays the count value from the 2-bit counter 52b as a fixed count value set in the comparison circuit 52a itself (in the embodiment, the count value is expressed as "00" in binary number and expressed in decimal number) 4). When the comparison circuit 52a reaches a fixed count value, the comparison circuit 52a ends the count-up of the 2-bit counter 52b, resets the count value, that is, fixes the count value to “00”.

The comparison circuit 52a continues to output an enable signal to the AND 52c while the 2-bit counter 52b outputs a binary number from the binary number "00" to a fixed count value.
As a result, since the AND 52c receives the enable signal from the comparison circuit 52a and the write request from the drawing circuit 10 as input signals, the write signal is sent to the external memory 30 when the logic of the enable signal is “0”. Output.

The selector 52d selects the pixel value from the drawing circuit when the coverage logic is “1”, and selects the pixel value from the pixel reading unit when the coverage logic is “0”. Then, the selector 52d outputs the selected pixel value to the external memory 30 as the pixel value.

6C, the pixel reading unit 53 in the first embodiment includes a pixel holding buffer 53a, a selector 53b, and an AND 53c.

The pixel holding buffer 53a is a circuit that receives pixel values from the external memory 30 and temporarily holds them. The pixel value temporarily stored is the pixel value at the upper left of the four pixel values of 2 × 2 in the vertical direction. This is because when all the four vertical 2 × horizontal pixel values of interest have the same color, only the upper left pixel value is output to the drawing circuit 10 and the other pixel values are not output.
The selector 53b selects the pixel value held in the pixel holding buffer 53a when the logic of the flag is “1”, and selects the pixel value from the external memory 30 when the logic of the flag is “0”. .
The AND 53 c outputs a read request to the external memory 30 when both the read request from the pixel writing unit 52 and the read request from the drawing circuit 10 are logic “1”.

FIG. 7 is a diagram for explaining the operation of the pixel access unit 50. However, the operation of the pixel access unit 50 described in FIG. 7 relates to one pixel block. The operation of the pixel access unit 50 when the logical value of the flag of the pixel block is changed from “1” to “0” by the drawing process will be described.
The pixel block C composed of the pixel values output from the external memory 30 to the pixel reading unit 53 is a set of pixel values each having the same color and having the upper left pixel and a flag. That is, the pixel block C includes a pixel value and a corresponding flag on the upper left, and the others have no pixel value.
A pixel block A including pixel values output from the drawing circuit 10 to the pixel writing unit 52 is a set of 2 × vertical × 2 horizontal pixel values with coverage = 1010. That is, in the coverage, the pixel block A has different pixel fill pixel values in the upper left and lower left corresponding to the logic “1” bit, but there is no pixel value in the upper right and lower right.
Therefore, the pixel block B written in the external memory 30 after the drawing process is inherited from the left half of the pixel block A, the filled pixel values of different colors in the upper left and lower left, and the same color inherited from the right half of the pixel block C. It consists of the filled pixel values.
The pixel value of the pixel block B is selected by the selector 52d, and in the coverage, the pixel value on the left half corresponding to the logical “1” bit and the pixel on the right half corresponding to the logical “0” bit This is because the value is selected.

FIG. 8 is a flowchart for explaining the entire writing operation of the pixel access unit 50. In addition, the writing operation described in FIG. 8 is an operation in which the pixel access unit 50 receives the pixel data after performing the drawing process on the pixel value of the vertical M × horizontal N pixel and writes it to the external memory 30. Say. However, the writing operation shown in FIG. 8 is for a vertical 2 × horizontal 2 pixel block, and by performing these operations a plurality of times, vertical M × horizontal N pixels are processed. Therefore, before starting this flowchart, a step of dividing the vertical M × horizontal N pixels into vertical 2 × horizontal 2 pixel blocks and recognizing them is performed. The flowchart will be described below in the order of steps.
Step OP10: The coverage of the pixels A1, A2, A3, A4 belonging to the pixel block A shown in FIG.
Step OP20: Whether all the pixels A1, A2, A3, and A4 belonging to the pixel block A after the drawing process are drawn is determined based on the logical value of the coverage of each pixel. For example, when all the logical values of the coverage of each pixel display a fill, it is determined that all are drawn, and when even one of the logical values of the coverage is not a solid display, it is not determined that all are drawn. When it is determined that all drawing is performed, the process proceeds to step OP40. If it is determined that all are not drawn, the process proceeds to step OP30.
Step OP30: The flag before the drawing process of the pixel block A is read from the external memory 30. Thereafter, the process proceeds to Step OP50.
Step OP50: The logical value of the flag before the drawing process read in step OP30 is rewritten to the logical value “0” and written again to the external memory 30. Thereafter, the process proceeds to Step OP60.

Step OP60: A branch in the flowchart is determined using the flag of the pixel block A read in step OP30. That is, when the logical value of the flav before drawing processing is “0”, among the pixels included in the pixel block C, there are pixels that are not painted and others that are painted, so the process proceeds to step OP100 corresponding to the situation. . On the other hand, when the logical value of the flag before the rendering process is “1”, all the pixels included in the pixel block C are filled pixels of the same color, so the process proceeds to step OP70 corresponding to the situation.

Step OP100: A pixel block B is created by overwriting the pixel block C with respect to the pixel having the logical value “1” of coverage among the pixels belonging to the pixel block A after the drawing process read out in step OP10. Then, the pixel value in the state of the pixel block B is written into the external memory 30. Thereafter, the pixel writing operation is terminated.

Step OP70: In step OP60, all the pixels included in the pixel block C are determined to be filled pixels of the same color before the drawing process. However, in the determination in step OP20, it is determined that all the pixels of the pixel block A are not filled after the drawing process. Therefore, in step OP70, the pixel value of the upper left pixel C1 stored in the external memory 30 among the pixels of the pixel block C before the drawing process is read.
Step OP80: The pixels C2, C3, and C4 are restored from the pixel C1 at the upper left of the pixel block C before drawing processing read from the external memory 30 in Step 70.
Step OP90: The pixels C1, C2, C3, and C4 of the pixel block C before the drawing process are sent to the pixel writing unit 52 and stored as the pixels B1, B2, B3, and B4 of the pixel block B on the register for writing. To do. After that, of the pixels of the pixel block A after the drawing process, pixels whose coverage logical value is “1” (for example, A1 and A3 when the coverage is (1010)) are overwritten on the upper right and lower right. Then, it progresses to step OP110.
Step OP110: Pixels B1, B2, B2, B2, and B3 formed by combining the pixels C1, C2, C3, and C4 of the pixel block C before the drawing process and the pixels A1, A2, A3, and A4 of the pixel block A after the drawing process B3 and B4 are written in the external memory 30 as pixel values of the pixel block B.

Step OP40: Since the pixels A1, A2, A3, and A4 belonging to the pixel block A after the drawing process are pixels that are filled with the same color, the logical value of the flag of the pixel block A is “1”. Therefore, the logical value of the flag and the pixel value of the upper left pixel of the pixel block A are set as the pixel value of the upper left pixel of the pixel block B. Thereafter, the process proceeds to step OP120.
Step OP120: Only the pixel value of the pixel A1 (upper left) belonging to the pixel block A after the drawing process is written in the external memory 30 as the upper left pixel value of the pixel block B.

From the above, when handling vertical M × horizontal N pixels after the rendering process, the pixel access unit 50 treats the pixel blocks by dividing them into vertical 2 × horizontal 2 pixel blocks. When writing the vertical M × horizontal N pixels after the drawing process to the external memory 30, if the logical value of the flag is “1” before and after the drawing process, the pixel values and coverages of all the pixel blocks are displayed. Instead of writing back to the external memory 30, only the upper left pixel value and the logical value of the flag are written back. Then, the number of accesses to the external memory 30 can be reduced as compared with the case where all pixel values and coverage belonging to the pixel block are written back. Furthermore, since the flag consists of only a 1-bit logical value, the storage area for storing the upper left pixel value and 1 bit of the flag stores the pixel value of each pixel related to one pixel block and the coverage of each pixel. It becomes smaller than the storage area.

Here, when dealing with vertical M × horizontal N pixels using the variable-length compressed data method, the vertical M × horizontal N pixels before the drawing processing are converted into vertical M × horizontal N pixels after the drawing processing. The number of accesses to the external memory 30 is compared with the number of accesses in the case of handling vertical M × horizontal N pixels using the method shown in this embodiment.

In the variable length compressed data method, the type and frequency of pixel values of vertical M × N horizontal pixels are analyzed, and “0” is set for the pixel value having the highest frequency, and “1” is set for the pixel value having the next highest frequency. Then, variable length data is assigned such that “10” is assigned to the pixel value having the next highest frequency. When the pixel value is a fixed length, for example, 4 bits, the storage area for storing the pixel value can be reduced by the amount replaced with the variable length data.

Therefore, it is considered that the pixel value of the vertical M × horizontal N pixel that is compressed by the variable length compression data method and stored in the external memory 30 is replaced with the pixel value after the drawing process. Then, in order to perform the above replacement, the following operation will be performed. First, in the first step, the compressed data is expanded to the original pixel values of M × N pixels. Next, a drawing process is performed in the second step. Next, variable length compression processing is performed on the pixel values of the vertical M × horizontal N pixels after the drawing processing in the third step, and the pixel values after the variable length compression processing are output to the external memory 30.
Then, in the first step, the compressed data is expanded into pixel values of vertical M × horizontal N pixels.
M × N × (1 + S1) + M × N × 4 (... Equation (1)) accesses are performed. Here, coverage is 1 bit, S1 is the average number of bits of variable-length pixel values of M × N pixels, and the number of bits of fixed-length pixel values corresponding to variable-length pixel values is 4 bits.
That is, the first term is accessed to read out the pixel values subjected to coverage and variable length compression processing. Furthermore, the second term is accessed to read out a fixed-length pixel value corresponding to the pixel value represented by the assigned variable-length bits.
Next, when writing pixel values of vertical M × horizontal N pixels represented by compressed data in the third step,
M × N × (1 + S2) (... Expression (2)) times of access is performed. Here, the coverage is 1 bit, and S2 is the average number of bits of variable length pixel values of M × N pixels. Note that the variable length compression process is performed by the pixel writing unit 52.

On the other hand, when the pixel value of the vertical M × horizontal N pixel is replaced with the pixel value of the vertical M × horizontal N pixel after the drawing processing by the method shown in the present embodiment, the first step is vertical M × horizontal N. The pixel value of each pixel is read from the external memory. In the second step, drawing processing is performed. Next, in the third step, pixel values of vertical M × horizontal N pixels are output to the external memory 30 by the method shown in the present embodiment.
First, in the first step, when the logical value of the flag of the pixel block of M × N × T1 (0 or more and less than 1) is “1”,
(M × N × (1−T1) × 5) + (M × N × T1 × 5/4) (... Expression (3)) times. Here, the coverage and flag are 1 bit, and the pixel value is 4 bits with a fixed length.
Further, in the third step, when the logical value of the flag of the pixel block of T2 (0 or more and less than 1) is “1”,
(M × N × (1−T2) × 5) + (M × N × T2 × 5/4) (... Expression (4)) times. Here, the coverage and flag are 1 bit, and the pixel value is 4 bits with a fixed length.

In this embodiment, the number of accesses to the pixel access unit 50 and the external memory 30 is the sum of Expression (3) and Expression (4), and is M × N × (10− (T1 + T2) × 3 × 5/4). .
On the other hand, when the variable compressed data is used as the pixel value of the pixel, the sum of Expression (3) and Expression (4) is obtained, which is M × N × (6 + S1 + S2).
Here, S1 and S2 are average bit numbers of variable-length pixel values of M × N pixels. Then, even if the average number of bits of the variable-length pixel value is approximately 1 bit, if T1 + T2 is 0.5 or more and 2 or less, the number of accesses from the pixel writing unit 52 to the external memory 30 in the present embodiment However, it can be seen that it decreases compared to the variable length compressed data system. That is, in most cases, the number of accesses between the pixel access unit 50 and the external memory 30 in this embodiment decreases.

FIG. 9 is a flowchart for explaining the entire reading operation of the pixel access unit 50. The read operation described with reference to FIG. 9 is an operation of reading from the external memory 30 in order to perform drawing for pixel values of vertical M × horizontal N pixels. However, the readout operation shown in FIG. 9 is for a vertical 2 × horizontal 2 pixel block, and by performing these operations a plurality of times, vertical M × horizontal N pixels are processed. Therefore, before starting this flowchart, a step of dividing the vertical M × horizontal N pixels into vertical 2 × horizontal 2 pixel blocks and recognizing them is performed. The flowchart will be described below in the order of steps.
Step OP210: The flag for the pixel block is read from the external memory 30.
Step OP220: If the logic of the read flag is “1”, the process proceeds to step OP230. On the other hand, if the logic of the read flag is “0”, the process proceeds to step 220.
Step OP230: Read pixel values for four pixels belonging to the pixel block from the external memory 30. Thereafter, the reading of the pixel value is finished.
Step OP240: Read out only the pixel value of the upper left pixel of the pixel block. Next, the process proceeds to step OP240.
Step OP250: The read pixel value of the upper left pixel is output to the drawing circuit 10 continuously four times. Instead of performing this step, pixel values for four pixels may be created in the drawing circuit 10 from the read pixel value of the upper left pixel.

FIG. 10 is a diagram for explaining the operation of the depth access unit 60 and the depth access unit 60.
The depth access unit 60 includes a flag generation unit 61, a depth writing unit 62, and a depth reading unit 63.
The depth access unit 60 creates a flag from the coverage of each pixel and stores it in the external memory 30 for a pixel block composed of 2 × 2 pixels when there are M × N pixels. Have
In addition, it has a function of changing the pixel value of the external memory 30 for the pixel block in which the logical value of the flag is “0” when the drawing process is performed on the vertical M × N horizontal pixels. Hereinafter, functions of each circuit unit included in the depth access unit 60 in order to provide the above-described functions will be described.
The flag generation unit 61 is a circuit that generates a flag from the coverage received from the drawing circuit 10.
The depth writing unit 62 receives the writing request from the drawing circuit 30 and outputs the depth value and the X, Y increment value to the external memory 30 together with the writing request. The depth writing unit 62 receives a flag from the flag generation unit 61. When receiving a write request from the drawing circuit, the depth writing unit 62 issues a read request to the depth reading unit 63 and receives a flag and a depth value.
The depth reading unit 63 receives the depth value from the drawing circuit 10 together with the read request. The depth reading unit 63 sends a read request to the external memory 30 and receives a flag, a depth value, and X and Y increment values. The depth reading unit 63 outputs a flag and a depth value when receiving a read request from the depth writing unit 62.

11A, 11B, and 11C show specific circuit examples of the flag generation unit 61, the depth writing unit 62, and the depth reading unit 63. FIG.
Referring to FIG. 11A, the flag generation unit 61 in the embodiment is a 4-input AND, and when a 4-bit coverage is input, a 1-bit flag is generated. Using the coverage indicating whether or not the pixel is painted, it is determined whether or not the depth is attached to each pixel. This is because the depth exists if the pixel is painted. Therefore, the coverage logic is 0 when there is no data in the depth direction, and is 1 when there is data in the depth direction. Here, when MSAA is executed using four times the number of pixels, a 4-bit coverage consisting of 2 columns × 2 rows is handled. In that case, the flag generation unit 61 becomes a 4-input AND as shown in FIG. 11A.

If so, the flag is set to 0 when no data in the depth direction is attached to all four pixels, in other words, when the four pixels to be drawn have no depth. On the other hand, if there is data in the depth direction in all, the flag is 1.

Continuing with reference to FIG. 11B, the depth writing unit 62 in the embodiment includes a comparison circuit 62a, a 2-bit counter 62b, an AND 62c, and a selector 62d.
When the flag representing the logic “0” is received from the flag generation unit 61, the depth writing unit 62 indicates that the logic of the read request to the depth reading unit 63 and the write request to the external memory 30 is “0”. Therefore, reading from the depth reading unit 63 to the depth writing unit 62 and writing to the external memory 30 from the depth writing unit 62 are not performed.

When the flag representing the logic “1” is received from the flag generation unit 61, the logic of the read request to the depth reading unit 63 is “1”, so that the reading request from the depth writing unit 62 to the depth reading unit 63 is made. Done. The flag of logic “1” is input to the 2-bit counter 62b, and the 2-bit counter 62b is counted up. The comparison circuit 62a displays the count value from the 2-bit counter 62b as a fixed count value set in the comparison circuit 62a itself (in the embodiment, the count value is expressed as "00" in binary number and expressed in decimal number) 4). When the comparison circuit 62a reaches the fixed count value, it finishes counting up the 2-bit counter 62b, resets the count value, that is, fixes the count value to “00”.

The comparison circuit 62a continues to output an enable signal to the AND 62c while the 2-bit counter 62b outputs a binary number from the binary number "00" to a fixed count value.
As a result, since the AND 62c receives the enable signal from the comparison circuit 62a and the write request from the drawing circuit 10 as input signals, the write signal is sent to the external memory 30 when the logic of the enable signal is “0”. Output.

The selector 62d selects the depth value from the drawing circuit when the coverage logic is “1”, and selects the depth value from the depth reading unit when the coverage logic is “0”. Then, the director 62d outputs the selected depth value to the external memory 30 as the depth value or the X, Y increment value.

11C, the depth reading unit 63 in the embodiment includes a depth holding buffer 63a, a selector 63b, an AND 63c, and a depth interpolation 63d.

The depth holding buffer 63a is a circuit that receives the depth value from the depth interpolation 63d and temporarily holds it.
The selector 63b selects the depth value held in the depth holding buffer 63a when the logic of the flag is "1", and selects the depth value output from the depth interpolation 63d when the logic of the flag is "0". An interpolated value with X, Y increment values is selected.
The AND 63 c outputs a read request to the external memory 30 when both the read request from the depth writing unit 62 and the read request from the drawing circuit 10 are logic “1”.

FIG. 12 is a diagram for explaining the operation of the depth access unit 60. However, the operation of the depth access unit 60 described in FIG. 12 relates to one pixel block. Also, the operation of the pixel access unit 60 when the logical value of the flag of the pixel block is changed from “1” to “0” by the drawing process will be described.
Here, the pixel block F has depth values for all the pixels, and the depth value of each pixel is represented by an X, Y increment value with the depth value at the upper left as a reference value. Further, the pixel block F has a flag related to the depth corresponding to the pixel value at the upper left.
The pixel block D is a set of 2 × vertical × 2 pixel values with coverage = 1010. That is, in the coverage, in the pixel block D, pixels having different depth values exist in the upper left and lower left, but there are no depth values in the upper right and lower right pixels, corresponding to the logic “1” bit.
Therefore, the pixel block E written to the external memory 30 after the drawing process is composed of the upper left and lower left depth values inherited from the left half of the pixel block D and the depth value inherited from the right half of the pixel block F. Yes. Here, the depth value from the pixel block F is obtained by adding the X and Y increments to the depth value for the upper left pixel as a reference.
The pixel value of the pixel block E is selected by the selector 62d. In the coverage, the left half pixel value corresponding to the logical “1” bit corresponds to the logical “0” bit, and the right half pixel corresponding to the logical “0” bit. This is because the value is selected.

FIG. 13 is a flowchart for explaining the entire writing operation of the depth access unit 60. The flowchart will be described below in the order of steps. However, the writing operation shown in FIG. 13 is for a vertical 2 × horizontal 2 pixel block, and by performing these operations a plurality of times, vertical M × horizontal N pixels are processed. Further, the writing operation described in FIG. 13 is an operation in which the depth access unit 50 receives the depth value after the drawing process is performed on the depth value of the vertical M × N horizontal pixel, and writes it to the external memory 30. Say.
Step OP310: The coverage of the pixels D1, D2, D3, D4 belonging to the pixel block D shown in FIG.
Step OP320: It is determined by the logical value of the coverage of each pixel whether there is a depth value for all of the pixels D1, D2, D3, D4 belonging to the pixel block D after the rendering process. When all the pixels are drawn and it is determined that a depth value exists, the process proceeds to step OP340. When it is determined that there is a pixel that is not drawn and there is a pixel that has no depth value, the process proceeds to step OP330.
Step OP330: The flag before the drawing process of the pixel block D is read from the external memory 30. Thereafter, the process proceeds to Step OP350.
Step OP350: The logical value of the flag before the drawing process read out in step OP330 is rewritten to the logical value “0” and written again in the external memory 30. Thereafter, the process proceeds to Step OP360.

Step OP360: The branch in the flowchart is determined using the flag of the pixel block D read in step OP330. That is, when the logical value of the flav before drawing processing is “0”, among the pixels included in the pixel block D, there are pixels that have no depth value and pixels that have a depth value. Proceed to On the other hand, when the logical value of the flag before the drawing process is “1”, all the pixels included in the pixel block D are pixels having depth values, and thus the process proceeds to step OP370 corresponding to the situation.

Step OP400: A pixel block E is created by overwriting the pixel block F with respect to the pixel having the logical value “1” of coverage among the pixels belonging to the pixel block D after the drawing process read out in the step OP310. Then, the depth value of the state of the pixel block E is written into the external memory 30. Thereafter, the depth writing operation is terminated.

Step OP370: In step OP360, the pixels included in the pixel block D are all determined to be filled pixels of the same color before the drawing process.
However, in the determination in step OP320, after the rendering process, it is determined that not all of the pixels in the pixel block D are filled and there are pixels for which there is no depth value.
Therefore, in step OP370, the depth value and the X and Y increment values of the upper left pixel F1 stored in the external memory 30 among the pixels of the pixel block F before the drawing process are read.
Step OP380: The depth value of the pixel F2, the depth value of F3, the depth value of F4 are read from the depth value of the upper left pixel F1 and the X and Y increment values of the pixel block F before drawing processing read from the external memory 30 in Step 370. Restore the value.
Step OP390: Sends the depth value of the pixel F1, the depth value of F2, the depth value of F3, and the depth value of F4 of the pixel block F before drawing processing to the depth writing unit 62, and the pixel block on the register for writing This is stored as the depth value of the pixel E1 of E, the depth value of E2, the depth value of E3, and the depth value of E4. After that, among the pixels of the pixel block D after the drawing process, the pixels whose coverage logical value is “1” (for example, when the coverage is (1010), the depth value of D1 and the depth value of D3), Overwrite in the lower right. Thereafter, the process proceeds to step OP410.
Step OP410: The depth value of the pixel F1, the depth value of F2, the depth value of F3, the depth value of F4 of the pixel block F before the drawing process, the depth value of the pixel D1 of the pixel block D after the drawing process, and the depth of D2 Value, the depth value of D3, and the depth value of D4, the depth value of the pixel E1, the depth value of E2, the depth value of E3, the depth value of E3, and the depth value of E4 are stored in the external memory 30 in the pixel block E. Write as a pixel.

Step OP340: Since the pixels D1, D2, D3, and D4 belonging to the pixel block D after the drawing process are pixels having a depth value, the logical value of the flag of the pixel block D is “1”. Therefore, the logical value of the flag is written in the external memory 30. Thereafter, the process proceeds to step OP420.
Step OP420: Write the depth value of the pixel D1 (upper left) belonging to the pixel block D after the rendering process and the X and Y increment values of the pixels D2, D3, and D4 to the external memory 30.

From the above, when handling vertical M × horizontal N pixels after the drawing process, the depth access unit 60 treats the pixel blocks by dividing them into vertical 2 × horizontal 2 pixel blocks. When writing the vertical M × horizontal N pixels after the drawing process to the external memory 30, if the logical value of the flag is “1” before and after the drawing process, the depth values of all the pixel blocks are stored in the external memory. Instead of writing back to 30, only the depth value at the upper left, the X and Y increment values, and the logical value of the flag are written back. As a result, the number of accesses to the external memory 30 can be reduced as compared with the case where all depth values and coverages belonging to the pixel block are written back. Further, since the flag consists of only a 1-bit logical value, the storage area for storing the upper left flag value, the X and Y increment values, and the 1 bit of the flag includes the depth value of each pixel related to one pixel block, This is smaller than the storage area for storing pixel coverage.

In the variable length compressed data method, the type and frequency of depth values of vertical M × N horizontal pixels are analyzed, and “0” is assigned to the pixel value having the highest frequency, and “1” is assigned to the pixel value having the next highest frequency. Then, variable length data is assigned such that “10” is assigned to the pixel value having the next highest frequency. When the pixel value is a fixed length, for example, 4 bits, the storage area for storing the pixel value can be reduced by the amount replaced with the variable length data.

Therefore, it is considered to replace the depth value of the vertical M × horizontal N pixel that is compressed by the variable length compression data method and stored in the external memory 30 with the depth value after the drawing process. Then, in order to perform the above replacement, the following operation will be performed. First, in the first step, the compressed data is expanded to the original depth M × N depth value. Next, a drawing process is performed in the second step. Next, variable length compression processing is performed on the depth value of the vertical M × width N pixels after the drawing processing in the third step, and the depth value after the variable length compression processing is output to the external memory 30.
Then, in the first step, the compressed data is expanded into pixel values of vertical M × horizontal N pixels.
M × N × 1 + M × N × S1 + M × N × 4 (... Expression (1)) accesses are performed. Here, coverage is 1 bit, S1 is the average number of bits of variable-length pixel values of M × N pixels, and the number of bits of fixed-length pixel values corresponding to variable-length pixel values is 4 bits.
That is, the first term of the equation (1) is accessed to read the coverage. Further, the second term is accessed to read the depth value that has been subjected to the variable length compression processing. Furthermore, the third term is accessed to read out a fixed length depth value corresponding to the depth value represented by the assigned variable length bits.
Then, when writing the depth value of the vertical M × horizontal N pixel represented by the compressed data in the third step,
M × N × 1 + M × N × S2 (... Equation (2)) accesses are performed. Here, the coverage is 1 bit, and S2 is the average number of bits of the variable length depth value of M × N pixels.

On the other hand, when the depth value of the vertical M × horizontal N pixel is replaced with the depth value of the vertical M × horizontal N pixel after the drawing processing by the method shown in the present embodiment, the first step is vertical M × horizontal N. The depth value of the pixel is read from the external memory. In the second step, drawing processing is performed. Next, in the third step, the depth value of the vertical M × N horizontal pixels is output to the external memory 30 by the method shown in the present embodiment.
First, in the first step, when the logical value of the flag of the pixel block of M × N × T1 (0 or more and less than 1) is “1”,
(M × N × (1−T1) × 5) + (M × N × T1 × 11/4) (... Expression (3)) times of access. Here, the coverage is 1 bit, the depth value is 4 bits with a fixed length, and the X and Y increment values are 2 bits.
Further, in the third step, when the logical value of the flag of the pixel block of T2 (0 or more and less than 1) is “1”,
(M × N × (1−T2) × 5) + (M × N × T2 × 11/4) (... Expression (4)) times. Here, the coverage is 1 bit and the pixel value is a fixed length of 4 bits.

In this embodiment, the number of accesses between the pixel access unit 50 and the external memory 30 is the sum of Expression (3) and Expression (4), and is M × N × (10− (T1 + T2) × 9/4).
On the other hand, when variable compressed data is used as the pixel value of a pixel, the sum of Expression (1) and Expression (2) is obtained, which is M × N × (6 + S1 + S2).
Here, S1 and S2 are average bit numbers of variable-length pixel values of M × N pixels. Then, even if the average number of bits of the variable-length pixel value is approximately 1, when T1 + T2 is 1 or more and 2 or less, the number of accesses from the depth writing unit 62 in this embodiment to the external memory 30 is It can be seen that this is reduced compared to the variable length compressed data system. That is, in most cases, the number of accesses between the depth access unit 60 and the external memory 30 in this embodiment decreases.

FIG. 14 is a flowchart for explaining the entire reading operation of the depth access unit 60. The flowchart will be described below in the order of steps. However, the readout operation shown in FIG. 14 is for a vertical 2 × horizontal 2 pixel block, and by performing these operations a plurality of times, vertical M × horizontal N pixels are processed. Further, the read operation described with reference to FIG. 14 refers to an operation of reading from the external memory 30 in order to perform drawing for pixel values of vertical M × horizontal N pixels.
Step OP510: The flag for the pixel block is read from the external memory 30.
Step OP520: If the logic of the read flag is “1”, the process proceeds to Step OP530. On the other hand, if the logic of the read flag is “0”, the process proceeds to step 540.
Step OP540: Depth values for four pixels belonging to the pixel block are read from the external memory 30. Thereafter, reading of the depth value is terminated.
Step OP530: Only the depth value of the upper left pixel of the pixel block and the X and Y increment values for four pixels are read out. Next, the process proceeds to step OP550.
Step OP550: A depth value for 4 pixels is generated from the read depth value of the upper left pixel and the X and Y increment values for 4 pixels. Instead of performing this step, a depth value for four pixels may be created in the drawing circuit 10 from the depth value of the upper left pixel and the X and Y increment values for four pixels.

It is possible to provide a method for forming image data for reducing the amount of image data used for anti-aliasing processing, and a writing method for reducing the number of times the formed image data is written to an external memory.

DESCRIPTION OF SYMBOLS 10 Drawing circuit 20 Image data processing circuit 30 External memory 50 Pixel access part 51 Flag generation part 52 Pixel writing part 53 Pixel reading part 60 Depth access part 61 Flag generation part 62 Depth writing part 63 Depth reading part

Claims

Dividing the pixels arranged in a matrix in the three-dimensional graphics image into pixel blocks composed of the pixels in K rows and KL columns;
For each pixel block, using the coverage indicating the color fill state of the pixel, for all the included pixels, if the same color is filled, a flag having the first logic is generated, and a part of the included pixels Generating a flag with second logic if is different color fill or no fill; and
In the pixel block having the flag having the first logic, selecting one pixel value from among the pixel values of the included pixels and setting it as the first pixel value;
In the pixel block having a flag having the second logic, all the pixel values of the included pixels are set as second pixel values;
Forming image data of the three-dimensional graphics image based on the first pixel value, the second pixel value, and a flag having the first and second logics. Image data forming method.
In the pixel block having the flag having the first logic, one depth is selected from the depths indicating the depth of the included pixels, the depth value of the selected depth is set as the first depth value, and the other Setting an X / Y increment value from the first depth for each depth value of the pixel;
In the pixel block having a flag having the second logic, the step of setting the depth values of all the included pixels to the second depth value, and
The step of forming the image data of the three-dimensional graphics image is based on the first depth value and the second depth value, in addition to the first pixel value, the second pixel value, and the flag. 2. The image data forming method according to claim 1, wherein the image data forming method is performed.
A method of writing image data including a first pixel value or a first depth value of a first pixel included in a three-dimensional graphics image after rendering processing,
Dividing the first pixels arranged in a matrix included in the three-dimensional graphics image after the drawing processing into first pixel blocks including the first pixels in K rows and L columns;
For each first pixel block, using the coverage indicating the color fill state of the first pixel, if the same color is filled for all the included first pixels, the first flag of the first logic is generated. Generating a first flag of a second logic if some of the included first pixels are filled in different colors or not filled, and
Selecting a first pixel value from among the first pixel values of the first pixels included in the first pixel block having the first flag of the first logic and setting it as a third pixel value;
A step of reading the corresponding second pixel block and second flag included in the three-dimensional graphics image before drawing processing stored in the external memory for the first pixel block having the first flag of the second logic. When,
When a part of the second pixel including the logic of the second flag indicates that a different color is filled or not filled, all the first pixels included in the first pixel block having the first flag of the second logic are included. Setting a first pixel value of one pixel as a third pixel value;
When the logic of the second flag indicates the same color fill, the first pixel value of the first pixel having a coverage indicating the color fill state among the first pixels of the first pixel block, and the color In place of the first pixel value of the first pixel having a coverage indicating the non-filled state of the second pixel value of the second pixel block,
And a step of writing pixel data comprising the third pixel value and the first flag to an external memory.
For the first pixel block having the first flag of the first logic, one first depth value is selected from the first depth values of the first pixels included, and is selected as the third depth value. Setting the increment from the selected first depth value to an X / Y increment value relative to the other first depth values that have not been performed;
A step of reading the corresponding second pixel block and second flag included in the three-dimensional graphics image before drawing processing stored in the external memory for the first pixel block having the first flag of the second logic. When,
When a part of the second pixel including the logic of the second flag indicates that a different color is filled or not filled, all the pixels included in the first pixel block having the first flag of the second logic are included. Setting the first depth value of the first pixel to the third depth value;
When the logic of the second flag indicates the same color fill, the first depth value of the first pixel having the coverage indicating the color fill state among the first pixels of the first pixel block, and the color Instead of the first depth value of the first pixel having the coverage indicating the non-filled state of the second pixel block, the second depth value of the second pixel block is set to the third depth value;
4. The image data according to claim 3, further comprising: writing the third depth value and the X / Y increment value as pixel data in an external memory in addition to the third pixel value and the first flag. Writing method.
The first pixel value or the first pixel value of the first pixel block composed of the first pixels in K rows and L columns formed by dividing the first pixels arranged in a matrix shape included in the three-dimensional graphics image after the rendering process. A pixel data processing circuit for processing pixel data consisting of one depth value,
For each first pixel block, using the coverage indicating the color fill state of the first pixel, if the same color is filled for all the included first pixels, the first flag of the first logic is generated. A flag generation circuit for generating a first flag of a second logic when a part of the included first pixel is filled in different colors or not filled, and
A pixel that reads out the corresponding second pixel block and second flag included in the three-dimensional graphics image before drawing processing stored in the external memory for the first pixel block having the first flag of the second logic. A readout circuit;
For the first pixel block having the first flag of the first logic, one first pixel value is selected from the first pixel values of the first pixels included, and is set as a third pixel value.
When a part of the second pixel including the logic of the second flag indicates that a different color is filled or not filled, all the pixels included in the first pixel block having the first flag of the second logic are included. The first pixel value of the first pixel is the third pixel value,
When the logic of the second flag indicates the same color fill, the first pixel value of the first pixel having a coverage indicating the color fill state among the first pixels of the first pixel block, and the color Instead of the first pixel value of the first pixel having coverage indicating the non-filled state of the second pixel value of the second pixel block, the third pixel value,
An image data processing circuit comprising: a writing circuit that writes pixel data including the third pixel value and the first flags of the first and second logics to an external memory.
For the first pixel block having the first flag of the second logic, the corresponding second pixel block and second X / Y increment value included in the three-dimensional graphics image before drawing processing stored in the external memory And a readout circuit for reading out the second flag;
For the first pixel block having the first flag of the first logic, one first depth value is selected from the first depth values of the first pixels included, and is set as a third depth value. Generating a first X / Y increment value indicative of an increment from the selected first depth value to a first depth value of
When a part of the second pixel including the logic of the second flag indicates that a different color is filled or not filled, all the pixels included in the first pixel block having the first flag of the second logic are included. The first depth value of the first pixel is the third depth value,
If the logic of the second flag indicates that the fill is the same color, generate a second depth value of the second pixel block according to the second X / Y increment value;
Among the first pixels of the first pixel block, a first depth value of a first pixel having a coverage indicating a color fill state and a first depth value of a first pixel having a coverage indicating a non-color fill state. Instead, the second depth value of the second pixel block is a third depth value,
The writing circuit writes the third depth value and the first X / Y increment value to the external memory as pixel data in addition to the third pixel value and the first flag of the first logic and the second logic. The image data processing circuit according to claim 5.