WO2012028077A1

WO2012028077A1 - Ldmos device and method for manufacturing the same

Info

Publication number: WO2012028077A1
Application number: PCT/CN2011/079041
Authority: WO
Inventors: Hsiao-Chia Wu; Tse-Huang Lo; Guipeng Sun
Original assignee: CSMC Technologies Fab1 Co Ltd; CSMC Technologies Fab2 Co Ltd
Current assignee: CSMC Technologies Fab1 Co Ltd; CSMC Technologies Fab2 Co Ltd
Priority date: 2010-08-31
Filing date: 2011-08-29
Publication date: 2012-03-08
Anticipated expiration: 2013-02-28
Also published as: CN102386211A; CN102386211B

Abstract

A lateral double-diffused metal oxide semiconductor (LDMOS) device includes a source region (107), a gate region (113), a drain region (109), a body region (103) and a drift region (115) with doping type opposite to the doping type of the body region (103), wherein the body region (103) is located on a substrate region, the drift region (115) is located between the drain region (109) and the body region (103). The LDMOS device further includes an insulation medium layer (117) located on the drift (115) and under the gate region (113). The breakdown voltage of the device is thus improved while simultaneously reducing the on-resistance and power consumption of the device. Moreover, during the manufacturing of the device, thickness and junction depth adjustments of the insulation medium layer (117) and the drift region (115) respectively have small influence on other devices on the same integrated circuit.

Description

LDMOS DEVICE AND METHOD FOR MANUFACTURING THE SAME

BACKGROUND

Field

The present invention relates generally to a semiconductor device and more particularly to a Lateral Double-diffused Metal Oxide Semiconductor (LDMOS) device and a method for manufacturing the same.

Description of Prior Art

The Lateral double-diffused MOS (LDMOS) transistor is a MOS device having a lightly doped drain. Because the LDMOS typically operates in a linear range and the electrical current thereof keeps constant, the power consumption of the LDMOS mainly depends upon the on-resistance value. In order to increase breakdown voltage (alternatively referred to herein as 'withstand voltage'), a drift region is arranged between an active region and the drain region. The impurity concentration of the drift region is relatively low to keep electric fields low to improve the breakdown voltage. Therefore, when a high voltage is applied to the drain of the LDMOS, the depletion region in the drift region can spread out due to the low impurity concentration therein and thus keep electric fields low to improve the breakdown voltage of the device.

Currently, conventional devices have a structure in which the drift region is made by a relatively deep well to withstand the high voltage applied to the device. Since the well is relatively deep and the doping concentration at the surface relatively high, depletion of the whole drift region is difficult. Accordingly, the doping concentration of the drift region must be reduced to improve the withstand voltage, thus making device on-resistance and power consumption overly high under identical working current. Moreover, the dimensions of such lower-doped drift region devices are relatively large, which results in an increase in chip area, a lower degree of integration, and difficulty meeting the requirements of current circuit designs.

BRIEF SUMMARY

According to one embodiment of the present invention, a LDMOS device includes a source region, a gate region, a drain region, a body region located on a substrate region, and a drift region located between the drain region and the body region . The doping type of the drift region is opposite to the doping type of the body region. The LDMOS device further includes an insulation medium layer located on the drift region and under the gate region.

According to one specific embodiment, the LDMOS device further includes a graded channel doping P-body region located on the body region and under the source region. According to another specific embodiment, the insulation medium layer is a silicon dioxide layer. According to another specific embodiment, the doping concentration of the drift region is between about 10¹⁷ and about 10¹⁸ cm^-3, and the junction depth of the drift region is between about 0.4μm and about 2.0μm. According to another specific embodiment, the doping concentration of the body region is between about 10¹⁷ and about 10¹⁸ cm^-3. According to another specific embodiment, the thickness of the insulation medium layer is not equal to that of a gate oxide layer.

According to one embodiment of the present invention, a method of manufacturing a LDMOS device having a source region, a gate region, a drain region, a body region and a drift region with doping type opposite to the doping type of the body region. The body region is located on a substrate region, the drift region is located between the drain region and the body region. The method includes the step of growing an insulation medium layer on the drift region.

According to one specific embodiment of manufacturing a LDMOS device, the LDMOS device further has a substrate contact region, a gate oxide layer, a gate side wall region located on both sides of the gate region, and a P-body region, the method of manufacturing a LDMOS device further includes the following steps. A substrate is formed by standard well implantation process. An isolation region is formed in the region of the LDMOS except where the channel region, the source region, the drain region, and the drift region may be later formed by layout of the active region by processing with a standard LOCOS or STI isolation process. The drift region is lightly doped and the insulation medium layer is then grown to form the drift region of the LDMOS device. The following steps are sequentially performed; forming the gate oxide layer, depositing and etching a gate material to form the gate region, implanting and annealing the P-body region, lightly doping the lightly doped drain region near the source contact region, forming the gate side wall, and performing implants of the source contact region, the drain contact region and the body contact region. The following steps are sequentially performed; depositing an isolation layer, photo-lithographically etching a contact hole, depositing metal, photo-lithographically etching metal interconnects, depositing a passivation layer, and photo-lithographically etching contact pads.

According to another specific embodiment of manufacturing a LDMOS device, a graded doping is performed for the drift region. According to another specific embodiment of manufacturing a LDMOS device, when the insulation medium layer is formed, the surface region of the device is covered by silicon nitride except for the isolation region and the drift region.

A better understanding of the nature and advantages of the embodiments of the present invention may be gained with reference to the following detailed description and the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a structural view of a LDMOS device, in accordance with a first embodiment of the present invention;

FIG. 2 is a structural view of a LDMOS device, in accordance with a second embodiment of the present invention; and

FIG. 3 is a structural view of a LDMOS device, in accordance with a third embodiment of the present invention.

DETAILED DESCRIPTION

As shown in Fig. 1, according to the embodiments of the present invention, a LDMOS device includes a substrate 101, a body region 103 (P-well), a body contact region 105, a source contact region 107, a drain contact region 109, a gate oxide layer 111, a gate region 113, a drift region 115, an insulation medium layer 117, a gate side wall region 119 located on both sides of the gate region 113, and a P-body region 121.

Insulation medium layer 117 may be located on drift region 115 and under gate region 113. Insulation medium layer 117 may be an electrical insulating material such as silicon dioxide. The thickness of insulation medium layer 117 may be relatively thin so as to improve the device's ability to withstand voltage breakdown. The thickness of insulation medium layer 117 may be determined according to the requirements of the device and may be typically between the thickness of gate oxide layer 111 and the thickness of the field oxide isolation or STI. Thus, the thickness of insulation medium layer 117 may be in the range from tens of nanometers to several thousand angstroms thick. By reducing the thickness of insulation medium layer 117, the influence of gate region 113 with the depletion region in drift region 115 increases and the breakdown voltage in the drift region can be further improved.

The body region 103, p-body region 121, and body contact region 105 may be doped with impurities to form P-type conductivity regions, while source contact region 107, drain contact region 109, and drift region 115 may be doped with impurities to form N-type conductivity regions. Correspondingly, for a P-type device, the conductivity type for each region may be opposite to that for the N-type LDMOS.

Preferably, the concentration in body region 103 may be relatively high and may be between about 10¹⁷ and 10¹⁸ cm^-3 so as to reduce body resistance and to prevent a parasitic bipolar device from conducting. The doping concentration of drift region 115 may be between about 10¹⁷and about 10¹⁸ cm^-3 and the junction depth of drift region 115 may be between about 0.4μm and about 2.0μm deep. In contrast, conventionally, the doping concentration in the drift region may be 7.5 x 10¹⁶ cm^-3, and the junction depth of the drift region may be 2.0μm.

Referring again to the embodiment shown in Figure 1, a graded channel doped region may be formed in P-body region 121 so as to adjust the value of the threshold voltage, reduce substrate resistance, prevent the parasitic bipolar from conducting, increase the concentration in the body region, shorten channel length, reduce on-resistance, and decrease the area of the device. The P-body region 121 is located on the body region and under the source region.

Therefore, the structures described above enhance the depletion of drift region 115 by means of insulation medium layer 117. Moreover, the depth of drift region 115 may be made shallower than the prior art devices while simultaneously the voltage breakdown ability of the device may be improved. The doping concentration of the drift region may be higher, which may be advantageous to the reduction of on-resistance.

Fig. 2 shows a structural view of a LDMOS device, in accordance with a second embodiment of the present invention. In this embodiment, the P-body region 121 previously shown in Fig. 1 may be omitted so that the structure may be more simplified.

Fig. 3 shows a structural view of LDMOS device, in accordance with a third embodiment of the present invention. In this embodiment, the junction depth of body contact doping region 122 may be deeper than source contact region 107 or body contact region 105, which was shown in Figure 1 and Figure 2. The doping concentration of body contact doping region 122 may be high so that the body resistance may be reduced and parasitic bipolar conduction may be prevented.

The manufacturing process for the LDMOS, in accordance with an embodiment of the invention, includes the following steps. A body region is formed in the substrate by standard well implant processing. Next, an isolation region is formed in the region of the LDMOS except where the channel, source, drain, and drift regions may be later formed by layout of the active region and process ed with standard local oxidation of silicon (LOCOS) or shallow trench isolation (STI) process. During the isolation process, in the region that is not isolated by LOCOS or STI, silicon dioxide and silicon nitride are typically used as a mask layer for the silicon surface. The following photo-etching steps are then performed on the silicon nitride to form the drift region with a mask for the drift region 115: (i) applying photoresist, (ii) exposing the photoresist, (iii) developing the photoresist, and (iv) etching the silicon nitride. Next, the lightly doped drift region is implanted and insulation medium layer 117 is grown annealing and driving the implant to form the drift region of the LDMOS device. The doping of the drift region can be formed in a uniform manner, or by a graded doping in which the doping concentration slowly varies from the drain region to body region 103.

The depth of the grown insulation medium layer can be adjusted according to the requirements for the voltage withstand ability of the device. At this time, the surface region of the device is entirely covered by silicon nitride except for the isolation region and the drift region, and the growth of the insulation medium layer has little influence on other types of devices integrated with the LDMOS in an integrated circuit.

Next, the gate, source and drain regions are formed by sequentially: (i) forming the gate oxide layer, (ii) depositing and etching the gate material to form the gate region, (iii) optionally implanting and annealing the P-body region, (iv) performing the lightly doped drain (LDD) doping implant only at the source end of the LDMOS, (v) forming the gate side walls, and (vii) then performing implants of the source contact region, the drain contact region and the body contact region to form the structure shown in Fig. 1. The next steps sequentially, deposit an isolation layer, photo-lithographically etch contact holes, deposit a metal layer, photo-lithographically etch metal interconnects, depositing a passivation layer, and photo-lithographically etching contact pads.

Embodiments of the present invention provide a LDMOS device. It will be apparent to those with skill in the art that modifications to the above methods and apparatuses may occur without deviating from the scope of the present invention. All material types provided herein to describe various dimensions, doping concentrations, and different semiconducting or insulating layers are for illustrative purposes only and not intended to be limiting. For example, the doping polarity of various silicon regions in the embodiments described herein may be reversed to obtain the opposite polarity type device of the particular embodiment. Accordingly, the disclosures and descriptions herein are intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims along with their full scope of equivalents.

Claims

A LDMOS device, comprising:

a source region;

a gate region;

a drain region;

a body region located on a substrate region;

a drift region located between the drain region and the body region wherein the doping type of the drift region is opposite to the doping type of the body region; and

an insulation medium layer located on the drift region and below the gate region .
The LDMOS device according to claim 1, wherein the LDMOS device further comprises a graded channel doping P-body region located on the body region and under the source region.
The LDMOS device according to claim 1, wherein the insulation medium layer is a silicon dioxide layer.
The LDMOS device according to claim 1, wherein the doping concentration of the drift region is between about 10¹⁷ and about 10¹⁸ cm^-3, and the junction depth of the drift region is between about 0.4μm and about 2.0μm.
The LDMOS device according to claim 1, wherein the doping concentration of the body region is between about 10¹⁷ and about 10¹⁸ cm^-3.
The LDMOS device according to claim 1, wherein the thickness of the insulation medium layer is not equal to that of a gate oxide layer.
A method of manufacturing a LDMOS device having a source region, a gate region, a drain region, a body region and a drift region with doping type opposite to the doping type of the body region, wherein the body region is located on a substrate region, the drift region is located between the drain region and the body region, wherein the method comprises the step of growing an insulation medium layer on the drift region.
The method of manufacturing a LDMOS device according to claim 7, wherein the LDMOS device further having a substrate contact region, a gate oxide layer, a gate side wall region located on both sides of the gate region, and a P-body region, the method further comprising the following steps:

forming a substrate by standard well implantation process;

forming an isolation region in the region of the LDMOS except where the channel region, the source region, the drain region, and the drift region may be later formed by layout of the active region, and by processing with a standard LOCOS or STI isolation process;

lightly doping the drift region and then growing said insulation medium layer to form the drift region of the LDMOS device;

sequentially forming the gate oxide layer, depositing and etching a gate material to form the gate region, implanting and annealing the P-body region, lightly doping the lightly doped drain region near the source contact region, forming the gate side wall, and performing implants of the source contact region, the drain contact region and the body contact region; and

sequentially depositing an isolation layer, photo-lithographically etching a contact hole, depositing metal, photo-lithographically etching metal interconnects, depositing a passivation layer, and photo-lithographically etching contact pads.
The method of manufacturing a LDMOS device according to claim 7, wherein a graded doping is performed for the drift region.
The method of manufacturing a LDMOS device according to claim 7, wherein when the insulation medium layer is formed, the surface region of the device is covered by silicon nitride except for the isolation region and the drift region.