WO2012021332A3 - Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations - Google Patents

Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations Download PDF

Info

Publication number
WO2012021332A3
WO2012021332A3 PCT/US2011/046239 US2011046239W WO2012021332A3 WO 2012021332 A3 WO2012021332 A3 WO 2012021332A3 US 2011046239 W US2011046239 W US 2011046239W WO 2012021332 A3 WO2012021332 A3 WO 2012021332A3
Authority
WO
WIPO (PCT)
Prior art keywords
jitter
circuitry
oscilloscope
integrated circuit
bit
Prior art date
Application number
PCT/US2011/046239
Other languages
French (fr)
Other versions
WO2012021332A2 (en
Inventor
Peng Li
Masashi Shimanouchi
Sergey Shumarayev
Weiqi Ding
Sriram Narayan
Daniel Tun Lai Chow
Mingde Pan
Original Assignee
Altera Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/884,305 external-priority patent/US8504882B2/en
Application filed by Altera Corporation filed Critical Altera Corporation
Priority to CN201180046719.3A priority Critical patent/CN103140768B/en
Priority to EP11816812.9A priority patent/EP2603805A4/en
Publication of WO2012021332A2 publication Critical patent/WO2012021332A2/en
Publication of WO2012021332A3 publication Critical patent/WO2012021332A3/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31708—Analysis of signal quality
    • G01R31/31709—Jitter measurements; Jitter generators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31708—Analysis of signal quality
    • G01R31/3171—BER [Bit Error Rate] test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31716—Testing of input or output with loop-back
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

An integrated circuit ("IC") may include circuitry for use in testing a serial data signal. The IC may include circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. The IC may also include circuitry for receiving the serial data signal and performing a bit error rate ("BER") analysis in such a signal. The IC may provide output signals indicative of results of its operations. The IC can operate in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.
PCT/US2011/046239 2010-08-13 2011-08-02 Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations WO2012021332A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201180046719.3A CN103140768B (en) 2010-08-13 2011-08-02 For perform or contribute to oscillograph, shake and/or bit error rate tester operation integrated circuit on Circuits System
EP11816812.9A EP2603805A4 (en) 2010-08-13 2011-08-02 Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US85622610A 2010-08-13 2010-08-13
US12/856,226 2010-08-13
US12/884,305 US8504882B2 (en) 2010-09-17 2010-09-17 Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations
US12/884,305 2010-09-17

Publications (2)

Publication Number Publication Date
WO2012021332A2 WO2012021332A2 (en) 2012-02-16
WO2012021332A3 true WO2012021332A3 (en) 2012-04-12

Family

ID=45568125

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2011/046239 WO2012021332A2 (en) 2010-08-13 2011-08-02 Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations

Country Status (3)

Country Link
EP (1) EP2603805A4 (en)
CN (1) CN103140768B (en)
WO (1) WO2012021332A2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8837571B1 (en) * 2013-08-02 2014-09-16 Altera Corporation Apparatus and methods for on-die instrumentation
CN105162543B (en) * 2015-08-17 2017-12-08 华北水利水电大学 A kind of device and method for the test of SDH clock jitters
CN106656229B (en) * 2016-11-25 2019-02-26 硅谷数模半导体（北京）有限公司 The method for implanting and circuit and eye figure monitor of shake data
US10641823B2 (en) * 2017-03-17 2020-05-05 Photonic Technologies (Shanghai) Co., Ltd. Method and apparatus for built-in self-test of CDR and non-CDR components with an on substrate test signal generator
KR102264159B1 (en) * 2017-06-08 2021-06-11 삼성전자주식회사 Serial communication interface circuit performing external loopback test and electrical device including the same
CN109217979B (en) 2017-06-30 2021-06-15 华为技术有限公司 Communication method, device and storage medium
TWI806539B (en) * 2022-04-08 2023-06-21 瑞昱半導體股份有限公司 Testing system and testing method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030023912A1 (en) * 2001-07-24 2003-01-30 Xilinx, Inc. Integrated testing of serializer/deserializer in FPGA
JP2005509890A (en) * 2001-08-22 2005-04-14 ウェイブクレスト・コーポレイション Method and apparatus for measuring waveforms
US20070277069A1 (en) * 2003-05-27 2007-11-29 Bonneau Dominique P Serializer/deserializer circuit for jitter sensitivity characterization
US20100097087A1 (en) * 2008-10-20 2010-04-22 Stmicroelectronics, Inc. Eye mapping built-in self test (bist) method and apparatus

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7743288B1 (en) * 2005-06-01 2010-06-22 Altera Corporation Built-in at-speed bit error ratio tester
US7869544B2 (en) * 2008-01-03 2011-01-11 International Business Machines Corporation System for measuring an eyewidth of a data signal in an asynchronous system
US8228972B2 (en) * 2008-06-04 2012-07-24 Stmicroelectronics, Inc. SERDES with jitter-based built-in self test (BIST) for adapting FIR filter coefficients

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030023912A1 (en) * 2001-07-24 2003-01-30 Xilinx, Inc. Integrated testing of serializer/deserializer in FPGA
JP2005509890A (en) * 2001-08-22 2005-04-14 ウェイブクレスト・コーポレイション Method and apparatus for measuring waveforms
US20070277069A1 (en) * 2003-05-27 2007-11-29 Bonneau Dominique P Serializer/deserializer circuit for jitter sensitivity characterization
US20100097087A1 (en) * 2008-10-20 2010-04-22 Stmicroelectronics, Inc. Eye mapping built-in self test (bist) method and apparatus

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2603805A4 *

Also Published As

Publication number Publication date
WO2012021332A2 (en) 2012-02-16
EP2603805A4 (en) 2016-10-19
CN103140768A (en) 2013-06-05
EP2603805A2 (en) 2013-06-19
CN103140768B (en) 2016-01-27

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