WO2012019563A1

WO2012019563A1 - Power management integrated circuit and control method thereof

Info

Publication number: WO2012019563A1
Application number: PCT/CN2011/078375
Authority: WO
Inventors: 肖丽荣
Original assignee: 上海炬力集成电路设计有限公司
Priority date: 2010-08-12
Filing date: 2011-08-12
Publication date: 2012-02-16
Also published as: CN102375464A; CN102375464B

Abstract

A power management integrated circuit and a control method thereof. A circuit having a structure identical to the structure of a step-down DC-DC circuit and constituted by a power transistor 1 (Q1), a power transistor 2 (Q2), a power transistor 3 (Q3), a controller (C1), and an inductor (L1). The controller (C1) is also used in the reception of an enable signal 1 and an enable signal 2. Within any given period of time, only one is effective between the enable signal 1 and the enable signal 2. When the enable signal 1 is in effect, by controlling the power transistors, the step-down DC-DC circuit is enabled; when the enable signal 2 is in effect, by controlling the power transistors, a LDO circuit is enabled. A selection according to need is enabled between the step-down DC-DC circuit having a relatively low power consumption and the LDO circuit having a relatively high performance, thereby enabling not only a retrenchment in the area of a SOC, but also a relatively low power consumption and a relatively high performance, while the reliability and the stability of the application are reassured.

Description

Power management integrated circuit control method and power management integrated circuit

Technical field

The present invention relates to the field of electrical engineering, and more particularly to power management techniques in the field of electrical engineering.

Background technique

Many lithium-battery-powered portable devices integrate a step-down DC-DC converter into a System-On-Chip ("SOC") and use a step-down DC-DC circuit to extend the battery. Life time. The step-down DC-DC circuit is characterized by high conversion efficiency and large switching noise. The switching frequency is in the range of several hundred KHz to several MHz. The circuit is shown in Figure 1: Q1, Q2, and Q3 are the step-down DC-DC circuits. Power supply tube. The working principle can be simply divided into three stages: the first stage controller C1 controls Q1 to turn on, Q2 to turn off, and Q3 to turn off. At this time, VIN (input voltage) charges inductor L1 and also supplies power to VOUT. The second stage controller C1 controls Q1 to turn off, Q2 to turn on, and Q3 to turn off. At this time, the inductor L1 is discharged to VOUT (output voltage) and the load on VOUT. The third stage controller C1 controls Q1 and Q2 to turn off and Q3 to turn on. The condition that occurs at this stage is that when the inductor current is 0, electromagnetic interference is generated to prevent the inductor current from oscillating. (Electromagnetic Interference (referred to as "EMI"), so turn Q1 and Q2 off, and turn Q3 on, that is, the excess energy in inductor L1 is consumed by Q3.

The portable device with the SOC integrated with the step-down DC-DC circuit supports both audio and video playback, as well as radio or radio (Radio) Frequency, referred to as "RF" and other functions. Circuits that implement functions such as audio or video are less sensitive to high-frequency noise (such as MHz level or higher), but circuits such as those that implement radio functions are very sensitive to high-frequency noise, even due to high-frequency noise. Interference can cause stations in certain frequency bands to be unreceived. One of the main sources of interference from these high frequency noise is the power-managed step-down DC-DC circuit in portable devices.

At present, in order to solve the problem that the circuit that realizes the radio and other functions is not interfered with by the step-down DC-DC high-frequency noise, the step-down DC-DC circuit is not used in the entire portable device, and the low-dropout linear regulator is used (Low). Dropout Regulator, referred to as "LDO" circuit, LDO circuit is characterized by low conversion efficiency and no switching noise. Its circuit is shown in Figure 2: Q4 is the power supply tube of the LDO. The working principle is that the controller C2 controls the PMOS transistor Q4 to be in the variable resistance region. When the VOUT voltage is slightly lower than the fixed value, the controller C2 reduces the on-resistance of Q4 through the output signal CQ4; when the VOUT voltage is slightly higher than the fixed value At the time of the value, the controller C2 increases the on-resistance of Q4 by the output signal CQ4, and finally stabilizes the output VOUT at a fixed voltage value. Therefore, a portable device using an LDO circuit does not generate high-frequency noise, but has disadvantages in that the battery is inefficient in use and has poor endurance.

Although, in order to balance power consumption and performance, another solution is proposed: design a set of step-down DC-DC circuits and a set of LDO circuits in the SOC, as shown in Figure 3, playing audio and video to the high frequency. In the case of noise insensitive applications, the buck DC-DC circuit is enabled by the enable signal 1 and the LDO circuit is stopped by the enable signal 2 to reduce the power consumption of the battery end to improve the battery utilization efficiency, playing the radio or using the RF function. In high frequency noise sensitive applications, the LDO circuit is enabled by enable signal 2 and the step down DC-DC circuit is stopped by enable signal 1 to improve circuit performance.

However, the inventors of the present invention have found that in this solution, the step-down DC-DC circuit and the LDO circuit are separate, and the entire circuit requires the use of multiple power transistors, namely Q1/Q2/Q3/Q4, and 2 With the control circuits A1/C1 and A2/C2, the area occupied by the SOC will be large.

technical problem

It is an object of the present invention to provide a power management integrated circuit control method and a power management integrated circuit that are implemented in an SOC The multiplexing of the step-down DC-DC circuit and the LDO circuit saves SOC area while balancing low power consumption and excellent performance.

Technical solution

In order to solve the above technical problem, an embodiment of the present invention further provides a method for controlling a power management integrated circuit in which one end of a power supply power tube 1 is connected to an input voltage, and the other end is connected to an inductor and a power supply. The tube 2 is connected, the other end of the power supply tube 2 is connected to a relatively zero potential, and a controller outputs a control signal to the power supply tube 1 and the gate of the power supply tube 2 to control the power supply tube 1 And turning on and off the power supply tube 2;

The method comprises the steps of:

The controller receives the enable signal 1 and the enable signal 2, and the enable signal 1 and the enable signal 2 are valid at the same time period;

If the enable signal 1 is valid, the power supply power tube 1 and the power supply power tube 2 are controlled according to the working principle of the step-down DC-DC circuit to implement a step-down DC-DC circuit; if the enable signal 2 If it is effective, the power supply power tube 1 and the power supply power tube 2 are controlled according to the working principle of the LDO circuit to implement the LDO circuit.

The embodiment of the present invention further provides a power management integrated circuit, including: a power supply power tube 1, a power supply power tube 2, a controller, an inductor, an enable signal 1 and an enable signal 2, and at the same time period, the The energy signal 1 and the enable signal 2 are selected to be valid;

One end of the power supply power tube 1 is connected to the input voltage, the other end is connected to the inductor and the power supply power tube 2, the other end of the power supply power tube 2 is connected with a relatively zero potential, and the controller outputs a control signal. Giving the power supply tube 1 and the gate of the power supply power tube 2 to control the conduction and the closing of the power supply power tube 1 and the power supply power tube 2;

The controller is configured to receive the enable signal 1 and the enable signal 2;

When the enable signal 1 is valid, the connection relationship between the controller and the power supply power tube 1, the power supply tube 2, and the connection between the controller and the two power supply tubes in the step-down DC-DC circuit are completely the same;

When the enable signal 2 is valid, the controller controls the connection between the controller and the power supply tube 1 by the control of the power supply power tube 1 and the power supply tube 2, which is equivalent to the LDO circuit. The connection relationship between the controller and the power supply tube.

Embodiments of the present invention also provide a method for controlling a power management integrated circuit, including the following steps:

One end of the power supply tube 1 is connected to the input voltage, the other end is connected to the inductor and the power supply tube 2, and the other end of the power supply tube 2 is connected with a relatively zero potential, and the power supply tube 3 is connected in parallel across the inductor, by the controller Outputting control signals to the power supply power tube 1, the power supply power tube 2, and the power supply power tube 3, controlling the power supply power tube 1, the power supply power tube 2, and the power supply power tube 3 to be turned on and off;

The controller receives the enable signal 1 and the enable signal 2, and the enable signal 1 and the enable signal 2 are selectively valid during the same period of time;

If the enable signal 1 is valid, the power supply power tube 1, the power supply tube 2, and the power supply tube 3 are controlled according to the working principle of the step-down DC-DC circuit to implement a step-down DC-DC circuit; if the enable signal 2 is valid According to the working principle of the low-dropout linear regulator LDO circuit, the power supply tube 1, the power supply tube 2, and the power supply tube 3 are controlled to realize the LDO circuit.

The embodiment of the present invention further provides a power management integrated circuit, including: a power supply power tube 1, a power supply power tube 2, a power supply power tube 3, a controller, an inductor, an enable signal 1 and an enable signal 2, at the same time. Segment, enable signal 1 and enable signal 2 are valid;

One end of the power supply tube 1 is connected to the input voltage, the other end is connected to the inductor and the power supply tube 2, the other end of the power supply tube 2 is connected with a relatively zero potential, the power supply power tube 3 is connected in parallel with the two ends of the inductor, and the controller outputs a control signal. The power supply power tube 1, the power supply power tube 2 and the power supply power tube 3 are gated, and the power supply power tube 1, the power supply power tube 2 and the power supply power tube 3 are controlled to be turned on and off;

The controller is configured to receive an enable signal 1 and an enable signal 2;

When the enable signal 1 is valid, the controller is connected to the power source power tube 1, the power source tube 2, the power source tube 3, and the controller and the three power sources in the step-down DC-DC circuit. The connection relationship of the tubes is exactly the same;

When the enable signal 2 is valid, the controller controls the connection between the controller and the power supply power tube 1 by controlling the power supply power tube 1, the power supply power tube 2, and the power supply power tube 3. It is equivalent to the connection relationship between the controller and the power supply tube in the LDO circuit.

Beneficial effect

Compared with the prior art, the main differences and effects of the embodiments of the present invention are as follows:

The power supply power tube 1, the power supply power tube 2, the power supply power tube 3, the controller and the inductor form the same circuit as the step-down DC-DC circuit, wherein the controller is further configured to receive the enable signal 1 and the enable signal 2, At the same time period, the enable signal 1 and the enable signal 2 are selected to be valid. When the enable signal 1 is valid, the step-down DC-DC circuit is realized by controlling the power supply power tube 1, the power supply power tube 2, and the power supply power tube 3. When the enable signal 2 is valid, the power supply power tube 1 is passed. The power supply tube 2 and the power supply tube 3 are controlled to implement an LDO circuit. Since the components of the circuit device are equivalent to the components of the step-down DC-DC circuit, the device for implementing the LDO circuit is not additionally added, and the power supply tubes are controlled correspondingly according to different enable signals, thereby achieving different The circuit corresponding to the signal. Therefore, the multiplexing of the step-down DC-DC circuit and the LDO circuit can be realized in the SOC without adding an additional device, which not only saves the SOC area, but also can decide to adopt a lower-voltage step-down DC-DC according to the need. The circuit is still using a better performance LDO circuit, taking into account low power consumption and excellent performance, ensuring the reliability and stability of the application solution.

Further, the power supply power tube 2 can be in a fully-on state, the power supply power tube 3 is in a fully-on state, and the power supply power tube 1 is operated in a variable resistance region to implement an LDO circuit. Through the ingenious control of the power supply tube, the power supply tube 1 is equivalent to the power supply tube Q4 in the LDO circuit, and the circuit structure of the step-down DC-DC is used to realize the multiplexing of the LDO circuit, thereby ensuring the step-down DC-DC circuit and the LDO. The feasibility of multiplexing the circuit.

Further, the power supply power tube 2 and the power supply power tube 3 can be in a completely off state, and the power supply power tube 1 can be operated in the variable resistance region to implement the LDO circuit. At this time, the combination of the inductance and the output capacitance achieves LC filtering. Thus, the present invention provides a flexible and versatile implementation.

Further, the power supply power tube 1 and the power supply power tube 3 use a PMOS tube, and the power supply power tube 2 uses an NMOS tube. Whether the step-down DC-DC circuit or the LDO circuit is implemented, the same material can be used as the power supply tube in the existing step-down DC-DC circuit or the LDO circuit, so that the present invention can be more advanced than the prior art. Good compatibility.

DRAWINGS

1 is a schematic structural diagram of a step-down DC-DC circuit commonly used in the prior art;

2 is a schematic structural diagram of an LDO circuit commonly used in the prior art;

3 is a schematic structural diagram of integrating a step-down DC-DC circuit and an LDO circuit in an SOC according to the prior art;

4 is a flow chart of a control method of a power management integrated circuit according to a first embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a circuit according to a first embodiment of the present invention; FIG.

6 is a schematic diagram showing the operation waveforms of connection points of respective circuits in a step-down DC-DC circuit commonly used in the prior art;

7 is a schematic diagram showing the operation waveforms of connection points of respective circuits in an LDO circuit commonly used in the prior art;

8 is a schematic diagram showing the operation waveforms of respective circuit connection points in the third embodiment of the present invention;

9 is a schematic diagram showing the operation waveforms of connection points of respective circuits in the fourth embodiment of the present invention;

Figure 10 is a schematic view showing the structure of a circuit in the fifth and sixth embodiments of the present invention;

FIG. 11 is a schematic diagram showing the circuit structure of the step-down DC-DC circuit of FIG.

BEST MODE FOR CARRYING OUT THE INVENTION

In the following description, numerous technical details are set forth in order to provide the reader with a better understanding of the present application. However, those skilled in the art can understand that the technical solutions claimed in the claims of the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.

The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

The first embodiment of the present invention relates to a method for controlling a power management integrated circuit. In this embodiment, the basic components of the circuit are Q1 (ie, power supply power tube 1), Q2 (ie, power supply power tube 2), and Q3 (ie, power supply power tube). 3), L1 (ie, inductance), the basic control unit is C1 (ie controller).

The specific process of this embodiment is shown in FIG. 4. In step 410, the power supply power tube 1, the power supply power tube 2, the power supply power tube 3, the controller, and the inductor are used to form the same circuit as the step-down DC-DC circuit. The Q1 end is connected to the input voltage, the other end is connected to L1 and Q2, the other end of Q2 is connected to the relative zero potential, Q3 is connected in parallel to L1, and the controller C1 outputs control signals to the gates of Q1, Q2 and Q3. Pole, control the conduction and closing of Q1, Q2 and Q3, as shown in Figure 5. Since the basic device of the step-down DC-DC circuit is also three power supply tubes, controllers, and inductors in the prior art, there is no technical difficulty in this step, and details are not described herein again.

Next, in step 420, the enable signal 1 and the enable signal 2 are received by the controller, and the enable signal 1 and the enable signal 2 are selectively asserted during the same period of time. That is to say, when the enable signal 1 is active high, the enable signal 2 can only be set to low invalid; when the enable signal 2 is active high, the enable signal 1 can only be set to low invalid.

Next, in step 430, it is determined whether the enable signal 1 is active high. If it is determined that the enable signal 1 is active high, then step 440 is entered.

In step 440, the power supply power tube 1, the power supply power tube 2, and the power supply power tube 3 are controlled according to the working principle of the step-down DC-DC circuit to implement a step-down DC-DC circuit. Specifically, when the enable signal 1 is active high (the enable signal 2 can only be set to low inactive), the specific working process can be easily divided into three stages as the existing step-down DC-DC circuit:

The first stage controller C1 controls Q1 on, Q2 off, and Q3 off by control signals CQ1, CQ2, and CQ3. At this time, VIN charges inductor L1 and also supplies power to VOUT.

The second stage controller C1 controls Q1 off, Q2 on, and Q3 off through control signals CQ1, CQ2, and CQ3, respectively, when inductor L1 is discharged to the loads on VOUT and VOUT.

The third stage controller C1 controls Q1 and Q2 to be turned off and Q3 to be turned on respectively through control signals CQ1, CQ2, and CQ3. The condition occurs at this stage when the current of the inductor L1 is 0. In order to prevent EMI from being generated by the inductor current oscillation, Q1 is used. And Q2 is turned off, and Q3 is turned on, that is, the excess energy in the inductor L1 is consumed by Q3.

It is not difficult to find that in the embodiment, the controller C1 realizes the step-down DC-DC circuit by controlling Q1, Q2, and Q3, and controls the Q1, Q2, and Q3 through the controller C1 in the prior art. The way to implement a step-down DC-DC circuit is exactly the same. In the prior art, Q1 and Q3 generally use a PMOS transistor (P-channel metal oxide semiconductor field effect transistor), and the PMOS transistor is in a fully conducting state when the control terminal is low (ie, in a constant current region, conducting The resistance is small and constant), in the fully off state when the control terminal is high (ie, in the pinch-off region, the resistance is infinite). Q2 uses an NMOS transistor (N-channel metal oxide semiconductor field effect transistor). The NMOS is fully turned on when the control terminal is high, and is completely turned off when it is low, that is, the existing step-down DC-DC circuit. The working timing of each control signal and the voltage waveform of the critical connection point circuit SW during operation are as shown in FIG. 6.

Therefore, in order to make the present embodiment more compatible with the prior art, in the present embodiment, the power supply power tube 1 (ie, Q1) and the power supply power tube 3 (ie, Q3) use a PMOS tube, and the power supply tube 2 (ie, Q2) Use an NMOS transistor. That is to say, when the enable signal 1 is active high, the operation timing of each control signal and the voltage waveform of the key connection point circuit SW during the operation of the power supply integrated circuit are the same as those of FIG. 6, and the control signals CQ1, CQ2, CQ3 and the middle The voltage waveform of the point SW is a fast flipping signal, and the frequency is generally in the range of several hundred KHz to several MHz, which will cause electromagnetic compatibility problems. However, according to the working principle of the step-down DC-DC circuit, the energy transmission efficiency can be as high as 90% or more. Therefore, when the performance requirement is not high, such as when playing audio or video, the enable signal 1 is enabled to be active, and the enable signal 2 is low, to improve conversion efficiency and reduce power consumption.

If, in step 430, it is determined that the enable signal 1 is not active high, even if the enable signal 1 is low, that is, the enable signal 2 is active high, then step 450 is entered.

In step 450, the power supply power tube 1, the power supply power tube 2, and the power supply power tube 3 are controlled according to the working principle of the LDO circuit to implement the LDO circuit.

Specifically, the power supply tube 2 is controlled to be in a completely off state by the controller, and the power supply tube 3 is controlled to be in a fully-on state by the controller, and the power supply tube 1 is controlled by the controller to operate in the variable resistance region, by reducing Or increase the on-resistance of the power supply tube 1 to ensure that the output voltage VOUT is stabilized at a fixed voltage value (ie, the power supply tube 1 is equivalent to the power supply tube Q4 in FIG. 2 or FIG. 3).

That is to say, the controller C1 controls the NMOS transistor Q2 to be in a completely off state, its resistance is approximately infinite, and controls the PMOS transistor Q3 to be in a fully conducting state, and the on-resistance is zero ohms, generally designed to be within 0.2 to 5 ohms. At the same time, the PMOS transistor Q1 is controlled to operate in the variable resistance region, which is equivalent to the power transistor Q4 in FIG. 2 or FIG. The resistance of Q1 is determined by the output voltage VOUT, and the resistance range may vary from a few Ω to several hundred kΩ. When the VOUT voltage is slightly lower than the fixed value, the controller C1 reduces the on-resistance of Q1 by the output signal CQ1; when the VOUT voltage is slightly higher than the fixed value, the controller C1 increases the conduction of Q1 by outputting the signal CQ1. The resistor eventually stabilizes the output VOUT at a fixed voltage value.

In theory, the smaller the resistance of Q3, the better, but the smaller the resistance, the larger the area of the corresponding integrated circuit, and the cost of the wafer is correspondingly increased. The Q3 value is also large, the area of the corresponding integrated circuit will be small, and the cost of the used wafer is also small. Considering the area cost and performance, the value is preferably 0.2 to 5 ohms. The circuit can work even when it is greater than 5 ohms, but the performance will be worse.

Since Q4 is a PMOS transistor in the existing LDO circuit, the waveform of the output signal CQ4 for controlling the on-resistance of the Q4 is a slowly varying waveform, and there is no fixed frequency, as shown in FIG. In the present embodiment, Q1 equivalent to Q4 is also a PMOS transistor. Therefore, when the enable signal 2 is active high, the waveform of CQ1 is also a slowly changing waveform, and there is no fixed frequency.

It can be seen that the control method of the power management integrated circuit of the embodiment can also implement the LDO circuit, and has the advantages of the LDO circuit: the power supply noise is small, and the stability is good. Therefore, when the performance requirements are high, such as the implementation of the radio function and the RF function, the enable signal 2 can be made active, and the enable signal 1 is low and effective to improve performance.

After step 440 or step 450, returning to step 420, continue to receive the enable signal 1 and the enable signal 2.

In this embodiment, the components of the circuit are equivalent to the components of the step-down DC-DC circuit, and the device for implementing the LDO circuit is not additionally added. According to different enable signals, the power transistors of the power supply are correspondingly Control, realize the circuit corresponding to different enable signals. Therefore, the multiplexing of the step-down DC-DC circuit and the LDO circuit can be realized in the SOC without adding an additional device, which not only saves the SOC area, but also can decide to adopt a lower-voltage step-down DC-DC according to the need. The circuit, or a better performance LDO circuit, takes into account power consumption and performance, ensuring the reliability and stability of the application.

A second embodiment of the present invention relates to a method of controlling a power management integrated circuit. The second embodiment is basically the same as the first embodiment, and the difference mainly lies in:

In the first embodiment, by placing the power supply power tube 2 in a completely off state, the power supply power tube 3 is in a fully-on state, and the power supply power tube 1 is operated in the variable resistance region, by reducing or increasing the power supply. The on-resistance of the tube 1 ensures that the output voltage VOUT is stabilized at a fixed voltage value to realize the LDO circuit.

However, in the second embodiment, by controlling the power supply power tube 2 and the power supply power tube 3 to be in a completely off state by the controller, the control power supply power tube 1 operates in the variable resistance region, by reducing or increasing the power supply power tube 1 The on-resistance ensures that the output voltage VOUT is stabilized at a fixed voltage value (ie, the power supply tube 1 is equivalent to the power supply tube Q4 in FIG. 2 or FIG. 3) to implement the LDO circuit. At this time, the combination of the inductance and the output capacitance achieves LC filtering. That is to say, when the enable signal 2 is active high (the enable signal 1 can only be set to low inactive), C1 controls Q1, Q2, and Q3 to make Q1 equal to the power supply tube in the LDO circuit. Q4, the multiplexing of the LDO circuit is realized by the circuit structure of the step-down DC-DC.

Since the power supply power tube 3 can be in a fully-on state or the power-off power tube 3 is in a fully-on state or a completely-off state, the power supply power tube 1 can be operated in a variable resistance region to implement an LDO circuit. It can be seen that the embodiments of the present invention can be flexibly implemented.

The method embodiments of the present invention can all be implemented in software, hardware, firmware, and the like. Regardless of whether the invention is implemented in software, hardware, or firmware, the instruction code can be stored in any type of computer-accessible memory (eg, permanent or modifiable, volatile or non-volatile, solid state Or non-solid, fixed or replaceable media, etc.). Also, the memory can be, for example, a programmable array logic (Programmable) Array Logic ("PAL" for short), Random Access Memory ("RAM") Programmable Read Only Memory ("PROM"), read-only memory (Read-Only) Memory, referred to as "ROM"), electrically erasable programmable read-only memory (Electrically Erasable Programmable) ROM, referred to as "EEPROM"), magnetic disk, optical disk, Digital Versatile Disc ("DVD") and so on.

A third embodiment of the present invention relates to a power management integrated circuit, the basic components of which are Q1 (ie, power supply tube 1), Q2 (ie, power supply tube 2), Q3 (ie, power supply tube 3), and L1 (ie, Inductor), the basic control unit is C1 (ie, controller), and the power management integrated circuit of the embodiment further includes two enable signals. Enable signal 1 and enable signal 2, enable signal 1 and enable signal 2 are valid at the same time. That is to say, when the enable signal 1 is active high, the enable signal 2 can only be set to low invalid; when the enable signal 2 is active high, the enable signal 1 can only be set to low invalid.

The circuit structure composed of the power supply tube 1, the power supply tube 2, the power supply tube 3, the controller and the inductor is the same as the conventional step-down DC-DC circuit, that is, the end of the power supply tube 1 is connected to the input voltage, and the other end is connected with The inductor is connected to the power supply tube 2, and the other end of the power supply tube 2 is connected to a relatively zero potential, and the power supply tube 3 is connected in parallel to the two ends of the inductor, and the controller outputs a control signal to the power supply tube 1 and the power supply tube 2 And the gate of the power supply tube 3 controls the conduction and shutdown of the power supply power tube 1, the power supply power tube 2, and the power supply power tube 3.

The controller is further configured to receive the enable signal 1 and the enable signal 2, and when the enable signal 1 is valid, the controller controls the power supply power tube 1, the power power tube 2, and the power power tube 3, and the controller The connection relationship between the power supply power tube 1, the power supply power tube 2, and the power supply power tube 3 is exactly the same as the connection relationship between the controller and the three power supply power tubes in the step-down DC-DC circuit; when the enable signal 2 is valid, the control is performed. By controlling the power supply power tube 1, the power supply tube 2, and the power supply tube 3, the connection relationship between the controller and the power supply tube 1 is equivalent to the connection relationship between the controller and the power supply tube in the LDO circuit, thereby According to the working principle of the LDO circuit, the power supply tube 1, the power supply tube 2, and the power supply tube 3 are controlled to realize the LDO circuit.

Specifically, when the enable signal 1 is active high (the enable signal 2 can only be set to low inactive), the controller controls the power supply power tube 1, the power supply power tube 2, and the power supply power tube 3, The existing step-down DC-DC circuit can be easily divided into three stages:

In the prior art, Q1 and Q3 generally use a PMOS tube, and Q2 uses an NMOS tube. Therefore, in order to make the present embodiment more compatible with the prior art, in the present embodiment, the power supply power tube 1 (ie, Q1) The same applies to the power supply tube 3 (ie, Q3), and the power supply tube 2 (ie, Q2) also uses the NMOS tube.

When the enable signal 2 is active high (the enable signal 1 can only be set to low inactive), C1 controls Q1, Q2, and Q3 to make Q1 equal to the power supply tube Q4 in the LDO circuit. The circuit structure of the DC-DC implements multiplexing of the LDO circuit. The specific work process is shown in Figure 8:

When the enable signal 1 changes from high active to low active, and the enable signal 2 changes from low inactive to active high, the controller C1 controls the NMOS transistor Q2 to be in a completely off state, its resistance is approximately infinite, and the control PMOS transistor Q3 is in The fully-on state, the on-resistance is zero ohms, generally designed to be within 0.2~5 ohms, and the PMOS transistor Q1 is controlled to operate in the variable resistance region, which is equivalent to the power transistor Q4 in FIG. 2 or FIG. The resistance of Q3 is determined by the output voltage VOUT, and the resistance range may vary from a few Ω to several hundred kΩ. When the VOUT voltage is slightly lower than the fixed value, the controller C1 reduces the on-resistance of Q1 by the output signal CQ1; when the VOUT voltage is slightly higher than the fixed value, the controller C1 increases the conduction of Q1 by outputting the signal CQ1. The resistor eventually stabilizes the output VOUT at a fixed voltage value.

Since Q4 is a PMOS transistor in the existing LDO circuit, the waveform of the output signal CQ4 for controlling the Q4 on-resistance is a slowly varying waveform, and there is no fixed frequency. In the present embodiment, Q1 equivalent to Q4 is also a PMOS transistor. Therefore, when the enable signal 2 is active high, the waveform of CQ1 is also a slowly changing waveform, and there is no fixed frequency. The waveform is basically the same as the output voltage waveform VOUT (as shown in Figure 9).

It can be seen that the power management integrated circuit of the embodiment can also implement the LDO circuit, and has the advantages of the LDO circuit: the power supply noise is small, and the stability is good. Therefore, when the performance requirements are high, such as the implementation of the radio function and the RF function, the enable signal 2 can be made active, and the enable signal 1 is low and effective to improve performance.

It is not difficult to find that the present embodiment is an apparatus embodiment corresponding to the first embodiment, and the present embodiment can be implemented in cooperation with the first embodiment. The related technical details mentioned in the first embodiment are still effective in the present embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related art details mentioned in the present embodiment can also be applied to the first embodiment.

A fourth embodiment of the present invention relates to a power management integrated circuit. The fourth embodiment is basically the same as the third embodiment, and the difference mainly lies in:

In the third embodiment, the controller places the power supply power tube 3 in a fully-on state by placing the power supply power tube 2 in a fully-off state, and operates the power supply power tube 1 in the variable resistance region, by reducing or increasing. The on-resistance of the power supply tube 1 ensures that the output voltage VOUT is stabilized at a fixed voltage value, so that the connection relationship between the controller and the power supply tube 1 is equivalent to the connection relationship between the controller and the power supply tube in the LDO circuit, thereby Implement the LDO circuit.

However, in the fourth embodiment, the controller controls the power supply power tube 1, the power supply power tube 2, and the power supply power tube 3 in the following manner, and the connection relationship between the controller and the power supply power tube 1 is equivalent to the control in the LDO circuit. Connection between the device and the power supply tube:

The controller controls the power supply tube 2 to be in a fully off state.

The controller controls the power supply tube 3 to be in a fully off state.

The controller controls the power supply tube 1 to operate in the variable resistance region, and by reducing or increasing the on-resistance of the power supply tube 1, the output voltage VOUT is stabilized at a fixed voltage value. At this time, the combination of the inductance and the output capacitance achieves LC filtering.

That is to say, when the enable signal 2 is active high (the enable signal 1 can only be set to low inactive), C1 controls Q1, Q2, and Q3 to make Q1 equal to the power supply tube in the LDO circuit. Q4, the multiplexing of the LDO circuit is realized by the circuit structure of the step-down DC-DC. The specific work process is shown in Figure 9:

When the enable signal 1 changes from high to low and the enable signal 2 changes from low to high, the controller C1 controls the NMOS transistor Q2 to be in a completely off state, its resistance is approximately infinite, and the PMOS transistor Q3 is also controlled. The state is completely turned off, and the PMOS transistor Q1 is controlled to operate in the variable resistance region, which is equivalent to the power transistor Q4 in FIG. 2 or FIG. The resistance of Q1 is determined by the output voltage VOUT, and the resistance range may range from a few Ω to several hundred kΩ. When the VOUT voltage is slightly lower than the fixed value, the controller C1 reduces the on-resistance of Q1 by the output signal CQ1; when the VOUT voltage is slightly higher than the fixed value, the controller C1 increases the conduction of Q1 by outputting the signal CQ1. The resistor eventually stabilizes the output VOUT at a fixed voltage value. The waveform of CQ1 is a slowly changing waveform, and there is no fixed frequency. At this time, the waveform of the SW point is basically the same as the output voltage waveform VOUT. Its energy transfer efficiency is the output voltage divided by the input voltage.

It is not difficult to find that the present embodiment is an apparatus embodiment corresponding to the second embodiment, and the present embodiment can be implemented in cooperation with the second embodiment. The related technical details mentioned in the second embodiment are still effective in the present embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related art details mentioned in the present embodiment can also be applied to the second embodiment.

Embodiments of the invention

A fifth embodiment of the present invention relates to a method of controlling a power management integrated circuit. This embodiment simplifies the first embodiment, and the main difference is that the power supply power transistor Q3 in the first embodiment is omitted. The flow of the control method and the operation mode of the circuit in the present embodiment are similar to those of the first embodiment, as long as the content of Q3 in the first embodiment is removed.

After Q3 is omitted, when the step-down DC-DC and LDO are implemented, the performance will be deteriorated to some extent, but the chip area can be further reduced and the cost can be saved.

Specifically, when the enable signal 1 is active high (the enable signal 2 can only be set to low inactive), the step-down DC-DC function is implemented, and the specific working process can be simply divided into two phases:

The first stage controller C1 controls Q1 to turn on and Q2 to turn off respectively through control signals CQ1 and CQ2. At this time, VIN charges inductor L1 and also supplies power to VOUT.

The second stage controller C1 controls Q1 to be turned off and Q2 to be turned on by the control signals CQ1 and CQ2, respectively, and the inductor L1 is discharged to the loads on VOUT and VOUT.

When the enable signal 2 is active high, the LDO circuit is implemented, specifically

The power supply tube 2 is controlled to be in a completely off state by the controller, and the power supply tube 1 is controlled by the controller to operate in the variable resistance region, and the output voltage VOUT is stabilized by reducing or increasing the on-resistance of the power supply power tube 1. The fixed voltage value (ie, the power supply tube 1 is equivalent to the power supply tube Q4 in FIG. 2 or FIG. 3).

Other details not related to Q3 can be referred to the first embodiment, and will not be described again here.

A sixth embodiment of the present invention relates to a power management integrated circuit. This embodiment simplifies the third embodiment, and the circuit configuration is as shown in FIG. The main difference between this embodiment and the third embodiment is that the power supply power tube Q3 in the third embodiment is omitted. The operation mode of the circuit in this embodiment is similar to that of the third embodiment, as long as the content of Q3 in the third embodiment is removed.

It is not difficult to find that the present embodiment is an apparatus embodiment corresponding to the fifth embodiment, and the present embodiment can be implemented in cooperation with the fifth embodiment. The related technical details mentioned in the fifth embodiment are still effective in the present embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related technical details mentioned in the present embodiment can also be applied to the fifth embodiment.

Although the invention has been illustrated and described with reference to the preferred embodiments of the present invention, it will be understood The spirit and scope of the invention.

Industrial applicability

Sequence table free content

Claims

1. A method for controlling a power management integrated circuit, comprising the steps of:

One end of the power supply power tube 1 is connected to the input voltage, the other end is connected to the inductor and the power supply power tube 2, and the other end of the power supply power tube 2 is connected with a relatively zero potential, and the controller outputs a control signal to the power supply power tube. 1 and a gate of the power supply power tube 2, controlling conduction and shutdown of the power supply power tube 1 and the power supply power tube 2;

2. The method of controlling a power management integrated circuit according to claim 1, further comprising the steps of:

The power supply power tube 3 is connected in parallel to the two ends of the inductor, and the controller outputs a control signal to the gate of the power supply power tube 3 to control the conduction and shutdown of the power supply power tube 3;

If the enable signal 1 is valid, the power supply power tube 1, the power supply tube 2, and the power supply power tube 3 are controlled according to the working principle of the step-down DC-DC circuit to implement a step-down DC-DC circuit; When the enable signal 2 is valid, the power supply power tube 1, the power supply power tube 2, and the power supply power tube 3 are controlled according to the working principle of the LDO circuit to implement the LDO circuit.

3. The method for controlling a power management integrated circuit according to claim 2, wherein the power supply power tube 1, the power supply tube 2, and the power supply power tube 3 are controlled according to an operation principle of the LDO circuit to implement an LDO circuit. The steps include the following substeps:

Controlling, by the controller, that the power supply power tube 2 is in a completely off state;

Controlling, by the controller, that the power supply power tube 3 is in a fully conducting state;

The power supply power tube 1 is controlled by the controller to operate in the variable resistance region, and the output voltage VOUT is stabilized at a fixed voltage value by reducing or increasing the on-resistance of the power supply power tube 1.

4. The control method of the power management integrated circuit according to claim 3, wherein the controller controls the power supply power tube 3 by designing the on-resistance of the power supply power tube 3 within 0.2 to 5 ohms. In full conduction.

5. The control method of the power management integrated circuit according to any one of claims 2 to 4, wherein the power supply power tube 1, the power supply power tube 2, and the power supply power tube 3 are according to the working principle of the LDO circuit. The steps to control and implement the LDO circuit include the following substeps:

Controlling, by the controller, the power supply power tube 2 and the power supply power tube 3 in a completely off state;

Controlling, by the controller, the power supply power tube 1 to operate in a variable resistance region, and reducing or increasing the on-resistance of the power supply power tube 1 to ensure that the output voltage VOUT is stable at a fixed voltage value; The combination of inductance and output capacitance enables LC filtering.

6. A power management integrated circuit, comprising: a power supply power tube 1, a power supply power tube 2, a controller, an inductor, an enable signal 1 and an enable signal 2, wherein the enable signal 1 and Enable signal 2 is valid;

7. The power management integrated circuit according to claim 6, further comprising: a power supply tube 3;

The power supply power tube 3 is connected in parallel to the two ends of the inductor, and the controller further outputs a control signal to the gate of the power supply power tube 3 to control the conduction and shutdown of the power supply power tube 3;

8. The power management integrated circuit according to claim 7, wherein the controller controls the power supply power tube 1, the power supply power tube 2, and the power supply power tube 3 by: The connection relationship of the power supply tube 1 is equivalent to the connection relationship between the controller and the power supply tube in the LDO circuit:

The controller controls the power supply power tube 2 to be in a completely off state;

The controller controls the power supply power tube 3 to be in a fully conductive state;

The controller controls the power supply power tube 1 to operate in a variable resistance region, and by reducing or increasing the on-resistance of the power supply power tube 1, the output voltage VOUT is stabilized at a fixed voltage value.

9. The power management integrated circuit according to claim 8, wherein the controller controls the power supply power tube 3 to be completely guided by designing the on-resistance of the power supply power tube 3 within 0.2 to 5 ohms. Pass state.

10. The power management integrated circuit according to any one of claims 7 to 9, wherein the controller controls the power supply power tube 1, the power supply power tube 2, and the power supply power tube 3 by: The connection relationship between the controller and the power supply power tube 1 is equivalent to the connection relationship between the controller and the power supply power tube in the LDO circuit:

The controller controls the power supply power tube 2 and the power supply power tube 3 to be in a completely off state;

The controller controls the power supply power tube 1 to operate in a variable resistance region, and reduces or increases the on-resistance of the power supply power tube 1 to ensure that the output voltage VOUT is stable at a fixed voltage value; Combined with the capacitance of the output to achieve LC filtering.

11. The power management integrated circuit according to any one of claims 7 to 9, wherein the power supply power tube 1 and the power supply power tube 3 use a PMOS tube; The power supply tube 2 uses an NMOS transistor.