Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/10—Programming or data input circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
  • G11C11/5628—Programming or writing circuits; Data input circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
  • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F2213/0038—System on Chip
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
  • G11C2211/564—Miscellaneous aspects
  • G11C2211/5643—Multilevel memory comprising cache storage devices
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
  • G11C2211/564—Miscellaneous aspects
  • G11C2211/5648—Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant

Definitions

• This application relates generally to managing data in a memory system. More specifically, this application relates to a memory system
• a system controller When writing data to multiple die in a conventional flash memory system, a system controller normally utilizes a programming sequence in which during a transaction, data is written to an upper page of a die before data is written to a lower page of the same die. Because of the amount of time for a cache of a die to release after writing data to an upper page of the die, a system controller must often wait idle for a substantial period of time during a transaction before the system controller may execute a write to a lower page of the die.
• a memory device comprising a first die and a second die, each of the first die and the second die comprising a plurality of pages, a first set of data is received. The first set of data is written to one or more pages of the first die and the second die.
• USB universal serial bus
• a second set of data is received after the first set of data is written to the one or more pages of the first die and the second die.
• a first portion of the second set of data is written to a lower page of the second die and a second portion of the second set of data is written to an upper page of the second die after writing the first portion of the second set of data to a lower page of the second die.
• a third portion of the second set of data may be written to an upper page of the first die prior to writing the first portion of the second set of data to the lower page of the second die. Further, a fourth portion of the second set of data may be written to a lower page of the first die after writing the second portion of the second set of data to the upper page of the second die.
• a second portion of the set of data is written to a lower page of the second die after the first portion of the set of data is written to the upper page of the first die.
• a third portion of the set of data is written to an upper page of the second die after the second portion of the set of data is written to the lower page of the second die.
• a fourth portion of the set of data is written to a lower page of the first die after the third portion of the set of data is written to the upper page of the second die.
• a memory device such as a USB memory device comprising a communication interface, a memory unit, and a processor
• the memory unit comprises a first die and a second die, each of the first die and the second die comprising a plurality of pages.
• the processor sequentially writes data received over the
• the processor is configured to receive a first set of data over the communication interface and write the first set of data to one or more pages of the first die and the second die.
• the processor is configured to receive a second set of data over the communication interface after writing the first set of data to the one or more pages of the first die and the second die.
• the processor is further configured to write a first portion of the second set of data to a lower page of the second die and to write a second portion of the second set of data to an upper page of the second die after writing the first portion of the second set of data to the lower page of the second die.
• FIG. 1 illustrates a host connected with a memory system having a multi-bank non-volatile memory containing multiple die.
• FIG. 2 is an example block diagram of an example flash memory system controller for use in the multiple die non-volatile memory of FIG. 1.
• FIG. 3 is an example one flash memory bank suitable as one of the non-volatile memory banks illustrated in FIG. 1.
• FIG. 4 is a representative circuit diagram of a memory cell array that may be used in the memory bank of FIG. 3.
• FIG. 5 illustrates an example physical memory organization of the memory bank of FIG. 3.
• FIG. 6a shows an expanded view of a portion of the physical memory of FIG. 5.
• FIG. 6b illustrates charge levels in a MLC memory operated to store two bits of data in a memory cell.
• FIG. 7 illustrates a two die memory system.
• FIGS. 8a and 8b are a flow chart of a method for implementing a modified programming sequence for sequentially writing data to a memory device that reduces an amount of time that a system controller must wait for a cache to release while writing data to one or more pages of a first die and a second die.
• FIGS. 1-8b A flash memory system suitable for use in implementing aspects of the invention is shown in FIGS. 1-8b.
• a host system 100 of FIG. 1 stores data into and retrieves data from a memory system 102.
• the memory system may be flash memory embedded within the host, such as in the form of a solid state disk (SSD) drive installed in a personal computer.
• the memory system 102 may be in the form of a card that is removably connected to the host through mating parts 104 and 106 of a mechanical and electrical connector as illustrated in FIG. 1.
• a flash memory configured for use as an internal or embedded SSD drive may look similar to the schematic of FIG. 1 , with the primary difference being the location of the memory system 102 internal to the host.
• SSD drives may be in the form of discrete modules that are drop-in replacements for rotating magnetic disk drives.
• the host system 100 of FIG. 1 may be viewed as having two major parts, in so far as the memory system 102 is concerned, made up of a
• the applications portion 108 can include a processor 112 running word processing, graphics, control or other popular application software, as well as the file system 114 for managing data on the host 100.
• the applications portion 108 includes the software that operates the camera to take and store pictures, the cellular telephone to make and receive calls, and the like.
• the memory system 102 of FIG. 1 may include non-volatile memory, such as flash memory 116, and a system controller 118 that both interfaces with the host 100 to which the memory system 102 is connected for passing data back and forth and controls the memory 116.
• the system controller 118 may convert between logical addresses of data used by the host 100 and physical addresses of the flash memory 116 during data programming and reading.
• the flash memory 116 may include any number of memory die 120 and two memory die are shown in FIG. 1 simply by way of illustration.
• the system controller 118 may include a front end 122 that interfaces with the host system, controller logic 124 for coordinating operation of the memory 116, flash
• FIMs flash interface modules
• the system controller 118 may be implemented on a single integrated circuit chip, such as an application specific integrated circuit (ASIC) such as shown in FIG. 2.
• the processor 206 of the system controller 118 may be configured as a multi-thread processor capable of communicating separately with each of the respective memory banks 120 via a memory interface 204 having I/O ports for each of the respective banks 120 in the flash memory 116.
• the system controller 118 may include an internal clock 218.
• ECC error correction code
• Each die 120 in the flash memory 116 may contain an array of memory cells organized into multiple planes.
• FIG. 3 shows such planes 310 and 312 for simplicity but a greater number of planes, such as four or eight planes, may instead be used.
• the memory cell array of a memory bank may not be divided into planes.
• each plane has its own column control circuits 314 and 316 that are operable independently of each other.
• the circuits 314 and 316 receive addresses of their respective memory cell array from the address portion 306 of the system bus 302, and decode them to address a specific one or more of respective bit lines 318 and 320.
• the word lines 322 are addressed through row control circuits 324 in response to
• Source voltage control circuits 326 and 328 are also connected with the respective planes, as are p-well voltage control circuits 330 and 332. If the bank 300 is in the form of a memory chip with a single array of memory cells, and if two or more such chips exist in the system, data are transferred into and out of the planes 310 and 312 through respective data input/output circuits 334 and 336 that are connected with the data portion 304 of the system bus 302. The circuits 334 and 336 provide for both
• each memory chip also contains some controlling circuitry that executes commands from the controller 118 to perform such functions.
• Interface circuits 342 are connected to the control and status portion 308 of the system bus 302. Commands from the controller 118 are provided to a state machine 344 that then provides specific control of other circuits in order to execute these commands.
• Control lines 346-354 connect the state machine 344 with these other circuits as shown in FIG. 3.
• Status information from the state machine 344 is communicated over lines 356 to the interface 342 for transmission to the controller 118 over the bus portion 308.
• a NAND architecture of the memory cell arrays 310 and 312 is discussed below, although other architectures, such as NOR, can be used instead.
• An example NAND array is illustrated by the circuit diagram of FIG. 4, which is a portion of the memory cell array 310 of the memory bank 300 of FIG. 3.
• a large number of global bit lines are provided, only four such lines 402- 408 being shown in FIG. 4 for simplicity of explanation.
• a number of series connected memory cell strings 410-424 are connected between one of these bit lines and a reference potential. Using the memory cell string 414 as
• a plurality of charge storage memory cells 426-432 are connected in series with select transistors 434 and 436 at either end of the string.
• select transistors 434 and 436 When the select transistors of a string are rendered conductive, the string is connected between its bit line and the reference potential. One memory cell within that string is then programmed or read at a time.
• Word lines 438-444 of FIG. 4 individually extend across the charge storage element of one memory cell in each of a number of strings of memory cells, and gates 446 and 450 control the states of the select transistors at each end of the strings.
• the memory cell strings that share common word and control gate lines 438-450 are made to form a block 452 of memory cells that are erased together. This block of cells contains the minimum number of cells that are physically erasable at one time.
• One row of memory cells, those along one of the word lines 438-444, are programmed at a time.
• the rows of a NAND array are programmed in a prescribed order, in this case beginning with the row along the word line 444 closest to the end of the strings connected to ground or another common potential.
• the row of memory cells along the word line 442 is programmed next, and so on, throughout the block 452.
• the row along the word line 438 is programmed last.
• a second block 454 is similar, its strings of memory cells being connected to the same global bit lines as the strings in the first block 452 but having a different set of word and control gate lines.
• the word and control gate lines are driven to their proper operating voltages by the row control circuits 324. If there is more than one plane in the system, such as planes 1 and 2 of FIG. 3, one memory architecture uses common word lines extending between them. There can alternatively be more than two planes that share common word lines. In other memory architectures, the word lines of individual planes are separately driven.
• the memory cells may be operated to store two levels of charge so that a single bit of data is stored in each cell. This is typically referred to as a binary or single level cell (SLC) memory. Alternatively, the memory cells may be operated to store more than two detectable levels of charge in each charge storage element or region, thereby to store more than one bit of data in each. This latter configuration is referred to as multi level cell (MLC) memory. Both types of memory cells may be used in a memory, for example binary flash memory may be used for caching data and MLC memory may be used for longer term storage.
• the charge storage elements of the memory cells are most commonly conductive floating gates but may alternatively be non-conductive dielectric charge trapping material. [0030] FIG.
• planes 502-508 may be on a single die, on two die (two of the planes on each die) or on four separate die. Of course, other numbers of planes, such as 1 , 2, 8, 16 or more may exist in each die of a system.
• the planes are individually divided into blocks of memory cells shown in FIG. 5 by rectangles, such as blocks 510, 512, 514 and 516, located in respective planes 502-508. There can be dozens or hundreds of blocks in each plane.
• a block of memory cells is the unit of erase, the smallest number of memory cells that are physically erasable together.
• the blocks are operated in larger metablock units.
• One block from each plane is logically linked together to form a metablock.
• the four blocks 510-516 are shown to form one metablock 518. All of the cells within a metablock are typically erased together.
• the blocks used to form a metablock need not be restricted to the same relative locations within their respective planes, as is shown in a second metablock 520 made up of blocks 522-528.
• the memory system can be operated with the ability to dynamically form metablocks of any or all of one, two or three blocks in different planes. This allows the size of the metablock to be more closely matched with the amount of data available for storage in one
• the individual blocks are in turn divided for operational purposes into pages of memory cells, as illustrated in FIG. 6a.
• the memory cells of each of the blocks 510-516 for example, are each divided into eight pages P0-P7.
• a metapage 602 is illustrated in FIG. 6a, being formed of one physical page from each of the four blocks 510-516.
• the metapage 602 for example, includes the page P2 in each of the four blocks but the pages of a metapage need not necessarily have the same relative position within each of the blocks.
• each memory cell is configured to store four levels of charge corresponding to values of "11 ,” “01 ,” “10,” and "00.”
• Each bit of the two bits of data may represent a page bit of a lower page or a page bit of an upper page, where the lower page and upper page span across a series of memory cells sharing a common word line.
• the less significant bit of the two bits of data represents a page bit of a lower page and the more significant bit of the two bits of data represents a page bit of an upper page.
• FIG. 6b illustrates one implementation of the four charge levels used to represent two bits of data in a memory cell.
• a value of "11" corresponds to an un-programmed state of the memory cell.
• the level of charge is increased to represent a value of "10" corresponding to a programmed state of the page bit of the lower page.
• FIG. 7 illustrates a memory 700 with two memory die 702, 704 each having a cache storage area 706, 708 and a main storage area 710, 712 arrangement that may be used to implement block interleaving.
• Block interleaving between multiple die such as die 702 and 704 in a flash memory 700 may be accomplished by writing sequentially addressed data received from a host to the cache storage area 706 of a first die 702 in flash memory.
• the controller of the flash memory When an amount of sequentially addressed data has been written to the cache storage area 706 of the first die that is equal to a size of a page of memory in a main storage area 710 of the first die, the controller of the flash memory writes a next group of received data from the host that is sequentially addressed to cache storage blocks in the next memory die 704 of the flash memory.
• the writing of sequentially addressed data into the cache storage area 708 of the second die 704 continues until, as with the first die 702, an amount of the cache storage area 708 of the second die 704 equal to a page size of a block in the main storage area 712 of the second die 704 is filled.
• a controller is not shown in FIG. 7, however the memory 700 of FIG. 7 may be associated with a discrete controller such as controller 118 shown in FIG. 2, may have one or more controllers integrated with the memory die on a single chip or may be configured to work with a combination of the two.
• a cache In a die, a cache typically releases approximately ⁇ after a write to an upper page of the die and the cache typically releases approximately 20 ⁇ after a write to a lower page of the die. Accordingly, when a system controller writes to a lower page of a die soon after writing to an upper page of the same die, the system controller often must wait a period of time to ensure that the cache releases. For example, in the second 64K transaction in the table above, assuming a data transfer time of 450 ⁇ to write to an upper page of a die with a 30MHz write clock, a system controller must wait approximately 450 ⁇ after writing data to an upper page of Die 1 i.e. Page 2 to write data to a lower page of Die 0 i.e.
• Page 3 to ensure that the system controller does not write data to the lower page of Die 0 i.e. Page 3 less than ⁇ after writing data to the upper page of Die 0 i.e. Page 2.
• the data transfer time of 450 ⁇ may be caused in part by delay in writing data due to, for example, scrambling.
• a data transfer time of 450 ⁇ to write to an upper page of a die may be the result of the absence of a delay in writing data because, for example, scrambling may already be accomplished and/or the data may be prepared to be written while the controller waits for the cache to release.
• the total transaction time for the second 64K transaction can be calculated as shown below.
• the programming sequence of the system controller may be modified to reduce the amount of time the system controller must wait for the cache to release during a transaction.
• the table below illustrates an initial three transactions in which a programming sequence has been modified to reduce the amount of time a system controller must wait for the cache to release during a transaction.
• the modified programming sequence may include any number of 64K transactions.
• a system controller takes 450 ⁇ to write data to an upper page of a die and to write data to a lower page of a die. Accordingly, a system controller operating under the modified programming sequence to perform the second 64K transaction, for example, needs only to wait 20 ⁇ after writing data to a lower page of Die 1 i.e. Page 3 to write data to an upper page of Die 1 i.e. Page 2 to ensure that the cache releases.
• the total transaction time for the second 64K transaction in the modified programming sequence can be calculated as shown below.
• a system controller is able to complete a 64K transaction in 1820 ⁇ 5 using the modified programming sequence versus 2100 ⁇ 5 using the traditional programming sequence.
• a data transfer time to write data to a page of a die is 280 ⁇ 5. Accordingly, in order to execute the second 64K transaction in traditional programming sequence from Table 1 , a system controller must wait
• the controller does not write data to a lower page of Die 0 i.e. Page 3 less than 900 ⁇ after writing data to an upper page of Die 0 i.e. Page 2.
• the total transaction time for the second 64K transaction can be calculated as shown below.
• a system controller is able to complete a 64K transaction with no delay between data in approximately ⁇ using the modified programming sequence versus 1740 ⁇ using the traditional
• Figures 8a and 8b are a flow chart of a method for implementing a modified programming sequence for sequentially writing data to a memory device such as a universal serial bus (USB) memory device that reduces an amount of time that a system controller must wait while waiting for a cache to release while writing data to one or more pages of a first die and a second die.
• a memory device such as a universal serial bus (USB) memory device that reduces an amount of time that a system controller must wait while waiting for a cache to release while writing data to one or more pages of a first die and a second die.
• USB universal serial bus
• the method 800 begins at step 802 with the memory device receiving a first set of data.
• the first set of data may be 64 kilobytes of data of a first 64K transaction that the memory device receives from a host device.
• the memory device writes the first set of data to one or more pages of the first die and the second die at step 804.
• the memory device receives a second set of data after writing the first set of data to the one or more pages of the first die and the second die.
• the second set of data may be 64
• the controller writes a first portion of the second set of data to an upper page of the first die.
• the controller writes a second portion of the second set of data to a lower page of the second die after writing the first portion of the second set of data to the upper page of the first die.
• the controller writes a third portion of the second set of data to an upper page of the second die after writing the second portion of the second set of data to the lower page of the second die.
• the controller writes a fourth portion of the second set of data to a lower page of the first die after writing the third portion of the second set of data to the upper page of the second die.
• the memory device receives a third set of data.
• the controller writes a first portion of the third set of data to an upper page of the first die after writing the fourth portion of the second set of data to the lower page of the first die.
• the controller writes a second portion of the third set of data to a lower page of the second die after writing the first portion of the third set of data to the upper page of the first die.
• the controller writes a third portion of the third set of data to an upper page of the second die after writing the second portion of the third set of data to the lower page of the second die.
• the controller writes a fourth portion of the third set of data to a lower page of the first die after writing the third portion of the third set of data to the upper page of the second die.
• steps 816, 818, 820, 822, and 824 could be repeated for further 64K transactions using the modified programming sequence.
• the memory device could receive a fourth set of data and write portions of the fourth set of data to upper and lower pages of the first and second die such that a portion of the fourth set of data is written to a lower page of a die prior to another portion of the fourth set of data being written to an upper page of the same die.
• the modified programming sequence has been described above with respect to a memory device receiving and writing data to upper and lower pages of first and second die, the same modified programming sequence can be used during garbage collection operations to write data already stored at the memory device to other upper and lower pages of the first and second die.

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• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Read Only Memory (AREA)
• Techniques For Improving Reliability Of Storages (AREA)

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• 2010
  • 2010-12-22 WO PCT/US2010/061717 patent/WO2012015457A1/en active Application Filing
  • 2010-12-22 CN CN201080069379.1A patent/CN103140896B/zh active Active
  • 2010-12-22 KR KR1020137004537A patent/KR20130110153A/ko not_active Application Discontinuation
• 2011
  • 2011-07-29 TW TW100127122A patent/TW201222250A/zh unknown

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