WO2012015085A1

WO2012015085A1 - Printed circuit board and method of manufacturing the same

Info

Publication number: WO2012015085A1
Application number: PCT/KR2010/005011
Authority: WO
Inventors: Min Seok Lee; Hye Sun Yoon
Original assignee: LG Innotek Co Ltd
Current assignee: LG Innotek Co Ltd
Priority date: 2010-07-30
Filing date: 2010-07-30
Publication date: 2012-02-02
Anticipated expiration: 2013-01-30

Abstract

Disclosed are a printed circuit board and a method of manufacturing the same. The method includes preparing a carrier formed with a first metal layer; attaching a chip onto the first metal layer; connecting a connection terminal of the chip to the first metal layer by using a wire; forming a first insulating layer on the first metal layer and the chip and forming a second metal layer on the first insulating layer; removing the carrier; and forming a first circuit pattern including a connection circuit pattern and a second circuit pattern by selectively removing the first and second metal layers.

Description

PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME

The disclosure relates to a printed circuit board and a method of manufacturing the same.

Recently, electronic products have become miniaturized, packaged and small-sized, so demand for a small-sized printed circuit board (PCB) has been increased.

In this regard, demand for an embedded PCB provided therein with a chip has also been increased.

The manufacturing process for the embedded PCB includes a step of connecting a chip embedded in a PCB with circuit patterns of the PCB.

The chip may include a bare chip and a wafer level package (WLP) chip which is obtained by forming a redistribution layer on the bare chip. In the case of the bare chip, a connection terminal connected to an external circuit or an element is too small and a pitch between connection terminals is very narrow so connection to the circuit patterns is very difficult. To solve this problem, a redistribution layer is additionally formed on the bare chip. However, since an additional process is required to form the redistribution layer, the manufacturing process is complicated and product yield is lowered, so that the manufacturing cost is increased.

Therefore, it is necessary to develop a method of manufacturing a PCB capable of connecting the connection terminal to the external circuit or the element by using the bare chip.

The embodiment provides a PCB having a novel structure and a method of manufacturing such a PCB.

The embodiment provides a PCB capable of connecting a chip to a circuit pattern through a simple process and a method of manufacturing such a PCB.

A method of manufacturing a printed circuit board according to the embodiment includes preparing a carrier formed with a first metal layer; attaching a chip onto the first metal layer; connecting a connection terminal of the chip to the first metal layer by using a wire; forming a first insulating layer on the first metal layer and the chip and forming a second metal layer on the first insulating layer; removing the carrier; and forming a first circuit pattern including a connection circuit pattern and a second circuit pattern by selectively removing the first and second metal layers.

A printed circuit board according to the embodiment includes a first circuit pattern including a connection circuit pattern; a chip on the first circuit pattern; a wire connecting a connection terminal of the chip to the connection circuit pattern; a first insulating layer on the chip and the first circuit pattern such that the chip is surrounded by the first insulating layer; and a second circuit pattern on the first insulating layer.

The embodiment can provide a PCB having a novel structure and a method of manufacturing such a PCB.

The embodiment can provide a PCB capable of effectively connecting a chip to a circuit pattern through a simple way by using a wire even if a connection terminal of the chip has a small size and the circuit pattern has a narrow pitch, and a method of manufacturing such a PCB.

FIGS. 1 to 11 are sectional views showing a printed circuit board and a method of manufacturing the same according to the embodiment.

In the description of an embodiment, it will be understood that, when a layer (or film), a region, a pattern, or a structure is referred to as being on or under another substrate, another layer (or film), another region, another pad, or another pattern, it can be directly or indirectly on the other substrate, layer (or film), region, pad, or pattern, or one or more intervening layers may also be present. Further, on or under of each layer is determined based on the drawing.

The thickness and size of each layer shown in the drawings can be exaggerated, omitted or schematically drawn for the purpose of convenience or clarity. In addition, the size of elements does not utterly reflect an actual size.

FIGS. 1 to 11 are sectional views showing a PCB and a method of manufacturing the same according to the embodiment.

The PCB shown in FIG. 11 is manufactured through the method according to the embodiment.

Referring to FIG. 11, the PCB includes a first circuit pattern 80 having a connection circuit pattern 85, a chip 40 attached onto the first circuit pattern 80, a wire 25 connecting a connection terminal 41 of the chip 40 to the connection circuit pattern 85, a first insulating layer 50 formed on the chip 40 and the first circuit pattern 80, a second circuit pattern 81 formed on the first insulating layer 50, a first conductive via 71 formed through the first insulating layer 50 to electrically connect the first circuit pattern 80 to the second circuit pattern 81, a second insulating layer 90 formed on the first and

second circuit patterns

80 and 81 and the first conductive via 71, a third circuit pattern 120 formed on the second insulating layer 90, and a second conductive via 110 for connecting the first and

second circuit patterns

80 and 81 to a third circuit pattern 120.

The wire 25 is bonded to the connection circuit pattern 85. The connection circuit pattern 85 may include material identical to that of the first circuit pattern 80.

In addition, a position determination hole 21 can be formed in the first circuit pattern 80. The position determination hole 21 may serve as a fiducial mark to detect an alignment position of the chip 40 and a bonding position of the wire 25.

The chip 40 may be aligned on an adhesive layer 30. The adhesive layer 30 makes contact with at least one of the first circuit pattern 80 and the second insulating layer 90. The adhesive layer 30 may have an area larger than that of the chip 40.

The chip 40 includes the connection terminal 41. The connection terminal 41 is connected to the first circuit pattern 80 through the wire 25.

The wire 25 may have a curved shape or a parabolic shape. That is, the wire 25 is convex upward and connected to the first circuit pattern 80 while being spaced apart from the adhesive layer 30 on which the chip 40 is aligned. The wire 25 extends by passing through the first insulating layer 50. The wire 25 has a first part located above the chip 40, a second part located below the chip 40, and a third part located at a lateral side of the chip 40. The wire 25 is surrounded by the first insulating layer 50.

At least a part of the second insulating layer 90 makes contact with the adhesive layer 30 and a part of the second insulating layer 90 is aligned in the first conductive via 71.

Hereinafter, the PCB and the method of manufacturing the same according to the embodiment will be described in detail with reference to FIGS. 1 to 11.

Referring to FIG. 1, a carrier 10 formed thereon with a first metal layer 20 is prepared.

For instance, the first metal layer 20 includes at least one of Cu, Sn, Al, Ni, Au, or Ag.

The first metal layer 20 may be formed over the whole area of the carrier 10.

The first metal layer 20 can be formed on the carrier 10 through the sputtering, the plating or the stacking process.

The carrier 10 may include metal or resin. The carrier 10 is formed by using material different from that of the first metal layer 20.

Referring to FIG. 2, the first metal layer 20 is selectively removed to form the position determination hole 21. The position determination hole 21 serves as a yardstick for determining the position of the first circuit pattern 80 and the connection circuit pattern 85 to be formed on the PCB and the attachment position of the chip 40. Details thereof will be described later with reference to the corresponding process.

In order to form the position determination hole 21, a photoresist pattern (not shown) is formed on the first metal layer 20 and the first metal layer 20 is selectively etched by using the photoresist pattern as a mask.

For instance, the position determination hole 21 can be formed at an outer peripheral portion of the first metal layer 20. In detail, the position determination hole 21 can be formed in the first circuit pattern 80 to be formed later. Preferably, the position determination hole 21 can be formed at the outer peripheral portion of the first circuit pattern 80. The position of the position determination hole 21 can be variously changed according to the applications.

Referring to FIG. 3, the adhesive layer 30 is formed on the first metal layer 20, and the chip 40 is attached onto the adhesive layer 30. The adhesive layer 30 may have an area larger than that of the chip 40.

Although FIG. 3 shows the adhesive layer 30 locally formed on the first metal layer 20, the adhesive layer 30 may be formed over the whole area of the first metal layer 20, if necessary.

The adhesive layer 30 can be formed by using material having adhesive property, such as epoxy resin or phenol resin.

The chip 40 may include a bare chip, a WLP chip obtained by forming a redistribution layer on the bare chip, or various chips connectable to the external device through the wire bonding scheme.

The chip 40 includes the connection terminal 41 that electrically connects the chip 40 to the external circuit or the element.

The attachment position of the chip 40 may be determined based on the position determination hole 21. In more detail, the adhesive layer 30 is formed on the attachment position of the chip 40, which is previously designed based on the position determination hole 21, and then the chip 40 is attached onto the adhesive layer 30.

Referring to FIG. 4, the connection terminal 41 of the chip 40 is connected to the first metal layer 20 through the wire 25.

The bonding position of the wire 25 on the first metal layer 20 may be determined based on the position determination hole 21.

The first meal layer 20 connected to the wire 25 is referred to as the connection circuit pattern 85, which will be described later in detail.

According to the related art, a conductive via is formed in an insulating layer between a chip and a circuit pattern in order to connect the chip to the circuit pattern.

However, as described above, the chip 40 may include the bare chip, the WLP chip obtained by forming the redistribution layer on the bare chip, or various chips connectable to the external device through the wire bonding scheme. If the bare chip serves as the chip 40, the pitch between the connection terminals 41 of the chip 40 is too narrow (about 150㎛ or less) and the width of the connection terminal 41 is too small (about 100㎛ or less), so it is difficult to form the conductive via to connect the chip 40 to the external circuit or the element.

To solve the above problem, according to the related art, the redistribution layer is formed on the bare chip through an additional process to connect the chip to the external circuit or the element although it may degrade the efficiency.

However, according to the embodiment, the connection terminal 41 of the chip 40 is electrically connected to the first metal layer 20 through the wire 25, so the electric connection can be easily achieved even if the bare chip is used for the chip 40. That is, the additional processes to form the redistribution layer and the conductive via may be omitted, so that the manufacturing process is simplified and the efficiency is improved.

The wire 25 can be manufactured by using metal including at least one of Cu, Sn, Al, Ni, Au, or Ag.

Referring to FIG. 5, the B-stage insulating layer 50 is prepared on the first metal layer 20 and the chip 40, and the second metal layer 60 is prepared on the first insulating layer 50.

The first insulating layer 50 surrounds the top surface of the first metal layer 20 and the chip 40 and includes a first layer 51 having the height corresponding to the height of the chip 40 and a second layer 52 covering the top surface of the chip 40 and the first layer 51. In addition, a plurality of first and

second layers

51 and 52 can be provided.

The first insulating layer 50 is formed by using material having adhesive and insulating properties. For instance, the first insulating layer may include resin material, such as epoxy resin or phenol resin. In addition, the first insulating layer 50 may include a prepreg, a polyimide film, or an ABF film. That is, the first insulating layer 50 may include various materials according to applications.

The second metal layer 60 can be formed by using metal including at least one of Cu, Sn, Al, Ni, Au, or Ag.

Referring to FIG. 6, the B-stage first insulating layer 50 and the second metal layer 60 prepared on the B-stage first insulating layer 50 are pressed against the first metal layer 20 and the chip 40 by applying heat and pressure. Then, the first insulating layer 50 is cured by applying heat and ultraviolet ray to the first insulating layer 50.

Since the first insulating layer 50 is prepared in a semi-cured state (B-stage), the wire 25 can be formed on the chip 40 and the first metal layer 20 without being damaged when the second metal layer and the first insulating layer 50 are pressed against the first metal layer 20 and the chip 40.

Therefore, the wire 25 extends by passing through the first insulating layer 50 to connect the connection terminal 41 of the chip 40 to the first metal layer 20.

Referring to FIG. 7, the carrier 10 is removed, and the first conductive via 71 is formed through the first and second metal layers 20 and 60 and the first insulating layer 50.

The first conductive via 71 is formed to electrically activate the circuit patterns to be formed on the top surface and the bottom surface of the PCB.

In order to form the first conductive via 71, a via hole 70 is formed through the first and second metal layers 20 and 60 and the first insulating layer 50 by a laser drilling process and a plating process is performed with respect to the via hole 70.

In the plating process, an electroless plating process is performed to form a seed layer and then an electroplating process is performed.

Referring to FIG. 8, the first and second metal layers 20 and 60 are selectively removed to form the first and

second circuit patterns

80 and 81. The first circuit pattern 80 includes the connection circuit pattern 85.

In order to form the first and

second circuit patterns

80 and 81 and the connection circuit pattern 85, a photoresist pattern (not shown) is formed on the first and second metal layers 20 and 60, and then the first and second metal layers 20 and 60 are etched by using the photoresist pattern as a mask.

The position of the first and

second circuit patterns

80 and 81 and the connection circuit pattern 85 can be determined based on the position determination hole 21.

The connection circuit pattern 85 is formed on a region to which the wire 25 is connected, so that the connection circuit pattern 85 is electrically connected to the connection terminal 41 of the chip 40 through the wire 25.

Since the first and

second circuit patterns

80 and 81 and the connection circuit pattern 85 are simultaneously formed by selectively removing the first metal layer 20, the manufacturing process can be simplified.

Referring to FIG. 9, the second insulating layer 90 is formed on the first and

second circuit patterns

80 and 81 and the first conductive via 71 and a third metal layer 100 is formed on the second insulating layer 90.

The second insulating layer 90 is formed by using material identical to that of the first insulating layer 50, so detailed description thereof will be omitted in order to avoid redundancy.

In order to form the second insulating layer 90 and the third metal layer 100, the B-stage second insulating layer 90 is prepared on the first and

second circuit patterns

80 and 81 and the third metal layer 100 is prepared on the second insulating layer 90. Then, the B-stage second insulating layer 90 and the third metal layer 100 are pressed against the first and

second circuit patterns

80 and 81 and the conductive via 71 by applying heat and pressure. After that, the second insulating layer 90 is cured.

The third metal layer 100 may include material identical to that of the first and second metal layers 20 and 60.

Referring to FIG. 10, the second conductive via 110 can be formed to electrically connect the first and

second circuit patterns

80 and 81 to the third metal layer 100.

In order to form the second conductive via 110, a via hole (not shown) is formed through the second insulating layer 90 and a plating process is performed with respect to the via hole.

Referring to FIG. 11, the third metal layer 100 is selectively removed to form the third circuit pattern 120.

The process for forming the third circuit pattern 120 is similar to the process for forming the first and

second circuit patterns

80 and 81, so detailed description thereof will be omitted in order to avoid redundancy.

Meanwhile, the process for forming the first and second insulating

layers

50 and 90 among the first to

third circuit patterns

80, 81 and 120 may be repeated or omitted depending on the circuits to be formed on the PCB. In addition, this process can be variously modified within the scope of the embodiment.

Then, a solder mask and a solder ball can be formed on the third circuit pattern 120 to connect the PCB with other circuits, elements or substrates.

Although the exemplary embodiments of the present invention have been described, it is understood that the present invention should not be limited to these exemplary embodiments but various changes and modifications can be made by one ordinary skilled in the art within the spirit and scope of the present invention as hereinafter claimed.

The embodiments are applicable to the PCB and the method of manufacturing the same.

Claims

A method of manufacturing a printed circuit board, the method comprising:

preparing a carrier formed with a first metal layer;

attaching a chip onto the first metal layer;

connecting a connection terminal of the chip to the first metal layer by using a wire;

forming a first insulating layer on the first metal layer and the chip and forming a second metal layer on the first insulating layer;

removing the carrier; and

forming a first circuit pattern including a connection circuit pattern and a second circuit pattern by selectively removing the first and second metal layers.
The method of claim 1, further comprising:

forming a position determination hole by selectively removing the first metal layer before the chip is attached onto the first metal layer,

wherein a position of the connection circuit pattern is determined based on the position determination hole.
The method of claim 1, further comprising:

forming an adhesive layer on the first metal layer before the chip is attached onto the first metal layer.
The method of claim 3, wherein the adhesive layer has an area larger than an area of the chip.
The method of claim 3, wherein the wire is spaced apart from the adhesive layer.
The method of claim 1, wherein the wire has a curved shape or a parabolic shape.
The method of claim 1, wherein the first insulating layer surrounds the wire.
The method of claim 1, further comprising:

forming a via hole through the first insulating layer and forming a conductive via in the via hole to electrically connect the first metal layer to the second metal layer before the first and second circuit patterns are formed.
A printed circuit board comprising:

a first circuit pattern including a connection circuit pattern;

a chip on the first circuit pattern;

a wire connecting a connection terminal of the chip to the connection circuit pattern;

a first insulating layer formed on the chip and the first circuit pattern such that the chip is surrounded by the first insulating layer; and

a second circuit pattern on the first insulating layer.
The printed circuit board of claim 9, further comprising a position determination hole in the first circuit pattern.
The printed circuit board of claim 9, further comprising an adhesive layer between the first circuit pattern and the chip.
The printed circuit board of claim 11, wherein the adhesive layer has an area larger than an area of the chip.
The printed circuit board of claim 11, wherein the wire is spaced apart from the adhesive layer.
The printed circuit board of claim 9, wherein the wire has a curved shape or a parabolic shape.
The printed circuit board of claim 9, wherein the first insulating layer surrounds the wire.
The printed circuit board of claim 9, further comprising a conductive via formed through the first insulating layer to electrically connect the first circuit pattern to the second circuit pattern.
The printed circuit board of claim 9, further comprising a second insulating layer formed on the first insulating layer, the first circuit pattern and the second circuit pattern.
The printed circuit board of claim 17, further comprising a third circuit layer on the second insulating layer, wherein the third circuit pattern is electrically connected to the first circuit pattern and the second circuit pattern through the conductive via.
The printed circuit board of claim 11, further comprising a second insulating layer formed on the first second insulating layer, the first circuit pattern and the second circuit pattern, wherein the second insulating layer makes contact with the adhesive layer.
The printed circuit board of claim 16, further comprising a second insulating layer formed on the first second insulating layer, the first circuit pattern and the second circuit pattern, wherein a part of the second insulating layer is disposed in the conductive via.