WO2012015084A1

WO2012015084A1 - Printed circuit board and method of manufacturing the same

Info

Publication number: WO2012015084A1
Application number: PCT/KR2010/005010
Authority: WO
Inventors: Min Seok Lee; Jae Bong Choi
Original assignee: Lg Innotek Co., Ltd.
Priority date: 2010-07-30
Filing date: 2010-07-30
Publication date: 2012-02-02

Abstract

Disclosed are a printed circuit board and a method of manufacturing the same. The printed circuit board includes an electric element; an insulating layer surrounding a top surface, a bottom surface and lateral sides of the electric element; a circuit pattern over the insulating layer; and a bump electrically connecting the electric element with the circuit pattern.

Description

PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME

The disclosure relates to a printed circuit board and a method of manufacturing the same.

Recently, as demand for a miniaturized, packaged and small-sized printed circuit board (PCB) has been increased, demand for an embedded PCB provided therein with an electric element, such as an active element or a passive element, has also been increased.

In such an embedded PCB, it is important to install the electric element in the embedded PCB such that the electric element is not exposed to the outside. In this case, the electric element is prevented from being damaged by external environment, so that reliability of the PCB can be improved.

However, if the embedded PCB is designed such that the electric element is not exposed to the outside, a thickness of the embedded PCB is enlarged and the degree of freedom for circuit design may be limited.

The embodiment provides a PCB having a thin thickness without limiting the degree of freedom for circuit design and a method of manufacturing such a PCB.

The embodiment provides a PCB having high reliability and a method of manufacturing such a PCB.

A printed circuit board according to the embodiment includes an electric element; an insulating layer surrounding a top surface, a bottom surface and lateral sides of the electric element; a circuit pattern over the insulating layer; and a bump electrically connecting the electric element with the circuit pattern.

A method of manufacturing a printed circuit board according to the embodiment includes preparing a first metal layer; forming a bump on the first metal layer; bonding an electric element onto the bump; forming an insulating layer to surround a top surface of the first metal layer and a top surface, a bottom surface and lateral sides of the electric element, and forming a third metal layer on the insulating layer; and forming a circuit pattern by selectively removing the first and third metal layers.

The embodiment can provide a PCB having a thin thickness without limiting the degree of freedom for circuit design and a method of manufacturing such a PCB.

The embodiment can provide a PCB having high reliability and a method of manufacturing such a PCB.

FIGS. 1 to 14 are sectional views showing a printed circuit board and a method of manufacturing the same according to the embodiment

In the description of an embodiment, it will be understood that, when a layer (or film), a region, a pattern, or a structure is referred to as being on or under another substrate, another layer (or film), another region, another pad, or another pattern, it can be directly or indirectly on the other substrate, layer (or film), region, pad, or pattern, or one or more intervening layers may also be present. Further, on or under of each layer is determined based on the drawing.

The thickness and size of each layer shown in the drawings can be exaggerated, omitted or schematically drawn for the purpose of convenience or clarity. In addition, the size of elements does not utterly reflect an actual size.

Hereinafter, a PCB according to the embodiment will be described with reference to FIG. 10.

Referring to FIG. 10, the PCB according to the embodiment includes an electric element 40, an insulating layer 50 including first and second

insulting layers

51 and 52 surrounding a top surface, a bottom surface and lateral sides of the electric element 40, a first circuit pattern 91 formed on the insulating layer 50, and a bump 30 electrically connecting the electric element 40 with the first circuit pattern 91.

The insulating layer 50 surrounding the top surface, the bottom surface and the lateral sides of the electric element 40 may be formed by using single material.

The first circuit pattern 91 has a first surface making contact with the insulating layer 50. The first surface of the circuit pattern 91 may be in contact with both insulating layer 50 and bump 30.

In addition, an interconnection layer 60 can be formed in the insulating layer 50.

An oxide layer can be formed on a contact surface of the first circuit pattern 91 that makes contact with the insulating layer 50.

In this manner, the insulating layer 50 surrounds the top surface, the bottom surface and the lateral sides of the electric element 40, so that the electric element 40 can be easily installed in the PCB and the electric element 40 can be protected from external environment without forming an additional protective layer.

Hereinafter, the PCB and the method of manufacturing the same according to the embodiments will be described in detail with reference to FIGS. 1 to 14.

Referring to FIG. 1, a carrier 20, an adhesive layer 21 formed on the carrier 20, a second metal layer 12 formed on the adhesive layer 21, and a first metal layer 11 formed on the second metal layer 12 are prepared.

The first metal layer 11 can be bonded to the second metal layer 12 to the extent that the first metal layer 11 can be easily separated from the second metal layer 12.

The first metal layer 11 may have a thickness of about 3㎛ to 20㎛.

The first metal layer 11 and the second metal layer 12 can be formed by using the same material or different materials. For instance, the first metal layer 11 and the second metal layer 12 may include at least one of Cu, Sn, Al, Ni, Au, or Ag.

The carrier 20 may include a metal or resin to support the first metal layer 11 and the second metal layer 12.

The adhesive layer 21 may include adhesive material, such as prepreg, epoxy resin or phenol resin.

Referring to FIG. 2, the carrier 20, the adhesive layer 21 and the first and

second metal layers

11 and 12 are press-bonded with each other.

Referring to FIG. 3, a photoresist pattern 25 is formed on the first metal layer 11.

The photoresist pattern 25 is used to form the bump 30 in the subsequent process. The photoresist pattern 25 may be formed corresponding to the bump 30 through a photography process.

Referring to FIG. 4, the bump 30 is formed by using the photoresist pattern 25 as a mask.

The bump 30 can be formed through a plating process, such as an electroless plating process and an electro plating process.

The bump 30 has a uniform thickness in the range of 10㎛ to 30㎛. The thickness of the bump 30 may vary depending on applications. Since the bump 30 has the uniform thickness, the electric element can be prevented from being slantingly bonded to the bump 30, so that the electric element is prevented from being damaged.

The bump 30 may include a metal. For instance, the bump 30 may include one of Cu, Sn, Au, Ag, Ni or an alloy thereof.

In addition, the bump 30 may include first and second layers. The first layer may include material different from that of the second layer. For instance, the first layer may include at least one of Ni, Cu, or Sn, and the second layer may include at least one of Au, Ag, or Ni.

The bump 30 can be plated, for example, with Au.

If the bump 30 includes a specific metal, such as Au, SMT (surface mounting technology) equipment may detect the bump 30. Thus, the electric element can be bonded to the bump 30 by using the SMT equipment.

Referring to FIG. 5, an adhesive material 35 is formed on the bump 30 to bond the electric element to the bump 30. For instance, the adhesive material 35 includes a solder ball, a conductive paste or a nonconductive paste.

An oxide layer (not shown) can be formed on the first metal layer 11 through the oxidation process.

In the case that the adhesive material 35 includes the solder ball, the oxide layer prevents the solder from being leaked when the electric element is bonded to the bump 30. That is, the solder is prevented from being leaked due to the surface property of the oxide layer.

Since the solder is not leaked, the short between the electric element and a circuit pattern, which will be formed later, can be prevented so that reliability of the PCB can be improved.

Meanwhile, a mask layer (not shown) can be formed between the bump 30 and the first metal layer 11 to deal with the leakage of the solder.

Referring to FIG. 6, the electric element 40 is bonded to the bump 30.

The electric element 40 may include an active element, such as a silicon chip, or a passive element, such as a resistor, an inductor or a capacitor.

As described above, the adhesive material 35 is formed between the electric element 40 and the bump 30 to securely fix the electric element 40.

Since the electric element 40 is bonded to the bump 30, a gap 45 may be formed between the electric element 40 and the first metal layer 11.

The gap 45 has a size corresponding to the thickness of the bump 30. For instance, the gap 45 has a size of about 10㎛ to 30㎛.

The subsequent processes performed on the electric element 40 and the first metal layer 11 will be described in first and second embodiments.

(First embodiment)

Hereinafter, the first embodiment will be described in detail with reference to FIGS. 7 to 10.

Referring to FIG. 7, the first insulating layer 51 is formed on the first metal layer 11 as shown in FIG. 6 to surround the electric element 40 and the interconnection layer 60 is formed on the first insulating layer 51. Then, the second insulting layer 52 is formed on the interconnection layer 60 and the electric element 40 and a third metal layer 70 is formed on the second insulting layer 52.

The first insulating layer 51, the interconnection layer 60 and the second insulting layer 52 may have a multi-layer structure, respectively.

In addition, the first and second insulating

layers

51 and 52 can be prepared in a semi-cured (B-stage) state.

The interconnection layer 60 may include a third insulating layer 62, third circuit patterns 61 formed on both surfaces of the third insulating layer 62, and a conductive via 63 for electrically interconnecting the third circuit patterns 61 formed on both surfaces of the third insulating layer 62.

The first to third insulating

layers

51, 52 and 62 can be formed by using the same material. For instance, the first to third insulating

layers

51, 52 and 62 can be formed by using resin material, such as epoxy resin or phenol resin. In addition, the first to third insulating

layers

51, 52 and 62 can be formed by using prepreg, a polyimide film, or an ABF film.

The third metal layer 70 may include at least one of Cu, Sn, Al, Ni, Au, or Ag.

Referring to FIG. 8, the first insulting layer 51, the interconnection layer 60, the second insulating layer 51 and the third metal layer 70 are press-bonded onto the first metal layer 11 and the electric element 40.

As a result, the insulating layer 50 including the first and second

insulting layers

51 and 52 may surround the top surface of the first metal layer 11 as well as the top surface, the bottom surface and the lateral sides of the electric element 40. In addition, the interconnection layer 60 is formed in the insulating layer 50 to surround the lateral sides of the electric element 40.

In particular, the gap 45 formed between the electric element 40 and the first metal layer 11 due to the bump 30 during the press-bonding process is filled with the first insulting layer 51 as indicated by reference numeral 55, so that the first insulating layer 51 may be formed at the bottom surface of the electric element 40.

Since the first insulating layer 51 is formed at the bottom surface of the electric element 40, the electric element 40 is not exposed to the outside so that the electric element 40 can be prevented from being damaged by external environment. In addition, the electric element 40 can be protected by the first insulating layer 51 without forming an additional protective layer, so that the PCB may have a thin thickness.

The first insulating layer 51 formed at the bottom surface of the electric element 40 may have the thickness equal to or larger than the thickness of the bump 30 because the adhesive material 35 can be formed on the bump 30.

Referring to FIG. 9, if the electric connection is necessary between the interconnection layer 60 and the first metal layer 11 or between the interconnection layer 60 and the third metal layer 70, a second conductive via 80 can be formed.

At this time, the carrier 20, the adhesive layer 21 and the second metal layer 12 can be removed. As mentioned above, the first metal layer 11 is bonded to the second metal layer 12 to the extent that the first metal layer 11 can be easily separated from the second metal layer 12, so the carrier 20, the adhesive layer 21 and the second metal layer 12 can be easily removed.

As the carrier 20, the adhesive layer 21 and the second metal layer 12 have been removed, the second conductive via 80 or the circuit pattern can be easily formed so that the degree of freedom for circuit design can be improved.

In order to form the second conductive via 80, a via hole (not shown) is formed through the first insulating layer 51 and the first metal layer 11 or the second insulating layer 52 and the third metal layer 70 by the laser drilling process and the plating process is performed with respect to the via hole.

Referring to FIG. 10, the first and

third metal layers

11 and 70 are selectively removed to form the first and

second circuit patterns

91 and 92.

In order to form the first and

second circuit patterns

91 and 92, a photoresist pattern (not shown) is formed on the first and

third metal layers

11 and 70 and then the first and

third metal layers

11 and 70 are etched by using the photoresist pattern as a mask.

After that, a solder mask and a solder ball are formed on the first and

second circuit patterns

91 and 92 according to the circuit design of the PCB so as to connect the PCB with other circuits, elements or substrates.

(Second embodiment)

Hereinafter, the second embodiment will be described in detail with reference to FIGS. 11 to 14.

Referring to FIG. 11, an insulating layer 100 is formed on the first metal layer 11 and the electric element 40 as shown in FIG. 6 and a third metal layer 110 is formed on the insulating layer 100.

The insulating layer 100 may include a first insulating layer 101 formed on the first metal layer 11 to surround the electric element 40 and a second insulating layer 102 formed on the first insulating layer 101 and the electric element 40.

The first and second insulating

layers

101 and 102 may have a multi-layer structure, respectively.

In addition, the insulating layer 100 can be prepared in a semi-cured (B-stage) state.

The insulating layer 100 can be formed by using resin material, such as epoxy resin or phenol resin. In addition, the insulating layer 100 can be formed by using prepreg, a polyimide film, or an ABF film.

The third metal layer 110 may include at least one selected from the group consisting of Cu, Sn, Al, Ni, Au, or Ag.

Referring to FIG. 12, the insulting layer 100 and the third metal layer 110 are press-bonded onto the first metal layer 11 and the electric element 40.

As a result, the insulating layer 100 may surround the top surface of the first metal layer 11 as well as the top surface, the bottom surface and the lateral sides of the electric element 40.

In particular, the gap 45 formed between the electric element 40 and the first metal layer 11 due to the bump 30 during the press-bonding process is filled with the first insulting layer 101 as indicated by reference numeral 56, so that the insulating layer 100 may be formed at the bottom surface of the electric element 40.

Since the insulating layer 100 is formed at the bottom surface of the electric element 40, the electric element 40 is not exposed to the outside so that the electric element 40 can be prevented from being damaged by external environment. In addition, the electric element 40 can be protected by the insulating layer 100 without forming an additional protective layer, so that the PCB may have a thin thickness.

The insulating layer 100 formed at the bottom surface of the electric element 40 may have the thickness equal to or larger than the thickness of the bump 30 because the adhesive material 35 can be formed on the bump 30.

Referring to FIG. 13, if the electric connection is necessary between the first and

third metal layers

11 and 110, a conductive via 120 can be formed.

As the carrier 20, the adhesive layer 21 and the second metal layer 12 have been removed, the conductive via 120 or the circuit pattern can be easily formed so that the degree of freedom for circuit design can be improved.

In order to form the conductive via 120, a via hole (not shown) is formed through the insulating layer 100, the first metal layer 11 and the third metal layer 110 by the laser drilling process and the plating process is performed with respect to the via hole.

Referring to FIG. 14, the first and

third metal layers

11 and 110 are selectively removed to form first and

second circuit patterns

131 and 132.

In order to form the first and

second circuit patterns

131 and 132, a photoresist pattern (not shown) is formed on the first and

third metal layers

11 and 110 and then the first and

third metal layers

11 and 110 are etched by using the photoresist pattern as a mask.

After that, a solder mask and a solder ball are formed on the first and

second circuit patterns

131 and 132 according to the circuit design of the PCB so as to connect the PCB with other circuits, elements or substrates.

Although the exemplary embodiments of the present invention have been described, it is understood that the present invention should not be limited to these exemplary embodiments but various changes and modifications can be made by one ordinary skilled in the art within the spirit and scope of the present invention as hereinafter claimed.

The embodiments are applicable to the PCBs and the method of manufacturing the same.

Claims

A printed circuit board comprising:

an electric element;

an insulating layer surrounding a top surface, a bottom surface and lateral sides of the electric element;

a circuit pattern over the insulating layer; and

a bump electrically connecting the electric element with the circuit pattern.
The printed circuit board of claim 1, wherein the insulating layer surrounding the top surface, the bottom surface and the lateral sides of the electric element is formed by using single material.
The printed circuit board of claim 1, further comprising an interconnection layer formed in the insulating layer.
The printed circuit board of claim 1, wherein the bump has a thickness of 10㎛ to 30㎛.
The printed circuit board of claim 1, wherein the bump includes at least one of Cu, Sn, Au, Ag, or Ni and has first and second layers, in which the first layer includes at least one of Ni, Cu, or Sn, the second layer includes at least one of Au, Ag, or Ni, and the first layer includes material different from material of the second layer.
The printed circuit board of claim 1, wherein an oxide layer is formed on a contact surface of the circuit pattern that makes contact with the insulating layer.
A method of manufacturing a printed circuit board, the method comprising:

preparing a first metal layer;

forming a bump on the first metal layer;

bonding an electric element onto the bump;

forming an insulating layer to surround a top surface of the first metal layer and a top surface, a bottom surface and lateral sides of the electric element, and forming a third metal layer on the insulating layer; and

forming a circuit pattern by selectively removing the first and third metal layers.
The method of claim 7, wherein the insulating layer surrounding the top surface, the bottom surface and the lateral sides of the electric element is formed by using single material.
The method of claim 7, wherein an interconnection layer is formed in the insulating layer.
The method of claim 7, further comprising forming an oxide layer by oxidizing a surface of the first metal layer after forming the bump on the first metal layer.
The method of claim 7, wherein the bump has a thickness of 10㎛ to 30㎛.
The method of claim 7, wherein the bump includes at least one of Cu, Sn, Au, or Ag, and has first and second layers, in which the first layer includes at least one of Ni, Cu, or Sn, the second layer includes at least one of Au, Ag, or Ni, and the first layer includes material different from material of the second layer.
The method of claim 7, wherein the insulating layer is formed by pressing a B-stage insulating layer such that the insulating layer is filled between the first metal layer and the electric element.