WO2012013690A1

WO2012013690A1 - Line current waveshaping

Info

Publication number: WO2012013690A1
Application number: PCT/EP2011/062856
Authority: WO
Inventors: Seamus O'driscoll; Peter Meaney
Original assignee: Texas Instruments (Cork) Limited
Priority date: 2010-07-26
Filing date: 2011-07-26
Publication date: 2012-02-02
Also published as: EP2599204A1; GB201012469D0

Abstract

The invention provides an AC line power converter comprising a regulation control loop to effect said regulation including means for generating a shaping signal, said shaping signal being substantially periodic at line frequency or harmonics thereof and summing means for introducing the shaping signal to the regulation control loop together with an error signal or control of said regulation control loop, whereby said shaping signal shapes the line current drawn by said converter within said period. The shaping waveform provides corrections for errors and unwanted behaviours and can be varied between cycles. Selection of a shaping waveform permits trade-off between parameters to meet performance goals at points in the operating envelope of the converter.

Description

LINE CURRENT WAVESHAPING

This invention relates to power converters and adapters and in particular provides improvements in various associated operating parameters, such as power factor, efficiency and distortion. For example in the area of external power supplies, such as computer notebook adapters, there is a requirement to maximize efficiency to achieve the highest possible power densities in spite of thermally challenging heat dissipation capabilities.

A known method for power factor correction (PFC) employs a multiplier inserted to the control loop of a converter for injection of a line phase sine reference or even a reference derived from measurement of the supply line voltage itself. Lower cost techniques operate without such a reference and exploit an inherent aspect of some simpler control scheme, such as the inherent line current shaping which occurs for discontinuous conduction mode (DCM) operation with a very low bandwidth outer voltage error loop.

Unfortunately a PFC scheme implemented for good performance under typical load conditions may be found wanting in other areas, for example at light load (with the powered appliance in a standby mode) and no-load with the appliance disconnected. These extremes of the problems may be tackled by entering alternative control regimes aimed principally at meeting ever reducing the dissipation specified for such special cases. However, this adds to the complexity and cost (another parameter which is specified ever lower) and becomes impracticable if two many special cases exist. Electronic equipment increasing include control regimes intended to minimise own power consumption for efficiency. Operating in this manner, however, can transfer the efficiency problem to the power supply or converting adapter since it must itself now cope with a varying load demand. The task of applying power factor and other corrections is now more complex and the present invention addresses such issues. Of course, supplying electrical equipment that presents a varying load is far from a new problem since such equipment is ubiquitous (including virtually anything with a motor), so that it is hoped that the principles set forth here may assist with the supply of such equipment as well.

The present invention provides apparatus and method as set forth in the claims.

In particular, the invention provides in one aspect thereof an AC line power converter comprising a regulation control loop to effect said regulation including means for generating a shaping signal, said shaping signal being substantially periodic at line frequency or harmonics thereof and means for introducing the shaping signal to the regulation control loop together with an error signal or control of said regulation control loop, whereby said shaping signal shapes the line current drawn by said converter within said period.

Moreover in another aspect thereof the invention provides an AC line power converter comprising a regulation control loop and in in ner PWM loop to effect said regulation including means for generating a shaping signal, said shaping signal being substantially periodic at line frequency or harmonics thereof and means for introducing the shaping signal to the regulation control loop together with an error signal of said regulation control loop, whereby said shaping signal shapes the line current drawn by said converter within said period such that predetermined shaping is applied to said line current during portions of said period, said predetermined shaping being variable from one portion to another and selected from a plurality of predetermined shaping portions on the basis of a prevailing regulation mechanism occurring within that portion, there being a plurality of such predetermined shaping signal portions for each of a number of different operating regimes of said converter, the plurality of predetermined shaping signal portions from which the predetermined shaping is selected being determined by said operating regime.

Typically, voltage regulating PFC converters operate with a low bandwidth outer loop to control regulation and a higher bandwidth inner loop to control a PWM arrangement to effect the regulation. ln accordance with an aspect of the present invention a waveshape modifier is added into the loop. This modifier is used to adjust the shape of the line current that would otherwise occur as a result of the particular choices of controller parameters made for a particular converter, such as voltage mode and current mode control loop gains. The application of the modifier is synchronise to the line voltage or current. The modifier may be used to enhance or optimise any or all of Efficiency, Power Factor ( PF) or com pensate for other circuit featu res wh ich m ight i ntroduce distortion or displacement. In order to accommodate a specified requirement or for overall optimisation, performance with regard to one parameter maybe traded-off against that with regard to another; importantly, the applied modification may be varied with operating conditions such as rms line voltage or load. This may occur either during a line cycle or on a per line cycle basis.

For the pulse width modulated (PWM) converter, the modifier may conveniently be introduced into the error signal path of the outer voltage loop of the PWM regulator.

What the invention achieves in one aspect thereof is modification to the main switch drive waveform applied to the main switching device that gates power to a load supplied by a converter. The modifier may be configured, for example not to gate through PWM drive pulses to the main switch during certain phases of the line cycle period. For example, the line current conduction angle may be limited by not allowing any power conversion to occur in regions close to the AC line voltage zero crossings. There may be very little available power to be transferred during these regions and so to maximise efficiency power switching is not performed. However, minimising the conduction angle would introducing some distortion and therefore be deleterious in that regard. Nonetheless, the present invention enables such a trade off to be available to the converter designer. Efficiency in terms of conduction angle (drawing line current only at higher or optimum regions of the line voltage) occurs naturally for limited conduction angle PFC topologies such as Buck; with the invention it may be applied to full conduction angle topologies such as Boost to create this advantage. Moreover, the application may be selective and dependent upon load conditions. Thus this invention pertains to the addition of a predetermined wave-shape which may be selected to optimise for a chosen set of criteria. The requirement might be to maximise efficiency in a thermally challenging application, subject to meeting minimum PF acceptability requirements. In PFC for a boost converter, for example, efficiency may be maximised for a line current shape that is non- true sinusoid, such as in the sine² example discussed below. The idea is to adjust control to provide a line current waveshape which is optim ised for highest overall efficiency, subject to meeting acceptable Power Factor (PF) and Total Harmonic Distortion (THD) standards. By contrast, traditional Power Factor Correction is applied from the perspective of maximizing PF and attempting to reduce THD. Now such regimes may be selectively available in a single controller and applied dependent upon load conditions or other selection criteria that are application specific.

It is a nticipated that, whilst the modifier may be generally specified provided the attributes described above, elements of the waveshape modifier may be derived to provide circuit specific waveshaping. For example, a waveshape modifier element may be applied to correct for a distorting or displacing attribute, such as bus capacitor ripple that might occur under certain operating regimes and thereby effect both an improvement in PF and efficiency. The modifier may even be used exclusively for such a purpose.

The invention is appropriate to any Power Factor Correction topology although different wave-shape modifiers will be required according to choice of methodology and modes and mode sequences in which it used. A discontinuous conduction (DCM) or Quasi Resonant (QR) Boost will have a different optimization to a Continuous Conduction Mode (CCM) Boost, for instance. As well as controlling where conduction currents are distributed, the invention may also be used to control the regions where power switching occurs and thereby reduce switching loss or circulating resonant energy loss as typically occurs with during switching cycles of low significant energy transfer.

It is anticipated that in particular, single stage combined power-factor-correction and output- voltage-regulation circuits could be greatly improved by the techniques of the present invention. ln order that features and advantages of the present invention may be further appreciated exemplary embodiments will now be described with reference to the accompanying diagrammatic drawings, of which:

Fig. 1 shows a prior art control scheme for a boost converter;

Fig. 2 shows the PWM modulator and Boost Converter of Fig. 1 in more detail;

Fig.3 shows waveforms associated with Fig. 2;

Fig 4 represents waveforms associated with Fig.l;

Fig. 5 shows a control scheme for a boost converter in accordance with the present invention.

Fig. 6 shows an exemplary shaping waveform;

Fig. 7 shows waveforms associated with Fig. 5;

Fig. 8 represents waveforms from a realisation of the embodiment of Fig.5 using

substantially the shaping wave form of Fig.6;

Fig. 9 represents an alternative embodiment of the invention;

Fig. 10 represents a further alternative embodiment of the invention; and

Fig.ll shows an alternative shaping waveform.

Many types of power converter are known but in a typical arrangement line voltage will be rectified to a nominal dc intermediate voltage that is not regulated to the accuracy or bandwidth required by the load. The intermediate voltage is switched to supply a load with current such that the supply voltage is regulated. Energy is supplied to the load via a switch that feeds an inductive element. The switch-inductor combination supplies energy to the load: if the voltage falls below its regulated value, the switch is turned on to increase supply, conversely if the output is above its regulated value, the switch may be turned off. As it well known, In order to make this intermittent switching periodic at a relatively high frequency where the efficiencies of the inductive configuration may be exploited, the switching is subjected to pulse width modulation (PWM) wherein switching occurs every PWM cycle: the switch being kept on for a relatively longer time if supply is demanded and a relatively shorter time (or not at all) if it is not. The regulated voltage is smoothed by a capacitor which can also supply the load at times when no energy is available from the switch-inductor combination. At times only the inductor supplies the load. It is common for the inductive element to be arranged as part of a transformer or with a transformer so that the load is electrically isolated from line mains supply.

For a buck type topology no line current can be drawn at times during the line cycle when the supply voltage is below the intermediate voltage. Hence a low intermediate voltage implies better inherent power factor since line current may be drawn over more of the line cycle and more closely follow the line voltage in magnitude as a consequence. Lower intermediate voltage however can result in higher current to a second stage and hence lower overall efficiency. On the other hand, regulating to a voltage that is below the intermediate voltage (buck configuration) may lead to a simpler design with lower stressed components and may well be the design choice even though the intrinsic power factor is worsened. There are numerous circuits for both boost and buck configurations that are known, and indeed combinations of the two. Boost PFC by contrast can generally have good power factor but will tend to have lower PFC stage efficiency when boosting from a lower line voltage situation. Also the higher intermediate voltage may result in higher switching losses in a second switching stage due to the higher step down ratio. This shows that there are a great number of trade-offs to be made by the converter designer and so the more the deleterious effect of a particular choice that can be ameliorated (such as with the present invention) the better.

Figure 1 below shows a typical control system model that may be employed for a Boost Power Factor Correction power converter stage for example implementing an Average Current Mode Control inner loop. Average current mode control is a well known control method whereby good control over the average value of current is achieved in the presence of variations in supply voltage or operating condition. Since it is not the purpose of Figure 1 is to show details of the converter circuitry itself, this is represented in the model by a PWM Generation and Boost Converter block 1 having two inputs and two outputs. The outputs are the inductor current and the output voltage, both of which are customarily measured or deduced in order to provide regulating control. The inputs are the intermediate voltage (Vdcinst) and a control signal Ctrl indicating supply demand, or not. It is this signal to which the block responds for example to increase PWM duty cycle. Vdcjnst is derived by applying the sinusoidal mains line input voltage 8 to a rectifier 9, modelled as an absolute value ( | u | ) block.

The inductor current, IL, being one of the outputs from the PWM Generation and Boost Converter block 1 is shown as the inner loop direct feedback quantity but in practice it could be any proxy that may be used to create a representation of the inductor or line current. For example, the power switch current during an on time might be passed through a current sense resistor or a current transformer and used in a scheme to synthesise the inductor current during both on switch on and switch off times. The power converter may operate in continuous, discontinuous mode or transition mode. Discontinuous conduction mode refers to the steady state operating condition whereby all of the inductor energy transfers to the output capacitor during each converter switching cycle. The inductor current will therefore decay to zero during each power switch off-time and build from zero during each power switch on-time. Continuous mode conduction here refers to the operating cond ition whereby the inductor current does not fully decay to zero during the off-time and therefore builds from a bias level during each on-time. Transition mode refers to the boundary between continuous and discontinuous modes. These terms are commonly used in the power supply field. An average current mode inner loop is used as an example but again the inner current loop may be of a variety of types, such as peak current mode or hysteretic. Peak current mode control is again a well known current control method and refers to the case where the switch on time is terminated in each switching cycle when the controlled instantaneous current reaches a trip point which is determined by an "outer control loop", Hysteretic current mode control refers to a control scheme whereby an instantaneous current is controlled to ramp up to one trip point and decay until a second trip point is reached. The variations of the embodiment described here will also be valid for single loop control schemes, such as cases where there is an outer Voltage mode control loop only. The Average Current Loop Compensated Error Amplifier 2 depicted has a DC gain of about 36dB and a pole at approximately 800Hz, followed by a zero above 10 KHz. in this case the zero is shown as being set at 47 KHz. The overall objective here is to have to have reasonably high DC gain to minimise steady state error, have filtering action above 800Hz to remove switching current ripple from the demand signal to the PW modulator, provide reasonable bandwidth and provide disturbance rejection for input filter voltage variations. The zero will satisfy stability requirements and provide a degree of instantaneous peak current feed-through to the modulator to offer some of the cycle by cycle benefit of peak current mode schemes. This compensated amplifier would be typical for analogue average current loops implemented in PFC systems.

There is an outer voltage loop with a compensated amplifier 3 to give good stability and a voltage loop crossover somewhere in the range 5Hz to 15Hz. This is to filter out line frequency fundamental and 2^nd harmonic ripple, as is well known in the art of PFC. The compensated amplifier in block 3 implements an integrator to remove loop steady state error and is given by the denominator s term. There is a zero implemented at 20 radians/ second or 3.18Hz to provide phase boost around the region of outer loop crossover and a further pole at 117 radians/ second (18.6 Hz) to filter out higher frequency noise at frequencies above loop crossover. This compensation will be typical for a PFC outer voltage loop. The output of the compensated amplifier 3 is essentially a steady demand level to satisfy the closed loop requirement for the DC output voltage set-point, which here is modelled by normalised value, Vonom, at 4 in Fig. 1 having a value of 1. As shown, the error signal for the compensated amplifier 3 is derived by subtracting a normalised version of the actual output voltage presently provided by the output of the PWM Generation and Boost Converter block 1, i.e. the voltage sensed across the load.

This steady compensated amplifier output, "Vcomp", is modulated by a reference shape, in a feedforward fashion, to shape the line current such that it will be sinusoidal or follow a replica of the AC line voltage. Either of these schemes may be used with a view to maximise power factor. Thee modulation is modelled by multiplier 5, which receives both the reference shape and Vcomp.

Figure 1 shows a scheme whereby the current shape should follow a replica of the AC line voltage. The instantaneous rectified line voltage, Vdcjnst is divided by Vacrms² derived from block 6 to give a current modifier 7, which will also support achieving constant power over line voltage variation, such as over 80VAC to 264VAC . Figure 1 depicts a scheme which may be thought of as representing the sate of the art in PFC control. The instantaneous voltage divided by Vacrms essentially provides a reference shape and the further division by Vacrms lim its the dynamic range required at the compensator output (block 3 in Figure 1), Vcomp, to cater for variations in input line voltage. This is standard technique. Generally Vacrms is derived from a heavily filtered sense on the line voltage.

The PWM Generation and Boost Converter Power stage will now be considered in more detail but are in accordance with the prior art. Figure 2 depicts the block diagram including a PWM modulator stage 20 creating a PWM signal for a power switch in a basic boost topology and has inputs and outputs which correspond to those of the PWM Generation and Boost Converter block 1 of Fig.l. This is fed to the Boost Converter Block 21 which here represents a basic boost converter providing a power current through the boost inductor. This current, minus a quantity which flows to the load, "Ro", is represented as feeding into Impedance of the smoothing (Boost) capacitor (Zcap 22) to create an output voltage, "Vo". The portion of inductor cu rrent which flows to the load is represented by the output voltage feeding a load admittance or in this case conductance; the reciprocal of Ro.

Figure 3 shows the waveforms for the basic PWM modulator of Fig 2, comprising a sawtooth ramp, "PWM_RAMP" (Fig. 3(b)), a modulating control signal, "Ctrl" (Fig. 3(a)) and a PWM output drive, "PWM Signal" (Fig. 3(c)). An example of a PWM signal with 70% duty signal is shown.

Figure 4 shows all of the key waveforms. Figure (4a) shows inductor current 40 and filtered line current 41. For the inductor current the transition between discontinuous and continuous conduction modes can be easily seen and occurs, for instance at a time a little greater than 0.022 seconds. Figure (4c) shows the output 45 of the current loop compensator, "Ctrl", (output of Block 2, Figure 1). Throughout most of the power transfer region it can be seen that this quantity is relatively constant and varies around 0.8 for the conditions shown. This wi!! correspond to a fairly constant duty cycle demand. The instantaneous voltage is however varying through the line cycle and will have corresponding varying volts-seconds applied to the inductor during the power switch on-times. The off-time volts seconds is however relatively constant because of the controlled fixed output voltage and the relatively constant duty cycle. Unequal volts-seconds between on and off-times creates the varying inductor current and for the case shown creates the transitions between discontinuous (DCM) and continuous (CCM) conduction modes.

Figure (4b) shows the voltage at the current sense feedback, "Vlsense"

Figure (4c) shows the Current loop error, "le" and the output 45 of the current loop compensator, "Ctrl". This is also the modulating input signal for the PWM generator.

Figure (4d) shows the output voltage and its ripple 46, "Vo". The inductor current approximately varies with sinusoidal shape and generally the application load on the power factor correction stage will be fairly constant. There is therefore an approximately sinusoidal difference in transfer and load current which must be smoothed by the PFC output capacitor, This capacitor will have finite capacitance value and a practical capacitor will have series resistance. The finite capacitance and resistance will therefore result in some voltage ripple.

Figure (4e) shows the voltage loop error, "Me", and the multiplying in reference shape, derived from "Vdc_inst"; this is the rectified sinewave 42. "Vcomp" 43 shows the steady output from the voltage loop compensator. Figure 5 shows a block diagram for a control system in accordance with the present invention. The block diagram for figure 5 is substantially similar to that for figure 1 but instead of deriving a sine reference from a scaled version of "Vdc_inst", a table look-up block is implemented in the Waveshape block. This block is synchronised with the line zero crossings and as Vac progresses through the line cycle, time indexed values are chosen from a table of feed forward values. Hence Fig. 5 includes a synchroniser 50 to synchronise the look up table 51 read out with the line input and an optional selector 52 to select which of a number of wave forms stored as look up tables is to be used dependant upon parameters measured around and within the converter. Otherwise the operation of the embodiment of Fig. 5 corresponds to that of the arrangement of Fig. 1.

The embodiment may appear such that the reference shape feed forward system generates an arbitrary waveshape, but in fact the shape may now be selected for desirable properties throughout the cycle according to the problems being solved or the parameters being optimised.

For example, the designer may choose to use a sine² sinusoidal shape with a view to decreasing conduction losses, thereby increasing efficiency, at the expense of degraded power factor. Some applications, such as thermal dissipation challenged adaptor power supplies, will benefit from increased efficiency for a small degradation in Power Factor. Separately, however, such waveshaping may be used to counteract other inherent distortion effects and actually reclaim lost power factor as a result of these distortions. There can be efficiency benefit for comparable power factor.

To illustrate how distortion may corrected with the waveshaping modifier the influence of output capacitor voltage ripple on line current for a basic mode voltage controlled buck is examined and corrected. A simple control scheme, such as basic Voltage mode control may be enhanced with wave shaping to give superior performance. Figure 12 shows a line current for a Buck converter operating at fixed duty cycle. A low bandwidth voltage mode controller on this converter would set the appropriate duty cycle to maintain the desired output voltage according to line and load. The duty cycle for this could be modified by the additive modifier waveshape as in Figure 13, Segments A and F preposition the duty command to be large to maximise the current ramp when the instantaneous line voltage exceeds the buck output capacitor voltage and thereby maximise the conduction angle for Buck topology PFC, B and E build the current to an appropriate shape during the shallow slope regions of discontinuous conduction. Different slopes in the C and D portions are to counteract the natural distortion which will arise due to the bulk capacitor voltage ripple. As the cycle progresses through time region C the bulk capacitor is charging and naturally begins to limit the current magnitude through time region D. This current in region D can be compensated for by adding a smaller magnitude negative modifier waveshape per segment D. Segments C and D are generally negative to compensate for the region of larger continuous mode current in this example illustrated.

Figures 6a and 6b show the sine² reference shape being applied to the boost converter. Table 1 below shows some of the table entries, with sampling interval every 40us. Note that waveforms for 50Hz (10ms half line cycle are depicted for example). The table entries here represent the sine² shape but with some entries about the line voltage zero crossings made equal zero. This is to eliminate loss in regions where power would not be transferred efficiently.

Time Value

0 0

40E-6 0

80E-6 0

120E-6 0.002358

160E-6 0.004191

200E-6 0.006545

240E-6 0.009419

280E-6 0.013

320E-6 0.017 The waveforms in Figure 7 should be contrasted with those in figure 4. Figure 7(e) shows the waveshape modifier, "Mult In Shape". This will correspond to the signal "Shape Reference" in figure 5. The waveform 72 in Figure 7(e) shows a sine² shape with its magnitude adjusted for comparable energy transfer to a sine shape. The table entries with deliberately zero'ed values to occur about the line voltage zero crossings and prevent against wasted switching and parasitic component resonant circulating current energies are shown at the 40E-6 and 80E-6 time values in the table, !t will often be appropriate to zero more of these values.

Figure (7a) shows inductor current 70 and filtered line current 71. The line current, 71, will be seen to be suppressed more around the zero crossings and achieves a greater magnitude at its peak, about 2,4 amperes by contrast with that for the line current 41 shown in figure 4(a), where it reaches about 2 amperes at peak. Figure (7b) shows the voltage on the current feedback. This is shown to peak at around 0.07 and is again a little higher than that in figure (4b). This will be commensurate with the higher peak in the waveshape modifier. Figure (7c) shows the output 75 of the block labelled "Compensated Amplifier for Average Mode Current Loop" in figure 5, "Ctrl". Figure (7c) will have subtle differences to figure (4c), particularly during the region of continuous mode conduction, because of the relatively high gain of the system during CCM . There will be more easily visible differences between figure (7c) and figure (4c) in the regions of DCM, close to the line voltage zero crossings.

Figure 7d shows the output voltage and its ripple 76, "Vo". Figure (7e) shows the voltage loop error 73, "Ve" in figure 5. Similarly with 43 in figure 4(e), this will be close to zero due to the integrating action of the "Voltage Loop Amplifier and Compensation" block in figures 1 or 5.

It will be appreciated that there may be different shapes selected from multi-dimensional tables, to have an optimised reference shape for any number of given operating points, such as line voltage, frequency or load. Interpolation techniques on the shapes may be chosen for intermediate operating conditions.

The modifying waveshapes shown as 72 in Figure 7(e) & 42 in Figure 4(e) are illustrative for 50Hz operation. This corresponds to 20 milliseconds line period. For other frequencies, such as 60Hz (16.66ms period) it will be appreciated that we may select another table of values or we may chose to modify the rate at which the table values in the second column are sampled. For the table above, we could chose to sample at 33.3E-6 seconds, instead of the 40E-06 seconds for 50Hz.

For major steps in different operating conditions, such as average toad current or different rms line voltage there will be different optimum sets of waveshape modifier values and as such multidimensional tables may be appropriate.

For smooth transition between operating conditions it will be appropriate to interpolate table waveshape modifier values for intermediate operating conditions or else to implement a smoothing function (such as filtering by integration) when transitioning between different sets of waveshape modifier values.

Table 2 shows results of a system having line synchronised sine² shaping (second row) in accordance with the present invention, compared to the prior art system of Fig. 1 (first row).

TABLE 2

It will be observed that efficiency has been improved at the expense of a trade-off in power factor. Figure represents waveforms obtained from an actual circuit realisation of a line synchronised sine² shaping embodiment of the invention. The traces represent: instantaneous DC voltage 85 which is the rectified and filtered instantaneous line voltage and corresponds to Vdcjnst shown in figure 5, Sine² Demand Reference (look up table read out) with zero values around zero crossings 86. Figure 8(b) is a zoom in on Fig. 8(a) around a line voltage zero crossing: line current 87, switch drive signal 88 and Vdcjnst 89.

An alternative embodiment is shown in Fig. 9.

Figure 10 shows a circuit for implementing waveshaping in accordance with the present invention at an alternative location and by alternative means in the system, the Figure showing how the arrangement of Fig.2 has been modified. Between the PWM signal generation block 80 and the Power Converter 81, there is inserted a block 82 for synchronised and selective blanking of PWM pulses. The blanking waveform shown here is used to suppress switching pulses at the points around the zero crossings where there is very low voltage and consequent low power availability. In many practical converters, such as Boost, this switching results in no real power transfer but creates circulating resonant currents in the resonant circuits formed around the switch capacitance. This causes distortion, degrades power factor and degrades efficiency. By blanking these pulses, such inefficiencies may be reduced. Typically, a well designed PWM regulation scheme will be robust enough to compensate for the missing pulse in other parts of the cycle without further modification. This type of control may be used in conjunction with the waveshaping feedforward into the control loop already described, for example with reference to Fig. 5. and both have been incorporated in the circuit which gave rise to Fig, 8.

In order that features and advantages of the present invention may be further appreciated yet another exemplary embodiment will now be described, this time centred on a Buck type converter to which a shaping waveform WSMOD will be applied. An exemplary algorithm as implemented here is by way of the WSMOD modifier to the usual low cost circuit implementation of a very low frequency outer voltage loop controlling an inner current loop. The waveshaping of the present invention however could be accommodated in any of the other standard control techniques for power factor correction, such as the low THD technique of generating a sine reference (or VAC) shape reference which acts as a multiplier into the error signal of the outer loop.

The algorithm may be implemented over some or all of the line and load range, according to where a performance enhancement is required. Preferably, the algorithm should be phased gradually into the control, particularly for very high gain regions (as occurs for example during continuous conduction mode). This may involve a variable gain on the effect of the algorithm. A normalised wave-shape modifier may for example be phased in according to load. Interpolations could be performed for load and line values between pre-programmed characteristics.

A feature of algorithm robustness is having accurate phasing with respect to line voltage, even in the presence of high distortion or frequency variation. A gradual introduction and release of the waveshape modifier may also be beneficial.

The waveshape characteristic may be based on measured positive or negative conduction angle, instead of line voltage and hence may be based on a switched current measurement. It may therefore not even require a line voltage reference. In this way, it may be made automatically compensating for line frequency change.

The general topography of the circuit of the supply is shown in Fig. 10. WSMOD is summed with the output of the voltage loop integrator 10 at summing point 11 and thereby into the high gain current loop controlling PWM switch 12. The circuit is of the Buck type with an AC line voltage applied that is rectified to an intermediate voltage which is down DC-DC converted to supply the load 12. Regulating switch 12 is controlled to regulate the voltage to the required level as the load varies. WS OD may be stored as values in a look up table clocked to a DAC in phase with the line voltage, although any convenient way of generating the shaping values may be used.

In this embodiment, the waveshaping table consists of 250 bytes and 40μ≤ modifier steps. If digital techniques are employed to generate the current loop control then the algorithm is only a small increment to an 8 bit Real Time Controller, operating at 20μ≤ T_s.

Other non-ideal features such as Line current skew due to smoothing capacitor ripple were compensated for by experimental "tweaking" of table values. In the example of Fig. 11 which shows a waveshape reference to a half line cycle, region B represents predominantly acceleration through discontinuous conduction mode and di/dt limitation in the continuous conduction mode ramp up, region C is a sinsusoidal harmonic modifier and current clamping, in region D the wave form is displaced from a sinusoid to compensate for the effect of capacitor ripple and manage downslope whilst region E prepositions the switch to be ready on for the onset of conduction following region A of the next ha lf cycle. I n situations where the compensation provided by WSMOD is to be introduced, changed or removed progressively it is advantageous to constra in the WSMOD waveform to be of equal area either side of zero.

Yet further improvements may be forthcoming if WSMOD is applied selectively in dependence upon operating conditions or indeed varied in response to changes thereof. For example, it may be applied when the system enters conditions which are known to be a trouble spot in the operating envelop, e.g. low power demand at high line or high power at low line input.

The application of a selected WSMOD may be made for example in response to line voltage, load current, conduction angle or conduction interval.

The wave-shaping algorithm has been implemented on a 300Watt Buck PFC Front End. Low Line PF increased from 0.924 to 0.944 and efficiency increased by 0.5%. Stability and transient response also improved significantly. This unit now exhibits a full load low efficiency of 91.1%, end to end, which exceeds the "80Plus" Gold Standard specification, f http://www.80plus.orgl by almost 4%. Systems with Buck PFC Front End, while achieving very high efficiencies, have suffered from poorer low line power factor. These may now be designed for power factor in the range 0.95 to 0.97.

One important aspect in certain embodiments is that WSMOD is put together with different shapes in different regions. In other words, the control is segmented within the period and different shaping applied dependent upon the prevailing conditions and/or which critical parameter has gone out of spec. Hence, WSMOD is segmented not only within the cycle but between cycles dependent upon prevailing conditions. Thus the look up table is a matrix of two or more dimensions from which predefined WSMOD segments can be chosen, one dimension being position within the cycle and the other being a measured or applied parameter.

More than two dimensions of addressing are possible for the look up table which may be in the form of a multi-dimensional matrix. There could be a temperature dimension, a power factor dimension and a THD dimension, all selected based on a determination of what is critical at the time .

In particular, an embodiment may provide an AC line power converter comprising a regulation control loop and in inner PWM loop to effect said regulation including means for generating a shaping signal, said shaping signal being substantially periodic at line frequency or harmonics thereof and summing means for introducing the shaping signal to the regulation control loop together with an error signal of said regulation control loop, whereby said shaping signal shapes the line current drawn by said converter within said period such that predetermined shaping is applied to said line current during portions of said period, said predetermined shaping being variable from one portion to another and selected from a plurality of predetermined shaping portions on the basis of a prevailing regulation mechanism occurring within that portion, there being a plurality of such predetermined shaping signal portions for each of a number of different operating regimes of said converter, the plurality of predetermined shaping signal portions from which the predetermined shaping is selected being determined by said operating regime. The invention provides an AC line power converter comprising a regulation control loop to effect said regulation including means for generating a shaping signal, said shaping signal being substantially periodic at line frequency or harmonics thereof and summing means for introducing the shaping signal to the regulation control loop together with an error signal or control of said regulation control loop, whereby said shaping signal shapes the line current drawn by said converter within said period. The shaping waveform provides corrections for errors and unwanted behaviours and can be varied between cycles. Selection of a shaping waveform permits trade-off between parameters to meet performance goals at points in the operating envelope of the converter.

Claims

Claims:

1. An AC line power converter comprising a regulation control loop to effect said regulation including means for generating a shaping signal, said shaping signal being substantially periodic at line frequency or harmonics thereof and means for introducing the shaping signal to the regulation control loop together with an error signal or control of said regulation control loop, whereby said shaping signal shapes the line current drawn by said converter within said period.

2. An AC line power converter as claimed in claim 1 wherein the shaping signal is configured to provide maximum converter efficiency subject to Power Factor and Total Harmonic Distortion constraints.

3. An AC line power converter as claimed in claim 1 or claim 2 wherein the shaping signal is applied over a portion of the operating range of said converter.

4. An AC line power converter as claimed in any preceding claim wherein application, change or removal of the shaping signal is gradual.

5. An AC line power converter as claimed in claim 4 wherein the shaping signal is constrained to be of equal area either side of zero.

6. An AC line power converter as claimed in any preceding claim wherein the shaping signal varies with load or line voltage.

7. An AC line power converter as claimed in any preceding claim wherein the shaping signal is selected from a plurality of predetermined shaping signals.

8. An AC line power converter as claimed in claim 7 wherein the shaping signal is interpolated for operating conditions for which no shaping signal has been predetermined.

9. An AC line power converter as claimed in any preceding claim wherein the control loop is a regulation loop of a PWM converter.

10. An AC line power converter as claimed in claim 9 wherein the shaping signal controls the portion of the line cycle in which PWM switching occurs.

11. An AC line power converter as claimed in claim 9, claim 10 or claim 11 wherein the shaping signal varies with conduction angle or conduction interval.

12. An AC line power converter as claimed in any preceding claim wherein shape signal values are stored in a look up table memory.

13. An AC line power converter as claimed in claim 12 wherein the look up table memory is clocked in phase with line voltage and connected to a DAC to generate the shaping signal.

14. An AC line power converter as claimed in claim 12 claims 13 wherein look up table values are normalized to operating conditions before shaping signal generation.

15. The subject matter of this application, or any part thereof, in any novel, inventive or useful combination thereof.

16. An AC line power converter as claimed in any preceding claim wherein the shaping signal is configured to correct for a distorting or displacing attribute of the converter.

17. An AC line power converter comprising a regulation control loop and an inner PWM loop to effect said regulation including means for generating a shaping signal, said shaping signal being substantially periodic at line frequency or harmonics thereof and means for introducing the shaping signal to the regulation control loop together with an error signal of said regulation control loop, whereby said shaping signal shapes the line current drawn by said converter within said period such that predetermined shaping is applied to said line current during portions of said period, said predetermined shaping being variable from one portion to another and selected from a plurality of predetermined shaping portions on the basis of a prevailing regulation mechanism occurring within that portion, there being a plurality of such predetermined shaping signal portions for each of a number of different operating regimes of said converter, the plurality of predetermined shaping signal portions from which the predeterm ined shaping is selected being determ ined by said operating regime.

18. An AC line power converter as claimed in any preceding claim wherein the shaping signal is nonlinear.

19. An AC line power converter as claimed in any preceding claim wherein the means for introducing the shaping signal to the regulation control loop comprises any one from the group of: modulating means, multiplying means and summing means.

20. A method of shaping the AC line current in an AC power converter comprising the steps of: regulating the input line current and output voltage or current by:

generating a shaping signal, said shaping signal being substantially periodic at line frequency or harmonics thereof; and

introducing the shaping signal to a control loop together with an error signal or setpoint of said control loop, whereby said shaping signal shapes the line current drawn by said converter within said period.