WO2012013080A1

WO2012013080A1 - Data transparent transmission method and system

Info

Publication number: WO2012013080A1
Application number: PCT/CN2011/074495
Authority: WO
Inventors: 陆志举
Original assignee: 中兴通讯股份有限公司
Priority date: 2010-07-30
Filing date: 2011-05-23
Publication date: 2012-02-02
Also published as: CN101901199B; CN101901199A

Abstract

A data transparent transmission system and method is disclosed. The system includes a processor, a storage and a logic module. The method comprises the following steps: the logic module is connected with an external interface to receive data transmitted from the external interface, and stores the data transmitted from the external interface in a reception storage unit; the processor inquires the reception storage unit, and acquires the data to be received when inquiring that the data to be received exists in the reception storage unit; and the processor stores the data to be transmitted to the external interface in the transmission storage unit; the logic module inquires the transmission storage unit, and acquires the data to be transmitted and transmits the data to be transmitted to the external interface when inquiring that the data to be transmitted exists in the transmission storage unit. The technical scheme effectively solves the problem of insufficient interface resources in an embedded system.

Description

Method and system for transparent transmission of data

TECHNICAL FIELD The present invention relates to the field of embedded system technologies, and in particular, to a method for transparent transmission of data in an embedded system.

Background technique

With the development of carrier-class devices toward high integration and miniaturization, more and more functions are integrated on a single board in a device, and more and more devices are on a single board, and the number of various types of interfaces required is also more and more. The existing embedded device data transmission method is through Ethernet, Peripheral Component Interconnect (PCI) bus, Serial Peripheral Interface (SPI), and local bus ( Local Bus ) and other methods to transfer different types of data. If you transfer different data types, you need a different data transfer interface. If there is not enough interface resources in the embedded system to transfer data of the corresponding interface type, the data cannot be transferred to the embedded device.

SUMMARY OF THE INVENTION The present invention provides a method and system for transparent transmission of data, the interface of the processor and various other interfaces (for example, Ethernet interface, SPI, serial Gigabit Media Independent Interface (SGMII) ), and an Inter-Integrated Circuit (I2C) interface, etc. to provide a transparent transmission of data, in the process of data transmission, does not require the participation of the processor, effectively solves the interface resources in the embedded system Insufficient problems. In order to solve the above technical problem, the present invention provides a system for transparent transmission of data, the system comprising a processor, a memory and a logic module, wherein: the memory comprises a receiving storage unit and a transmitting storage unit; The logic module is connected to an external interface, the logic module is configured to: receive data sent by the external interface, and store data sent by the external interface into the receiving storage unit; and query the sending data storage a unit, when querying that the data in the sending storage unit needs to be sent, acquiring data that needs to be sent and transmitting the data that needs to be sent to the external interface; the processor is configured to: need to send to the The data of the external interface is stored in the sending storage unit; and the receiving storage unit is queried, and if there is data in the receiving storage unit that needs to be received, the data to be received is acquired. In the system of the present invention, the receiving storage unit includes a receiving storage subunit corresponding to each external interface, and the sending storage unit includes a transmitting storage subunit corresponding to each external interface; the external interface The number of the data is one or more; the logic module is configured to store data sent by the external interface to the receiving storage unit in the following manner: storing data received from each external interface in each external interface Receiving the storage subunit; the logic module is configured to query the sending storage unit according to the following manner, and when the data is sent to the sending storage unit, the data to be sent is acquired, and the data needs to be sent. The data is sent to the external interface: respectively, the sending storage sub-unit corresponding to each external interface is queried, and when the data to be sent is sent in the sending storage sub-unit corresponding to an external interface, the data to be sent is acquired Sending the data to be sent to the external interface; the processor is set to press The following manner: storing data that needs to be sent to the external interface to the sending storage unit: storing data that needs to be sent to each external interface to a sending storage subunit corresponding to each external interface; the processor is The method is as follows: querying the receiving storage unit, if there is data in the receiving storage unit that needs to be received, acquiring the data that needs to be received: separately querying the receiving storage subunit corresponding to each external interface, and querying If data in the receiving storage subunit corresponding to an external interface needs to be received, the data to be received is acquired. In the system of the present invention,

The receiving storage subunit includes a receiving data storage subunit and a receiving address storage subunit; the transmitting storage subunit includes a transmitting data storage subunit and a sending address storage subunit; The logic module is configured to: store data received from each external interface in a receiving storage subunit corresponding to each external interface: store data of each external interface in a corresponding receiving of each external interface The data storage subunit, and the storage location information and the data length information of the data of each external interface are respectively stored in the receiving address storage subunit corresponding to each external interface; the logic module is set as follows: The sending storage sub-unit corresponding to the external interface acquires the data to be sent and sends the data to be sent to the external interface when it is queried that the data needs to be sent in the sending storage sub-unit corresponding to the external interface: Querying the sending address storage sub-unit corresponding to each external interface separately, and if the storage location information and the data length information included in the sending address storage sub-unit corresponding to an external interface are queried, according to the storage location information and the data length information, Transmit data storage subunit corresponding to the external interface Obtaining data, and then sending the obtained data to the external interface, and clearing the sending address storage subunit corresponding to the external interface; the processor is configured to respectively query the receiving storage subunit corresponding to each external interface as follows If the data is to be received in the receiving storage subunit corresponding to an external interface, the data to be received is obtained: the receiving address storage subunit corresponding to each external interface is separately queried, if an external interface is queried The corresponding receiving address storage subunit includes storage location information and data length information, and then reads data from the received data storage subunit corresponding to the external interface according to the storage location information and the data length information, and corresponding to the external interface. The receiving address storage subunit is emptied; the processor is configured to store data to be sent to each external interface to the sending storage subunit corresponding to each external interface as follows: data to be sent to each external interface Stored separately to the corresponding external interfaces Data storage sub-unit, and needs to be sent to the storage location information and data length information of the data written to each of the external interfaces are sent to the address storage subunit corresponding to each of the external interfaces. In the system of the present invention,

The processor includes at least a high speed peripheral component interconnect (PCIE) interface, and the processor is connected to the logic module via the PCIE interface; The logic module is configured to store data of each external interface in a received data storage subunit corresponding to each external interface, and store storage location information and data length information of data of each external interface respectively. a receiving address storage subunit corresponding to each external interface: transmitting a direct memory access (DMA) write request and data of each external interface to the processor, and controlling the external unit by the DMA write request The data of the interface is respectively written into the receiving data storage subunit corresponding to each external interface, and the data length information and the storage location information of each external interface are written into the receiving address storage subunit corresponding to each external interface;

The logic module is configured to separately query a sending address storage subunit corresponding to each external interface as follows: send a DMA read/write request to the processor, and first control the processor to query the external interface by using a DMA read request Corresponding sending address storage subunit; and the logic module is configured to clear the sending address storage subunit corresponding to the external interface as follows: controlling, by the DMA write request, the processor to clear the receiving address corresponding to the external interface Subunit. In the system of the present invention, the logic module includes an interface processing module, a DMA module, a PCIE transceiver processing module, and a PCIE IP core, and the interface processing module is further connected to the PCIE transceiver processing module via a PCIE address data bus. The interface processing module is configured to: connect to one or more external interfaces, and after receiving data of each external interface, generate and send control to the processor to write data of each external interface into the respective a DMA write request in the receive data storage subunit corresponding to the external interface to the DMA module; generating and transmitting a DMA read request for controlling the processor to query a send address storage subunit corresponding to each external interface to the DMA module; And receiving, from the PCIE address data bus, a response indicating that the storage location information and the data length information in the transmission address storage subunit of an external interface are generated, and transmitting, according to the storage location information, Data length information DMA for reading data from the transmission data storage subunit corresponding to the external interface Requesting; and after receiving data from the PCIE address data bus that needs to be sent to an external interface, transmitting the data to a corresponding external interface, generating and transmitting a sending address that controls the processor to correspond to the external interface A DMA write request that the storage subunit is emptied; The DMA module includes a DMA request queue unit and a DMA command generating unit, wherein: the DMA request queue unit is configured to: sort the received DMA read/write requests; the DMA command generating unit is set to: according to the DMA The sorting order of the DMA read/write request in the request queue unit generates a corresponding DMA read/write command, and sends the DMA command to the PCIE transceiver processor; the PCIE transceiver processor is configured to: send the DMA module Sending a DMA read/write command to the PCIE IP core; and transmitting, by the PCIE IP core, a response corresponding to the DMA read request of the sending address address subunit corresponding to each external interface by the processor to the PCIE The address data bus is sent to the interface processing module; after receiving the DMA write command that controls the processor to write the data of each external interface into the received data storage subunit corresponding to each external interface, a PCIE address data bus acquires the external interface data received by the interface processing module and transmits the same to the PCIE IP core; and receives the PCIE IP After the data sent by the core needs to be sent to an external interface, it is sent to the interface processing module via the PCIE address data bus; the PCIE IP core is integrated with a physical layer, a data link layer, and a transaction layer. Function, the PCIE

The IP core is configured to: after receiving the DMA read/write request sent by the PCIE transceiver processor, send the DMA read/write request to the processor; and receive the sending address corresponding to each external interface sent by the processor. The response corresponding to the DMA read request of the storage subunit is sent to the PCIE transceiver processor; after receiving the data of an external interface sent by the PCIE transceiver processor, it is sent to the processor; and receiving After the data sent by the processor that needs to be sent to an external interface is sent to the PCIE transceiver processor. In the system of the present invention, the logic module is configured to: after receiving data of an external interface, first query a receiving address storage subunit corresponding to the external interface, if the receiving address corresponding to the external interface is a storage subunit Empty, the data of the external interface is stored in the receiving data storage subunit corresponding to the external interface;

The processor is configured to: when sending data to an external interface, first query a sending address storage subunit corresponding to the external interface, if the sending address corresponding to the external interface is The unit is empty, and the data that needs to be sent to the external interface is stored in the corresponding data storage subunit corresponding to the external interface. In order to solve the above technical problem, the present invention provides a method for transparently transmitting data by using the above system, the method comprising: connecting a logic module to an external interface, receiving data sent by the external interface, and transmitting the data from the external interface. The data is stored in the receiving storage unit; the processor queries the receiving storage unit, and if there is data in the receiving storage unit that needs to be received, the data that needs to be received is acquired; and the processor needs to send to the storage unit The data of the external interface is stored in the sending storage unit; the logic module queries the sending storage unit, and when the data is sent to the sending storage unit, the data to be sent is acquired, and the data needs to be sent. Data is sent to the external interface. In the method of the present invention, the receiving storage unit includes a receiving storage subunit corresponding to each external interface, and the sending storage unit includes a sending storage subunit corresponding to each external interface; the external interface The number of the data is one or more; the step of storing, by the logic module, the data sent by the external interface into the receiving storage unit comprises: storing the data received from each external interface in the receiving storage subunit corresponding to each external interface The logic module queries the sending storage unit, when querying that the data in the sending storage unit needs to be sent, the step of acquiring data to be sent and transmitting the data to be sent to the external interface includes: Querying the sending storage sub-units corresponding to the external interfaces respectively, and when the data is sent to the sending storage sub-unit corresponding to the external interface, the data to be sent is sent and the data to be sent is sent to The external interface; the processor will need to send data to the external interface The step of storing in the sending storage unit includes: storing data that needs to be sent to each external interface to a sending storage subunit corresponding to each external interface; the processor querying the receiving storage unit, querying the location The step of obtaining the data to be received in the receiving storage unit includes: separately querying the receiving storage subunit corresponding to each external interface, and querying the corresponding external interface If there is data in the receiving storage subunit that needs to be received, the data to be received is acquired. In the method of the present invention, the receiving storage subunit includes a receiving data storage subunit and a receiving address storage subunit; the transmitting storage subunit includes a transmitting data storage subunit and a sending address storage subunit; the logic module will The step of storing the data received by each external interface in the receiving storage subunit corresponding to each external interface includes: storing data of each external interface in a receiving data storage subunit corresponding to each external interface And storing the storage location information and the data length information of the data of each external interface in a receiving address storage subunit corresponding to each external interface; the logic module respectively querying the sending storage subunit corresponding to each external interface, When the data to be sent is sent to the sending storage subunit corresponding to the certain external interface, the step of acquiring the data to be sent and sending the data to be sent to the external interface includes: separately querying the external The sending address storage sub-unit corresponding to the interface, if the query is for a certain The storage address storage sub-unit corresponding to an external interface includes storage location information and data length information, and then acquires data from the transmission data storage sub-unit corresponding to the external interface according to the storage location information and the data length information, and then acquires the obtained data. Sending data to the external interface, and clearing the sending address storage subunit corresponding to the external interface; the processor separately querying the receiving storage subunit corresponding to each external interface, and querying the receiving storage subunit corresponding to an external interface If the data needs to be received, the step of obtaining the data to be received includes: separately querying the receiving address storage sub-unit corresponding to each external interface, and if the query is to receive the corresponding address, the receiving sub-unit includes the storage The location information and the data length information are read from the received data storage subunit corresponding to the external interface according to the storage location information and the data length information, and the receiving address storage subunit corresponding to the external interface is emptied; The processor will need to be sent to each The step of storing the data of the part interface in the sending storage subunit corresponding to each external interface includes: storing data that needs to be sent to each external interface to the sending data storage subunit corresponding to each external interface, and The storage location information and the data length information of the data sent to the external interfaces are respectively written in corresponding to the external interfaces. The send address is stored in the subunit. In the method of the present invention, the processor in the system includes at least a high speed peripheral component interconnect (PCIE) interface, and the processor is connected to the logic module via the PCIE interface, wherein: the logic module The data of each external interface is stored in the received data storage subunit corresponding to each external interface, and the storage location information and the data length information of the data of the external interfaces are respectively stored in the corresponding external interfaces. The receiving address storage subunit includes: transmitting a direct memory access (DMA) write request and data of the external interfaces to the processor, and controlling, by the DMA write request, the data of each external interface by the processor Writing to the received data storage subunit corresponding to each external interface, and writing data length information and storage location information of each external interface into the receiving address storage subunit corresponding to each external interface; The sending address storage subunit corresponding to each external interface includes: sending a DMA read/write request to the processor The DMA read request is used to control the processor to query the sending address storage subunit corresponding to each external interface; the logic module clearing the sending address storage subunit corresponding to the external interface includes: controlling by DMA write request The processor clears the receiving address storage subunit corresponding to the external interface. In the method of the present invention, the logic module includes an interface processing module, a DMA module, a PCIE transceiver processor, and a PCIE IP core, which are sequentially connected, and the interface processing module is further connected to the PCIE transceiver processor via a PCIE address data bus. The DMA module includes a DMA request queue unit and a DMA command generating unit, and the method further includes: the interface processing module receiving data sent by one or more external interfaces, and after receiving data of an external interface, generating Transmitting, by the processor, the data of each external interface is respectively written into a DMA write request in the receive data storage subunit corresponding to each external interface to the DMA request queue unit; the DMA request queue unit receives the DMA After the write request is added to the DMA request queue, the DMA write request is sent to the DMA command generating unit when the DMA write request is dequeued, and the DMA command generating unit generates a corresponding DMA write command and sends the DMA command to the a PCIE transceiver processor; after receiving the DMA write command that controls the processor to write the data of each external interface to the received data storage subunit corresponding to each external interface, The PCIE address data bus acquires data of the external interface received by the interface processing module, and sends the acquired data and the DMA write command to the processor via the PCIE IP core and the PCIE interface of the processor. The processor executes the DMA write command, writes the data of the external interface into the receiving data storage subunit corresponding to the external interface, and writes the storage location information and the data length information of the data of the external interface to the external The interface corresponding to the receiving address storage subunit; the interface processing module generates and sends a DMA read request for controlling the processor to query the sending address storage subunit corresponding to each external interface to the DMA request queue unit; the DMA request After receiving the DMA read request, the queue unit adds it to the DMA request queue, and sends the DMA read request to the DMA command when it is dequeued. a generating unit, after the DMA command generating processor receives the DMA read command for querying the sending address storage subunit corresponding to each external interface, the DMA read command passes the PCIE IP core and the The PCIE interface of the processor is sent to the processor; the processor executes the DMA read command, and queries a sending address storage subunit corresponding to each external interface in the memory, and sends and receives the PCIE IP core and the PCIE. The processor and the PCIE address data bus return a response corresponding to the DMA read request to the interface processing module; the interface processing module receives storage location information in a sending address storage subunit corresponding to an external interface And responding to the data length information, generating and transmitting a DMA read request for controlling the processor to acquire data from the transmit data storage subunit corresponding to the external interface according to the storage location information and the data length information to the DMA request queue unit The DMA request queue unit receives the DMA read request and adds it to the DMA request queue, when the DMA read request is dequeued Which is sent to the DMA command generation unit, by the DMA

The PCIE transceiver processor controls the DMA read command of the data from the transmit data storage sub-unit corresponding to the external interface according to the storage location information and the data length information, and passes the DMA read command to the PCIE IP core and the Sending, to the processor, a PCIE interface of the processor, the processor executing the DMA read command, and reading data from the sending data storage subunit corresponding to the external interface according to the storage location information and the data length information, and The data read is described The PCIE interface of the processor, the PCIE IP core, the PCIE transceiver processor, and the PCIE address data bus are sent to the interface processing module; after receiving the data that needs to be sent to an external interface, the interface processing module Send it to the corresponding external interface. In the method of the present invention, the logic module stores the data of each external interface in a receiving data storage subunit corresponding to each external interface, where the logic module receives an external interface. After the data is received, the receiving address storage sub-unit corresponding to the external interface is first queried, and if the receiving address storage sub-unit corresponding to the external interface is empty, the data of the external interface is stored to the receiving data storage sub-unit corresponding to the external interface. The processor stores the data that needs to be sent to each external interface to a corresponding one of the sending data storage subunits of the external interfaces, where the processor needs to send data to an external interface. Querying the sending address storage sub-unit corresponding to the external interface, if the sending address storage sub-unit corresponding to the external interface is empty, storing the data that needs to be sent to the external interface to the sending data storage sub-unit corresponding to the external interface .

The invention provides a data transparent transmission method and system, and provides a transparent data transmission function between an interface of a processor and various other interfaces (for example, an Ethernet interface, an SPI, an SGMIL, an I2C interface, etc.). In the process of data transmission, the participation of the processor is not needed, and the problem of insufficient interface resources in the embedded system is effectively solved.

1 is a block diagram of a system for transparent data transmission of a PCIE interface according to an embodiment of the present invention; FIG. 2 is a schematic diagram of a field for indicating storage location information in a transmit data storage subunit according to an embodiment of the present invention; A schematic diagram of a field in a data storage subunit for indicating storage location information; FIG. 4 is a block diagram showing the composition of a logic module according to an embodiment of the present invention; FIG. 5 is a flowchart of a method for transparent data transmission of a PCIE interface according to an embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION The present invention provides a method and system for transparent transmission of PCIE data for providing a transparent transmission of data between an interface of a processor and various other interfaces. In order to make the objects, the technical solutions and the advantages of the present invention more clearly, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in the case of no conflict, the features in the embodiments and the embodiments of the present application may be arbitrarily combined with each other. Referring to FIG. 1, a system for transparent data transmission of a PCIE interface according to an embodiment of the present invention is shown. The system includes a processor, a memory, and a logic module, where: the memory includes a receiving storage unit (Rx_Mem) and a transmitting storage unit ( Tx_ Mem ). The logic module is connected to an external interface, and the logic module is configured to: receive data sent by the external interface, and store data sent by the external interface into the receiving storage unit; and query the sending storage unit, in query When there is data in the sending storage unit that needs to be sent, the data that needs to be sent is acquired and sent to the external interface. The processor is configured to: store data that needs to be sent to the external interface into the sending storage unit; and query the receiving storage unit, and obtain the data after querying that the receiving storage unit has data to be received The data that needs to be received. In the system of this embodiment, the number of the external interfaces is one or more, that is, the external interfaces may include interface 0, interface 1, and interface N. The memory includes one or more external interfaces (interface 0, interface 1 interface)

Each external interface in N) corresponds to the receive storage subunit (Rx0_ Mem, Rxl_

Mem RxN—Mem ) and the corresponding transmit subunit (TxO—for each of the external interfaces (interface 0, interface 1 interface N)

Mem, Txl-Mem, TxN-Mem). The logic module is configured to store data sent by the external interface to the In the receiving storage unit: the received data of the interface 0 and the interface 1 interface N are respectively stored in the receiving storage subunit RxO-Mem corresponding to the interface 0 and the interface 1 interface N.

Rxl_Mem RxN - Mem, for processing by the processor; and the logic module is configured to query the sending storage unit according to the following manner, and when the data is sent to the sending storage unit to be sent, the need is obtained Send the data and send it to the external interface: Query the sending storage subunit corresponding to each external interface (interface 0, interface 1 interface N) ( Tx0_

Mem, Txl—Mem TxN—Mem), when data is sent to the sending storage subunit corresponding to an external interface, the data is acquired and sent out through the corresponding external interface. The processor mainly completes RxO-Mem, Rxl-Mem RxN in the memory

Data processing of Mem, TxO-Mem, Txl-Mem and TxN-Mem. That is, when data to be sent to the external interface is stored in the transmission storage unit, data that needs to be sent to each external interface is separately stored in a transmission storage subunit corresponding to each external interface; When the storage unit is received, the receiving storage sub-unit corresponding to each external interface is separately queried, and when data is received in the receiving storage sub-unit corresponding to an external interface, the data is acquired. In the system of this embodiment, the receiving storage subunits corresponding to the external interfaces (RxO-Mem, Rxl-Mem RxN)

Mem ) includes receive data storage sub-units (RxO—Data—Mem, Rxl—Data—Mem, and RxN_Data_Mem) and receive address storage sub-units (RxO_Info_Mem,

Rxl—Info—Mem and RxN—Info—Mem); Transmit storage subunits corresponding to each external interface (TxO—Mem, Txl—Mem, and TxN—Mem) include transmit data storage subunits (TxO—Data—Mem, Txl— Data—Mem and TxN—Data—Mem and send address storage subunits (TxO—Info—Mem, Txl—Info—Mem, and TxN—Info—Mem); the logic module is set to be external from the following The data received by the interface is respectively stored in the receiving storage subunit corresponding to each external interface: the data of each external interface is separately stored in the receiving data storage subunit corresponding to each external interface, and the external interfaces are The storage location information and the data length information of the data are respectively stored in the receiving addresses corresponding to the external interfaces. In the storage subunit, the logic module is configured to respectively query the sending storage subunits corresponding to the external interfaces as follows: respectively query the sending address storage subunits corresponding to the external interfaces, if the query corresponds to an external interface The storage address storage sub-unit includes storage location information and data length information, and then acquires data from the transmission data storage sub-unit corresponding to the external interface according to the storage location information and the data length information, and then sends the acquired data to the The external interface, and the sending address storage subunit corresponding to the external interface are also emptied; the processor is configured to separately query the receiving storage subunits corresponding to the external interfaces as follows: respectively query the receiving corresponding to the external interfaces An address storage subunit, if the storage location information and the data length information are included in the receiving address storage subunit corresponding to a certain external interface, the receiving data storage device corresponding to the external interface according to the storage location information and the data length information Read data in the unit, and The receiving address storage subunit corresponding to the external interface is cleared; the processor is configured to store data to be sent to each external interface to the sending storage subunit corresponding to each external interface as follows: The data to the external interfaces are respectively stored in the transmission data storage subunits corresponding to the external interfaces, and the storage location information and the data length information of the data to be sent to the external interfaces are respectively written in the corresponding external interfaces. The send address is stored in the subunit. The information carried by the sending address storage subunit corresponding to each external interface in the memory may be as shown in FIG. 2, where the Tx Length field indicates TxO_Data_Mem, Txl_Data_Mem TxN_Data in the memory. – the length of the data stored in the Mem unit; Tx Start

Address Ptr indicates the starting storage address of the data in the TxO—Data—Mem, Txl—Data—Mem TxN—Data—Mem unit. In the system of this embodiment, the information carried by the receiving address storage subunit corresponding to each external interface in the memory may be as shown in FIG. 3, where the Rx Length field indicates RxO_Data_Mem in the memory.

Rxl—Data— Mem RxN—Data—the length of data stored in the Mem unit; Rx Start

Address Ptr represents the starting storage address of the data in the RxO—Data—Mem, Rxl—Data—Mem, and RxN—Data—Mem units. In the system of this embodiment, the logic module is configured to: after receiving data of an external interface, first query a receiving address storage subunit corresponding to the external interface, and if it is empty, the external interface is The data is stored in the receiving data storage subunit corresponding to the external interface; the processor is configured to: when the data needs to be sent to an external interface, first query the sending address storage subunit corresponding to the external interface, if it is Empty, the data that needs to be sent to the external interface is stored in the corresponding data storage subunit corresponding to the external interface. With the continuous improvement of the Peripheral Component Interconnect Express (PCIE) standard, more and more embedded devices integrate PCIE interfaces. PCIE has high speed, simple circuit connection and good technical compatibility. There are more and more applications in communication and other data transmission. Therefore, the transparent transmission scheme of the present invention is described below by taking a processor having a PCIE interface as follows: The processor is connected to the logic module via a PCIE interface. The logic module is configured to store the data of each external interface in a receiving data storage subunit corresponding to each external interface as follows: Send a direct memory access (DMA) to the processor. Writing a request and data of the external interfaces, controlling, by the DMA write request, the data of each external interface to be respectively written into the receiving data storage subunit corresponding to each external interface, and the length of the data of each external interface And the storage location information is written into the receiving address storage subunit corresponding to each external interface; the logic module is configured to separately query the sending address storage subunit corresponding to each external interface as follows: sending a DMA read to the processor Write request, firstly, the DMA read request is used to control the processor to query the sending address storage subunit corresponding to each external interface, and the storage location information and the data length information are included in the sending address storage subunit corresponding to a certain external interface. At the time, according to the storage location information and the data length information from the external interface pair The transmission data storage sub-unit to read data and DMA write request by the processor to control emptying of the external interface corresponding to the received address storage subunit. As shown in FIG. 4, the logic module includes an interface processing module, a direct memory access (DMA) module, a PCIE transceiver processor, and a PCIE IP core (Intellectual Property core), which are sequentially connected, and the interface processing module is also The number of PCIE addresses of the PCIE transceiver processor According to the bus connection, wherein: the interface processing module has functions such as interface 0 transceiver processing, interface 1 transceiver processing, data transmission and reception processing of interface N, generation of DMA request, and processing of PCIE address data bus; DMA module includes DMA The request queue and the DMA command generation module respectively perform the DMA read/write request sorting and the DMA command generation function of the interface 0 to the interface N; the PCI Express transceiver processing module mainly completes the processing of the DMA command and the processing of the PCIE IP CORE interface data; The IP CORE is provided by the logic chip manufacturer and integrates the functions of the physical layer, the data link layer, and the transaction layer. The PCIE transceiver processor further has a splitting and merging function of the data packet to meet the requirements of the PCIE IP core. The following further describes how the above modules cooperate in the logic module to implement the transparent transmission function of the present invention: the interface processing module is configured to: connect with one or more external interfaces, and after receiving data of each external interface, Generating and transmitting a DMA write request for controlling, by the processor, the data of each external interface to the received data storage sub-unit corresponding to each external interface to the DMA module; generating and transmitting the processor to query each a DMA read request of the transmit address storage sub-unit corresponding to the external interface to the DMA module; storage location information and data length in the transmit address storage sub-unit received from the PCIE address data bus to indicate an external interface And responsive to the information, generating and transmitting a DMA read request that controls the processor to read data from the transmit data storage sub-unit corresponding to the external interface according to the storage location information and the data length information; and at the slave PCIE address After the data bus receives the data that needs to be sent to an external interface, the data is sent Corresponding external interface, generating and sending a DMA write request for controlling the processor to clear the sending address storage subunit corresponding to the external interface; the DMA module includes a DMA request queue unit and a DMA command generating unit, where: The DMA request queue unit is configured to: sort the received DMA read/write requests; the DMA command generating unit is configured to: generate a corresponding DMA read/write command according to a sort order of the DMA read/write requests in the DMA request queue unit And sending the DMA command to the PCIE transceiver processor; the PCIE transceiver processor is configured to: send the DMA read/write life of the DMA module Sending to the PCIE IP core; sending, by the PCIE IP core, a response corresponding to the DMA read request of the processor to query the sending address storage subunit corresponding to each external interface is sent to the PCIE address data bus to The interface processing module: after receiving the DMA write command that controls the processor to respectively write the data of each external interface into the received data storage subunit corresponding to each external interface, obtain the DMA write command via the PCIE address data bus The interface processing module receives the external interface data and sends it to the PCIE IP core; and after receiving the data sent by the PCIE IP core that needs to be sent to an external interface, The PCIE address data bus is sent to the interface processing module; the PCIE IP core is integrated with a physical layer, a data link layer, and a transaction layer function, and the PCIE IP core is set to: receive the PCIE transceiver processing After the DMA read/write request sent by the device, send it to the processor; and receive the sending address corresponding to each external interface sent by the processor. The response corresponding to the DMA read request of the subunit is sent to the PCIE transceiver processor; after receiving the data of an external interface sent by the PCIE transceiver processor, it is sent to the processor; and after receiving After the data sent by the processor needs to be sent to an external interface, it is sent to the PCIE transceiver processor. Based on the above functions of the logic module, the processor only needs to execute the received DMA read/write command. The processor does not need to participate in transparent transmission control by using RxO-Info-Mem, RxO-Data-Mem, TxO-Info-Mem, TxO-Data-Mem in the memory,

Rxl—Info— Mem, Rxl—Data— Mem, Txl—Info—Mem, Txl—Data—Mem, , RxN— Info— Mem, RxN—Data—Mem, TxN—Info—Mem, and TxN—Data—Mem Data The processing can read the data sent from the external interface from the memory, and store the data to be sent on the memory for the logic module of the present invention to send to the corresponding interface. In the system of this embodiment, the logic module is configured to: after receiving data of an external interface, first query a receiving address storage subunit corresponding to the external interface, and if it is empty, the external interface is The data is stored in the receiving data storage subunit corresponding to the external interface; the processor is configured to: when the data needs to be sent to an external interface, first query the sending address storage subunit corresponding to the external interface, if it is Empty, will need to be sent to the external connection The data of the port is stored in the sending data storage subunit corresponding to the external interface. The system for transparent transmission of data in the embodiment of the present invention may further include a switch (not shown), wherein: the switch is mainly a bridge function, and completes interface data of the processor and forwarding of interface data of the logic module. A function that can connect the processor to one or more of the logic modules to implement interface expansion.

Referring to FIG. 5, the figure shows a method for performing transparent transmission of data by using the above system, the method comprising the following steps: Step S501: The logic module is connected to an external interface, and receives data sent by the external interface, and The storage is stored in the receiving storage unit; Step S502: The processor queries the receiving storage unit, and if the data is received in the receiving storage unit, the data to be received is acquired; Step S503: The processor stores data that needs to be sent to the external interface to the sending storage unit; Step S504: The logic module queries the sending storage unit, and when there is data in the sending storage unit that needs to be sent, Acquiring the data that needs to be sent and sending it to the external interface. There is no order requirement between the above steps, which can be performed at the same time, and the invention is not limited herein. For example, when the logic module writes the received interface data to the memory, the processor can also write data to be transmitted to the memory at the same time.

The number of the external interfaces is one or more, that is, the external interfaces may include interface 0, interface 1, and interface N. The memory includes a receiving storage subunit (RxO-Mem, Rxl-Mem RxN-Mem) corresponding to each of one or more external interfaces (interface 0, interface 1 interface N) and one or more Each of the external interfaces (interface 0, interface 1 interface N) - the corresponding transmit storage subunit

(TxO—Mem, Txl Mem TxN—Mem). The logic module stores the data sent by the receiving interface 0 and the interface 1 interface N when the data sent by the external interface is stored in the receiving storage unit, and is respectively stored in the interface 0 and the interface 1 interface N. Receiving storage subunits RxO—Mem, Rxl—

Mem RxN—Mem for processing by the processor; and querying the sending storage subunits corresponding to each external interface (interface 0, interface 1 interface N) (TxO—Mem, Txl—Mem

TxN_Mem), when it is found that there is data in the sending storage sub-unit corresponding to an external interface, the data is acquired and sent through the corresponding external interface. The processor, the processor mainly completes RxO-Mem, Rxl in the memory-

Mem RxN—Mem, TxO—Mem, Txl—Mem TxN—Mem data processing. That is, when data to be sent to the external interface is stored in the transmission storage unit, data that needs to be sent to each external interface is separately stored in a transmission storage subunit corresponding to each external interface; When the storage unit is received, the receiving storage sub-unit corresponding to each external interface is separately queried, and when data is received in the receiving storage sub-unit corresponding to an external interface, the data is acquired.

Where: the receiving storage subunit corresponding to each external interface (RxO—Mem, Rxl—Mem RxN

Mem ) includes receiving data storage subunits ( Rx0_Data_Mem ,

Rxl—Data— Mem RxN—Data—Mem and receive address storage subunit

( RxO— Info— Mem, Rxl—Info— Mem RxN— Info— Mem ; The transmit storage subunits corresponding to each external interface (TxO—Mem, Txl—Mem TxN—Mem) include the transmit data storage subunit (TxO_Data_Mem, Txl) Data Mem TxN Data Mem ) and a transmission address storage subunit (TxO—Info—Mem, Txl—Info—Mem TxN—Info—Mem); the logic module stores data received from each external interface in the When receiving the storage subunits corresponding to the external interfaces, the data of the external interfaces are respectively stored in the received data storage subunits corresponding to the external interfaces, and the storage location information of the data of the external interfaces is further The data length information is respectively stored in the receiving address storage subunit corresponding to each external interface;

The logic module is configured to separately query the sending storage subunits corresponding to the external interfaces. Querying the sending address storage sub-unit corresponding to each external interface, if the storage location information and the data length information included in the sending address storage sub-unit corresponding to an external interface are queried, according to the storage location information and the data length information Obtaining data from the sending data storage subunit corresponding to the external interface, and then sending the acquired data to the external interface, and also clearing the sending address storage subunit corresponding to the external interface; the processor separately querying the When receiving the storage sub-unit corresponding to each external interface, the receiving address storage sub-unit corresponding to each external interface is separately queried, and if the storage address sub-unit corresponding to the external interface is included, the storage location information and the data length information are included. And reading data from the received data storage subunit corresponding to the external interface according to the storage location information and the data length information, and also clearing the receiving address storage subunit corresponding to the external interface; the processor, where Data sent to each external interface is stored separately When stored in the transmission storage subunit corresponding to each external interface, the data to be sent to each external interface is separately stored in the transmission data storage subunit corresponding to each external interface, and also needs to be sent to the external The storage location information and the data length information of the data of the interface are respectively written in the transmission address storage subunits corresponding to the respective external interfaces. The information carried by the sending address storage subunit corresponding to each external interface may be as shown in FIG. 2, where the Tx Length field indicates TxO_Data_Mem in the memory,

Txl—Data— Mem TxN—Data—the length of data stored in the Mem unit; Tx Start

Address Ptr indicates the starting storage address of the data in the TxO—Data—Mem, Txl—Data—Mem TxN—Data—Mem unit. The information carried by the receiving address storage subunit corresponding to each external interface may be as shown in FIG. 3, where the Rx Length field indicates RxO_Data_Mem in the memory,

Address Ptr represents the starting storage address of the data in the RxO—Data—Mem, Rxl—Data—Mem, and RxN—Data—Mem units. Using the above method, by querying the storage address storage subunit storing the storage location information and the length information of the data that needs to be sent to the external interface, it can be determined whether the processor has data to be sent to an external interface, and By storing data with the received external interface The receiving address storage sub-unit storing the location information and the length information can perform a query to determine whether data of a certain external interface has been stored in the memory for the processor to use. The method further includes: after receiving the data of an external interface, querying the receiving address storage subunit corresponding to the external interface, and if the space is empty, storing the data of the external interface to the external The receiving data storage subunit corresponding to the interface; the processor, when the data needs to be sent to an external interface, first query the sending address storage subunit corresponding to the external interface, and if it is empty, it needs to be sent to the The data of the external interface is stored in the transmission data storage subunit corresponding to the external interface. The following is a description of the transparent transmission method of the present invention by using a processor having a PCIE interface. The processor has at least one PCIE interface, and the processor is connected to the logic module via the PCIE interface. The method includes: The logic module sends the DMA write request and the data of each external interface to the processor when the data of each external interface is stored in the received data storage subunit corresponding to each external interface, by using DMA Writing a request to the processor to write data of each external interface into the receiving data storage subunit corresponding to each external interface, and writing data length and storage location information of each external interface to the external interfaces Corresponding receiving address storage sub-unit; the logic module, when separately querying the sending address storage sub-unit corresponding to each external interface, sending a DMA read/write request to the processor, first controlling the DMA read request The processor queries the sending address storage subunit corresponding to each external interface, and queries the sending corresponding to an external interface. When the location storage subunit includes the storage location information and the data length information, the data is read from the transmission data storage subunit corresponding to the external interface according to the storage location information and the data length information, and then the processing is controlled by a DMA write request. The device clears the receiving address storage subunit corresponding to the external interface. The logic module includes an interface processing module, a direct memory access (DMA) module, a PCIE transceiver processor, and a PCIE IP core, and the interface processing module is further connected to the PCIE transceiver processor via a PCIE address data bus. Connected, the DMA module includes a DMA request queue a unit and a DMA command generating unit, wherein: the interface processing module receives data sent by one or more external interfaces, and after receiving data of an external interface, generates and sends a control to the processor to the external interfaces. The data is respectively written into the DMA write request unit in the receive data storage subunit corresponding to each external interface to the DMA request queue unit; the DMA request queue unit receives the DMA write request and adds it to the DMA request queue, The DMA write request is sent to the DMA command generating unit when it is dequeued, and is generated by the DMA command generating unit to generate a corresponding DMA write command, and then sent to the PCIE transceiver processor; the PCIE transceiver processor receives the same Controlling, by the processor, the data of each external interface is respectively written into the DMA write command in the receiving data storage subunit corresponding to each external interface, and acquiring the received by the interface processing module via the PCIE address data bus Data of the external interface, sending the acquired data and the DMA write command to the PCIE IP core and the PCIE interface of the processor to the The processor executes the DMA write command, writes the data of the external interface into the receiving data storage subunit corresponding to the external interface, and writes the storage location information and the data length information of the data of the external interface. Entering a receiving address storage sub-unit corresponding to the external interface; the interface processing module generates and sends a DMA read request for controlling the processor to query a sending address storage sub-unit corresponding to each external interface to the DMA request queue unit; After receiving the DMA read request, the DMA request queue unit adds it to the DMA request queue, and sends the DMA read request to the DMA command generating unit when the DMA read request is dequeued, and the DMA command generating processor receives the DMA command. After the processor queries the DMA read command of the sending address storage subunit corresponding to each external interface, the DMA read command is sent to the processor via the PCIE IP core and the PCIE interface of the processor; The processor executes the DMA read command, and queries a sending address storage subunit corresponding to each external interface in the memory, and the PCIE IP core and the PCIE Transceiver processor and said PCIE address data bus returning a response corresponding to said DMA read request to said interface processing module; said interface processing module receiving a storage location in said send address storage subunit corresponding to an external interface After the response of the information and the data length information, generating and transmitting a DMA read request for controlling the processor to acquire data from the transmit data storage subunit corresponding to the external interface according to the storage location information and the data length information to the DMA request queue unit; The DMA request queue unit adds the DMA read request to the DMA request queue, and sends the DMA read request to the DMA command generating unit when the DMA read request is dequeued, by the DMA

The PCIE transceiver processor controls the DMA read command of the data from the transmit data storage sub-unit corresponding to the external interface according to the storage location information and the data length information, and passes the DMA read command to the PCIE IP core and the Sending, to the processor, a PCIE interface of the processor, the processor executing the DMA read command, and reading data from the sending data storage subunit corresponding to the external interface according to the storage location information and the data length information, and The read data is sent to the interface processing module via the PCIE interface of the processor, the PCIE IP core, the PCIE transceiver processor, and the PCIE address data bus; the interface processing module needs to send to the receiving After the data of an external interface is sent to the corresponding external interface. The method further includes: after receiving the data of an external interface, querying the receiving address storage sub-unit corresponding to the external interface, and if the space is empty, storing the data of the external interface to the external The receiving data storage subunit corresponding to the interface; the processor, when the data needs to be sent to an external interface, first query the sending address storage subunit corresponding to the external interface, and if it is empty, it needs to be sent to the The data of the external interface is stored in the transmission data storage subunit corresponding to the external interface. The above method further includes: connecting the processor to one or more of the logic modules in a switch module to implement interface expansion. The switch is mainly a bridging function, and completes the interface data of the processor and the forwarding function of the interface data of the logic module, which can connect the processor with one or more of the logic modules to implement interface expansion. According to the foregoing method of the embodiment of the present invention, the logic module is mainly responsible for transparent transmission processing, and the processor only needs to execute the received DMA read/write command, and does not need to participate in transparent transmission control, that is, the processor passes the RxO in the memory - Info - Mem, RxO - Data - Mem, TxO - Info - Mem, TxO - Data - Mem, Rxl - Info - Mem, Rxl - Data - Mem,

Txl—Info— Mem, Txl— Data— Mem, , RxN— Info— Mem, RxN—Data— Mem,

TxN—Info—Mem, TxN—Data—Mem data can be read from the memory to the external interface The data sent by the port stores the data to be sent on the memory for the logic module of the present invention to send to the corresponding interface.

One of ordinary skill in the art will appreciate that all or a portion of the above steps may be accomplished by a program instructing the associated hardware, such as a read-only memory, a magnetic disk, or an optical disk. Alternatively, all or part of the steps of the above embodiments may also be implemented using one or more integrated circuits. Correspondingly, each module unit in the above embodiment may be implemented in the form of hardware or in the form of a software function module. The invention is not limited to any specific form of combination of hardware and software. The invention may, of course, be embodied in various other forms and modifications without departing from the spirit and scope of the invention.

Industrial Applicability The present invention provides a data transparent transmission method and system, which provides a transparent data transmission function between an interface of a processor and various other interfaces, and does not require the participation of a processor in the process of data transmission. , effectively solve the problem of insufficient interface resources in the embedded system.

Claims

Claim

A system for transparent transmission of data, the system comprising a processor, a memory and a logic module, wherein: the memory comprises a receiving storage unit and a transmitting storage unit; the logic module is connected to an external interface, the logic module The method is configured to: receive data sent by the external interface, and store data sent by the external interface into the receiving storage unit; and query the sending data storage unit, and query data in the sending storage unit When the transmission is required, the data to be sent is acquired and the data to be sent is sent to the external interface; the processor is configured to: store data that needs to be sent to the external interface into the sending storage unit; And querying the receiving storage unit, and acquiring data that needs to be received after querying that the receiving storage unit has data to be received.

2. The system according to claim 1, wherein: said receiving storage unit comprises a receiving storage subunit corresponding to each external interface, said transmitting storage unit comprising a transmitting storage unit corresponding to each external interface in one-to-one correspondence The number of the external interfaces is one or more; the logic module is configured to store data sent by the external interface into the receiving storage unit as follows: data received from each external interface respectively Storing in the receiving storage subunit corresponding to each external interface; the logic module is configured to query the sending storage unit in the following manner, and obtain data to be sent when there is data in the sending storage unit that needs to be sent. Sending the data to be sent to the external interface: respectively, querying a sending storage subunit corresponding to each external interface, and acquiring the data when the data is to be sent in the sending storage subunit corresponding to an external interface. Data to be sent and the data to be sent is sent to the external interface; The processor is configured to: store data that needs to be sent to the external interface to the sending storage unit: store data that needs to be sent to each external interface to a sending storage subunit corresponding to each external interface The processor is configured to query the query as follows Receiving a storage unit, if there is data in the receiving storage unit that needs to be received, acquiring the data that needs to be received: separately querying a receiving storage subunit corresponding to each external interface, and querying a receiving storage corresponding to an external interface If there is data in the subunit that needs to be received, the data to be received is acquired.

3. The system of claim 2, wherein: the receiving storage subunit comprises a receiving data storage subunit and a receiving address storage subunit; the transmitting storage subunit comprising a transmitting data storage subunit and a sending address storage subunit The logic module is configured to: store data received from each external interface in a receiving storage subunit corresponding to each external interface: store data of each external interface in each external interface Receiving the data storage subunit, and storing the storage location information and the data length information of the data of each external interface in the receiving address storage subunit corresponding to each external interface;

The logic module is configured to: query the sending storage subunit corresponding to each external interface separately, and obtain the data to be sent when the data to be sent is sent in the sending storage subunit corresponding to an external interface. And sending the data to be sent to the external interface: respectively querying a sending address storage subunit corresponding to each external interface, and if the query is to send a storage address corresponding to an external interface, the storage sub-unit includes storage location information and a data length And acquiring information from the transmission data storage subunit corresponding to the external interface according to the storage location information and the data length information, and then sending the acquired data to the external interface, and sending a storage address corresponding to the external interface. The unit is emptied; the processor is configured to separately query the receiving storage subunits corresponding to the external interfaces according to the following manner, and if the data is to be received in the receiving storage subunit corresponding to an external interface, the required receiving is obtained. Data: query each external interface pair separately a receiving address storage subunit, if the storage location information and the data length information included in the receiving address storage subunit corresponding to a certain external interface are queried, the receiving data corresponding to the external interface according to the storage location information and the data length information Reading data in the storage subunit, and clearing the receiving address storage subunit corresponding to the external interface; the processor is configured to separately store data to be sent to each external interface as follows Storing in the transmission storage subunit corresponding to each external interface: storing data that needs to be sent to each external interface to the transmission data storage subunit corresponding to each external interface, and data to be sent to the external interfaces The storage location information and the data length information are respectively written in the transmission address storage subunits corresponding to the respective external interfaces.

4. The system of claim 3, wherein: said processor comprises at least a high speed peripheral component interconnect (PCIE) interface, said processor being coupled to said logic module via said PCIE interface; said logic The module is configured to store data of each external interface in a receiving data storage subunit corresponding to each external interface, and store storage location information and data length information of each external interface in each external interface, respectively. Corresponding receiving address storage subunit: sending a direct memory access (DMA) write request and data of each external interface to the processor, and controlling, by the DMA write request, the data of the external interface by the processor Writing the data length sub-units corresponding to the external interfaces, and writing the data length information and the storage location information of the external interfaces into the receiving address storage sub-units corresponding to the external interfaces; The module is configured to separately query the sending address storage subunits corresponding to the external interfaces as follows: Transmitting, by the processor, a DMA read/write request, first controlling, by the DMA read request, the processor to query a sending address storage subunit corresponding to each external interface; and the logic module is configured to correspond to the external interface as follows The transmit address storage subunit is emptied: the DMA write request is used to control the processor to clear the receive address storage subunit corresponding to the external interface.

5. The system of claim 4, wherein: the logic module comprises an interface processing module, a DMA module, a PCIE transceiver processing module, and a PCIE IP core, which are sequentially connected, the interface processing module and the PCIE transceiver processing module. Connected via a PCIE address data bus, wherein: the interface processing module is configured to: connect to one or more external interfaces, and after receiving data of each external interface, generate and send control to the processor to the external interfaces Data score Writing a DMA write request in the receive data storage sub-unit corresponding to each external interface to the DMA module; generating and transmitting a DMA read request to control the processor to query the transmit address storage sub-unit corresponding to each external interface a DMA module; when receiving a response from the PCIE address data bus to indicate storage location information and data length information in a transmission address storage subunit of an external interface, generating and transmitting control of the processor according to the Determining, by the storage location information and the data length information, a DMA read request for reading data from a transmit data storage subunit corresponding to the external interface; and after receiving data to be sent to an external interface from the PCIE address data bus, Sending the data to the corresponding external interface, generating and transmitting a DMA write request for controlling the processor to clear the sending address storage subunit corresponding to the external interface; the DMA module includes a DMA request queue unit and a DMA command generating unit, Wherein: the DMA request queue unit is set to: sort the received DMA read and write requests; The DMA command generating unit is configured to: generate a corresponding DMA read/write command according to a sort order of the DMA read/write request in the DMA request queue unit, and send the DMA command to the PCIE transceiver processor; the PCIE The transceiver processor is configured to: send a DMA read/write command sent by the DMA module to the PCIE IP core; and send the PCIE IP core to control the processor to query a sending address storage device corresponding to each external interface. Sending a response corresponding to the DMA read request of the unit to the interface processing module via the PCIE address data bus; and receiving, by the processor, the data of each external interface is respectively written into the received data storage corresponding to each external interface After the DMA write command in the subunit, acquiring the external interface data received by the interface processing module via the PCIE address data bus and transmitting the same to the PCIE IP core; and receiving the PCIE IP core transmission After the data needs to be sent to an external interface, it is sent to the interface processing module via the PCIE address data bus; the PCIE IP core is integrated with the object The function of the layer, the data link layer, and the transaction layer, the PCIE IP core is configured to: after receiving the DMA read/write request sent by the PCIE transceiver processor, send the DMA read/write request to the processor; Sending, by the processor, a response corresponding to the DMA read request of the sending address storage subunit corresponding to each external interface to the PCIE transceiver processor; receiving an external interface sent by the PCIE transceiver processor After the data is sent to the processor; and after receiving the need to send the processor to send to an external connection After the data of the port, it is sent to the PCIE transceiver processor.

6. The system according to any one of claims 3-5, wherein: the logic module is configured to: after receiving data of an external interface, first query a receiving address storage subunit corresponding to the external interface If the receiving address corresponding to the external interface is empty, the data of the external interface is stored in the receiving data storage subunit corresponding to the external interface;

The processor is configured to: when the data needs to be sent to an external interface, first query the sending address storage sub-unit corresponding to the external interface, and if the sending address storage sub-unit corresponding to the external interface is empty, the processor needs to send The data to the external interface is stored in the transmit data storage subunit corresponding to the external interface.

7. A method of applying the system of claim 1 for data transparent transmission, the method comprising:

The logic module is connected to the external interface, receives the data sent by the external interface, and stores the data sent by the external interface into the receiving storage unit; the processor queries the receiving storage unit, and queries the receiving storage unit And acquiring, by the processor, the data that needs to be received; and the processor storing the data that needs to be sent to the external interface into the sending storage unit; the logic module querying the sending storage unit, in the query When there is data in the sending storage unit that needs to be sent, the data that needs to be sent is acquired and the data that needs to be sent is sent to the external interface.

8. The method according to claim 7, wherein: the receiving storage unit comprises a receiving storage subunit corresponding to each external interface, the transmitting storage unit comprising a one-to-one corresponding sending storage corresponding to each external interface. a subunit; the number of the external interfaces is one or more; the logic module storing the data sent by the external interface into the receiving storage unit comprises: storing data received from each external interface separately in the external unit Receiver corresponding to the interface In the unit, the logic module queries the sending storage unit, and when the data to be sent in the sending storage unit is queried, the step of acquiring data to be sent and sending the data to be sent to the external interface is performed. The method includes: querying, respectively, a sending storage sub-unit corresponding to each external interface, and when data is sent to be sent in a sending storage sub-unit corresponding to an external interface, acquiring the data to be sent and sending the data to be sent Up to the external interface; the step of the processor storing data that needs to be sent to the external interface to the sending storage unit comprises: storing data that needs to be sent to each external interface to a sending storage corresponding to each external interface In the subunit, the processor queries the receiving storage unit, and if there is data in the receiving storage unit that needs to be received, the step of acquiring the data to be received includes: separately querying the receiving storage corresponding to each external interface Subunit, in the receiving storage subunit corresponding to an external interface There are data to receive, then the acquired data needs to receive.

9. The method of claim 8, wherein: the receiving storage subunit comprises a receiving data storage subunit and a receiving address storage subunit; the transmitting storage subunit comprising a transmitting data storage subunit and a sending address storage subunit The step of storing, by the logic module, the data received from the external interfaces in the receiving storage subunits corresponding to the external interfaces, respectively: storing the data of the external interfaces in the external interfaces respectively. And the storage location information and the data length information of the data of each external interface are respectively stored in the receiving address storage subunit corresponding to each external interface; the logic module separately queries each external interface And corresponding to the sending storage subunit, when the data is sent to the sending storage subunit corresponding to the certain external interface, the step of acquiring the data to be sent and sending the data to be sent to the external interface includes: : separately querying the sending address storage subunit corresponding to each external interface If the storage location information and the data length information included in the sending address storage sub-unit corresponding to an external interface are queried, the data is obtained from the sending data storage sub-unit corresponding to the external interface according to the storage location information and the data length information. And then sending the obtained data to the external interface, and clearing the sending address storage subunit corresponding to the external interface; the processor separately querying the receiving storage subunit corresponding to each external interface, and querying a certain The step of obtaining the data to be received by the receiving storage sub-unit corresponding to the external interface includes: separately querying the receiving address storage sub-unit corresponding to each external interface, if the corresponding external interface is queried The storage address storage subunit includes storage location information and data length information, and then reads data from the received data storage subunit corresponding to the external interface according to the storage location information and the data length information, and receives the corresponding external interface. The address storage subunit is emptied; the processor storing the data that needs to be sent to each external interface to the transmission storage subunit corresponding to each external interface, respectively, includes: storing data that needs to be sent to each external interface to the The storage data storage subunit corresponding to each external interface, and the storage location information and the data length information of the data to be transmitted to the external interfaces are respectively written in the transmission address storage subunits corresponding to the respective external interfaces.

10. The method of claim 9, wherein the processor in the system comprises at least a high speed peripheral component interconnect (PCIE) interface, the processor being connected to the logic module via the PCIE interface, The logic module stores the data of each external interface in a receiving data storage subunit corresponding to each external interface, and stores storage location information and data length information of the data of each external interface separately. The step of receiving the sub-units corresponding to the external interfaces includes: transmitting a direct memory access (DMA) write request to the processor and data of the external interfaces, and controlling the processor by using a DMA write request The data of each external interface is respectively written into the receiving data storage subunit corresponding to each external interface, and the data length information and the storage location information of each external interface are written into the receiving address storage subunit corresponding to each external interface. The step of the logic module separately querying the sending address storage subunits corresponding to the external interfaces includes: Sending a DMA read/write request to the processor, first controlling, by the DMA read request, the processor to query a sending address storage subunit corresponding to each external interface; the logic module clearing the sending address storage subunit corresponding to the external interface The steps include: controlling, by the DMA write request, the processor to clear the receiving address storage subunit corresponding to the external interface.

The method according to claim 10, wherein the logic module comprises a connection connected in sequence a port processing module, a DMA module, a PCIE transceiver processor, and a PCIE IP core, the interface processing module is further connected to the PCIE transceiver processor via a PCIE address data bus, and the DMA module includes a DMA request queue unit and a DMA command generation unit The method further includes: the interface processing module receiving data sent by one or more external interfaces, and after receiving data of an external interface, generating and transmitting, respectively, controlling, by the processor, data of each external interface Writing a DMA write request in the receive data storage sub-unit corresponding to each external interface to the DMA request queue unit; the DMA request queue unit adds the DMA write request to the DMA request queue, and writes the DMA request queue in the DMA request queue Sending a request to the DMA command generating unit, sending a corresponding DMA write command to the PCIE transceiver processor after the DMA command generating unit sends the team; the PCIE transceiver processor receiving the control After the processor writes the data of each external interface to the DMA write command in the receiving data storage subunit corresponding to each external interface, Obtaining, by the PCIE address data bus, the data of the external interface received by the interface processing module, and sending the acquired data and the DMA write command to the PCIE IP core and the PCIE interface of the processor to the The processor executes the DMA write command, writes the data of the external interface into the receiving data storage subunit corresponding to the external interface, and writes the storage location information and the data length information of the data of the external interface. Entering a receiving address storage sub-unit corresponding to the external interface; the interface processing module generates and sends a DMA read request for controlling the processor to query a sending address storage sub-unit corresponding to each external interface to the DMA request queue unit; After receiving the DMA read request, the DMA request queue unit adds it to the DMA request queue, and sends the DMA read request to the DMA command generating unit when the DMA read request is dequeued, and the DMA command generating processor receives the DMA command. After the processor queries the DMA read command of the sending address storage subunit corresponding to each external interface, the DMA read command is passed through the PCIE IP core and The PCIE interface of the processor is sent to the processor; the processor executes the DMA read command, and queries a sending address storage subunit corresponding to each external interface in the memory, and the PCIE IP core and the PCIE Transceiver processor and said PCIE address data bus returning a response corresponding to said DMA read request to said interface processing module; said interface processing module receiving a signal indicating that an external interface corresponds After the address storage subunit has a response to store the location information and the data length information, generate and send the control to acquire data from the transmit data storage subunit corresponding to the external interface according to the storage location information and the data length information. a DMA read request to the DMA request queue unit; the DMA request queue unit adds the DMA read request to the DMA request queue, and sends the DMA read request to the DMA command generating unit when the DMA read request is dequeued By the DMA

The PCIE transceiver processor controls the DMA read command of the data from the transmit data storage sub-unit corresponding to the external interface according to the storage location information and the data length information, and passes the DMA read command to the PCIE IP core and the Sending, to the processor, a PCIE interface of the processor, the processor executing the DMA read command, and reading data from the sending data storage subunit corresponding to the external interface according to the storage location information and the data length information, and The read data is sent to the interface processing module via the PCIE interface of the processor, the PCIE IP core, the PCIE transceiver processor, and the PCIE address data bus; the interface processing module needs to send to the receiving After the data of an external interface is sent to the corresponding external interface.

The method according to any one of claims 9-11, wherein: the logic module stores the data of each external interface in a step of respectively receiving the data storage sub-unit corresponding to each external interface. After receiving the data of an external interface, the logic module first queries the receiving address storage subunit corresponding to the external interface, and if the receiving address corresponding to the external interface is empty, the external interface is The data is stored in the receiving data storage subunit corresponding to the external interface; the processor stores the data that needs to be sent to each external interface into the sending data storage subunit corresponding to each external interface, When the processor needs to send data to an external interface, the processor first queries the sending address storage sub-unit corresponding to the external interface, and if the sending address storage sub-unit corresponding to the external interface is empty, the data to be sent to the external interface is required. Stored in the transmit data storage subunit corresponding to the external interface.