WO2012012963A1

WO2012012963A1 - Device and method for converting digital sampling rate

Info

Publication number: WO2012012963A1
Application number: PCT/CN2010/077042
Authority: WO
Inventors: 周鹏; 陈月峰; 叶辉; 赵兴山
Original assignee: 中兴通讯股份有限公司
Priority date: 2010-07-28
Filing date: 2010-09-17
Publication date: 2012-02-02
Also published as: CN102347768A; CN102347768B

Abstract

A device and method for converting digital sampling rate is provided in the present invention. When a first sampling period is greater than a second sampling period, the multiple phase filter in the device is used to control a first switch to be in a first state, and makes a first multiplier doesn't have the input of a first normalized distance and a second multiplier have the input of a second normalized distance by controlling a second switch and a third switch. When the first sampling period is less than the second sampling period, the multiple phase filter is also used to control said first switch to be in a second state, and makes the first multiplier have the input of the first normalized distance and the second multiplier doesn't have the input of the second normalized distance by controlling said second switch and said third switch. By applying the present invention, flexibility of sampling rate conversion device is enhanced, and hardware implement architecture of Farrow filter is simplified.

Description

TECHNICAL FIELD The present invention relates to the field of digital signal processing, and in particular, to a digital sample rate conversion apparatus and method. Background technique

The goal of software radio is to change the air interface by loading the appropriate software on a common hardware platform. For communication standards and protocols of different sampling rates, a common strategy in software radio is to use a fixed rate regardless of the symbol rate of the input signal, and then digitally convert the unsynchronized sample values. (SRC) to achieve symbol synchronization requirements.

The problem of sample rate conversion can be summarized as a repetitive process. The principle is shown in Figure 1. First, the input discrete signal ^χ ( ) with the sample period ^Τ ι is reconstructed into an analog signal ^通过 by an ideal digital-to-analog converter (DAC). ^{( ί} ); Then, the analog signal is ^resampled with the desired sampling period to obtain a sample signal y( ^M7 ^) , where ^A . W is a continuous-time filter to prevent mirroring or aliasing caused by the signal spectrum during sample rate conversion, usually ^A. w is also a low pass filter. The above process can be expressed by the following formula: y(mT ₂ ) = ^x(kT _l ) h(mT ₂ -kT _l )

In the above formula, ^ means rounding down. ^e [M is the position of the current sample within the sample period ⁷ ; The Farrow filter implementation based on polynomial fitting is essentially a polynomial piecewise function to fit the time domain response ^{A of the} low pass filter. W , usually expressed by the following formula:

Where w is the number of segments of the low-pass filter; (", ⁷ ^ is called the basis function of the polynomial, Γ is the segment interval; M is the highest power of the polynomial. Currently, the basis function in the mainstream design scheme is formula:

The number of segments of the filter at this time is an even number, and its coefficient is evenly symmetric, that is, it satisfies:

Different Farrow filters have different functions and effects when implementing the sample rate conversion due to their structural differences. In general, the classical Farrow filter structure implements a well-documented de-mirror function and is therefore suitable for interpolation filtering. The transposed Farrow filter structure has a good anti-aliasing function and is therefore suitable for decimation filtering. Due to the structural differences between the classic Farrow filter and the transposed Farrow filter, two sets of circuits are usually used to implement their respective functions. Summary of the invention

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital sampling rate conversion apparatus and method for solving the technical problem that the prior art requires two sets of circuits to implement the interpolation filter structure and the decimation filter structure, respectively.

In order to achieve the above object, a digital sample rate conversion apparatus is provided for converting an input first sample sequence having a first sample period into a second sample having a second sample period a sequence of values output, wherein the apparatus comprises a polyphase filter, and a first switch, a second switch, and a third switch disposed in the polyphase filter;

The polyphase filter is configured to control the first switch to be in a first state when the first sampling period is greater than the second sampling period, and to control the second switch and the third switch The first multiplier has no input of the first normalized distance, and the second multiplier has an input of the second normalized distance; when the first sampling period is less than the second sampling period, the first is controlled The switch is in the second state, and by controlling the second switch and the third switch, the first multiplier has an input of a first normalized distance, and the second multiplier has no second normalized distance input of.

Preferably, the polyphase filter further includes: a plurality of sub-filter stages; a first switch is connected to an input end of each of the plurality of sub-filter stages, when the first switch is in the first state, The first stage of the plurality of sub-filter stages directly receives the first sample sequence, and other stages of the plurality of sub-filter stages except the first stage are directly connected to the output of the first multiplier Receiving, in a second state, the first one of the plurality of sub-filter stages receives the first sample sequence by an accumulator, wherein the plurality of sub-filter stages Other stages outside the first stage are connected to the output of the first multiplier by an accumulator;

All of the first multipliers are connected in series, and each of the first multipliers is connected to the second switch; the second switch is configured to control the first switch when the first switch is in the second state Input of a first normalized distance between the second sample sequence and the first sample sequence; the output of the last stage, the output of the last stage, and the input of the second multiplier Connected, an output of each of the plurality of sub-filter stages, except for the last stage, is connected to an input of the first adder, and the different first adders pass between a second multiplier connected in series, the output of each second multiplier being coupled to the input of the first adder, and the first adder coupled to the output of the first stage of the plurality of sub-filter stages The output is used to output the second sample sequence;

a third switch is connected to each of the second multipliers; the third switch is used to When the first switch is in the first state, the input of the second normalized distance between the second sample sequence and the first sample sequence is controlled.

Preferably, the conversion device, wherein the conversion filter in the polyphase filter is used to calculate a time domain impulse response using a formula;

Wherein, the number of segments of the time domain impulse response is an odd number, that is, w is an even number, and the highest power of the basis function M is an integer, and T is a segmentation period;

T) is a basis function;

Make the coefficients satisfy:

Preferably, the conversion device, wherein the polyphase filter is further configured to compare a ratio of the first sampling period to the second sampling period to L/M, and L and M are relatively prime a positive integer, and L is greater than M, controlling the first switch to be in the first state, and the second sample value of the mth sample time corresponds to the first sample value of the kth sample time, Where m is an integer, ^k = L ^mM / ^L+1 / ² J, and the second return between the second sample value at the mth sample time and the first sample value at the kth time is calculated The distance is:

_Mkl = mM/L- [mM/L+

And _0·5 ≤ _Al <0·5; wherein, L is the first sampling period; Μ is the second sampling period.

Preferably, the conversion device, wherein the polyphase filter is further configured to use a ratio of the first sample period to the second sample period to be L/M, and L and Μ are mutually prime a positive integer, and if L is less than Μ, controlling the first switch to be in a second state, the accumulator And an integral accumulation of the first sample value for accumulating the first sample value from the k1th sample time to the k2 sample time, wherein k1 < k2, the second time of the mth sample time The cumulative time corresponding to the sample value is:

Where L is the first sampling period;

M is the second sampling period.

Preferably, the conversion device, wherein the polyphase filter is further configured to calculate a second sample value of the mth sample time in the output signal and a kth sample time in the input signal The normalized distance between the first sample values is:

Where _{fe e} [H,fe ₂ ] ; L is the first sampling period; M is the second sampling period.

Preferably, the conversion device, wherein each sub-filter stage comprises: an even-order finite impulse response filter; and the coefficients of the even-order finite impulse response filter are oddly symmetric.

Preferably, the switching device, wherein, when the first switch is in the first state, the device further comprises: cascading an integer multiple of the interpolating finite impulse response filter in front of the polyphase filter.

Preferably, the switching device, wherein, when the first switch is in the second state, the device further comprises: cascading an integer multiple of the decimating finite impulse response filter after the polyphase filter.

In another aspect, a method for performing digital sample rate conversion using a digital sample rate conversion apparatus according to an embodiment of the present invention is provided for converting an input first sample sequence sequence having a first sample period to have a second sample sequence output of the second sample cycle, wherein the method includes: when the first sample cycle is greater than the second sample cycle, controlling the first switch to be in the first state, and by controlling the second switch and a third switch, such that the first multiplier has no input of a first normalized distance, and the second multiplier has an input of a second normalized distance; When the first sampling period is less than the second sampling period, controlling the first switch to be in the second state, and by controlling the second switch and the third switch, so that the first multiplier has a first normalized distance Input, there is no input of a second normalized distance on the second multiplier.

The method further includes: calculating a time domain impulse response of the conversion filter in the polyphase filter using a formula;

T) is a basis function;

0, t is another value such that the coefficient ^e »w satisfies: c

The technical effects of the present invention are:

By setting three switches, it is only necessary to control the state of the switch, which can realize the conversion of the sample rate during interpolation or extraction, and unify the structure of the interpolation filter and the structure of the decimation filter, which enhances the flexibility of the sample rate conversion device. , simplifies the hardware implementation architecture of the filter and improves data throughput

DRAWINGS

1 is a schematic diagram of the principle of the prior art sample rate conversion;

2 is a schematic structural diagram of a digital sample rate conversion device according to an embodiment of the present invention; FIG. 3 is a schematic structural diagram of a digital sample rate conversion device according to another embodiment of the present invention; FIG. Schematic diagram of the principle structure of the digital sampling rate conversion device FIG. 5 is a schematic structural diagram of a digital sample rate conversion apparatus according to still another embodiment of the present invention; FIG. 6 is a time domain impulse response diagram of a conversion filter in a Farrow filter according to still another embodiment of the present invention. detailed description

The present invention will be described in detail below with reference to the drawings and specific embodiments.

FIG. 2 is a schematic structural diagram of a digital sample rate conversion apparatus according to an embodiment of the present invention. The digital sampling rate conversion apparatus of the embodiment of the present invention is for converting the input first sample sequence sequence having the first sample period T _in to have the second sample period T. The second sample sequence of _ut , as shown in FIG. 2, includes: a polyphase filter 100, the polyphase filter further comprising:

a plurality of sub-filter stages, each of which is connected to a first switch (K1), wherein when the first switch is in the first state: the first of the plurality of sub-filter stages is directly Receiving the first sample sequence, the other stages of the plurality of sub-filter stages except the first stage are directly connected to the output end of a first multiplier 101; the first switch is in the second state The first stage of the plurality of sub-filter stages receives the first sample sequence by an accumulator, and the other stages of the plurality of sub-filter stages except the first stage pass an accumulation Connected to an output of the first multiplier;

All the first multipliers 101 are connected in series, and each of the first multipliers is connected with a second switch (K2) for controlling the control station when the first switch is in the second state. Inputting a first normalized distance μ _η between the second sample sequence and the first sample sequence;

The output of the last stage of the plurality of sub-filter stages is connected to the input of a second multiplier 102, and each of the other stages of the plurality of sub-filter stages except the last stage The output end is connected to the input end of a first adder 103, and the different first adders are connected in series by a second multiplier, the output end of each second multiplier and a first adder The input ends are connected, and the output of the first adder connected to the output of the first stage of the plurality of sub-filter stages is used to output the second sample sequence;

Each of the second multipliers is connected to a third switch (K3), and the third switch is configured to control the second sample sequence and the first when the first switch is in the first state The input of the second normalized distance ₂ between the sample sequence of values.

Exemplarily, as shown in FIG. 2, when the first switch K1 is in the first state, K1 is turned to the I direction, and the branch without the accumulator is turned on; when the first switch K1 is in the second state, K2 is dialed to the D direction. , the branch with the accumulator is switched on. In the implementation process of the embodiment of the present invention, when L is greater than M, K1 is turned to the I direction, so that the branch without the accumulator is turned on, and the second switch is turned on, and the third switch is closed. At this time, the polyphase filter is realized. Is an interpolation filter; when L is less than M, K1 is turned to the D direction, so that the branch with the accumulator is turned on, and the second switch is closed, and the third switch is turned on. At this time, the polyphase filter is implemented as a decimation type. filter.

As shown in Fig. 2, x ( k ), k is an integer representing the kth input signal, that is, the kth first sample value; y ( m ), m is an integer representing the output of the mth sample time The signal, that is, the mth second sample value.

Preferably, embodiments of the present invention provide a generalized Farrow filter based on a polynomial fit using a polyphase filter structure. The design of the universal Farrow filter unifies the classical filter structure and the transposed filter structure, and is only realized by the switching circuit for interpolation and extraction to increase the flexibility of the sample rate conversion device, and also simplifies the Farrow structure. Hardware structure.

In a specific implementation of the embodiment of the present invention, the plurality of first switches may be configured as a linkage switch; similarly, the plurality of second switches may also be configured as linkage switches, and the plurality of third switches may also be configured as linkage switches.

FIG. 3 is a schematic structural diagram of a digital sample rate conversion apparatus according to another embodiment of the present invention. In this embodiment of the invention, the time of the conversion filter in the Farrow filter based on the polynomial fit The domain impulse response expression is as follows:

N M

h(t) =∑∑c _m (n) f _m (n,T,t)

η=Ο ϊ?ρ=0

Wherein, the number of segments of the impulse response is an odd number, that is, w is an even number, Μ is an integer, and 分段 is a piecewise basis function: for r<t <(n+l)r

At the same time, the time domain response of the time domain low-pass filter satisfies the odd symmetry, even if the coefficients satisfy:

In a specific implementation, each of the sub-filter stages includes: an even-order finite impulse response filter, and the coefficients of the finite impulse response filter are oddly symmetric.

For the sampling rate conversion during interpolation and decimation, the traditional Farrow filter is implemented by the classical Farrow structure and the transposed Farrow structure, respectively, and in the present invention, only three switching circuits are used for interpolation and extraction. The sample rate conversion during interpolation and extraction is realized. The principle structure is shown in Figure 3. Let the sampling period of the input signal be the sampling period of the output signal is ^, and set ^{Τ Τ} . = ^L I ^M , where £ and A are two prime positive integers.

In this example, the specific technical solutions and implementation steps are as follows:

a, the general-purpose Farrow filter uses a (M+1) (N+1) polyphase filter structure, that is, there are a total of A + 1 sub-filter stages, and each filter stage includes a sub-filter, each sub-carrier The device is an FIR filter with a tap number of w+i, wherein the tap coefficients are oddly symmetric.

b, when the first sample period of the input first sample sequence is greater than the second sample period of the output second sample sequence, ie, >>, the interpolation is performed, and at this time, K3 is turned off and K2 is turned off, and Will K1 Pulling out in the I direction, the output signal of the mth sample time corresponds to the input signal X ( k ) which is the L-^ + i/2j sample time, and at this time, the normalized distance between the output signals is output. , can be expressed as _k ,

And satisfy _0·5 ≤ _Al < 0·5.

C, when the first sample period of the input first sample sequence is smaller than the second sample period of the output second sample sequence, that is, when <A, the extraction is performed, and at this time, K2 is closed and K3 is disconnected. K1 and pull in the direction D, in this state, from a first accumulator for accumulating achieve Bian kl th sample value of the time to preclude the kind of k2 preclude accumulating a first integrator samples preclude the sample time, wherein by ^Σ To indicate the integral accumulation process, that is, the pair is from kl ie 13⁄4. The input signal of the time is always accumulated and stored in the input signal of k2, that is, the time of the sample. Where kl < k2, that is, k^e^ kupp^ for the output of the first output, that is, the mth sample time, the corresponding accumulation time is:

(m_l/2) M/Le difficult set

― l^ M/L is not a difficult set

Where W and W respectively represent rounding up and up; indicating the normalized distance between the current output ^ and the first fe _e [Η, ] input signals, which can be expressed as ^

And satisfying -0.5 < μ, ₂ < 0.5 In the sampling rate conversion device of other embodiments of the present invention, preferably, for the sample rate conversion processing for performing interpolation, an integer multiple interpolation may be cascaded before the Farrow filter Finite Impulse Response (FIR) filter; for the sample rate conversion process for decimation, an integer multiple of the FIR filter can be cascaded after the Farrow filter to improve the Farrow filter when interpolating and extracting. Performance. Specifically, it can be referred to FIG. 4 and FIG. 5. In Figure 4, the Farrow filter is implemented as an interpolation filter. In Figure 5, the Farrow filter is implemented as a decimation filter.

The digital sample rate conversion device according to an embodiment of the present invention uses the structure of a general-purpose Farrow filter suitable for interpolation and extraction, and has the following main features: (1) The Farrow filter uses a polyphase filter structure of (M+l) (N+l); and the tap coefficients of the sub-filters in each sub-filter stage are odd, which is beneficial to the filtered signal. Timing reception; Secondly, each sub-filter uses an odd-symmetric FIR filter, which reduces the number of multipliers.

(2) The interpolation filtering and decimation filtering operations are realized by controlling the switching circuit. The advantages are firstly to unify the Farrow filter implementation structure and simplify the hardware implementation architecture. Secondly, for interpolation and extraction processing, the multiphase in the unified structure The filters are all operating at low sample rates, which increases data throughput.

(3) For the interpolation and decimation processing, the out-of-band suppression and the removal of the image can be improved by cascading the corresponding FIR filter, thereby improving the performance of the Farrow filter for interpolation and extraction processing.

The embodiment of the present invention further provides a method for performing digital sample rate conversion by using the digital sample rate conversion device of the above embodiments of the present invention, for inputting the first sample value having the first sample period The sequence is converted to a second sample sequence output having a second sample period, including the following steps:

Controlling the first switch to be in a first state when the first sampling period is greater than the second sampling period, and controlling the second and third switches such that there is no first normalized distance on the first multiplier Input, having an input of a second normalized distance on the second multiplier;

Controlling the first switch to be in a second state when the first sampling period is less than the second sampling period, and controlling the second and third switches such that the first multiplier has a first normalized distance The input has no input of a second normalized distance on the second multiplier.

The embodiment of the present invention further provides a method for performing digital sample rate conversion by using the digital sample rate conversion device of the above embodiments of the present invention, for inputting the first sample value having the first sample period Converting the sequence to a second sample sequence output having a second sample period, wherein the method is; The time domain impulse response expression of the conversion filter in the polyphase filter is as follows:

N M

h(t) =∑∑c _m (n)f _m (n,T,t)

η=Ο ϊ?ρ=0

Wherein, the number of segments of the impulse response is an odd number, that is, w is an even number, Μ is an integer, and Τ is a segmentation period;

The basis function is:

Make the coefficients satisfy:

-n) m is ί^

, , ^ n = N/2+l,...,N

-c _m (Nn) m is a mine. The embodiment of the present invention provides a general method and apparatus for sampling rate conversion (SRC) in digital signal processing, using a polynomial-based SRC filter structure principle. Combining the classic Farrow filter suitable for interpolation and the transposed Farrow filter suitable for decimation into a unified filter structure, the interpolation and extraction are only realized by the switching circuit to increase the flexibility of the sample rate conversion, and the simplified The hardware implementation architecture improves the data throughput; and because the even-order FIR filter is used as the sub-filter, it facilitates the filtered symbol timing reception; further, since the coefficients of the sub-carrier are odd-symmetric, the multiplication is performed. The number of devices is reduced by half; finally, the performance of the Farrow filter for interpolation and decimation can be improved by a cascaded FIR filter.

The specific application of the digital sampling rate conversion apparatus and method of the embodiment of the present invention will be described below. Specifically, in the digital intermediate frequency processing chip project, the downlink digital up-conversion (DUC) processing module needs to up-convert the baseband signals formed by various standards to a fixed sampling rate, and the processing at this time can be passed. The conversion device of the present invention implements an interpolation filtering process; the uplink digital down conversion (DDC) processing module requires a high sampling rate of various modes. Transforming to the respective baseband sampling rate, the processing at this time can implement the decimation filtering process by the conversion device of the present invention. The specific implementation steps are as follows:

6 is a time-domain response diagram of a conversion filter in a Farrow filter according to an embodiment of the present invention, where N=10 and M=4, that is, the Farrow filter is a 釆5×11 polyphase filter structure.

In the DUC processing module, the baseband signals formed by various standards are first subjected to 2x interpolation transformation through a half-band filter; then, the interpolation processing is performed by the Farrow filter to convert to the desired sampling rate, wherein the Farrow filter is used. The relevant steps when performing the interpolation process can be referred to the process of L>M described above.

In the DDC processing module, the received signals of various standards for the input at a higher sampling rate are first extracted by the Farrow filter, and the output sampling rate is twice the required sampling rate; then the half-band filtering is performed. The device performs a 2-fold decimation transformation to the desired sampling rate, and the relevant steps when the Farrow filter performs the decimation processing can be referred to the processing at the time of L < M described above.

The above description is only a preferred embodiment of the present invention, and it should be noted that those skilled in the art can also make several improvements and retouchings without departing from the principles of the present invention. It is considered as the scope of protection of the present invention.

Claims

Claim

A digital sample rate conversion device for converting an input first sample sequence sequence having a first sample period into a second sample sequence output having a second sample period, wherein The device includes a polyphase filter, and a first switch, a second switch, and a third switch disposed in the polyphase filter;

2. The conversion apparatus according to claim 1, wherein the polyphase filter further comprises: a plurality of sub-filter stages; and the input ends of each of the plurality of sub-filter stages are connected to the first a first stage of the plurality of sub-filter stages directly receiving the first sample sequence, wherein the first stage is divided by the first stage The other stages are directly connected to the output of the first multiplier; when the first switch is in the second state, the first one of the plurality of sub-filter stages receives the first sample sequence by the accumulator, Among the plurality of sub-filter stages, other stages than the first stage are connected to an output end of the first multiplier by an accumulator;

All first multipliers are connected in series, and each of the first multipliers is connected to the second switch; the second switch is configured to control the second switch when the first switch is in the second state An input of a first normalized distance between the sample sequence of values and the sequence of first sample values;

The output of the last stage of the plurality of sub-filter stages is connected to the input of the second multiplier, and the output of each of the other stages of the plurality of sub-filter stages except the last stage The end is connected to the input end of the first adder, and the different first adders pass the second multiplication The detectors are connected in series, the output of each second multiplier is connected to the input of the first adder, and the output of the first adder connected to the output of the first stage of the plurality of sub-filter stages The end is configured to output the second sample sequence of values;

a third switch is connected to each of the second multipliers; the third switch is configured to control the second sample sequence and the first sample value when the first switch is in the first state The input of the second normalized distance between the sequences.

The conversion device according to claim 2, wherein the polyphase filter further comprises: a conversion filter; and the conversion filter is used for a formula

N M calculates the time domain impulse response;

Wherein, the number of segments of the time domain impulse response is an odd number, and T is a segmentation period;

/ T ) is a basis function;

The conversion device according to claim 2, wherein the polyphase filtering is further configured to use a ratio of the first sample period to the second sample period to be L/M, L and M is a positive positive integer, and when L is greater than M, the first switch is controlled to be in the first state, and the second sample value of the mth sample time corresponds to the first time of the kth sample time The sample value, where m is an integer, fc = M/£+i/ ² ”, calculates the relationship between the second sample value of the first „! sample time and the first sample value at the _kth time The second normalized distance is:

a = mM/L- [mM/L+

And _0·5 ≤ _Al <0·5; wherein, L is the first sampling period; The second sampling cycle.

The conversion device according to claim 2, wherein the polyphase filter is further configured to use a ratio of the first sample period to the second sample period to be L/M, L And M is a positive positive integer, and L is less than M, the first switch is controlled to be in a second state, and the accumulator is configured to implement the first sample value from the k1th sample time to be added to the first The integral accumulation of the first sample value at k2 sample times, where kl < k2, the cumulative time corresponding to the second sample value at the mth sample time is:

Where L is the first sampling period;

M is the second sampling period.

The conversion device according to claim 5, wherein the polyphase filter is further configured to calculate a second sample value of the mth sample time and an kth of the input signal in the output signal The normalized distance between the first sample values at the time of the sample is:

Where [H, fe 2 ] ; L is the first sampling period; M is the second sampling period.

7. The conversion apparatus according to claim 2, wherein each of the sub-filter stages comprises: an even-order finite impulse response filter; and the coefficients of the even-order finite impulse response filter are oddly symmetric.

8. The conversion device according to claim 2, wherein, when the first switch is in the first state, the device further comprises: cascading an integer multiple of the interpolation finite impulse response filter in front of the polyphase filter Device.

The conversion device according to claim 2, wherein, when the first switch is in the second state, the device further comprises: cascading an integer multiple of the finite impulse response filter after the polyphase filter Device.

10. A method for converting a digital sample rate, the method comprising: When the first sampling period is greater than the second sampling period, controlling the first switch to be in the first state, and by controlling the second switch and the third switch, so that the first multiplier has no input of the first normalized distance, An input having a second normalized distance on the second multiplier;

When the first sampling period is less than the second sampling period, controlling the first switch to be in the second state, and by controlling the second switch and the third switch, the first multiplier has the input of the first normalized distance, There is no input of the second normalized distance on the second multiplier.

11. The conversion method according to claim 10, wherein the method further comprises: using a formula

Calculating the time domain impulse response of the conversion filter in the polyphase filter;

/„^,r, is the basis function;

Make the coefficients satisfy: