WO2012008067A1 - Semiconductor storage device and method for manufacturing same - Google Patents

Semiconductor storage device and method for manufacturing same Download PDF

Info

Publication number
WO2012008067A1
WO2012008067A1 PCT/JP2011/000642 JP2011000642W WO2012008067A1 WO 2012008067 A1 WO2012008067 A1 WO 2012008067A1 JP 2011000642 W JP2011000642 W JP 2011000642W WO 2012008067 A1 WO2012008067 A1 WO 2012008067A1
Authority
WO
WIPO (PCT)
Prior art keywords
impurity
conductivity type
semiconductor region
impurity layer
layer
Prior art date
Application number
PCT/JP2011/000642
Other languages
French (fr)
Japanese (ja)
Inventor
高橋信義
荒井雅利
Original Assignee
パナソニック株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Publication of WO2012008067A1 publication Critical patent/WO2012008067A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

Definitions

  • Each bit line diffusion layer 12 is formed by ion implantation in a region of the semiconductor substrate 10 where the ONO film is removed, and a bit line insulating film 50 is formed on each bit line diffusion layer 12.
  • channel regions 15 are formed between the bit line diffusion layers 12 in the semiconductor substrate 10.
  • the first resist pattern 115 is removed by ashing or the like. Thereafter, a heat treatment is performed on the semiconductor substrate 101 in an oxidizing atmosphere by, for example, a thermal oxidation method to form the bit line insulating films 109 on the respective bit line diffusion layers 108.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

Disclosed is a semiconductor storage device (100) which has: a plurality of bit line diffusion layers (108) which are formed to extend in parallel to each other in the upper portion of a P-type semiconductor substrate (101); and a plurality of word line electrodes (110) which are respectively formed to extend parallel to each other in the direction that intersects the bit line diffusion layers (108) on the semiconductor substrate (101). Furthermore, in a region below the word line electrodes (110) on the semiconductor substrate (101), a plurality of P-type third impurity layers (111A) having a concentration lower than that of the periphery are formed in a self-aligned manner.

Description

半導体記憶装置及びその製造方法Semiconductor memory device and manufacturing method thereof
　本発明は、半導体記憶装置及びその製造方法に関し、特にビット線拡散層とその上に交差して形成されたワード線電極とを有する半導体記憶装置及びその製造方法に関する。 The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly to a semiconductor memory device having a bit line diffusion layer and a word line electrode formed intersecting thereon and a method for manufacturing the same.
　ビット線拡散層とそれと交差するワード線電極とを有する半導体記憶装置は、メモリセルの面積を低減する上で優れた構造を持つことから、より一層の微細化の進行に伴い重要度を増してきている。さらに、本構造を採る半導体記憶装置において、さらなる微細化の進行と信頼性の改善とを両立することが求められている。 A semiconductor memory device having a bit line diffusion layer and a word line electrode intersecting with the bit line diffusion layer has an excellent structure for reducing the area of the memory cell. ing. Furthermore, in the semiconductor memory device adopting this structure, it is required to achieve both the progress of further miniaturization and the improvement of reliability.
　図８（ａ）及び図８（ｂ）にビット線に拡散層構造を有する従来の半導体記憶装置について説明する（例えば、特許文献１を参照。）。 8A and 8B illustrate a conventional semiconductor memory device having a diffusion layer structure on a bit line (see, for example, Patent Document 1).
　図８（ａ）及び図８（ｂ）に示すように、従来の半導体記憶装置は、半導体基板１０の上部に互いに並行に延びるように形成された複数のビット線拡散層１２と、該複数のビット線拡散層１２の上にそれぞれ交差し且つ互いに並行に延びるように形成された複数のワード線電極６０とを有している。さらに、ワード線電極６０と半導体基板１０との間には、電荷保持膜である上部酸化物層２０、窒化物層１７及び下部酸化物層１８の積層構造よりなるＯＮＯ（oxide-nitride-oxide）膜が形成されている。各ビット線拡散層１２は、半導体基板１０におけるＯＮＯ膜が除去された領域にイオン注入により形成され、各ビット線拡散層１２の上には、ビット線絶縁膜５０がそれぞれ形成されている。ここで、半導体基板１０における各ビット線拡散層１２同士の間には、それぞれチャネル領域１５が形成される。 As shown in FIGS. 8A and 8B, the conventional semiconductor memory device includes a plurality of bit line diffusion layers 12 formed on the semiconductor substrate 10 so as to extend in parallel with each other, and the plurality of bit line diffusion layers 12. A plurality of word line electrodes 60 are formed on the bit line diffusion layer 12 so as to intersect with each other and extend in parallel to each other. Further, between the word line electrode 60 and the semiconductor substrate 10, an ONO (oxide-nitride-oxide) having a stacked structure of an upper oxide layer 20, a nitride layer 17, and a lower oxide layer 18 that are charge holding films. A film is formed. Each bit line diffusion layer 12 is formed by ion implantation in a region of the semiconductor substrate 10 where the ONO film is removed, and a bit line insulating film 50 is formed on each bit line diffusion layer 12. Here, channel regions 15 are formed between the bit line diffusion layers 12 in the semiconductor substrate 10.
特開２００１－０７７２２０号公報JP 2001-072220 A
　ところで、前記従来の半導体記憶装置は、チャネル領域の不純物プロフィル（チャネルプロファイル）に関して、特に言及されていない。 Incidentally, the conventional semiconductor memory device is not particularly referred to regarding the impurity profile (channel profile) of the channel region.
　しかしながら、メモリセル構造が微細化されると、ＭＯＮＯＳ（metal oxide-nitride-oxide semiconductor）型メモリ装置の代表的な書き込み方式であるＣＨＥ（channel hot electron）書き込みを行う際に、半導体基板内での２次インパクトイオン化により発生する２次電子が、ＯＮＯ膜におけるチャネル領域の中央部付近にトラップされる。ＯＮＯ膜にトラップされた２次電子は、例えば消去及び書き込み回数と不良ビットの出現との関係を表すエンデュランス特性や、データ保持特性であるリテンション特性を悪化させるという問題がある。 However, when the memory cell structure is miniaturized, when CHE (channel hot ion) writing, which is a typical writing method of a MONOS (metal oxide-nitride-oxide semiconductor) type memory device, is performed in a semiconductor substrate. Secondary electrons generated by secondary impact ionization are trapped near the center of the channel region in the ONO film. The secondary electrons trapped in the ONO film have a problem that the endurance characteristic indicating the relationship between the number of times of erasing and writing and the appearance of defective bits and the retention characteristic which is a data retention characteristic are deteriorated.
　また、書き込み時にＯＮＯ膜のチャネル中央部付近に電子がトラップされると、代表的な消去方法であるＢＴＢＴ（band to band tunneling）ホール注入を行う際に、多量のホールを注入する必要がある。これにより、ドレイン拡散層の上に余剰のホールが生じ、多回数の書き換え動作を繰り返す際に消去速度が遅くなって、エンデュランス特性が劣化する。 In addition, when electrons are trapped near the center of the channel of the ONO film during writing, it is necessary to inject a large amount of holes when performing BTBT (band-to-band-tunneling) hole injection, which is a typical erasing method. As a result, surplus holes are generated on the drain diffusion layer, and the erasure speed becomes slow when the rewrite operation is repeated many times, and the endurance characteristics deteriorate.
　また、書き込み状態において、書き込み電子と余剰のホールとが再結合することにより、リテンション特性が劣化する。 Also, in the written state, the retention characteristics deteriorate due to recombination of write electrons and surplus holes.
　このように、半導体基板内での２次インパクトイオン化により発生する２次電子を抑制することにより、エンデュランス特性及びリテンション特性等の信頼性を改善することがＭＯＮＯＳ型メモリ装置の微細化において重要となる。 As described above, it is important for miniaturization of the MONOS memory device to improve the reliability such as the endurance characteristic and the retention characteristic by suppressing the secondary electrons generated by the secondary impact ionization in the semiconductor substrate. .
　本発明は、前記の問題に鑑み、ビット線に拡散層を用いる半導体記憶装置のチャネル領域に発生する２次電子を抑制して、記憶装置としての信頼性を向上できるようにすることにある。 In view of the above problems, the present invention is to improve the reliability of a memory device by suppressing secondary electrons generated in the channel region of a semiconductor memory device using a diffusion layer for a bit line.
　前記の目的を達成するため、本発明は、半導体記憶装置を、半導体基板における２次インパクトイオン化が生じる領域の基板キャリア濃度を低減する構成とする。 To achieve the above object, according to the present invention, a semiconductor memory device is configured to reduce the substrate carrier concentration in a region where secondary impact ionization occurs in a semiconductor substrate.
　具体的に、本発明に係る半導体記憶装置は、第１導電型の半導体領域の上部にそれぞれが互いに並行に延びるように形成された複数のビット線拡散層と、半導体領域の上で、且つそれぞれが各ビット線拡散層と交差する方向に互いに並行に延びるように形成された複数のワード線電極と、半導体領域における各ワード線電極の下方の領域にそれぞれ自己整合的に形成され、周囲よりも濃度が低い第１導電型の複数の第１の不純物層とを備えている。 Specifically, the semiconductor memory device according to the present invention includes a plurality of bit line diffusion layers formed on the first conductivity type semiconductor region so as to extend in parallel with each other, and on the semiconductor region, respectively. Are formed in a self-aligned manner in a plurality of word line electrodes formed so as to extend in parallel with each other in a direction intersecting with each bit line diffusion layer, and in a region below each word line electrode in the semiconductor region, A plurality of first impurity layers of a first conductivity type having a low concentration.
　本発明の半導体記憶装置によると、半導体領域における各ワード線電極の下方の領域にそれぞれ自己整合的に形成され、周囲よりも濃度が低い第１導電型の複数の第１の不純物層を備えている。すなわち、第１導電型の半導体領域において、書き込み動作時に２次インパクトイオン化が起こる領域に、周囲よりも濃度が低い第１導電型の複数の第１の不純物層を設けているため、２次インパクトイオン化が起こる領域のキャリア濃度が低減されて電界が緩和されることにより、２次電子の発生量を抑制することができる。その結果、エンデュランス特性及びリテンション特性等のメモリの信頼性を向上することができる。 According to the semiconductor memory device of the present invention, the semiconductor memory device includes the plurality of first impurity layers of the first conductivity type that are formed in a self-aligned manner in the region below each word line electrode in the semiconductor region and have a lower concentration than the surroundings. Yes. In other words, in the first conductivity type semiconductor region, a plurality of first impurity layers of the first conductivity type having a lower concentration than the surroundings are provided in a region where secondary impact ionization occurs during the write operation, so that the secondary impact is provided. The amount of secondary electrons generated can be suppressed by reducing the carrier concentration in a region where ionization occurs and relaxing the electric field. As a result, the reliability of the memory such as endurance characteristics and retention characteristics can be improved.
　本発明の半導体記憶装置は、半導体領域における各ワード線電極同士の間の下方の領域にそれぞれ自己整合的に形成され、周囲よりも濃度が低い第１導電型の複数の第２の不純物層をさらに備え、第１の不純物層と第２の不純物層との互いの不純物濃度は同等であり、半導体領域において、複数の第２の不純物層は、複数の第１の不純物層よりも深く形成されていることが好ましい。 The semiconductor memory device according to the present invention includes a plurality of second impurity layers of the first conductivity type formed in a self-aligned manner in regions below the respective word line electrodes in the semiconductor region and having a lower concentration than the surroundings. Further, the first impurity layer and the second impurity layer have the same impurity concentration, and the plurality of second impurity layers are formed deeper than the plurality of first impurity layers in the semiconductor region. It is preferable.
　本発明の半導体記憶装置において、第１の不純物層の濃度ピークは、半導体領域の主面から５０ｎｍ以上且つ１５０ｎｍ以下の深さに設定されていることが好ましい。 In the semiconductor memory device of the present invention, the concentration peak of the first impurity layer is preferably set to a depth of 50 nm or more and 150 nm or less from the main surface of the semiconductor region.
　本発明の半導体記憶装置において、第２の不純物層の濃度ピークは、半導体領域の主面から２５０ｎｍ以上且つ４００ｎｍ以下の深さに設定されていることが好ましい。 In the semiconductor memory device of the present invention, the concentration peak of the second impurity layer is preferably set to a depth of 250 nm or more and 400 nm or less from the main surface of the semiconductor region.
　本発明の半導体記憶装置において、半導体領域における第１導電型の不純物濃度は、第２の不純物層を含む領域が他の領域と比べて高くなるように設定されていることが好ましい。 In the semiconductor memory device of the present invention, it is preferable that the impurity concentration of the first conductivity type in the semiconductor region is set so that the region including the second impurity layer is higher than the other regions.
　本発明の半導体記憶装置は、半導体領域と各ワード線電極との間に形成され、下から順次形成された下部シリコン酸化膜、シリコン窒化膜及び上部シリコン酸化膜からなるゲート絶縁膜をさらに備えていることが好ましい。 The semiconductor memory device according to the present invention further includes a gate insulating film formed between a semiconductor region and each word line electrode, and sequentially formed from the bottom and made of a lower silicon oxide film, a silicon nitride film, and an upper silicon oxide film. Preferably it is.
　本発明に係る半導体記憶装置の製造方法は、半導体領域に第１導電型の第１の不純物層を形成する工程（ａ）と、半導体領域における第１の不純物層の下に、第１導電型の第２の不純物層を形成する工程（ｂ）と、半導体領域の上に、電荷蓄積層を有するゲート絶縁膜を形成する工程（ｃ）と、形成されたゲート絶縁膜に対して互いに並行に延びる複数の開口部を選択的に形成する工程（ｄ）と、半導体領域における各開口部から露出する領域に、それぞれビット線拡散層を形成する工程（ｅ）と、形成された各ビット線拡散層の上にそれぞれビット線絶縁膜を形成する工程（ｆ）と、ゲート絶縁膜及びビット線絶縁膜を含む半導体領域の上で、且つ各ビット線拡散層と交差する方向に互いに並行に延びる複数のワード線電極を選択的に形成する工程（ｇ）と、各ワード線電極及びゲート絶縁膜をマスクとして、半導体領域に対して、第２導電型の不純物を注入することにより、半導体領域における各ワード線電極の下方の領域に、周囲の第１導電型の第１の不純物層における第１導電型の不純物濃度よりも不純物濃度が低い第１導電型の複数の第３の不純物層を形成すると共に、半導体領域における各ワード線電極同士の間の下方の領域に、周囲の第１導電型の第２の不純物層における第１導電型の不純物濃度よりも不純物濃度が低い第１導電型の複数の第４の不純物層を形成する工程（ｈ）とを備えている。 The method of manufacturing a semiconductor memory device according to the present invention includes a step (a) of forming a first impurity layer of a first conductivity type in a semiconductor region, and a first conductivity type below the first impurity layer in the semiconductor region. The step (b) of forming the second impurity layer, the step (c) of forming a gate insulating film having a charge storage layer on the semiconductor region, and the formed gate insulating film in parallel with each other A step (d) of selectively forming a plurality of extending openings, a step (e) of forming a bit line diffusion layer in a region exposed from each opening in the semiconductor region, and each bit line diffusion formed A step (f) of forming a bit line insulating film on each layer, and a plurality of portions extending in parallel with each other in a direction intersecting with each bit line diffusion layer on the semiconductor region including the gate insulating film and the bit line insulating film Select word line electrodes selectively Step (g), and by implanting a second conductivity type impurity into the semiconductor region using each word line electrode and the gate insulating film as a mask, in the region below each word line electrode in the semiconductor region, Forming a plurality of third impurity layers of the first conductivity type having an impurity concentration lower than the impurity concentration of the first conductivity type in the surrounding first impurity layer of the first conductivity type, and each word line electrode in the semiconductor region; A plurality of fourth impurity layers of the first conductivity type whose impurity concentration is lower than the impurity concentration of the first conductivity type in the surrounding second impurity layer of the first conductivity type are formed in a lower region between them. Step (h).
　本発明の半導体記憶装置の製造方法によると、ワード線電極を形成した後、形成された各ワード線電極及びゲート絶縁膜をマスクとして、半導体領域に対して、第２導電型の不純物を注入することにより、半導体領域における各ワード線電極の下方の領域に、周囲の第１導電型の第１の不純物層における第１導電型の不純物濃度よりも不純物濃度が低い第１導電型の複数の第３の不純物層を形成すると共に、半導体領域における各ワード線電極同士の間の下方の領域に、周囲の第１導電型の第２の不純物層における第１導電型の不純物濃度よりも不純物濃度が低い第１導電型の複数の第４の不純物層を形成する。すなわち、書き込み動作時に２次インパクトイオン化が起こる領域に、それぞれ周囲よりも濃度が低い第１導電型の複数の第３の不純物層及び複数の第４の不純物層を形成するため、２次インパクトイオン化が起こる領域のキャリア濃度が低減されて電界が緩和される。このため、２次電子の発生量を抑制することができるので、エンデュランス特性及びリテンション特性等のメモリの信頼性を向上することができる。 According to the method for manufacturing a semiconductor memory device of the present invention, after the word line electrode is formed, a second conductivity type impurity is implanted into the semiconductor region using the formed word line electrode and the gate insulating film as a mask. As a result, a plurality of first conductivity type first impurity types having a lower impurity concentration than the first conductivity type impurity concentration in the surrounding first conductivity type first impurity layer are formed in a region below each word line electrode in the semiconductor region. 3 impurity layer is formed, and the impurity concentration in the lower region between the word line electrodes in the semiconductor region is higher than the impurity concentration of the first conductivity type in the surrounding second impurity layer of the first conductivity type. A plurality of fourth impurity layers having a low first conductivity type are formed. That is, secondary impact ionization is performed in order to form a plurality of third impurity layers and a plurality of fourth impurity layers of the first conductivity type having lower concentrations than the surroundings in regions where secondary impact ionization occurs during the write operation. The carrier concentration in the region where the occurrence occurs is reduced and the electric field is relaxed. For this reason, since the generation amount of the secondary electrons can be suppressed, the reliability of the memory such as the endurance characteristic and the retention characteristic can be improved.
　本発明の半導体記憶装置の製造方法は、工程（ｈ）において、第２導電型の不純物は、第３の不純物層の濃度ピークが半導体領域の主面から５０ｎｍ以上且つ１５０ｎｍ以下の深さとなるエネルギーで注入することが好ましい。 In the method for manufacturing a semiconductor memory device of the present invention, in the step (h), the second conductivity type impurity is such that the concentration peak of the third impurity layer has a depth of 50 nm or more and 150 nm or less from the main surface of the semiconductor region. It is preferable to inject by.
　本発明の半導体記憶装置の製造方法は、工程（ｈ）において、第２導電型の不純物は、第４の不純物層の濃度ピークが半導体領域の主面から２５０ｎｍ以上且つ４００ｎｍ以下の深さとなるエネルギーで注入することが好ましい。 In the method for manufacturing a semiconductor memory device of the present invention, in the step (h), the second conductivity type impurity is such that the concentration peak of the fourth impurity layer has a depth of 250 nm or more and 400 nm or less from the main surface of the semiconductor region. It is preferable to inject by.
　本発明の半導体記憶装置の製造方法は、工程（ｂ）において、第２の不純物層は、第４の不純物層が形成される領域に、第１導電型の不純物濃度のピークが位置するように形成することが好ましい。 In the method for manufacturing a semiconductor memory device of the present invention, in the step (b), the second impurity layer is arranged such that the peak of the first conductivity type impurity concentration is located in the region where the fourth impurity layer is formed. It is preferable to form.
　本発明に係る半導体記憶装置及びその製造方法によると、チャネル領域に発生する２次電子が抑制されて、記憶装置としての信頼性を向上することができる。 According to the semiconductor memory device and the manufacturing method thereof according to the present invention, secondary electrons generated in the channel region are suppressed, and the reliability as the memory device can be improved.
図１は本発明の一実施形態に係る半導体記憶装置を示す模式的な平面図である。FIG. 1 is a schematic plan view showing a semiconductor memory device according to an embodiment of the present invention. 図２（ａ）及び図２（ｂ）は本発明の一実施形態に係る半導体記憶装置を示し、図２（ａ）は図１のＡ－Ａ線における断面図であり、図２（ｂ）は図１のＢ－Ｂ線における断面図である。2A and 2B show a semiconductor memory device according to an embodiment of the present invention. FIG. 2A is a cross-sectional view taken along the line AA in FIG. 1, and FIG. FIG. 2 is a cross-sectional view taken along line BB in FIG. 図３（ａ）及び図３（ｂ）は本発明の一実施形態に係る半導体記憶装置の製造方法の一工程を示し、図３（ａ）は図１のＡ－Ａ線と対応する断面図であり、図３（ｂ）は図１のＢ－Ｂ線と対応する断面図である。3A and 3B show a step of the method of manufacturing the semiconductor memory device according to the embodiment of the present invention, and FIG. 3A is a cross-sectional view corresponding to the line AA in FIG. FIG. 3B is a cross-sectional view corresponding to the line BB in FIG. 図４（ａ）及び図４（ｂ）は本発明の一実施形態に係る半導体記憶装置の製造方法の一工程を示し、図４（ａ）は図１のＡ－Ａ線と対応する断面図であり、図４（ｂ）は図１のＢ－Ｂ線と対応する断面図である。4A and 4B show one step of the method of manufacturing the semiconductor memory device according to the embodiment of the present invention, and FIG. 4A is a cross-sectional view corresponding to the line AA in FIG. FIG. 4B is a cross-sectional view corresponding to the line BB in FIG. 図５（ａ）及び図５（ｂ）は本発明の一実施形態に係る半導体記憶装置の製造方法の一工程を示し、図５（ａ）は図１のＡ－Ａ線と対応する断面図であり、図５（ｂ）は図１のＢ－Ｂ線と対応する断面図である。5A and 5B show a step of the method of manufacturing the semiconductor memory device according to the embodiment of the present invention, and FIG. 5A is a cross-sectional view corresponding to the line AA in FIG. FIG. 5B is a cross-sectional view corresponding to the line BB in FIG. 図６（ａ）及び図６（ｂ）は本発明の一実施形態に係る半導体記憶装置の製造方法の一工程を示し、図６（ａ）は図１のＡ－Ａ線と対応する断面図であり、図６（ｂ）は図１のＢ－Ｂ線と対応する断面図である。6A and 6B show a step of the method of manufacturing the semiconductor memory device according to the embodiment of the present invention, and FIG. 6A is a cross-sectional view corresponding to the line AA in FIG. FIG. 6B is a cross-sectional view corresponding to the line BB in FIG. 図７（ａ）及び図７（ｂ）は本発明の一実施形態に係る半導体記憶装置の製造方法の一工程を示し、図７（ａ）は図１のＡ－Ａ線と対応する断面図であり、図７（ｂ）は図１のＢ－Ｂ線と対応する断面図である。7A and 7B show a step of the method of manufacturing the semiconductor memory device according to the embodiment of the present invention, and FIG. 7A is a cross-sectional view corresponding to the line AA in FIG. FIG. 7B is a cross-sectional view corresponding to the line BB in FIG. 図８（ａ）及び図８（ｂ）は従来例に係るビット線拡散層構造を有する半導体記憶装置を示し、図８（ａ）は模式的な平面図であり、図８（ｂ）は図８（ａ）のVIIIｂ－VIIIｂ線における模式的な断面図である。8A and 8B show a conventional semiconductor memory device having a bit line diffusion layer structure, FIG. 8A is a schematic plan view, and FIG. 8B is a diagram. FIG. 8A is a schematic sectional view taken along line VIIIb-VIIIb in FIG.
　（一実施形態）
　本発明の一実施形態について図１、図２（ａ）及び図２（ｂ）を参照しながら説明する。 (One embodiment)
An embodiment of the present invention will be described with reference to FIG. 1, FIG. 2 (a) and FIG. 2 (b).
　図１、図２（ａ）及び図２（ｂ）に示すように、本実施形態に係る半導体記憶装置１００は、半導体基板１０１の上部に形成された、例えばＰ型の第１の不純物層１０２と、該第１の不純物層１０２の下に形成され、複数のメモリセル同士を互いに絶縁するＰ型の第２の不純物層１０３とを有している。ここで、第２の不純物層１０３は、その不純物濃度が第１の不純物層１０２の不純物濃度よりも高くなるように形成されている。 As shown in FIGS. 1, 2A, and 2B, the semiconductor memory device 100 according to this embodiment includes, for example, a P-type first impurity layer 102 formed on the semiconductor substrate 101. And a P-type second impurity layer 103 which is formed under the first impurity layer 102 and insulates a plurality of memory cells from each other. Here, the second impurity layer 103 is formed so that its impurity concentration is higher than that of the first impurity layer 102.
　第１の不純物層１０２の上部には、複数のビット線拡散層１０８が一の方向に互いに間隔をおいて並行に延びるように形成されている。また、第１の不純物層１０２の上であって、各ビット線拡散層１０８同士の間及び各ビット線拡散層１０８の両側部を含む領域に、ＯＮＯ膜であるゲート絶縁膜１０７が形成されている。ゲート絶縁膜１０７は、下から順次形成された下部シリコン酸化膜１０４、シリコン窒化膜１０５及び上部シリコン酸化膜１０６から構成されている。 A plurality of bit line diffusion layers 108 are formed on the upper portion of the first impurity layer 102 so as to extend in parallel in one direction at intervals. Further, a gate insulating film 107 which is an ONO film is formed on the first impurity layer 102 in a region including between the bit line diffusion layers 108 and on both sides of each bit line diffusion layer 108. Yes. The gate insulating film 107 includes a lower silicon oxide film 104, a silicon nitride film 105, and an upper silicon oxide film 106 that are sequentially formed from the bottom.
　各ビット線拡散層１０８の上で且つゲート絶縁膜１０７の開口部の上には、それぞれ中央部が膨らんだ断面楕円状のビット線絶縁膜１０９が形成されている。さらに、ゲート絶縁膜１０７及び各ビット線絶縁膜１０９の上で且つ各ビット線絶縁膜１０９と交差する方向には、例えばポリシリコンからなる複数のワード線電極１１０が互いに間隔をおいて並行に延びるように形成されている。 On each bit line diffusion layer 108 and on the opening of the gate insulating film 107, a bit line insulating film 109 having an elliptical cross section with a swelled center is formed. Further, on the gate insulating film 107 and each bit line insulating film 109 and in a direction intersecting with each bit line insulating film 109, a plurality of word line electrodes 110 made of, for example, polysilicon extend in parallel at intervals. It is formed as follows.
　本実施形態の特徴として、Ｐ型の第１の不純物層１０２における各ワード線電極１１０の下方の領域には、周囲のＰ型の第１の不純物層１０２におけるＰ型の不純物濃度よりも不純物濃度が低いＰ型の第３の不純物層１１１Ａがそれぞれ自己整合的に形成されている。さらに、Ｐ型の第２の不純物層１０３における各ワード線電極１１０同士の間の下方の領域には、周囲のＰ型の第２の不純物層１０３におけるＰ型の不純物濃度よりも不純物濃度が低いＰ型の第４の不純物層１１１Ｂがそれぞれ自己整合的に形成されている。また、第４の不純物層１１１Ｂは、第３の不純物層１１１Ａよりも深い位置に形成されている。 As a feature of the present embodiment, the region below each word line electrode 110 in the P-type first impurity layer 102 has an impurity concentration higher than the P-type impurity concentration in the surrounding P-type first impurity layer 102. P-type third impurity layers 111A having low self-alignment are formed in a self-aligned manner. Further, in the region between the word line electrodes 110 in the P-type second impurity layer 103, the impurity concentration is lower than the P-type impurity concentration in the surrounding P-type second impurity layer 103. P-type fourth impurity layers 111B are formed in a self-aligned manner. Further, the fourth impurity layer 111B is formed at a deeper position than the third impurity layer 111A.
　以下、前記のように構成された半導体記憶装置１００の製造方法の一例について図３～図７を参照しながら説明する。 Hereinafter, an example of a manufacturing method of the semiconductor memory device 100 configured as described above will be described with reference to FIGS.
　まず、図３（ａ）及び図３（ｂ）に示すように、例えばＰ型の半導体基板１０１の上部に、Ｐ型の不純物であるホウ素（Ｂ＋）イオンを注入して、Ｐ型の第１の不純物層１０２を形成する。続いて、半導体基板１０１の主面から第１の不純物層１０２の下側にホウ素（Ｂ＋）イオンを注入して、該第１の不純物層１０２よりも不純物濃度が高いＰ型の第２の不純物層１０３を形成する。ここでは、第１の不純物層１０２及び第２の不純物層１０３を併せて、Ｐ型不純物領域と呼ぶ。なお、第１の不純物層１０２と第２の不純物層１０３との形成順序は特に問われない。 First, as shown in FIGS. 3A and 3B, boron (B + ) ions, which are P-type impurities, are implanted into, for example, an upper portion of a P-type semiconductor substrate 101 to form P-type first. One impurity layer 102 is formed. Subsequently, boron (B + ) ions are implanted into the lower surface of the first impurity layer 102 from the main surface of the semiconductor substrate 101, so that a P-type second layer having an impurity concentration higher than that of the first impurity layer 102 is obtained. An impurity layer 103 is formed. Here, the first impurity layer 102 and the second impurity layer 103 are collectively referred to as a P-type impurity region. Note that the order of forming the first impurity layer 102 and the second impurity layer 103 is not particularly limited.
　続いて、公知の方法により、半導体基板１０１の主面上に、例えば、膜厚が５ｎｍの下部シリコン酸化膜１０４、膜厚が５ｎｍで電荷蓄積層となるシリコン窒化膜１０５及び膜厚が１５ｎｍの上部シリコン酸化膜１０６を順次形成し、これら下部シリコン酸化膜１０４、シリコン窒化膜１０５及び上部シリコン酸化膜１０６からゲート絶縁膜１０７を形成する。 Subsequently, by a known method, for example, a lower silicon oxide film 104 having a thickness of 5 nm, a silicon nitride film 105 having a thickness of 5 nm and serving as a charge storage layer, and a thickness of 15 nm are formed on the main surface of the semiconductor substrate 101. An upper silicon oxide film 106 is sequentially formed, and a gate insulating film 107 is formed from the lower silicon oxide film 104, the silicon nitride film 105, and the upper silicon oxide film 106.
　次に、図４（ａ）及び図４（ｂ）に示すように、リソグラフィ法により、ゲート絶縁膜１０７の上に、互いに間隔をおいて並行に延びる複数のビット線拡散層の形成領域を開口する第１のレジストパターン１１５を形成する。続いて、ドライエッチング法により、第１のレジストパターン１１５をマスクとして、ゲート絶縁膜１０７をエッチングする。その後、再度、第１のレジストパターン１１５をマスクとして、第１の不純物層１０２にＮ型の不純物イオン、例えばヒ素（Ａｓ＋）イオンを注入して、第１の不純物層１０２の上部に複数のビット線拡散層１０８を形成する。なお、ヒ素イオンのドーズ量は、例えば１×１０１５／ｃｍ２程度とする。また、必要に応じて、１×１０１３／ｃｍ２オーダのホウ素イオンを、例えばチルト角（Ｔｌ）２５°で角度注入することにより、ビット線拡散層１０８同士のパンチスルーを抑制してもよい。 Next, as shown in FIGS. 4A and 4B, openings for forming a plurality of bit line diffusion layers extending in parallel with a distance from each other are formed on the gate insulating film 107 by lithography. A first resist pattern 115 is formed. Subsequently, the gate insulating film 107 is etched by dry etching using the first resist pattern 115 as a mask. After that, again, using the first resist pattern 115 as a mask, N-type impurity ions such as arsenic (As + ) ions are implanted into the first impurity layer 102, and a plurality of impurity ions are formed on the first impurity layer 102. A bit line diffusion layer 108 is formed. The dose amount of arsenic ions is, for example, about 1 × 10 15 / cm 2 . Further, if necessary, punch-through between the bit line diffusion layers 108 may be suppressed by implanting boron ions of the order of 1 × 10 13 / cm 2 at a tilt angle (Tl) of 25 °, for example. .
　次に、図５（ａ）及び図５（ｂ）に示すように、第１のレジストパターン１１５をアッシング等により除去する。その後、例えば熱酸化法により、半導体基板１０１に対して酸化性雰囲気で熱処理を行うことにより、各ビット線拡散層１０８の上部にそれぞれビット線絶縁膜１０９を形成する。 Next, as shown in FIGS. 5A and 5B, the first resist pattern 115 is removed by ashing or the like. Thereafter, a heat treatment is performed on the semiconductor substrate 101 in an oxidizing atmosphere by, for example, a thermal oxidation method to form the bit line insulating films 109 on the respective bit line diffusion layers 108.
　次に、図６（ａ）及び図６（ｂ）に示すように、例えば化学的気相堆積（ＣＶＤ）法により、各ビット線絶縁膜１０９を含むゲート絶縁膜１０７の上に、厚さが２００ｎｍ程度のポリシリコン膜を堆積する。続いて、堆積したポリシリコン膜に、Ｎ型の不純物イオン、例えばリン（Ｐ＋）イオンを６×１０１５／ｃｍ２程度のドーズ量で注入する。その後、リソグラフィ法により、ポリシリコン膜の上に、各ビット線拡散層１０８（ビット線絶縁膜１０９）とそれぞれ交差して並行に延びる複数の開口部を有する第２のレジストパターン（図示せず）を形成する。　続いて、第２のレジストパターンをマスクとして、ドライエッチング法によりポリシリコン膜をエッチングして、該ポリシリコン膜から複数のワード線電極１１０を形成する。 Next, as shown in FIGS. 6A and 6B, the thickness is formed on the gate insulating film 107 including each bit line insulating film 109 by, for example, chemical vapor deposition (CVD). A polysilicon film of about 200 nm is deposited. Subsequently, N-type impurity ions such as phosphorus (P + ) ions are implanted into the deposited polysilicon film at a dose of about 6 × 10 15 / cm 2 . Thereafter, a second resist pattern (not shown) having a plurality of openings extending in parallel with each bit line diffusion layer 108 (bit line insulating film 109) on the polysilicon film by lithography. Form. Subsequently, using the second resist pattern as a mask, the polysilicon film is etched by a dry etching method to form a plurality of word line electrodes 110 from the polysilicon film.
　次に、図７（ａ）及び図７（ｂ）に示すように、各ワード線電極１１０をマスクとして、Ｐ型の第１の不純物層１０２及びＰ型の第２の不純物層１０３に対して、Ｎ型の不純物イオン、例えばリンイオンをカウンタ注入する。このカウンタ注入により、Ｐ型の第１の不純物層１０２における各ワード線電極１１０の下方の領域に、周囲の第１の不純物層１０２におけるＰ型の不純物濃度よりも不純物濃度が低いＰ型の第３の不純物層１１１Ａがそれぞれ自己整合的に形成される。これと同時に、Ｐ型の第２の不純物層１０３における各ワード線電極１１０同士の間の下方の領域に、周囲の第２の不純物層１０３におけるＰ型の不純物濃度よりも不純物濃度が低いＰ型の第４の不純物層１１１Ｂがそれぞれ自己整合的に形成される。 Next, as shown in FIGS. 7A and 7B, with respect to the P-type first impurity layer 102 and the P-type second impurity layer 103, using each word line electrode 110 as a mask. N-type impurity ions such as phosphorus ions are counter-implanted. By this counter implantation, the P-type first impurity layer having a lower impurity concentration than the P-type impurity concentration in the surrounding first impurity layer 102 in the region below each word line electrode 110 in the P-type first impurity layer 102. Three impurity layers 111A are formed in a self-aligned manner. At the same time, in the region below the word line electrodes 110 in the P-type second impurity layer 103, the P-type impurity concentration is lower than the P-type impurity concentration in the surrounding second impurity layer 103. The fourth impurity layers 111B are formed in a self-aligned manner.
　低濃度のＰ型の第３の不純物層１１１Ａは、例えば濃度ピークが半導体基板１０１の主面から５０ｎｍ以上且つ１５０ｎｍ以下の深さとなるような注入エネルギーで形成される。このときの低濃度のＰ型の不純物濃度は、第１の不純物層１０２におけるＰ型の不純物濃度の、例えば半分程度とする。このように、Ｐ型の第１の不純物層１０２の内部にカウンタ注入により、周囲の第１の不純物層１０２におけるＰ型の不純物濃度よりも不純物濃度が低いＰ型の第３の不純物層１１１Ａを形成すると、第３の不純物層１１１Ａが形成された領域においては、キャリア濃度が低減して電界が緩和されるため、２次インパクトイオン化が生じにくくなる、その結果、チャネル領域において２次電子の発生が抑制される。 The low-concentration P-type third impurity layer 111A is formed, for example, with an implantation energy such that the concentration peak is 50 nm or more and 150 nm or less from the main surface of the semiconductor substrate 101. At this time, the low-concentration P-type impurity concentration is, for example, about half of the P-type impurity concentration in the first impurity layer 102. In this way, the P-type third impurity layer 111A having an impurity concentration lower than the P-type impurity concentration in the surrounding first impurity layer 102 is formed by counter implantation into the P-type first impurity layer 102. When formed, in the region where the third impurity layer 111A is formed, the carrier concentration is reduced and the electric field is relaxed, so that secondary impact ionization is less likely to occur. As a result, generation of secondary electrons in the channel region occurs. Is suppressed.
　これに対し、低濃度のＰ型の第４の不純物層１１１Ｂは、ワード線電極１１０を透過しないため、例えば濃度ピークが半導体基板１０１の主面から２５０ｎｍ以上且つ４００ｎｍ以下の深さとなる。前述したように、Ｐ型の第２の不純物層１０３は、素子分離のために設けられている。従って、この素子分離のためのＰ型の第２の不純物層１０３に、ワード線電極１１０同士の間に注入されたカウンタ注入による、周囲の第２の不純物層１０３におけるＰ型の不純物濃度よりも不純物濃度が低いＰ型の第４の不純物層１１１Ｂが形成されることが好ましい。このとき、第２の不純物層１０３は第１の不純物層１０２よりも深い位置に形成されており、且つＰ型の不純物濃度が第１の不純物層１０２よりも濃いため、第２の不純物層１０３内におけるワード線電極１１０同士の間に周囲よりも濃度が低いＰ型の第４の不純物層１１１Ｂが形成されても、ビット線リークの原因となることはない。なお、カウンタ注入は１回のみのイオン注入で行っているが、必ずしも１回の注入で行う必要はなく、複数回に分けてもよい。 On the other hand, since the low-concentration P-type fourth impurity layer 111B does not transmit the word line electrode 110, for example, the concentration peak has a depth of 250 nm or more and 400 nm or less from the main surface of the semiconductor substrate 101. As described above, the P-type second impurity layer 103 is provided for element isolation. Therefore, the P-type impurity concentration in the surrounding second impurity layer 103 by the counter injection injected between the word line electrodes 110 into the P-type second impurity layer 103 for element isolation is larger than the P-type impurity concentration in the surrounding second impurity layer 103. A P-type fourth impurity layer 111B having a low impurity concentration is preferably formed. At this time, since the second impurity layer 103 is formed at a deeper position than the first impurity layer 102 and the P-type impurity concentration is higher than that of the first impurity layer 102, the second impurity layer 103. Even if the P-type fourth impurity layer 111B having a lower concentration than the surroundings is formed between the word line electrodes 110 in the inside, it does not cause a bit line leak. Although the counter implantation is performed by only one ion implantation, it is not necessarily performed by one implantation, and may be divided into a plurality of times.
　また、本実施形態においては、カウンタ注入を、ワード線電極１１０を形成した後に行っている。これにより、ワード線電極１１０を形成するよりも前、例えばゲート絶縁膜１０７の形成工程、及び周辺素子のゲート絶縁膜の形成工程等の熱処理工程の影響を受けることなく且つ制御性良くキャリア濃度を選択的に低減することができる。 In this embodiment, the counter injection is performed after the word line electrode 110 is formed. Thus, before the word line electrode 110 is formed, the carrier concentration is controlled with good controllability without being affected by the heat treatment process such as the gate insulating film 107 forming process and the peripheral element gate insulating film forming process. It can be selectively reduced.
　なお、カウンタ注入を行う際に、ゲート絶縁膜１０７上におけるワード線電極１１０同士の間の領域にマスクを形成して、低濃度のＰ型の第４の不純物層１１１Ｂを形成されないようにし、ワード線電極１１０の下側にのみ低濃度のＰ型の第３の不純物層１１１Ａを形成してもよい。 Note that when the counter implantation is performed, a mask is formed in a region between the word line electrodes 110 on the gate insulating film 107 so that the low-concentration P-type fourth impurity layer 111B is not formed. The low-concentration P-type third impurity layer 111A may be formed only on the lower side of the line electrode 110.
　さらに、本実施形態においては、Ｐ型の第１の不純物層１０２の下に、複数のメモリセル同士を互いに絶縁するＰ型の第２の不純物層１０３を形成した場合について説明したが、Ｐ型の第２の不純物層１０３は必ずしも形成する必要はない。その場合、カウンタ注入によって、Ｐ型の半導体基板１０１におけるワード線電極１１０同士の間に周囲のＰ型の第１の不純物層１０２よりも低濃度の、第４の不純物層１１１Ｂに相当するＰ型の第５の不純物層（図示せず）が形成される。このとき、Ｐ型の第５の不純物層の不純物濃度は、同時に形成されるＰ型の第３の不純物層１１１Ａの不純物濃度と同等となる。 Furthermore, in this embodiment, the case where the P-type second impurity layer 103 that insulates a plurality of memory cells from each other is formed under the P-type first impurity layer 102 has been described. The second impurity layer 103 is not necessarily formed. In that case, the P-type corresponding to the fourth impurity layer 111B having a lower concentration than the surrounding P-type first impurity layer 102 between the word line electrodes 110 in the P-type semiconductor substrate 101 by the counter implantation. The fifth impurity layer (not shown) is formed. At this time, the impurity concentration of the P-type fifth impurity layer is equivalent to the impurity concentration of the P-type third impurity layer 111A formed at the same time.
　次に、図示はしていないが、ワード線電極１１０同士の間の絶縁膜埋め込み工程、シリサイド形成工程、コンタクト形成工程及び配線形成工程を順次実施する。 Next, although not shown, an insulating film burying step, a silicide forming step, a contact forming step, and a wiring forming step between the word line electrodes 110 are sequentially performed.
　以上説明したように、本実施形態に係る半導体記憶装置１００の製造方法によると、各ワード線電極１１０の下側の第１の不純物層１０２に、ワード線電極１１０に対して自己整合的にカウンタ注入を行っている。これにより、該半導体記憶装置１００の書き込み動作時に２次インパクトイオン化が起こる領域のキャリア濃度が低減されて、チャネル領域の電界を緩和することができる。すなわち、各ワード線電極１１０の下側領域において発生する２次電子の発生量を抑制することができるので、エンデュランス特性及びリテンション特性等のメモリセルの信頼性を向上することができる。 As described above, according to the manufacturing method of the semiconductor memory device 100 according to the present embodiment, the first impurity layer 102 below each word line electrode 110 is countered in a self-aligned manner with respect to the word line electrode 110. Injecting. Thereby, the carrier concentration in the region where secondary impact ionization occurs during the write operation of the semiconductor memory device 100 is reduced, and the electric field in the channel region can be relaxed. That is, since the amount of secondary electrons generated in the lower region of each word line electrode 110 can be suppressed, the reliability of the memory cell such as endurance characteristics and retention characteristics can be improved.
　また、ワード線電極１１０を形成した後に、カウンタ注入を行うことにより、半導体基板１０１におけるワード線電極１１０同士の間の領域においては、第４の不純物層１１１Ｂが第３の不純物層１１１Ａよりも深い領域、例えば素子分離用の注入で不純物濃度が第１の不純物層１０２よりも高い第２の不純物層１０３に自己整合的に形成される。これにより、ビット線拡散層１０８とワード線電極１１０とが行列状に交差するメモリアレイにおいて、第４の不純物層１１１Ｂを介したビット線リークの発生を防止することができる。 Further, by performing counter implantation after forming the word line electrode 110, the fourth impurity layer 111B is deeper than the third impurity layer 111A in the region between the word line electrodes 110 in the semiconductor substrate 101. A region, for example, a second impurity layer 103 having an impurity concentration higher than that of the first impurity layer 102 is formed in a self-aligned manner by implantation for element isolation. As a result, in the memory array in which the bit line diffusion layer 108 and the word line electrode 110 intersect in a matrix, it is possible to prevent the occurrence of a bit line leak through the fourth impurity layer 111B.
　なお、本実施形態においては、第１の不純物層１０２及び第２の不純物層１０３をＰ型とし、第３の不純物層１１１Ａ及び第４の不純物層１１１Ｂを低濃度のＰ型としたが、必ずしもこの導電型に限られず、全不純物領域においてＰ型とＮ型とを一括して互いに入れ替えることも可能である。 In the present embodiment, the first impurity layer 102 and the second impurity layer 103 are P-type, and the third impurity layer 111A and the fourth impurity layer 111B are low-concentration P-type. It is not limited to this conductivity type, and the P-type and the N-type can be interchanged together in all impurity regions.
　本発明に係る半導体記憶装置及びその製造方法によると、チャネル領域に発生する２次電子が抑制されて、記憶装置としての信頼性を向上することができ、ビット線拡散層とその上に交差して形成されたワード線電極とを有する、例えばＭＯＮＯＳ型の半導体記憶装置及びその製造方法等に有用である。 According to the semiconductor memory device and the manufacturing method thereof according to the present invention, secondary electrons generated in the channel region can be suppressed, and the reliability as the memory device can be improved, and the bit line diffusion layer intersects with the bit line diffusion layer. For example, it is useful for a MONOS type semiconductor memory device having a word line electrode formed in this manner, a manufacturing method thereof, and the like.
１００　　半導体記憶装置
１０１　　半導体基板
１０２　　（Ｐ型）第１の不純物層
１０３　　（Ｐ型）第２の不純物層
１０４　　下部シリコン酸化膜
１０５　　シリコン窒化膜
１０６　　上部シリコン酸化膜
１０７　　ゲート絶縁膜（ＯＮＯ膜）
１０８　　ビット線拡散層
１０９　　ビット線絶縁膜
１１０　　ワード線電極
１１１Ａ　（低濃度のＰ型）第３の不純物層
１１１Ｂ　（低濃度のＰ型）第４の不純物層
１１５　　第１のレジストパターン DESCRIPTION OF SYMBOLS 100 Semiconductor memory device 101 Semiconductor substrate 102 (P type) 1st impurity layer 103 (P type) 2nd impurity layer 104 Lower silicon oxide film 105 Silicon nitride film 106 Upper silicon oxide film 107 Gate insulating film (ONO film)
108 bit line diffusion layer 109 bit line insulating film 110 word line electrode 111A (low concentration P type) third impurity layer 111B (low concentration P type) fourth impurity layer 115 first resist pattern

Claims (10)

  1. 　第１導電型の半導体領域の上部にそれぞれが互いに並行に延びるように形成された複数のビット線拡散層と、
    　前記半導体領域の上で、且つそれぞれが前記各ビット線拡散層と交差する方向に互いに並行に延びるように形成された複数のワード線電極と、
    　前記半導体領域における前記各ワード線電極の下方の領域にそれぞれ自己整合的に形成され、周囲よりも濃度が低い第１導電型の複数の第１の不純物層とを備えている半導体記憶装置。     A plurality of bit line diffusion layers formed on the first conductivity type semiconductor region so as to extend in parallel with each other;
    A plurality of word line electrodes formed on the semiconductor region and extending in parallel with each other in a direction intersecting with each of the bit line diffusion layers;
    A semiconductor memory device comprising: a plurality of first impurity layers of a first conductivity type formed in a self-aligned manner in regions below the respective word line electrodes in the semiconductor region and having a lower concentration than the surroundings.
  2. 　請求項１において、
    　前記半導体領域における前記各ワード線電極同士の間の下方の領域にそれぞれ自己整合的に形成され、周囲よりも濃度が低い第１導電型の複数の第２の不純物層をさらに備え、
    　前記第１の不純物層と前記第２の不純物層との互いの不純物濃度は同等であり、
    　前記半導体領域において、前記複数の第２の不純物層は、前記複数の第１の不純物層よりも深く形成されている半導体記憶装置。     In claim 1,
    A plurality of second impurity layers of a first conductivity type formed in a self-aligned manner in regions below the respective word line electrodes in the semiconductor region and having a lower concentration than the surroundings;
    The impurity concentrations of the first impurity layer and the second impurity layer are equal to each other,
    In the semiconductor region, the plurality of second impurity layers are formed deeper than the plurality of first impurity layers.
  3. 　請求項１又は２において、
    　前記第１の不純物層の濃度ピークは、前記半導体領域の主面から５０ｎｍ以上且つ１５０ｎｍ以下の深さに設定されている半導体記憶装置。     In claim 1 or 2,
    The semiconductor memory device, wherein the concentration peak of the first impurity layer is set to a depth of 50 nm or more and 150 nm or less from the main surface of the semiconductor region.
  4. 　請求項２において、
    　前記第２の不純物層の濃度ピークは、前記半導体領域の主面から２５０ｎｍ以上且つ４００ｎｍ以下の深さに設定されている半導体記憶装置。     In claim 2,
    The semiconductor memory device, wherein the concentration peak of the second impurity layer is set to a depth of 250 nm or more and 400 nm or less from the main surface of the semiconductor region.
  5. 　請求項２又は４において、
    　前記半導体領域における第１導電型の不純物濃度は、前記第２の不純物層を含む領域が他の領域と比べて高くなるように設定されている半導体記憶装置。     In claim 2 or 4,
    The semiconductor memory device, wherein an impurity concentration of the first conductivity type in the semiconductor region is set so that a region including the second impurity layer is higher than other regions.
  6. 　請求項１～５のいずれか１項において、
    　前記半導体領域と前記各ワード線電極との間に形成され、下から順次形成された下部シリコン酸化膜、シリコン窒化膜及び上部シリコン酸化膜からなるゲート絶縁膜をさらに備えている半導体記憶装置。     In any one of claims 1 to 5,
    A semiconductor memory device further comprising a gate insulating film formed between a lower silicon oxide film, a silicon nitride film, and an upper silicon oxide film formed between the semiconductor region and each word line electrode and sequentially formed from below.
  7. 　半導体領域に第１導電型の第１の不純物層を形成する工程（ａ）と、
    　前記半導体領域における前記第１の不純物層の下に、第１導電型の第２の不純物層を形成する工程（ｂ）と、
    　前記半導体領域の上に、電荷蓄積層を有するゲート絶縁膜を形成する工程（ｃ）と、
    　形成された前記ゲート絶縁膜に対して互いに並行に延びる複数の開口部を選択的に形成する工程（ｄ）と、
    　前記半導体領域における前記各開口部から露出する領域に、それぞれビット線拡散層を形成する工程（ｅ）と、
    　形成された前記各ビット線拡散層の上にそれぞれビット線絶縁膜を形成する工程（ｆ）と、
    　前記ゲート絶縁膜及びビット線絶縁膜を含む前記半導体領域の上で、且つ前記各ビット線拡散層と交差する方向に互いに並行に延びる複数のワード線電極を選択的に形成する工程（ｇ）と、
    　前記各ワード線電極及びゲート絶縁膜をマスクとして、前記半導体領域に対して、第２導電型の不純物を注入することにより、前記半導体領域における前記各ワード線電極の下方の領域に、周囲の第１導電型の第１の不純物層における第１導電型の不純物濃度よりも不純物濃度が低い第１導電型の複数の第３の不純物層を形成すると共に、前記半導体領域における前記各ワード線電極同士の間の下方の領域に、周囲の第１導電型の第２の不純物層における第１導電型の不純物濃度よりも不純物濃度が低い第１導電型の複数の第４の不純物層を形成する工程（ｈ）とを備えている半導体記憶装置の製造方法。     Forming a first conductivity type first impurity layer in the semiconductor region;
    A step (b) of forming a second impurity layer of a first conductivity type under the first impurity layer in the semiconductor region;
    Forming a gate insulating film having a charge storage layer on the semiconductor region (c);
    A step (d) of selectively forming a plurality of openings extending in parallel with each other with respect to the formed gate insulating film;
    A step (e) of forming a bit line diffusion layer in each of the regions exposed from the openings in the semiconductor region;
    A step (f) of forming a bit line insulating film on each of the formed bit line diffusion layers;
    A step (g) of selectively forming a plurality of word line electrodes extending in parallel with each other in the direction intersecting with each bit line diffusion layer on the semiconductor region including the gate insulating film and the bit line insulating film; ,
    By implanting a second conductivity type impurity into the semiconductor region using the word line electrodes and the gate insulating film as a mask, a peripheral second region is formed in the region below the word line electrodes in the semiconductor region. Forming a plurality of third impurity layers of the first conductivity type having an impurity concentration lower than the impurity concentration of the first conductivity type in the first impurity layer of one conductivity type; and the word line electrodes in the semiconductor region Forming a plurality of first conductivity type fourth impurity layers having an impurity concentration lower than the first conductivity type impurity concentration in the surrounding first conductivity type second impurity layer in a lower region between (H) A method for manufacturing a semiconductor memory device.
  8. 　請求項７において、
    　前記工程（ｈ）において、第２導電型の不純物は、前記第３の不純物層の濃度ピークが前記半導体領域の主面から５０ｎｍ以上且つ１５０ｎｍ以下の深さとなるエネルギーで注入する半導体記憶装置の製造方法。     In claim 7,
    In the step (h), the second conductivity type impurity is implanted with energy at which the concentration peak of the third impurity layer is 50 nm or more and 150 nm or less from the main surface of the semiconductor region. Method.
  9. 　請求項７又は８において、
    　前記工程（ｈ）において、第２導電型の不純物は、前記第４の不純物層の濃度ピークが前記半導体領域の主面から２５０ｎｍ以上且つ４００ｎｍ以下の深さとなるエネルギーで注入する半導体記憶装置の製造方法。     In claim 7 or 8,
    In the step (h), the second conductivity type impurity is implanted with energy such that the concentration peak of the fourth impurity layer is 250 nm or more and 400 nm or less from the main surface of the semiconductor region. Method.
  10. 　請求項７～９のいずれか１項において、
    　前記工程（ｂ）において、前記第２の不純物層は、前記第４の不純物層が形成される領域に、第１導電型の不純物濃度のピークが位置するように形成する半導体記憶装置の製造方法。     In any one of claims 7 to 9,
    In the step (b), the second impurity layer is formed so that the peak of the first conductivity type impurity concentration is located in a region where the fourth impurity layer is formed. .
PCT/JP2011/000642 2010-07-15 2011-02-04 Semiconductor storage device and method for manufacturing same WO2012008067A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010-160905 2010-07-15
JP2010160905A JP2012023247A (en) 2010-07-15 2010-07-15 Semiconductor storage device and manufacturing method of the same

Publications (1)

Publication Number Publication Date
WO2012008067A1 true WO2012008067A1 (en) 2012-01-19

Family

ID=45469087

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2011/000642 WO2012008067A1 (en) 2010-07-15 2011-02-04 Semiconductor storage device and method for manufacturing same

Country Status (2)

Country Link
JP (1) JP2012023247A (en)
WO (1) WO2012008067A1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001118943A (en) * 1999-10-22 2001-04-27 Fujitsu Ltd Nonvolatile semiconductor memory device and method of manufacturing the same
JP2005522880A (en) * 2002-04-08 2005-07-28 スパンション エルエルシー Method for manufacturing a memory having bit line insulation
JP2006165451A (en) * 2004-12-10 2006-06-22 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2006210706A (en) * 2005-01-28 2006-08-10 Matsushita Electric Ind Co Ltd Nonvolatile semiconductor memory device, its manufacturing method, and its driving method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001118943A (en) * 1999-10-22 2001-04-27 Fujitsu Ltd Nonvolatile semiconductor memory device and method of manufacturing the same
JP2005522880A (en) * 2002-04-08 2005-07-28 スパンション エルエルシー Method for manufacturing a memory having bit line insulation
JP2006165451A (en) * 2004-12-10 2006-06-22 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2006210706A (en) * 2005-01-28 2006-08-10 Matsushita Electric Ind Co Ltd Nonvolatile semiconductor memory device, its manufacturing method, and its driving method

Also Published As

Publication number Publication date
JP2012023247A (en) 2012-02-02

Similar Documents

Publication Publication Date Title
JP3976729B2 (en) Memory cell, memory cell configuration, and manufacturing method
KR100642898B1 (en) Transistor of semiconductor device and mathod for manufacturing the same
TWI720350B (en) Split-gate type non-volatile memory and manufacturing method thereof
JP5707224B2 (en) Semiconductor device and manufacturing method thereof
JP2006286720A (en) Semiconductor device and its manufacturing method
JP2008053498A (en) Semiconductor device and its manufacturing method
JP2004356562A (en) Method for manufacturing semiconductor device and semiconductor device
US20060244014A1 (en) Nonvolatile memory device and method of forming same
JP4445353B2 (en) Manufacturing method of direct tunnel semiconductor memory device
JP2010087046A (en) Nonvolatile semiconductor device and method of manufacturing the same
US20140209993A1 (en) Non-Volatile Memory With Silicided Bit Line Contacts
US8044455B2 (en) Semiconductor device and method of manufacturing the same
JP2007335787A (en) Nonvolatile semiconductor memory device, and method of manufacturing the same
JP3975349B2 (en) Semiconductor device and manufacturing method thereof
JP2000260887A (en) Nonvolatile semiconductor memory device and its manufacture
US8334182B2 (en) Method for manufacturing non-volatile memory
KR100673017B1 (en) Nonvalitile memory device and method for fabricating the same
JP2007158093A (en) Nonvolatile semiconductor memory device, and manufacturing method thereof
JPWO2006035503A1 (en) Semiconductor device and method of manufacturing semiconductor device
JP2013004791A (en) Semiconductor device and manufacturing method of the same
WO2012008067A1 (en) Semiconductor storage device and method for manufacturing same
US8779500B2 (en) Memory device
JP5529216B2 (en) Semiconductor device and manufacturing method of semiconductor device
US20080054333A1 (en) Semiconductor Device and Manufacturing Method Thereof
KR101038838B1 (en) Flash memory device and method for fabricating the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11806404

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11806404

Country of ref document: EP

Kind code of ref document: A1