WO2011137768A1 - 检测电路以及同步整流电路 - Google Patents

检测电路以及同步整流电路 Download PDF

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Publication number
WO2011137768A1
WO2011137768A1 PCT/CN2011/074092 CN2011074092W WO2011137768A1 WO 2011137768 A1 WO2011137768 A1 WO 2011137768A1 CN 2011074092 W CN2011074092 W CN 2011074092W WO 2011137768 A1 WO2011137768 A1 WO 2011137768A1
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WIPO (PCT)
Prior art keywords
module
fet
source
field effect
effect transistor
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PCT/CN2011/074092
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English (en)
French (fr)
Inventor
陈文彬
黄伯宁
代胜勇
梁泽华
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华为技术有限公司
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Publication of WO2011137768A1 publication Critical patent/WO2011137768A1/zh

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to the field of electronic technologies, and in particular, to a detection circuit and a synchronous rectifier circuit provided with the detection circuit.
  • the resistance of the FET to the conduction between the drain and the source of the FET (the resistance is called the on-resistance) is lower than that of the Schottky diode due to the FET compared with the Schottky diode.
  • the resistance is lower when conducting between, and the lower the on-resistance is, the less power loss is caused to the circuit. Therefore, the rectifier circuit for realizing the high-efficiency conversion of alternating current to direct current is more and more popular by using the field effect transistor. Rectification is replaced by a Schottky diode.
  • the detection chip controls whether the drain of the FET and the source of the FET are turned on or off by detecting the voltage value of the voltage between the drain of the FET and the source of the FET. For example, after the detecting chip detects the voltage value of the voltage between the drain of the FET and the source of the FET, the voltage value is compared with a preset threshold value and a turn-on threshold, and is turned on. The threshold value is greater than the cut-off threshold. If the voltage value detected by the detecting chip is greater than the turn-on threshold, the detecting chip sends a high level signal to the gate of the FET, and the gate of the FET receives a high level.
  • the detection chip After the signal, it will control the conduction between the drain of the FET and the source of the FET, if the detection chip detects the electricity When the voltage value is less than the cutoff threshold, the detection chip will send a low level signal to the gate of the FET, and the gate of the FET will control the drain and FET of the FET after receiving the low level signal.
  • the source is between the cutoffs.
  • the detection and detection of the voltage value between the package lead inductance L 1 and the source S of the field effect transistor Q are affected by the package lead inductance L 1 , so the detected voltage value and the drain D of the field effect transistor Q are
  • the effective voltage value of the voltage between the source S of the field effect transistor Q ie, the ideal voltage value, or the theoretical voltage value
  • R 1 and the field effect transistor Q are directly detected.
  • the line a in Figure 2 shows the effective voltage between the drain D of the FET Q and the source S of the FET Q, that is, the source of point B to the FET Q.
  • the curve of the voltage value of the voltage between the poles S, the b line represents the curve of the voltage value on the package lead inductance L 1 of the field effect transistor Q, and the c line represents the drain D of the field effect transistor Q and the field effect transistor Q.
  • the phase of the c-line is earlier than the phase of the a-line
  • the detection chip controls the drain D of the FET Q according to the magnitude of the voltage value indicated by the detected c-line.
  • the source S of the FET Q is turned on or off, the voltage value of the voltage between the drain D of the FET Q and the source S of the FET Q is earlier than the preset value.
  • a fixed cut-off threshold (for example, 0 V), which in turn causes the drain D of the FET Q and the source S of the FET Q to be turned off early, the drain D of the FET Q and the source of the FET Q
  • S is cut off early, the current in the synchronous rectifier circuit will flow through the body diode of the FET Q. Since the resistance of the body diode of the FET Q is much larger than the resistance of the FET of the FET, it will synchronously rectify. The circuit causes a large loss of power.
  • the effective voltage value between the drain D of the FET Q and the source S of the FET Q is detected or the source level S of the FET Q drain D and the FET Q is detected.
  • the current value it is necessary to detect outside the lead D of the field effect transistor Q and the source S of the field effect transistor Q, so that the voltage between the package lead inductance L 1 and the source S of the field effect transistor Q is detected.
  • the voltage value and the current value of the current flowing through the drain of the FET Q and the source S of the FET Q are affected by the package lead inductance L 1 , resulting in the detected voltage value and the FET Q.
  • the effective voltage value between the drain D and the source S of the FET Q, the detected current value and the effective current value flowing through the FET Q drain D and the FET Q source S are both Large, so it is impossible to accurately detect the effective voltage value between the drain D of the FET Q and the source S of the FET Q and the effective flow through the FET Q drain D and the FET Q source S Current value.
  • the embodiment of the invention provides a detecting circuit and a synchronous rectifying circuit provided with the detecting circuit, which solves the problem that the voltage value and the flow of the voltage between the drain of the FET and the source of the FET cannot be accurately detected in the prior art.
  • the detecting circuit includes an inductor module, a resistor module and a detecting module, wherein: the inductor module and the resistor module are connected in series with each other, and the inductor module is connected in series with each other And the resistor module is connected between the source of the FET and the drain of the FET; the detecting module is configured to obtain a connection point of the inductor module and the resistor module by measurement Deriving a voltage value between the source of the FET or a current value of a current flowing through the resistance module and a source of the FET, and deriving the source of the FET according to the voltage value or current An effective voltage value between the pole and the drain or an effective current value of a current flowing through the source and drain of the field effect transistor.
  • the synchronous rectification circuit includes a transformer, a FET, and a detection circuit, wherein: a primary line of the transformer is used to acquire an alternating current, and a secondary line of the transformer is used to output an alternating current;
  • a drain of the FET is connected to a first tap of a secondary winding of the transformer, a second tap of a secondary winding of the transformer, and a source of the FET are respectively connected to a power consuming device ;
  • the power consumption device is configured to obtain electric energy in a form of direct current from the second tap and a source of the FET;
  • the detecting circuit includes an inductor module, a resistor module and a detecting module, wherein: the inductor module and the resistor module are connected in series with each other, and the inductor module and the resistor module connected to each other are connected to a source of the FET and Between the drains of the FETs; the detecting module is configured to obtain an effective voltage value between the source and the drain of the FET or a source flowing through the FET by measurement The effective current value with the drain.
  • the detecting module may obtain a voltage value between the connection point of the inductor module and the resistor module to the source of the FET or flow through the resistor module and the a current value of a current of a source of the field effect transistor, and an effective voltage value between the source and the drain of the field effect transistor or a source flowing through the field effect transistor according to the voltage value or current value
  • the effective current value of the drain With the effective current value of the drain, the influence of the package lead inductance of the FET is avoided, and the voltage value of the voltage between the on-resistance of the FET and the source of the FET can be more accurately obtained.
  • the effective voltage value between the source of the FET and the drain of the FET or the current value of the current flowing through the FET of the FET and the source of the FET, that is, the source flowing through the FET The effective current value of the drain of the pole and the FET, so that the prior art cannot accurately detect the difference between the drain of the FET and the source of the FET.
  • FIG. 1 is a circuit diagram of an equivalent model of a field effect transistor in the prior art
  • FIG. 2 is a waveform diagram of a theoretically ideal voltage waveform line a between the drain of the field effect transistor and the source of the field effect transistor, and the voltage detected on the package lead inductance of the field effect transistor.
  • FIG. 3 is a schematic diagram of a connection relationship between a detection circuit and a field effect transistor according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram showing a connection relationship between an equivalent component and a field effect transistor of each component in a detecting circuit according to a preferred embodiment of the first embodiment of the present invention
  • FIG. 5 is a waveform line of a voltage line d line detected from the point E of FIG. 4 to the source of the field effect transistor, and a voltage detected from the point F to the source of the field effect transistor.
  • FIG. 6 is a schematic diagram of a waveform line f line of a voltage detected between a line G and a source of a field effect transistor;
  • FIG. 6 is a diagram showing a detection circuit and a field effect according to still another embodiment of the first embodiment of the present invention. Schematic diagram of the connection relationship of the tubes;
  • FIG. 7 is a schematic diagram showing a connection relationship between a detecting circuit and a field effect transistor according to Embodiment 2 of the present invention.
  • FIG. 9 is a schematic diagram of Embodiment 1 of the present invention provided by an embodiment of Embodiment 3 of the present invention. Or a schematic diagram of a synchronous rectification circuit of the detection circuit provided in Embodiment 2;
  • Embodiment 10 is a schematic diagram of a synchronous rectification circuit of a detection circuit according to Embodiment 1 or Embodiment 2 of the present invention, which is provided by still another embodiment of Embodiment 3 of the present invention;
  • FIG. 1 is a schematic diagram showing a connection relationship between a detection circuit and a field effect transistor according to an embodiment of the present invention.
  • an embodiment of the present invention provides a detection circuit, as shown by a broken line in the figure, including a detection resistor Rcs, a detection capacitor Ccs, an inverter Fcs, a first switch Sa, a second switch Sb, and detection.
  • the chip Ag and the detecting chip Ag are provided with a first pin G1 and a second pin G2, wherein:
  • the first pin G1 is connected between the detecting resistor Res and the detecting capacitor Ccs, and the second pin G2 is connected to the source S of the field effect transistor Q;
  • the detecting chip Ag is used for measuring the voltage value of the voltage between the detecting capacitor Ccs and the source S of the field effect transistor Q through the first pin G1 and the second pin G2;
  • the inverter Fes is for causing the first switch Sa and the second switch Sb to be in an alternate state; when the drain D of the field effect transistor Q is turned on with the source S of the field effect transistor Q, the first switch Sa is closed The second switch Sb is turned off, at this time, the detecting capacitor Ccs and the detecting resistor Res are connected in series, and the series detecting capacitor Ccs and the detecting resistor Res are connected in parallel with the field effect transistor Q;
  • the detection resistor Res is detected in the detection circuit
  • ⁇ represents the inductance of the package lead inductance L 1 of the field effect transistor Q
  • ⁇ represents the on-resistance R1 of the field effect transistor Q.
  • Resistance value, W 2 represents the resistance value of the detection resistor Res in the detection circuit
  • C represents the capacitance value of the detection capacitance Ccs in the detection circuit;
  • the first switch Sa and the second switch Sb are arranged to short-circuit the detecting capacitor Ccs when the drain D of the field effect transistor Q and the source S of the field effect transistor Q are turned off. Since the capacitor has a strong charge storage capability, the detecting capacitor Ccs When short-circuiting, the charge stored in the detecting capacitor Ccs can be released, thereby preventing the charge stored in the capacitor Ccs from being detected by the MOSFET Q when the drain D of the FET Q and the source S of the FET Q are turned on.
  • the voltage between the drain D and the source S of the field effect transistor Q is affected, thereby ensuring that the resistance value of the detecting resistor Res and the capacitance of the detecting capacitor Ccs in the detecting circuit are better satisfied by the above formula, thereby more accurately detecting
  • the effective voltage value of the voltage between the drain D of the field effect transistor Q and the source S of the field effect transistor Q is theoretically equal to the voltage value of the voltage between the on-resistance R1 of the field effect transistor Q and the source S of the field effect transistor Q.
  • the voltage value of the voltage between the on-resistance R1 and the source S of the field effect transistor Q can be detected more accurately by the existing detection circuit, that is, the drain D of the field effect transistor Q and the field effect transistor Q
  • the effective voltage value of the voltage between the source S can further control the conduction and the cutoff between the drain D of the field effect transistor Q and the source S of the field effect transistor Q.
  • the detection circuit shown in FIG. 8 it is necessary to use various types of electronic devices such as the detection capacitor Ccs, the detection resistor Res, the inverter Fcs, the first switch Sa, and the second switch Sb, due to the type and number of electronic devices used.
  • the more the average ratio the more complicated the structure of the existing detection circuit formed by connecting these electronic devices, and the higher the cost; the connection operation of connecting the electronic devices to form the detection circuit is troublesome, and at the same time, due to the needs of the existing detection circuit
  • the first switch Sa and the second switch Sb are used, at least two switches are used, and the operation of controlling the two switches is cumbersome, complicated, and error-prone, which makes the whole circuit difficult to control, detecting The operation is troublesome.
  • embodiments of the present invention also provide a detection circuit having a simple circuit construction, low cost, and easy connection, and a synchronous rectification circuit provided with the detection circuit.
  • the embodiment of the present invention provides a detection circuit, as shown by the dashed box in FIG. 3 (the left side of the dotted line is the equivalent model circuit diagram of the field effect transistor), including the inductor module 1 and the resistance module 2 And a detection module 3; wherein:
  • the inductor module 1 and the resistor module 2 are connected in series with each other, and the inductor module 1 and the resistor module 2 connected in series are connected between the source S of the field effect transistor Q and the drain D of the field effect transistor Q;
  • the detecting module 3 is configured to obtain a voltage value between the connection point of the inductance module 1 and the resistance module 2 to the source S of the FET Q or a current flowing through the resistance module 1 and the source S of the FET Q The current value, and the effective voltage value between the source S and the drain D of the field effect transistor Q or the effective current value flowing through the source S and the drain D of the field effect transistor Q according to the above voltage value or current value.
  • the detecting module can obtain a voltage value between the connection point of the inductor module and the resistor module to the source of the FET or flow through the resistor module and the a current value of a current of a source of the field effect transistor, and an effective voltage value between the source and the drain of the field effect transistor or a source flowing through the field effect transistor according to the voltage value or current value
  • the effective current value of the current with the drain avoids the influence of the package lead inductance of the field effect transistor, thereby more accurately determining the voltage between the on-resistance of the field effect transistor and the source of the field effect transistor.
  • the value that is, the effective voltage value between the source of the FET and the drain of the FET or the current value of the current flowing through the FET and the source of the FET, that is, flowing through the FET
  • the effective current value of the source and the drain of the FET so that the prior art cannot accurately detect the effective voltage value between the drain of the FET and the source of the FET and flow through the drain of the FET
  • Measure the voltage value across the resistance module 2 ie, the voltage between the connection of the inductor module and the resistor module in Figure 3 to the source S of the FET Q
  • the current value of the current of the source S of the effect transistor Q, and the source S of the field effect transistor Q and the drain D of the field effect transistor Q are obtained according to the principle that the measured voltage value or current value and the voltage across the parallel circuit are equal.
  • Embodiment 1 As shown in FIG. 3, the detection circuit provided by the embodiment of the present invention is shown by a broken line frame in FIG. 3 (the left side of the dotted line frame is an equivalent model circuit diagram of the field effect transistor), and includes an inductance module 1.
  • the first module 31 and the second terminal 32 are disposed on the detection module 3 in the present embodiment; the first connection 31 is connected between the inductor module 1 and the resistor module 2, and the second connection is The terminal 32 is connected to the source S of the field effect transistor Q; wherein:
  • the inductor module 1 and the resistor module 2 are connected in series with each other, and the inductor module 1 and the resistor module 2 connected in series are connected between the source S of the field effect transistor Q and the drain D of the field effect transistor Q;
  • the detecting module 3 is specifically configured to measure the voltage values across the resistor module 2 through the first connecting end 31 and the second connecting end 32 (ie, the connection point of the inductor module 1 and the resistor module 2 in FIG. 3 to the source of the FET Q)
  • the voltage value between S) or the current value of the current flowing through the resistance module 2 and the source S of the field effect transistor Q, and the measured voltage value or current value is used as the connection point of the inductance module 1 and the resistance module 2, respectively.
  • the principle is obtained by the effective voltage value between the source S of the field effect transistor Q and the drain D of the field effect transistor Q or the effective current value flowing through the source S of the field effect transistor Q and the drain D of the field effect transistor Q.
  • the inductor module 1 and the resistor module 2 are connected in series, and the inductor module 1 and the resistor module 2 connected in series are connected to the source S of the field effect transistor Q and the drain of the field effect transistor Q. Between the poles D, the inductor module 1 connected in series with the resistor module 2 is connected in parallel with the source S of the field effect transistor Q and the drain D of the field effect transistor Q, so at this time, as shown in FIG.
  • the inductor The equivalent inductance L2 of module 1 simulates the field effect transistor Q
  • the package lead inductance L1 and the equivalent resistance R2 of the resistance module 2 simulate the on-resistance R1 of the field effect transistor Q, the voltage value of the voltage between the resistance module 2 and the source S of the field effect transistor Q (ie, the resistance module 2
  • the voltage value of the terminal that is, the voltage value between the connection point of the inductor module 1 and the resistor module 2 in FIG.
  • the detecting module 3 can measure the voltage value of the voltage between the resistance module 2 and the source S of the FET Q or measure the voltage flowing through the resistance module 2 and the source S of the FET Q.
  • the current value of the current avoids the influence of the package lead inductance L1 of the field effect transistor Q, thereby enabling more accurate measurement or calculation between the on-resistance R1 of the field effect transistor Q and the source S of the field effect transistor Q.
  • the voltage value of the voltage that is, the effective voltage value between the source S of the field effect transistor Q and the drain D of the field effect transistor Q or the on-resistance R1 flowing through the field effect transistor Q and the source S of the field effect transistor Q
  • the current value of the current that is, the effective current value flowing through the source S of the field effect transistor Q and the drain D of the field effect transistor Q, so that the prior art cannot accurately detect the drain and the field effect transistor of the field effect transistor.
  • the leakage of the tube Q should be connected to the source S of the tube, and the series and parallel connections
  • the connection operation not only has fewer steps, but also connects the operation unit, and the inductance module 1 has a certain inductance, and the resistance module 2 has a certain resistance, and only needs to use ordinary inductance and resistance to realize, which is beneficial to reducing the cost of the detection circuit; Further, the detecting circuit provided in this embodiment does not need to use the detecting circuit used in FIG.
  • the electronic device used in the detection circuit of the invention has fewer types and the number of electronic devices, and the connection relationship between the electronic devices is also relatively small. Therefore, the circuit structure formed by connecting these electronic devices is also more compact.
  • FIG. 6 is a schematic diagram showing a connection relationship between a detection circuit and a field effect transistor according to still another embodiment of the first embodiment of the present invention.
  • the detecting module 3 is provided with a first connecting end 31, a second connecting end 32 and a signal transmitting end 33, wherein:
  • the first connection end 31 is connected between the inductance module 1 and the resistance module 2, and the second connection end 32 is connected to the source S of the field effect transistor Q.
  • the detection module 3 passes through the signal transmission end 33 and the gate G of the FET Q.
  • the detecting module 3 is further configured to send, according to the obtained effective voltage value or the effective current value, the signal S to the gate G of the FET Q to control the source S and the field effect of the FET Q.
  • a level signal that is turned on or off between the drains D of the transistors Q.
  • the effective voltage value between the source S of the field effect transistor Q and the drain D of the field effect transistor Q obtained by the detection circuit of the present embodiment, and the drain D of the field effect transistor Q and the source of the field effect transistor Q is more accurate. Therefore, according to the effective voltage value or the effective current value obtained by the detecting circuit of the embodiment, the source S of the field effect transistor Q and the drain D of the field effect transistor Q are turned on or off. When the FET Q can be controlled more accurately, the drain D of the FET Q and the source S of the FET Q can be effectively prevented from being cut off early, thereby avoiding the circuit where the FET Q is located.
  • the current in (for example, the synchronous rectification circuit shown in Fig. 9 or Fig. 10) flows through the body diode of the field effect transistor Q, causing a large loss to the circuit in which the field effect transistor Q is located.
  • L2 in FIG. 4 represents the equivalent inductance of the inductor module 1, that is, the value L 2 of the inductance of the equivalent inductor L2 is the same as the value of the inductance of the inductor module 1, and R2 is the equivalent of the resistor module 2.
  • the resistance, that is, the resistance R 2 of R2 is the same as the resistance of the resistance module 2.
  • the value of the inductance of the inductance module 1 and the resistance module 2 in this embodiment is equal to the ratio of the value of the inductance of the package lead inductance L 1 of the field effect transistor Q to the resistance of the on-resistance R1 of the field effect transistor Q.
  • the ratio of the value of the inductance of the inductor module 1 to the resistance of the resistor module 2 is equal to the ratio of the value of the inductance of the package lead inductance L 1 of the field effect transistor Q to the resistance of the on-resistance R1 of the field effect transistor Q
  • the voltage value of the voltage between the resistance module 2 and the source S of the field effect transistor Q is equal to the voltage value of the voltage between the on-resistance R1 of the field effect transistor Q and the source S of the field effect transistor Q, so
  • the voltage value of the voltage between the resistance module 2 and the source S of the field effect transistor Q can directly obtain the voltage value of the voltage between the on-resistance R1 of the field effect transistor Q and the source S of the field effect transistor Q (the field effect transistor Q
  • the effective voltage value of the voltage between the drain D and the source S of the field effect transistor Q that is, the voltage value of the voltage between the resistance module 2 and the source S of the field effect transistor Q.
  • the voltage value of the voltage between the point F in FIG. 4 and the source S of the field effect transistor Q and the voltage value between the point G and the source S of the field effect transistor Q are equal, so that only By detecting the circuit in this embodiment, the F point and the field can be directly and accurately detected.
  • the voltage value of the voltage between the source S of the effect transistor Q is the voltage value of the voltage between the drain D of the field effect transistor Q and the source S of the field effect transistor Q.
  • the voltage value can be derived by testing the magnitude of the current value, and the source S and the field of the current effect transistor Q can also be derived by the magnitude of the test voltage value.
  • the disclosed technical solution delineates how to specifically measure and derive the magnitude of the effective current value flowing through the source S of the field effect transistor Q and the drain D of the field effect transistor Q, so that it is not developed here.
  • the voltage value of the voltage between the E point and the source S of the field effect transistor Q and the voltage value of the voltage between the point F and the source S of the field effect transistor Q are quite different, from FIG. 5 It can be seen that the nucleus of the voltage value of the voltage between the E point and the source S of the FET Q is the negative voltage shown in the portion of the circle D of the line D is caused by the package lead inductance L1, because Due to the rapid drop of the current, the package lead inductance L1 induces a reverse voltage to prevent the current from dropping. The faster the current decreases, the greater the negative pressure here, resulting in the detection of the E point and the FET Q.
  • the voltage value of the voltage between the source S is very inaccurate, and after connecting the detection circuit of the embodiment, the waveform of the change of the effective voltage value between the G point and the source S of the field effect transistor Q is detected as shown by the f-line. Since the waveform of the voltage value change between the voltage between the point F and the source S of the field effect transistor Q is as shown by the e-line, it can be seen that the e-line and the f-line are the same, which means that the detection circuit of the embodiment can indeed Detecting the FET Q accurately The effective voltage value between the drain D and the source S of the field effect transistor Q, and when the field effect transistor Q is applied in the synchronous rectification circuit, the detection module 3 can more accurately control the field effect transistor Q, avoiding the field effect transistor Q The drain D and the source S of the field effect transistor Q are cut off in advance.
  • the ratio of the inductance value of the inductance module 1 to the resistance value of the resistance module 2 in this embodiment is not equal to the value of the inductance of the package lead inductance L1 of the field effect transistor Q and the conduction of the field effect transistor Q
  • the ratio of the resistance of the resistor R1 is detected, the voltage value of the voltage between the resistor module 2 and the source S of the field effect transistor Q can be detected by the detecting circuit of the embodiment, and then the value of the inductance of the inductor module 1 and the resistor are used.
  • the ratio of the resistance of the module 1 calculates the effective voltage value between the drain D of the field effect transistor Q and the source S of the field effect transistor Q.
  • the detection circuit in this embodiment further includes a switch module 4, and the switch module 4 and the inductor module 1 and the resistor module 2 are connected in series, wherein:
  • the switch module 4 is connected between the inductor module 1 and the resistor module 2 for disconnecting the inductor module 1 from the resistor module 2 when the source S of the field effect transistor Q is disconnected from the drain D of the field effect transistor Q.
  • the inductor module 1 and the resistance module 2 are connected;
  • the switch module 4 is connected between the resistor module 2 and the source S of the field effect transistor Q or the drain D of the field effect transistor Q for the source S of the field effect transistor Q and the drain D of the field effect transistor Q.
  • the resistance module 2 is disconnected from the source S of the field effect transistor Q or the drain D of the field effect transistor Q; between the source S of the field effect transistor Q and the drain D of the field effect transistor Q.
  • the resistor module 2 is connected to the source S of the field effect transistor Q or the drain D of the field effect transistor Q;
  • the switch module 4 is connected between the inductor module 1 and the drain D of the field effect transistor Q or the source S of the field effect transistor Q for the source S of the field effect transistor Q and the drain D of the field effect transistor Q.
  • the inductance module 1 When disconnected, the inductance module 1 is disconnected from the drain D of the field effect transistor Q or the source S of the field effect transistor Q; between the source S of the field effect transistor Q and the drain D of the field effect transistor Q.
  • the inductor module 1 is connected to the drain D of the field effect transistor Q or the source S of the field effect transistor Q.
  • the equivalent electronic device of the switch module 4 is an equivalent switch K as shown in FIG. 4.
  • the presence of the switch module 4 enables the inductor module 1 not only when the drain D of the field effect transistor Q and the source S of the field effect transistor Q are turned off.
  • the resistor module 2 is disconnected from the parallel circuit formed by the drain D of the field effect transistor Q and the source S of the field effect transistor Q, thereby reducing the circuit in which the inductor module 1 and the resistor module 2 are placed on the field effect transistor Q (for example, The loss caused by the synchronous rectification circuit shown in Figure 9 or Figure 10,
  • the inductive component is an energy storage component
  • the inductor module 1 itself has a certain energy storage function, and the switch module 4 can store the inductive module 1 when the drain D of the field effect transistor Q and the source S of the field effect transistor Q are turned off.
  • the electrical energy is released, thereby preventing the electrical energy stored in the inductive module 1 from being between the drain D of the field effect transistor Q and the source S of the field effect transistor Q, between the resistance module 2 and the source S of the field effect transistor Q.
  • the voltage has an influence, so that the voltage value or current value detected by the detecting circuit of the embodiment can be more accurate.
  • the electrical energy stored by the inductor module 1 in this embodiment is opposite to the circuit in which the FET Q is located (for example, synchronous rectification as shown in FIG. 9 or FIG. 10).
  • the loss caused by the circuit is far lower than the influence of the detection capacitance of the existing detection circuit on the synchronous rectifier circuit where the FET Q is located, so the drain D of the FET Q and the source S of the FET Q
  • the switch module 4 provided in this embodiment may not be provided.
  • the switch module 4 is connected to the detecting module 3 through the signal transmitting end 33, wherein:
  • the detecting module 3 is further configured to send a control command to the switch module 4 through the signal sending end 33 according to the obtained voltage value or the magnitude of the current value;
  • the control command is the same as the level signal for controlling the conduction or deactivation between the source S of the field effect transistor Q and the drain D of the field effect transistor Q;
  • the switch module 4 is configured to receive a control command sent by the detection module 3, and control the inductance module 1 and the resistance module 2 according to the control instruction, or control the resistance module 2 and the source S of the FET Q or the FET Q. Between the drains D, or, the control inductor module 1 is disconnected or connected to the drain D of the field effect transistor Q or the source S of the field effect transistor Q.
  • the detecting module 3 measures the current flowing through the voltage between the resistor module 2 and the source S of the field effect transistor Q or the current flowing through the source S of the resistor module 1 and the field effect transistor Q. The value enables synchronous control of the switching module 4 and the FET Q.
  • the same detection module 3 uses the same signal transmitting end 33, and the method of transmitting the same level signal can realize simultaneous, synchronous control of the switch module 4 and the FET Q, Only the data processing capability of the detection module 3 can be fully utilized, so that the existing resources can be utilized more effectively, and the control of the switch module 4 and the FET Q is more convenient and convenient.
  • the switch module 4 is a MOS transistor (Metal-Oxide-Semiconductor) or a triode, preferably a MOS transistor.
  • MOS tube or the triode is a technically mature, stable and reliable electronic switching device, and can control the MOS tube or the triode by transmitting a level signal to the gate or the base, so it is suitable for application as a
  • the switching module 4 of the embodiment of course, the switching module 4 in this embodiment may also be a MOS transistor and other switching electronic devices other than the triode.
  • the detecting module 3 can use the detecting chip existing in the prior art, and can also use other detecting devices or detecting devices having data processing capabilities similar to those of the detecting chip.
  • the detection circuit of this embodiment further includes a gate G connected to the signal transmitting end 33 and the FET Q and/or a driving module 7 connected between the signal transmitting end 33 and the switch module 4, wherein:
  • the driving module 7 is configured to receive the level signal sent by the detecting module 3, and send the level signal to the gate G and/or the switching module 4 of the FET Q.
  • the driving module 7 amplifies the level signal by boosting to enhance the ability of the level signal to drive, control the FET Q and/or the switching module 4, and further expand the FET Q and/or which can be controlled by the detecting module 3. Or the type and range of the switch module 4.
  • the ratio of the inductance of the inductance module 1 to the value of the inductance of the package lead inductance L1 of the field effect transistor Q is at least 100, and/or the resistance of the resistance module 2 is at least 50 ⁇ .
  • the package lead inductance is also present in the MOS transistor or the triode itself as the switch module 4, so the inductance value of the inductance module 1 and the inductance of the package lead inductance L1 of the field effect transistor Q as shown in FIG.
  • the ratio of the value of the quantity is larger, the voltage between the package lead inductance of the MOS transistor or the triode of the switch module 4 and the source S of the resistance module 2 and the field effect transistor Q flows through the resistance module 2 and the field effect transistor Q.
  • the voltage value of the voltage or the current value of the current flowing through the resistance of the resistor module 2 and the source S of the field effect transistor Q is also more accurate.
  • the ratio of the resistance value of the resistance module 2 to the resistance value of the on-resistance of the MOS transistor or the triode is larger, the MOS transistor or the triode The effect of the on-resistance that exists in itself is smaller.
  • the ratio of the inductance of the inductance module 1 to the value of the inductance of the package lead inductance L1 of the field effect transistor Q shown in FIG. 4 is at least 100, and/or the resistance of the resistance module 2 is at least At 50 ⁇ , the inductance module 1 and the resistance module 2 do not cause much loss to the circuit where the FET Q is located, and the voltage between the resistance module 2 and the source S of the FET Q detected by the detection circuit of this embodiment
  • the voltage value or the current value of the current flowing through the resistance of the resistor module 1 and the source S of the field effect transistor Q is also relatively accurate.
  • the ratio of the inductance of the inductance module 1 to the value of the inductance of the package lead inductance L1 of the FET Q as shown in FIG. 4 is 800 to 1200, preferably 1000, and/or, the resistance module 2
  • the resistance is 80 to 120 ⁇ , preferably 100 ⁇ .
  • the inductor module 1 and the resistor module 2 not only cause too much loss to the circuit in which the field effect transistor Q is located, but also The voltage value of the voltage between the resistance module 2 and the source S of the field effect transistor Q or the current value of the current flowing through the resistance module 2 and the source S of the field effect transistor Q is more accurately detected.
  • the inductor module 1 is an inductor or an inductor module.
  • the resistor module 2 is a plurality of inductors connected in parallel and/or in series.
  • the resistor module 2 is a resistor or a resistor module.
  • the resistor modules 2 are connected in parallel and/or in series.
  • the resistor module 2 is only one resistor, or is connected in parallel and/or in series by multiple resistors, as long as the inductance of the inductor module 1 is ensured.
  • the ratio of the value of the resistor to the resistance of the resistor module 2 is equal to the ratio of the value of the inductance of the package lead inductance L1 of the field effect transistor Q to the resistance of the on-resistance R1 of the field effect transistor Q, which can ensure the resistance module 2 and Voltage and field effect between source S of field effect transistor Q
  • the voltage between the on-resistance R1 of Q and the source S of the field effect transistor Q is equal, so that the drain D of the field effect transistor Q and the source S of the field effect transistor Q can be detected more accurately. Effective voltage value.
  • Embodiment 2 As shown in FIG. 7 , this embodiment is basically the same as the first embodiment, and the difference is that: in this embodiment, the resistor R3 can be connected in series between the inductor module 1 and the resistor module 2, and at this time, the first The connection end 31 is connected between the resistance module 2 and the connection resistor R3.
  • the connection resistor R3 may be either a resistor or a plurality of resistors connected in parallel and/or in series.
  • the resistance of the connection resistor R3 is R 3
  • the resistance of the resistance module 2 is R 2
  • the voltage value of the voltage between the connection resistor R3 and the source S of the field effect transistor Q is U 3
  • the resistance module 2 and the field effect transistor The voltage value of the voltage between the source S of Q is U 2
  • the detection module 3 measures the voltage value U 2 of the voltage between the resistance module 2 and the source S of the field effect transistor Q through the first connection end 31 and the second connection end 32, the above formula can be adopted.
  • Calculating the voltage value of the voltage between the connection resistance R3 and the source S of the field effect transistor Q is U 3 , and further, the voltage of the voltage between the source S of the field effect transistor Q and the drain D of the field effect transistor Q can be obtained.
  • the value is the voltage value of the voltage between point F in Figure 4 and source S of field effect transistor Q.
  • the detection module 3 measures the flow through the resistance module 2 and the field effect in this embodiment
  • the source S flowing through the FET Q and the drain D of the FET Q can be calculated based on the measured current value and the voltage across the parallel circuit. The current value of the current.
  • the resistor module 2 can be either a resistor or a plurality of resistors connected in parallel and/or in series.
  • Embodiment 2 can also be understood that the resistance module 2 and the connection resistor R3 constitute a larger resistance module, and the detection module 3 can detect the voltage of a part of the resistance of the larger resistance module, and the voltage of the partial resistance detected.
  • the voltage value between the resistance module 2 and the source S of the field effect transistor Q is calculated by using the ratio of the resistance of the partial resistor to the resistance of the full resistance module.
  • the field effect transistor as shown in FIG. 4 can also be measured or calculated.
  • Embodiment 3 As shown in FIG. 9, the synchronous rectification circuit provided by the embodiment of the present invention includes a transformer 5, a field effect transistor Q, and any one of the technical solutions provided by Embodiment 1 or Embodiment 1 of the present invention. Detection circuit, where:
  • the primary winding ⁇ 5 1 of the transformer 5 is used to obtain alternating current, and the secondary winding ⁇ 52 of the transformer 5 is used for outputting alternating current;
  • the drain D of the FET Q is connected to the first tap of the secondary winding 52 of the transformer 5, the second tap of the secondary winding 52 of the transformer 5, and the source S of the FET Q and the power consumption module 6, respectively.
  • the power consumption module 6 is configured to obtain electric energy in the form of direct current from the second tap and the source S of the field effect transistor Q;
  • the detecting module 3 is configured to measure a voltage value of a voltage between the resistance module 2 and a source S of the field effect transistor Q or to measure a current value of a current flowing through the resistance module 2 and the source S of the field effect transistor Q, and according to the measurement
  • the voltage value or current value and the principle of the voltage across the parallel circuit are equal.
  • the voltage value of the voltage between the source S of the field effect transistor Q and the drain D of the field effect transistor Q or the source S of the FET Q flows.
  • the detection circuit can detect the voltage value of the voltage between the source S of the field effect transistor Q and the drain D of the field effect transistor Q or the source S of the field effect transistor Q and the drain of the field effect transistor Q.
  • the current value of the current of D is transmitted between the source S of the field effect transistor Q and the drain D of the field effect transistor Q according to the detected voltage value or current value to the gate G of the field effect transistor Q. Whether or not the level signal is turned on, and rectifying the alternating current output from the secondary line 52 by controlling whether the source S and the drain D of the field effect transistor Q are turned on, rectify the alternating current into direct current.
  • the inductance module 1 and the resistance module 2 are connected in series, and the inductance module 1 and the resistor are connected in series with each other.
  • the module 2 is connected between the source S of the field effect transistor Q and the drain D of the field effect transistor Q, so the inductance module 1 and the resistance module 2 are connected in series with the source S of the field effect transistor Q and the field effect transistor Q.
  • the drain D is connected in parallel, so at this time, the inductor module 1 simulates the field effect transistor Q as shown in FIG.
  • the package lead inductance L1 the resistance module 2 simulates the on-resistance R1 of the field effect transistor Q
  • the resistance module 1 Corresponding relationship between the voltage value of the voltage between the source S of the field effect transistor Q and the voltage value of the voltage between the on-resistance R1 of the field effect transistor Q and the source S of the field effect transistor Q can be based on the parallel circuit The principle that the voltages at both ends are equal is derived and calculated. It can be seen that the detection module 3 can measure the voltage value of the voltage between the resistance module 2 and the source S of the FET Q or measure the flow through the resistance module 2 and the FET.
  • the current value of the current of the source S of Q To avoid the influence of the package lead inductance L1 of the field effect transistor Q, and to more accurately measure or calculate the voltage value of the voltage between the on-resistance R1 of the field effect transistor Q and the source S of the field effect transistor Q or The current value of the current flowing through the on-resistance R1 of the field effect transistor Q and the source S of the field effect transistor Q is measured, so that the prior art cannot be solved.
  • the resistance module 2 has a certain resistance, which can be realized only by using ordinary inductance and resistance, which is beneficial to reducing the cost of the detection circuit; and the connection relationship between the electronic devices is also relatively simple, so through these electronic devices
  • the connected circuit structure is also more compact.
  • the voltage value between the source S of the field effect transistor Q and the drain D of the field effect transistor Q obtained by the detecting circuit in this embodiment, and the on-resistance R1 and the field effect transistor Q flowing through the field effect transistor Q is more accurate, so when the source S of the FET Q and the drain D of the FET Q are controlled to be turned on or off according to the voltage value or current value detected by the detecting circuit.
  • the field effect transistor Q can also be controlled more accurately, thereby effectively avoiding the early cutoff between the drain D of the field effect transistor Q and the source S of the field effect transistor Q during the rectification process, thereby avoiding the field effect transistor.
  • the current in the synchronous rectification circuit where Q is located flows through the body diode of the FET Q, and causes a large loss to the circuit in which the FET Q is located.
  • the synchronous rectification circuit of this embodiment can be either a half-wave rectification circuit as shown in FIG. 9 or a full-wave rectification circuit as shown in FIG.
  • the primary winding 51 of the transformer 5 in the rectifier circuit is connected to the series resonant converter
  • the FET Q is connected to the secondary winding 52 of the transformer 5
  • the detecting circuit is used for detecting the FET Q field effect transistor.
  • the manner in which the source S and the drain D of the tube Q are turned on rectifies the alternating current output from the secondary coil 52, and rectifies the alternating current into direct current.
  • the power consumption module 6 shown in FIG. 9 or FIG. 10 can be either a separate power device or a power consumption circuit configured with a plurality of power devices.
  • the primary winding 51 of the transformer 5 in this embodiment can obtain AC power from a power circuit such as a LLC resonant converter as shown in Fig. 9, a series resonant converter, a converter, and/or a buck converter as shown in FIG.
  • a power circuit such as a LLC resonant converter as shown in Fig. 9, a series resonant converter, a converter, and/or a buck converter as shown in FIG.
  • the primary winding 51 of the transformer 5 can also draw AC power from other power circuits than the power circuits disclosed above.

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Abstract

一种检测电路（100）以及同步整流电路，应用于检测并控制同步整流电路中的场效应管，解决了无法准确检测出场效应管的漏极与源极之间电压的电压值以及流过场效应管漏极和源极的电流的电流值的技术问题。检测电路（100），包括电感模块（1）、电阻模块（2）以及检测模块（3），互相串联的电感模块（1）与电阻模块（2）连接于场效应管源极与漏极之间；检测模块（3），用于通过测量获得电感模块（1）和电阻模块（2）的连接点到场效应管源极之间的电压值或流过电阻模块与场效应管的源极的电流的电流值，并根据电压值或电流值得出场效应管的源极与漏极之间的有效电压值或场效应管的源极与漏极的有效电流值。

Description

检测电路以及同步整流电路 本申请要求于 2 0 1 0 年 1 1 月 9 日提交中国专利局、 申请号为 2 0 1 0 1 0 5 3 8 3 3 8 . 4、 发明名称为 "检测电路以及同步整流电路" 的中 国专利申请的优先权， 其全部内容通过引用结合在本申请中。
技术领域
本发明涉及电子技术领域， 具体涉及一种检测电路以及设有该 检测电路的同步整流电路。
背景技术
目前， 由于场效应管与肖特基二极管相比， 场效应管的漏极与 源极之间导通时的电阻 （该电阻被称为导通电阻） 比肖特基二极管 的正极与负极之间导通时的电阻更低， 而导通电阻越低则对电路所 造成的电能损耗也越少， 所以用以实现交流电至直流电的高效率转 化的整流电路中越来越流行通过使用场效应管代替肖特基二极管进 行整流。
在现有的使用场效应管进行交流电至直流电转换的同步整流电 路中， 需要使用检测芯片来检测场效应管的漏极和场效应管的源级 之间电压的电压值或检测流过场效应管漏极和场效应管的源级的电 流值， 从而根据电压值或电流值的大小来控制场效应管的漏极与场 效应管的源极之间是导通还是断开。
以检测芯片通过检测场效应管的漏极和场效应管的源级之间电 压的电压值的大小来控制场效应管的漏极与场效应管的源极之间是 导通还是断开为例， 当检测芯片检测出场效应管的漏极和场效应管 的源级之间电压的电压值之后， 会将该电压值与预先设定的截止阀 值以及导通阀值进行对比， 导通阀值大于截止阀值， 若检测芯片所 检测到的电压值大于导通阀值， 则检测芯片会对场效应管的栅极发 送高电平信号， 场效应管的栅极接收到高电平信号后， 会控制场效 应管的漏极与场效应管的源极之间导通， 若检测芯片所检测到的电 压值小于截止阀值， 则检测芯片会对场效应管的栅极发送低电平信 号， 场效应管的栅极接收到低电平信号后， 会控制场效应管的漏极 与场效应管的源极之间截止。
但是， 从图 1 所示场效应管 Q 的等效模型电路图可知： 由于场 效应管 Q 不可避免的存在封装引线电感 L 1 以及导通电阻 R 1 , 封装 引线电感 L 1的存在会导致检测场效应管 Q的漏极 D与场效应管 Q的 源极 S之间导通时， 场效应管 Q的漏极 D与场效应管 Q的源极 S之 间电压的电压值非常困难， 这主要是因为检测场效应管 Q 的漏极 D 与场效应管 Q 的源极 S之间电压的电压值时， 需要在场效应管 Q 的 漏极 D与场效应管 Q 的源极 S 的引线之外进行检测， 检测封装引线 电感 L 1与场效应管 Q的源极 S之间电压的电压值会受到封装引线电 感 L 1 的影响， 所以检测出来的电压值与场效应管 Q的漏极 D与场效 应管 Q的源极 S之间电压的有效电压值， （ 即， 理想的电压值， 或称 理论上的电压值） 差别较大， 若直接检测导通电阻 R 1 与场效应管 Q 的源极 S之间电压的电压值， 则可以避开封装引线电感 L 1 的影响， 故而导通电阻 R 1与场效应管 Q的源极 S之间电压的电压值与场效应 管 Q的漏极 D与场效应管 Q 的源极 S之间电压的理想的电压值更为 接近， 所以导通电阻 R 1 与场效应管 Q的源极 S之间电压的电压值通 常可以被认为是场效应管 Q的漏极 D与场效应管 Q的源极 S之间有 效电压值。
如图 2所示， 图 2 中 a 线表示如图 1 所示场效应管 Q 的漏极 D 与场效应管 Q 的源极 S之间的有效电压， 即 B点至场效应管 Q 的源 极 S 之间电压的电压值的变化曲线， b 线表示场效应管 Q 的封装引 线电感 L 1 上的电压值的变化曲线， c线表示在场效应管 Q 的漏极 D 与场效应管 Q 的源极 S 的引线之外进行检测时， 所检测出的场效应 管 Q 的漏极 D与场效应管 Q 的源极 S之间电压即 A点至场效应管 Q 的源极 S之间电压的电压值的变化曲线。
由图 2 中可以看出： c线的相位早于 a线的相位， 当检测芯片根 据所检测出的 c 线所示的电压值的大小来控制场效应管 Q 的漏极 D 与场效应管 Q 的源极 S之间是导通还是断开时， 场效应管 Q 的漏极 D 与场效应管 Q 的源极 S 之间电压的电压值会更早的低于预先设定 的截止阀值 （例如 0 V ) , 进而会导致场效应管 Q 的漏极 D 与场效应 管 Q的源极 S提前截止， 场效应管 Q的漏极 D与场效应管 Q的源极 S 提前截止时， 同步整流电路内的电流会流过场效应管 Q 的体二极 管， 由于场效应管 Q 的体二极管的电阻远大于场效应管 Q 的导通电 阻的阻值， 所以会对同步整流电路造成较大的电能损耗。
本发明人在实现本发明的过程中发现， 现有技术至少存在以下 问题：
现有技术中， 检测场效应管 Q 的漏极 D 与场效应管 Q 的源极 S 之间的有效电压值或检测流过场效应管 Q漏极 D和场效应管 Q 的源 级 S 的有效电流值时， 需要在场效应管 Q的漏极 D与场效应管 Q的 源极 S的引线之外进行检测， 这样， 在检测封装引线电感 L 1 与场效 应管 Q的源极 S之间电压的电压值以及流过场效应管 Q漏极 D和场 效应管 Q的源级 S的电流的电流值的过程中会受到封装引线电感 L 1 的影响， 导致检测出来的电压值与场效应管 Q 的漏极 D与场效应管 Q的源极 S之间的有效电压值、检测出来的电流值与流过场效应管 Q 漏极 D和场效应管 Q 的源级 S 的有效电流值差别均较大， 所以无法 准确检测出场效应管 Q的漏极 D与场效应管 Q的源极 S之间的有效 电压值以及流过场效应管 Q漏极 D和场效应管 Q 的源级 S 的的有效 电流值。
发明内容
本发明实施例提供了一种检测电路以及设有该检测电路的同步整流 电路， 解决了现有技术无法准确检测出场效应管的漏极与场效应管的源 极之间电压的电压值以及流过场效应管漏极和场效应管的源级的电流的 电流值的技术问题。
为达到上述目的， 本发明的实施例采用如下技术方案：
该检测电路， 包括电感模块、 电阻模块以及检测模块， 其中： 所述电感模块与所述电阻模块互相串联，且互相串联的所述电感模块 与所述电阻模块连接于场效应管的源极与所述场效应管的漏极之间； 所述检测模块，用于通过测量获得所述电感模块和所述电阻模块的连 接点 'J所述场效应管源极之间的电压值或流过所述电阻模块与所述场效 应管的源极的电流的电流值，并根据所述电压值或电流值得出所述场效应 管的源极与漏极之间的有效电压值或流过所述场效应管的源极与漏极的 电流的有效电流值。
该同步整流电路， 包括变压器、 场效应管以及检测电路， 其中： 所述变压器的初级线圏用于获取交流电， 所述变压器的次级线圏用 于输出交流电；
所述场效应管的漏极与所述变压器的次级线圏的第一抽头相连，所述 变压器的次级线圏的第二抽头以及所述场效应管的源极分别与功耗器件 相连；
所述功耗器件， 用于从所述第二抽头以及所述场效应管的源极获取 直流电形式的电能；
所述检测电路包括电感模块、 电阻模块以及检测模块， 其中： 所述电感模块与所述电阻模块互相串联， 且互相串联的所述电感模 块与所述电阻模块连接于场效应管的源极与所述场效应管的漏极之间； 所述检测模块，用于通过测量得出所述场效应管的源极与漏极之间的 有效电压值或流过所述场效应管的源极与漏极的有效电流值。
本发明实施例通过以上技术方案， 检测模块可以通过测量获得所述 电感模块和所述电阻模块的连接点到所述场效应管源极之间的电压值或 流过所述电阻模块与所述场效应管的源极的电流的电流值，并根据所述电 压值或电流值得出所述场效应管的源极与漏极之间的有效电压值或流过 所述场效应管的源极与漏极的有效电流值的方式，避开场效应管的封装引 线电感的影响，进而能够更为精确地得出场效应管的导通电阻与场效应管 的源极之间电压的电压值，即场效应管的源极与场效应管的漏极之间有效 电压值或测量出流过场效应管的导通电阻与场效应管的源极的电流的电 流值， 即流过场效应管的源极与场效应管的漏极的有效电流值， 所以解 决了现有技术无法准确检测出场效应管的漏极与场效应管的源极之间有 效电压值以及流过场效应管漏极和场效应管的源级的有效电流值的技术 问题。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对 本发明实施例或现有技术描述中所需要使用的附图作筒单地介绍，显而易 见地， 下面描述中的附图仅仅是本发明的一些实施例， 对于本领域普通技 术人员来讲， 在不付出创造性劳动的前提下， 还可以根据这些附图获得其 他的附图。
图 1为现有技术中场效应管的等效模型的电路示意图；
图 2为图 1所示场效应管的漏极与场效应管的源极之间的理论上较为 理想的电压的波形线 a线、场效应管的封装引线电感上所检测出的电压的 波形线 b线以及从图 1所示 A点至场效应管的源极之间所检测出的电压的 波形线 c线的示意图；
图 3为本发明实施例 1的一种实施方式所提供的检测电路与场效应管 的连接关系的示意图；
图 4为本发明实施例 1的优选实施方式所提供的检测电路中各部件的 等效元器件与场效应管的连接关系的示意图；
图 5为从图 4所示 E点至场效应管的源极之间所检测出的电压的波形 线 d线、从 F点至场效应管的源极之间所检测出的电压的波形线 e线以及 从 G点至场效应管的源极之间所检测出的电压的波形线 f 线的示意图； 图 6为本发明实施例 1的又一种实施方式所提供的检测电路与场效应 管的连接关系的示意图；
图 7为本发明实施例 2所提供的检测电路与场效应管的连接关系的示 意图； 意图；
图 9为本发明实施例 3的一种实施方式所提供的应用本发明实施例 1 或实施例 2所提供的检测电路的同步整流电路的示意图；
图 1 0为本发明实施例 3的又一种实施方式所提供的应用本发明实施 例 1或实施例 2所提供的检测电路的同步整流电路的示意图；
图 1 1 为本发明实施例一种实施方式所提供的检测电路与场效应管的 连接关系的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进 行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例， 而不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没 有付出创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护 的范围。
如图 8所示，本发明实施例提供一种检测电路，如图中的虚线框所示， 包括检测电阻 Rcs、 检测电容 Ccs、 反相器 Fcs、 第一开关 Sa、 第二开关 Sb以及检测芯片 Ag , 检测芯片 Ag设置有第一管脚 Gl、 第二管脚 G2 , 其中：
第一管脚 G1 连接于检测电阻 Res 与检测电容 Ccs之间， 第二管脚 G2与场效应管 Q的源极 S相连；
检测芯片 Ag ,用于通过第一管脚 Gl、第二管脚 G2测量检测电容 Ccs 与场效应管 Q的源极 S之间电压的电压值；
反相器 Fes ,用于使第一开关 Sa与第二开关 Sb处于交替导通的状态； 当场效应管 Q的漏极 D与场效应管 Q的源极 S导通时，第一开关 Sa 闭合， 第二开关 Sb断开， 此时检测电容 Ccs以及检测电阻 Res串联在一 起， 且串联的检测电容 Ccs以及检测电阻 Res与场效应管 Q并联；
当场效应管 Q的漏极 D与场效应管 Q的源极 S截止时，第一开关 Sa 断开， 第二开关 Sb闭合， 此时， 检测电容 Ccs与检测电阻 Res之间断开， 检测电容 Ccs被短路；
根据并联电路两端电压相等的原理， 使得检测电路中检测电阻 Res 的阻值以及检测电容 Ccs的容值满足公式： = R2c； 上述公式中， Α表示场效应管 Q的封装引线电感 L 1的电感量， ^表 示场效应管 Q 的导通电阻 R1 的阻值， W2表示检测电路中检测电阻 Res 的阻值， C表示检测电路中检测电容 Ccs的容值；
设置第一开关 Sa与第二开关 Sb可以在场效应管 Q的漏极 D与场效 应管 Q的源极 S截止时， 使检测电容 Ccs短路， 由于电容具有较强的电 荷存储能力， 检测电容 Ccs短路时， 可以释放掉检测电容 Ccs内存储的电 荷， 进而避免在场效应管 Q的漏极 D与场效应管 Q的源极 S导通时， 检 测电容 Ccs内存储的电荷对场效应管 Q的漏极 D与场效应管 Q的源极 S 之间的电压造成影响，从而保证检测电路中检测电阻 Res的阻值以及检测 电容 Ccs的容值更好的满足上述公式，进而更为准确地检测出场效应管 Q 的漏极 D与场效应管 Q的源极 S之间电压的有效电压值。 公式时， 检测电容 Ccs与场效应管 Q的源极 S之间电压的电压值理论上 同场效应管 Q的导通电阻 R1 与场效应管 Q的源极 S之间电压的电压值 是相等的， 故而通过现有的检测电路可以较为准确地检测出导通电阻 R1 与场效应管 Q的源极 S之间电压的电压值， 即， 场效应管 Q的漏极 D与 场效应管 Q的源极 S之间电压的有效电压值， 进而能更为精确地控制场 效应管 Q的漏极 D与场效应管 Q的源极 S之间导通和截止。
但是在图 8 所示的检测电路中， 需要使用检测电容 Ccs、 检测电阻 Res , 反相器 Fcs、 第一开关 Sa以及第二开关 Sb等多种电子器件， 由于 所采用的电子器件种类和数量均比越多，所以导致由这些电子器件连接而 成的现有的检测电路电路构造复杂， 成本较高； 连接各电子器件形成检测 电路的连接操作比较麻烦， 同时， 由于现有的检测电路需要同时使用第一 开关 Sa以及第二开关 Sb , 至少要使用两个开关， 对两个开关进行控制的 操作比较麻烦、 复杂， 容易出错， 导致整个电路控制起来难度较大， 检测 操作比较麻烦。
为此， 本发明实施例还提供了一种电路构造筒单、 成本低且易于连接 的检测电路以及设有该检测电路的同步整流电路。
如图 11所示， 本发明实施例提供一种检测电路， 如图 3 中的虚线框 所示， （虚线框得左边是场效应管的等效模型电路图）， 包括电感模块 1、 电阻模块 2以及检测模块 3； 其中：
电感模块 1与电阻模块 2互相串联，且互相串联的电感模块 1与电阻 模块 2连接于场效应管 Q的源极 S与场效应管 Q的漏极 D之间；
检测模块 3 , 用于通过测量获得电感模块 1和电阻模块 2的连接点到 场效应管 Q源极 S之间的电压值或流过电阻模块 1与所述场效应管 Q的 源极 S的电流的电流值， 并根据上述电压值或电流值得出场效应管 Q的 源极 S与漏极 D之间的有效电压值或流过场效应管 Q的源极 S与漏极 D 的有效电流值。
本发明实施例通过以上技术方案，检测模块可以通过测量获得所述电 感模块和所述电阻模块的连接点到所述场效应管源极之间的电压值或流 过所述电阻模块与所述场效应管的源极的电流的电流值，并根据所述电压 值或电流值得出所述场效应管的源极与漏极之间的有效电压值或流过所 述场效应管的源极与漏极的电流的有效电流值的方式，避开场效应管的封 装引线电感的影响，进而能够更为精确地得出场效应管的导通电阻与场效 应管的源极之间电压的电压值，即场效应管的源极与场效应管的漏极之间 有效电压值或测量出流过场效应管的导通电阻与场效应管的源极的电流 的电流值， 即流过场效应管的源极与场效应管的漏极的有效电流值， 所以 解决了现有技术无法准确检测出场效应管的漏极与场效应管的源极之间 有效电压值以及流过场效应管漏极和场效应管的源级的有效电流值的技 术问题。
测量电阻模块 2两端的电压值（即， 图 3中电感模块和电阻模块的连 接端到场效应管 Q的源极 S之间的电压值） 或测量流过电阻模块 2与场 效应管 Q的源极 S 的电流的电流值， 并根据测量到的电压值或电流值以 及并联电路两端电压相等的原理得出场效应管 Q的源极 S与场效应管 Q 的漏极 D之间有效电压值或流过场效应管 Q的源极 S与场效应管 Q的漏 极 D的有效电流值。
实施例 1 : 如图 3所示， 本发明实施例所提供的检测电路， 如图 3中得虚线框所 示 （虚线框得左边是场效应管的等效模型电路图）， 包括电感模块 1、 电 阻模块 2以及检测模块 3 ,本实施例中检测模块 3上设置有第一连接端 31 和第二连接端 32; 第一连接端 31连接于电感模块 1与电阻模块 2之间， 第二连接端 32与场效应管 Q的源极 S相连； 其中：
电感模块 1与电阻模块 2互相串联，且互相串联的电感模块 1与电阻 模块 2连接于场效应管 Q的源极 S与场效应管 Q的漏极 D之间；
检测模块 3 , 具体用于通过第一连接端 31和第二连接端 32测量电阻 模块 2两端的电压值（即， 图 3中电感模块 1和电阻模块 2的连接点到场 效应管 Q的源极 S之间的电压值） 或测量流过电阻模块 2与场效应管 Q 的源极 S的电流的电流值，将测量得到的电压值或电流值分别作为电感模 块 1和电阻模块 2的连接点到场效应管 Q的源极 S之间的电压值或流过 电阻模块 2与场效应管 Q的源极 S的电流的电流值； 根据测量到的电压 值或电流值以及并联电路两端电压相等的原理得出场效应管 Q 的源极 S 与场效应管 Q的漏极 D之间有效电压值或流过场效应管 Q的源极 S与场 效应管 Q的漏极 D的有效电流值。
由于本发明实施例所提供的检测电路中， 电感模块 1 与电阻模块 2 互相串联， 且互相串联的电感模块 1 与电阻模块 2连接于场效应管 Q的 源极 S与场效应管 Q的漏极 D之间， 所以互相串联的电感模块 1与电阻 模块 2同场效应管 Q的源极 S以及场效应管 Q的漏极 D并联在了一起， 所以此时， 如图 4所示， 电感模块 1的等效电感 L2模拟了场效应管 Q的 封装引线电感 Ll、 电阻模块 2的等效电阻 R2模拟了场效应管 Q的导通 电阻 R1 , 电阻模块 2与场效应管 Q的源极 S之间电压的电压值 （即， 电 阻模块 2两端的电压值， 也就是说， 图 3中电感模块 1和电阻模块 2的连 接点到场效应管 Q的源极 S之间的电压值， 本申请以下实施例中关于电 阻模块 1与场效应管 Q的源极 S之间电压的电压值的解释， 如无特别的 说明， 均如上所述）与场效应管 Q的导通电阻 R1 (图 3和图 4中的 F点） 与场效应管 Q的源极 S之间电压的电压值 (即场效应管 Q的源极 S与漏 极 D 之间的有效电压值， 如图特别说明， 本发明以下实施例中的场效应 管 Q的源极 S与漏极 D之间的有效电压值的含义均如上所述） 之间的对 应关系， 可以根据并联电路两端电压相等的原理推导、 计算出来；
由此可见，本发明实施例中检测模块 3可以通过测量电阻模块 2与场 效应管 Q的源极 S之间电压的电压值或测量流过电阻模块 2与场效应管 Q 的源极 S的电流的电流值的方式，避开场效应管 Q的封装引线电感 L1的 影响，进而能够更为精确地测量或计算出场效应管 Q的导通电阻 R1与场 效应管 Q的源极 S之间电压的电压值， 即场效应管 Q的源极 S与场效应 管 Q的漏极 D之间有效电压值或测量出流过场效应管 Q的导通电阻 R1 与场效应管 Q的源极 S的电流的电流值， 即流过场效应管 Q的源极 S与 场效应管 Q的漏极 D的有效电流值， 所以解决了现有技术无法准确检测 出场效应管的漏极与场效应管的源极之间的有效电压值以及流过场效应 管漏极和场效应管的源级的有效电流值的技术问题； 电阻模块 2互相串联后， 接着与场效应管 Q的源极 S与场效应管 Q的漏 应管 Q源极 S的连接， 串联、 并联的电连接操作不仅步骤少， 而且连接 操作筒单， 而且要满足电感模块 1具有一定电感量、 电阻模块 2具有一定 电阻，仅需使用普通的电感与电阻即可实现，有利于降低检测电路的成本； 进一步地，本实施例提供的检测电路无需采用图 8中检测电路中所使用的 构造复杂且成本相对电感、 电阻较高的反相器、 电容等电子器件， 由于本 发明检测电路中所使用的电子器件的种类和数量均较少，而且电子器件之 间的连接关系也比较筒单，故而通过这些电子器件所连接而成的电路构造 也更为筒单。
图 6为为本发明实施例 1的又一种实施方式所提供的检测电路与场效 应管的连接关系的示意图。 如图 6所示， 本实施例中检测模块 3上设置有 第一连接端 31、 第二连接端 32以及信号发送端 33 , 其中：
第一连接端 31连接于电感模块 1与电阻模块 2之间， 第二连接端 32 与场效应管 Q的源极 S相连； 检测模块 3通过信号发送端 33与场效应管 Q的栅极 G相连；
检测模块 3 , 还用于根据得出的有效电压值或有效电流值的大小， 通 过信号发送端 33对场效应管 Q的栅极 G发送用以控制场效应管 Q的源 极 S与场效应管 Q的漏极 D之间导通或截止的电平信号。
由于本实施例检测电路所得出的场效应管 Q的源极 S与场效应管 Q 的漏极 D之间的有效电压值以及流过场效应管 Q的漏极 D与场效应管 Q 的源极 S的有效电流值更为准确，所以根据本实施例检测电路所得出的有 效电压值或有效电流值控制场效应管 Q的源极 S与场效应管 Q的漏极 D 之间导通或截止时， 也可以将场效应管 Q 控制的更为精确， 进而可以有 效的避免场效应管 Q的漏极 D与场效应管 Q的源极 S提前截止， 从而可 以避免场效应管 Q所在的电路 （例如如图 9或图 10所示同步整流电路） 内的电流流过场效应管 Q的体二极管， 而对场效应管 Q所在的电路造成 较大的损耗。
图 4为本发明实施例 1的优选实施方式所提供的检测电路中各部件的 等效元器件与场效应管的连接关系的示意图。 如图 4所示， 图 4中 L2表 示电感模块 1 的等效电感， 即等效电感 L2的电感量的值 L2与电感模块 1 的电感量的值相同， R2为电阻模块 2的等效电阻， 即 R2的阻值 R2与电 阻模块 2的阻值相同。 本实施例中电感模块 1的电感量的值与电阻模块 2 的阻值的比值等于场效应管 Q的封装引线电感 L 1的电感量的值与场效应 管 Q的导通电阻 R1的阻值的比值。
当电感模块 1的电感量的值与电阻模块 2的阻值的比值等于场效应管 Q的封装引线电感 L 1的电感量的值与场效应管 Q的导通电阻 R1的阻值 的比值时， 电阻模块 2与场效应管 Q的源极 S之间电压的电压值与场效 应管 Q的导通电阻 R1 与场效应管 Q的源极 S之间电压的电压值是相等 的， 所以根据电阻模块 2与场效应管 Q的源极 S之间电压的电压值可以 直接得出场效应管 Q的导通电阻 R1与场效应管 Q的源极 S之间电压的 电压值 (场效应管 Q的漏极 D与场效应管 Q的源极 S之间电压的有效电 压值）， 即电阻模块 2与场效应管 Q的源极 S之间电压的电压值。 具体推 导过程详述如下：
由于电感模块 1 的等效电感 L2的电感量的值为 L2 , 电阻模块 2的等 效电阻 R2 的阻值为 R2 , 流过如图 4所示场效应管 Q的封装引线电感 L 1 以及场效应管 Q的导通电阻 R1回路的电流为 流过电感模块 1的等效电 感 L2,电阻模块 1的等效电阻 R2回路的电流为 ^根据并联电路两端电压 相等的原理， 在 S域中可以得到：
Figure imgf000014_0001
经过移位推导可以得到： iA (i + ¾ = i2R2 (1 + ¾ 则当 1 + R 2 ;
Figure imgf000014_0002
L、 L7
当 ^ 时， 图 4中 F点与场效应管 Q的源极 S之间电压的电压值和 G点与场效应管 Q的源极 S之间电压的电压值是相等的， 故而只要使得 = 通过本实施例检测电路， 就可以直接、 准确地检测出 F点与场
Figure imgf000014_0003
效应管 Q的源极 S之间电压的电压值即场效应管 Q的漏极 D与场效应管 Q的 源极 S之间电压的电压值。 与此同理， 由于电流与电压之间是可以互相转换的， 即可以通过测试 电流值的大小推导出电压值， 也可以通过测试电压值的大小推导出电流 效应管 Q的源极 S与场效应管 Q的漏极 D之间有效电压值的实施方式， 本领域技术人员在不付出创造性劳动的前提下，完全可以根据电压与电流 之间的变换关系即公式 U=IR, 根据本实施例所公开的技术方案推导出如 何具体测量并得出流过场效应管 Q的源极 S与场效应管 Q的漏极 D的有 效电流值的大小， 所以此处不再展开。
因为封装引线电感 L1的存在， E点与场效应管 Q的源极 S之间电压 的电压值和 F点与场效应管 Q的源极 S之间电压的电压值相差颇大， 从 图 5可以看出： E点与场效应管 Q的源极 S之间电压的电压值的波形线 d 线的圓圏 D内的部分中所示的负压就是由封装引线电感 L1 引起的， 原因 是由于电流的急速下降， 封装引线电感 L1会感应出一个反方向的电压阻 止电流的下降， 电流下降速度越快， 此处的负压就会越大， 从而导致检测 E点与场效应管 Q的源极 S之间电压的电压值非常不准确， 而连接上本 实施例检测电路后， 检测到 G点与场效应管 Q的源极 S之间有效电压值 变化的波形如 f 线所示， 由于 F点与场效应管 Q的源极 S之间电压的电 压值变化的波形如 e线所示， 由此可见， e线与 f线是一样的， 这说明： 本实施例检测电路确实能够准确地检测到场效应管 Q的漏极 D与场效应 管 Q的源极 S之间有效电压值， 进而当场效应管 Q应用于同步整流电路 内时， 检测模块 3 能够更为精确地控制场效应管 Q , 避免场效应管 Q的 漏极 D以及场效应管 Q的源极 S之间提前截止。
当本实施例中电感模块 1的电感量的值与电阻模块 2的阻值的比值不 等于场效应管 Q的封装引线电感 L1的电感量的值与场效应管 Q的导通电 阻 Rl的阻值的比值时， 可以通过本实施例检测电路检测出电阻模块 2与 场效应管 Q的源极 S之间电压的电压值之后， 再根据电感模块 1 的电感 量的值与电阻模块 1的阻值的比值关系计算出场效应管 Q的漏极 D与场 效应管 Q的源极 S之间的有效电压值。
如图 6所示， 本实施例中检测电路还包括开关模块 4 , 开关模块 4与 电感模块 1、 电阻模块 2互相串联， 其中：
开关模块 4连接于电感模块 1与电阻模块 2之间，用于在场效应管 Q 的源极 S与场效应管 Q的漏极 D之间断开时， 使电感模块 1与电阻模块 2之间断开；在场效应管 Q的源极 S与场效应管 Q的漏极 D之间导通时 , 使电感模块 1与电阻模块 2之间相连；
或者， 开关模块 4连接于电阻模块 2与场效应管 Q的源极 S或场效 应管 Q的漏极 D之间，用于在场效应管 Q的源极 S与场效应管 Q的漏极 D之间断开时， 使电阻模块 2与场效应管 Q的源极 S或场效应管 Q的漏 极 D之间断开； 在场效应管 Q的源极 S与场效应管 Q的漏极 D之间导通 时， 使电阻模块 2与场效应管 Q的源极 S或场效应管 Q的漏极 D之间相 连；
或者， 开关模块 4连接于电感模块 1与场效应管 Q的漏极 D或场效 应管 Q的源极 S之间， 用于在场效应管 Q的源极 S与场效应管 Q的漏极 D之间断开时， 使电感模块 1与场效应管 Q的漏极 D或场效应管 Q的源 极 S之间断开； 在场效应管 Q的源极 S与场效应管 Q的漏极 D之间导通 时， 使电感模块 1与场效应管 Q的漏极 D或场效应管 Q的源极 S之间相 连。
开关模块 4的等效电子器件为如图 4所示等效开关 K, 开关模块 4的 存在不仅能够在场效应管 Q的漏极 D与场效应管 Q的源极 S截止时， 使 得电感模块 1、 电阻模块 2与场效应管 Q的漏极 D、 场效应管 Q的源极 S 所形成的并联回路断开，进而减少电感模块 1以及电阻模块 2对场效应管 Q所在的电路 (例如如图 9或图 10所示同步整流电路） 所造成的损耗， 而且由于电感元件为储能元件， 电感模块 1本身具有一定的储能作用， 开 关模块 4可以在场效应管 Q的漏极 D与场效应管 Q的源极 S截止时， 使 电感模块 1 内存储的电能释放掉，进而避免电感模块 1 内存储的电能在场 效应管 Q的漏极 D与场效应管 Q的源极 S导通时， 对电阻模块 2与场效 应管 Q的源极 S之间电压造成影响， 故而可以保证本实施例检测电路所 检测到的电压值或电流值更为准确。
由于电感元件相对于电容元件而言， 对电路所造成的损耗更小， 本实 施例中电感模块 1 所存储的电能对场效应管 Q所在的电路 （例如如图 9 或图 10所示同步整流电路） 所造成的损耗远低于现有的检测电路中检测 电容对场效应管 Q所在的同步整流电路所造成的影响，所以在场效应管 Q 的漏极 D与场效应管 Q的源极 S之间电压的电压值检测准确性不太高时， 也可以不设置本实施例所提供的开关模块 4。
如图 4、 6或 7所示， 本实施例中开关模块 4通过信号发送端 33与检 测模块 3相连， 其中：
检测模块 3 , 还用于根据得出的电压值或电流值的大小， 通过信号发 送端 33对开关模块 4发送控制指令；
控制指令与用以控制场效应管 Q的源极 S与场效应管 Q的漏极 D之 间导通或截止的电平信号相同；
开关模块 4 , 用于接收检测模块 3发出的控制指令， 并根据控制指令 控制电感模块 1与电阻模块 2之间， 或者， 控制电阻模块 2与场效应管 Q 的源极 S或场效应管 Q的漏极 D之间， 或者， 控制电感模块 1与场效应 管 Q的漏极 D或场效应管 Q的源极 S之间断开或相连。
本实施例中检测模块 3根据所检测出的电阻模块 2与场效应管 Q的 源极 S之间电压的电压值或测量流过电阻模块 1与场效应管 Q的源极 S 的电流的电流值可以实现对开关模块 4以及场效应管 Q的同步控制。
由于本实施例中同一检测模块 3 采用同一信号发送端 33 , 发送同一 电平信号的方法可以实现同时、 同步控制开关模块 4以及场效应管 Q , 不 仅可以充分利用检测模块 3的数据处理能力，从而更为有效的利用已有资 源， 而且对开关模块 4以及场效应管 Q的控制更为筒单、 方便。
本实施例中开关模块 4为 MOS管 （Metal-Oxide-Semiconductor, 金 属 -氧化物-半导体） 或三极管， 优选为 MOS管。 MOS管或三极管均为技 术上较为成熟、 性能稳定、 可靠的电子开关器件， 而且可以通过对栅极或 基极发送电平信号的方式对 MOS管或三极管进行控制， 所以适宜于应用 于作为本实施例开关模块 4 , 当然， 本实施例中开关模块 4也可以为 MOS 管以及三极管之外的其他开关电子器件。
本实施例中检测模块 3可以使用现有技术中已有的检测芯片，也可以 使用具有类似检测芯片功能的具有数据处理能力的其他检测器件或检测 设备。
如图 6所示， 本实施例检测电路还包括连接于信号发送端 33与场效 应管 Q的栅极 G和 /或连接于信号发送端 33与开关模块 4之间的驱动模 块 7 , 其中：
驱动模块 7, 用于接收检测模块 3发出的电平信号， 并将电平信号升 压之后发送至场效应管 Q的栅极 G和 /或开关模块 4。
驱动模块 7采用升压的方式放大电平信号可以增强电平信号驱动、控 制场效应管 Q和 /或开关模块 4的能力， 进而还可以扩大检测模块 3所能 控制的场效应管 Q和 /或开关模块 4的种类和范围。
本实施例中电感模块 1 的电感量的值与场效应管 Q的封装引线电感 L1的电感量的值的比值至少为 100 ,和 /或，电阻模块 2的阻值至少为 50Ω。
由于本实施例检测电路中， 作为开关模块 4的 MOS管或三极管本身 也存在封装引线电感，所以电感模块 1的电感量的值与如图 4所示场效应 管 Q的封装引线电感 L1的电感量的值的比值越大时， 作为开关模块 4的 MOS管或三极管的封装引线电感对电阻模块 2与场效应管 Q的源极 S之 间电压或流过电阻模块 2与场效应管 Q的源极 S的电流所造成的影响越 小，进而本实施例检测电路所检测出的电阻模块 2与场效应管 Q的源极 S 之间电压的电压值或流过电阻模块 2与场效应管 Q的源极 S的电流的电 流值也会更为准确。
与之同理， 作为开关模块 4的 MOS管或三极管本身也存在的导通电 阻， 电阻模块 2的阻值与 MOS管或三极管的导通电阻的阻值的比值越大 时， MOS管或三极管本身所存在的导通电阻所造成的影响越小。
实践证明： 电感模块 1 的电感量的值与如图 4所示场效应管 Q的封 装引线电感 L1的电感量的值的比值至少为 100时， 和 /或， 电阻模块 2的 阻值至少为 50Ω时， 电感模块 1以及电阻模块 2对场效应管 Q所在的电 路造成损耗不会太大，而且本实施例检测电路所检测出的电阻模块 2与场 效应管 Q的源极 S之间电压的电压值或流过电阻模块 1与场效应管 Q的 源极 S的电流的电流值也比较精确。
本实施例中电感模块 1 的电感量的值与场效应管 Q的如图 4所示封 装引线电感 L1的电感量的值的比值为 800 ~ 1200 , 优选为 1000 , 和 /或， 电阻模块 2的阻值为 80 ~ 120Ω , 优选为 100Ω。
当电感模块 1的电感量的值和 /或电阻模块 2的阻值符合上述条件时， 电感模块 1 以及电阻模块 2不仅不会对场效应管 Q所在的电路造成太大 的损耗，而且也可以更为精确地检测出电阻模块 2与场效应管 Q的源极 S 之间电压的电压值或流过电阻模块 2与场效应管 Q的源极 S的电流的电 流值。
本实施例中电感模块 1 为一个电感或电感模块 1 为多个电感并联和 / 或串联而成， 电阻模块 2为一个电阻或电阻模块 2为多个电阻并联和 /或 串联而成。
无论电感模块 1仅为一个电感， 还是由多个电感并联和 /或串联而成， 电阻模块 2仅为一个电阻， 还是由多个电阻并联和 /或串联而成， 只要保 证电感模块 1 的电感量的值与电阻模块 2 的阻值的比值等于场效应管 Q 的封装引线电感 L1的电感量的值与场效应管 Q的导通电阻 R1的阻值的 比值， 既可以保证电阻模块 2与场效应管 Q的源极 S之间的电压与场效 应管 Q的导通电阻 R1与场效应管 Q的源极 S之间的电压相等， 便可以 更为精确地检测出场效应管 Q的漏极 D与场效应管 Q的源极 S之间的有 效电压值。
实施例 2: 如图 7所示， 本实施例与实施例 1基本相同， 其不同点在于： 本实施 例中电感模块 1与电阻模块 2之间还可以串联连接电阻 R3 , 此时， 第一 连接端 31连接于电阻模块 2与连接电阻 R3之间。 本实施例中连接电阻 R3既可以为一个电阻， 也可以为多个电阻并联和 /或串联而成。
假设连接电阻 R3的阻值为 R3，电阻模块 2的阻值为 R2 , 连接电阻 R3 与场效应管 Q的源极 S之间电压的电压值为 U3 , 电阻模块 2与场效应管 Q的源极 S之间电压的电压值为 U2 , 则 U3/ U2 = ( R3 + R2 ) / R2 由此可以导出 U3=[ ( R3 + R2 ) * U2 ]/ R2 , 所以当检测模块 3通过第一连 接端 31、第二连接端 32测量出电阻模块 2与场效应管 Q的源极 S之间电 压的电压值 U2时，可以通过上述公式计算出连接电阻 R3与场效应管 Q的 源极 S之间电压的电压值为 U3 ,进而也可以得到场效应管 Q的源极 S与场 效应管 Q的漏极 D之间电压的电压值即图 4中 F点至场效应管 Q的源极 S 之间电压的电压值。 由上述公式可以看出： 当连接电阻 R3的阻值 R3与电阻模块 2的阻值 R2的比值越小时， 本实施例检测电路所测出的电阻模块 1 与场效应管 Q 的源极 S之间的电压越接近场效应管 Q的等效电路中导通电阻 R1与场效 应管 Q的源极 S之间电压的电压值， 即效应管 Q的源极 S与漏极 D之间 的有效电压值。
与之同理，当本实施例中检测模块 3测量出流过电阻模块 2与场效应 管 Q的源极 S 的电流的电流值时， 也可以根据测量到的电流值以及并联 电路两端电压相等的原理计算出流过场效应管 Q的源极 S与场效应管 Q 的漏极 D的电流的电流值。
4艮好理解的是， 由于电阻模块 2既可以为一个电阻， 也可以为多个电 阻并联和 /或串联而成。 实施例 2还可以理解成电阻模块 2与连接电阻 R3 组成了一个更大的电阻模块，检测模块 3可以对这个更大的电阻模块的部 分电阻的电压进行检测， 通过检测到的部分电阻的电压， 利用部分电阻的 阻值和全电阻模块的阻值的比值， 计算获得电阻模块 2与场效应管 Q的 源极 S之间电压的电压值。
由于本发明实施例 1以及实施例 2中无需同时使用如图 8对应实施例 中的检测电路所示第一开关 Sa以及第二开关 Sb , 也可以测量或计算出如 图 4所示场效应管 Q的导通电阻 R1与场效应管 Q的源极 S之间电压的 电压值或测量出流过场效应管 Q的导通电阻 R1 与场效应管 Q的源极 S 的电流的电流值，故而可以节省控制第一开关 Sa以及第二开关 Sb的操作， 进而本发明实施例 1 以及实施例 1所提供的检测电路检测操作更为筒单。
实施例 3 : 如图 9所示， 本发明实施例所提供的同步整流电路， 包括变压器 5、 场效应管 Q 以及上述本发明实施例 1或实施例 1 所提供的任一技术方案 中所提供的检测电路， 其中：
变压器 5 的初级线圏 5 1 用于获取交流电， 变压器 5 的次级线圏 52 用于输出交流电；
场效应管 Q的漏极 D与变压器 5的次级线圏 52的第一抽头相连，变 压器 5的次级线圏 52的第二抽头以及场效应管 Q的源极 S分别与功耗模 块 6相连；
功耗模块 6 ,用于从第二抽头以及场效应管 Q的源极 S获取直流电形 式的电能； 检测模块 3 ,用于测量电阻模块 2与场效应管 Q的源极 S之间电压的 电压值或测量流过电阻模块 2与场效应管 Q的源极 S的电流的电流值， 并根据测量到的电压值或电流值以及并联电路两端电压相等的原理得出 场效应管 Q的源极 S与场效应管 Q的漏极 D之间电压的电压值或流过场 效应管 Q的源极 S与场效应管 Q的漏极 D的电流的电流值。
本实施例中， 检测电路能够检测出场效应管 Q的源极 S 以及场效应 管 Q的漏极 D之间电压的电压值或流过场效应管 Q的源极 S以及场效应 管 Q的漏极 D的电流的电流值， 并根据所检测到的电压值或电流值对场 效应管 Q的栅极 G发送用以控制场效应管 Q的源极 S以及场效应管 Q的 漏极 D之间是否导通的电平信号， 进而通过控制场效应管 Q的源极 S与 漏极 D是否导通的方式对次级线圏 52所输出交流电进行整流， 将交流电 整流为直流电。
与上述本发明实施例 1或实施例 2所提供的检测电路同理，由于本发 明实施例所提供的检测电路中， 电感模块 1与电阻模块 2互相串联， 且互 相串联的电感模块 1与电阻模块 2连接于场效应管 Q的源极 S与场效应 管 Q的漏极 D之间， 所以互相串联的电感模块 1与电阻模块 2同场效应 管 Q的源极 S以及场效应管 Q的漏极 D并联在了一起， 所以此时， 电感 模块 1模拟了场效应管 Q如图 4所示的封装引线电感 Ll、 电阻模块 2模 拟了场效应管 Q的导通电阻 R1 , 电阻模块 1与场效应管 Q的源极 S之间 电压的电压值与场效应管 Q的导通电阻 R1 与场效应管 Q的源极 S之间 电压的电压值之间的对应关系，可以根据并联电路两端电压相等的原理推 导、 计算出来， 由此可见， 检测模块 3可以通过测量电阻模块 2与场效应 管 Q的源极 S之间电压的电压值或测量流过电阻模块 2与场效应管 Q的 源极 S的电流的电流值的方式，避开场效应管 Q的封装引线电感 L1的影 响， 进而能够更为精确地测量或计算出场效应管 Q的导通电阻 R1与场效 应管 Q的源极 S之间电压的电压值或测量出流过场效应管 Q的导通电阻 R1与场效应管 Q的源极 S的电流的电流值， 所以解决了现有技术无法准 确检测出场效应管的漏极与场效应管的源极之间电压的电压值以及流过 场效应管漏极和场效应管的源级的电流的电流值的技术问题； 电阻模块 2互相串联后， 接着与场效应管 Q的源极 S与场效应管 Q的漏 应管 Q源极 S的连接， 串联、 并联的电连接操作不仅步骤少， 而且连接 操作筒单， 而且要满足电感模块 1具有一定电感量、 电阻模块 2具有一定 电阻，仅需使用普通的电感与电阻即可实现，有利于降低检测电路的成本； 且电子器件之间的连接关系也比较筒单，故而通过这些电子器件所连接而 成的电路构造也更为筒单。
另外， 由于本实施例中检测电路所得出的场效应管 Q的源极 S与场 效应管 Q的漏极 D之间的电压值以及流过场效应管 Q的导通电阻 R1与 场效应管 Q的源极 S 电流的电流值更为准确， 所以根据检测电路所检测 出的电压值或电流值控制场效应管 Q的源极 S与场效应管 Q的漏极 D之 间导通或截止时， 也可以将场效应管 Q控制的更为精确， 进而可以有效 的避免整流过程中场效应管 Q的漏极 D与场效应管 Q的源极 S之间提前 截止， 从而可以避免场效应管 Q 所在的同步整流电路内的电流流过场效 应管 Q的体二极管， 而对场效应管 Q所在的电路造成较大的损耗。
本实施例同步整流电路既可以为如图 9所示半波整流电路，也可以为 如图 10所示全波整流电路。
如图 10所示，整流电路中变压器 5的初级线圏 51与串联谐振转换器 相连， 场效应管 Q与变压器 5的次级线圏 52相连， 检测电路用于检测场 效应管 Q场效应管 Q的源极 S以及场效应管 Q的漏极 D之间电压的电压 值或流过场效应管 Q的源极 S以及场效应管 Q的漏极 D的电流的电流值 , 进而通过控制场效应管 Q的源极 S与漏极 D是否导通的方式对次级线圏 52所输出交流电进行整流， 将交流电整流为直流电。 本实施例中如图 9或图 10所示功耗模块 6既可以为单独的用电器件， 也可以为一个设置有多个用电器件所构成的功耗电路。
本实施例中变压器 5的初级线圏 51可以从如图 9所示 LLC谐振转换 器、 如图 10所示串联谐振转换器、 激转换器和 /或降压转换器等功率电路 获取交流电。 当然， 变压器 5的初级线圏 51也可以从以上所公开功率电 路之外的其他功率电路获取交流电。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局 限于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可 轻易想到的变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发 明的保护范围应以权利要求的保护范围为准。

Claims

权 利 要 求 书
1、 一种检测电路， 其特征在于： 包括电感模块、 电阻模块以及检测模 块， 其中：
所述电感模块与所述电阻模块互相串联， 且互相串联的所述电感模块 与所述电阻模块连接于场效应管的源极与所述场效应管的漏极之间；
所述检测模块， 用于通过测量获得所述电感模块和所述电阻模块的连 接点到所述场效应管源极之间的电压值或流过所述电阻模块与所述场效应 管的源极的电流的电流值， 并根据所述电压值或电流值得出所述场效应管 的源极与漏极之间的有效电压值或流过所述场效应管的源极与漏极的有效 电流值。
2、 根据权利要求 1所述的检测电路， 其特征在于： 所述检测模块上设 置有第一连接端、 第二连接端以及信号发送端， 其中：
所述第一连接端连接于所述电感模块与所述电阻模块之间， 所述第二 连接端与所述场效应管的源极相连；
所述检测模块， 具体用于通过所述第一连接端和所述第二连接端测量 所述电阻模块的两端电压值或流过所述电阻模块与所述场效应管的源极的 电流的电流值， 将测量得到的电压值或电流值分别作为所述电感模块和所 述电阻模块的连接点到所述场效应管源极之间的电压值或流过所述电阻模 块与所述场效应管的源极的电流的电流值；
所述检测模块通过所述信号发送端与所述场效应管的栅极相连； 所述检测模块， 还用于根据得出的所述电压值或所述电流值的大小， 通过所述信号发送端对所述场效应管的栅极发送用以控制所述场效应管的 源极与所述场效应管的漏极之间导通或截止的电平信号。
3、 根据权利要求 2所述的检测电路， 其特征在于： 所述电感模块的电 感量的值与所述电阻模块的阻值的比值等于所述场效应管的引线电感的电 感量的值与所述场效应管的导通电阻的阻值的比值；
此时， 所述电感模块和所述电阻模块的连接点到所述场效应管源极之 间的电压值或流过所述电阻模块与所述场效应管的源极的电流的电流值分 别为所述场效应管的源极与漏极之间的有效电压值或流过所述场效应管的 源极与漏极的有效电流值。
4、 根据权利要求 1或 2所述的检测电路， 其特征在于： 该检测电路还 包括开关模块， 所述开关模块与所述电感模块、 所述电阻模块互相串联， 其中：
所述开关模块连接于所述电感模块与所述电阻模块之间， 用于在所述 场效应管的源极与所述场效应管的漏极之间断开时， 使所述电感模块与所 述电阻模块之间断开； 在所述场效应管的源极与所述场效应管的漏极之间 导通时， 使所述电感模块与所述电阻模块之间相连；
或者， 所述开关模块连接于所述电阻模块与所述场效应管的源极或所 述场效应管的漏极之间， 用于在所述场效应管的源极与所述场效应管的漏 极之间断开时， 使所述电阻模块与所述场效应管的源极或所述场效应管的 使所述电阻模块与所述场效应管的源极或所述场效应管的漏极之间相连； 或者， 所述开关模块连接于所述电感模块与所述场效应管的漏极或所 述场效应管的源极之间， 用于在所述场效应管的源极与所述场效应管的漏 极之间断开时， 使所述电感模块与所述场效应管的漏极或所述场效应管的 使所述电感模块与所述场效应管的漏极或所述场效应管的源极之间相连。
5、 根据权利要求 4所述的检测电路， 其特征在于： 所述检测模块通过 所述信号发送端与所述开关模块相连， 其中： 通过所述信号发送端对所述开关模块发送控制指令；
所述控制指令与用以控制所述场效应管的源极与所述场效应管的漏极 之间导通或截止的电平信号相同；
所述开关模块， 用于接收所述控制指令， 并根据所述控制指令控制所 述电感模块与所述电阻模块之间断开或相连， 或者， 控制所述电阻模块与 所述场效应管的源极或所述场效应管的漏极之间断开或相连， 或者， 控制 所述电感模块与所述场效应管的漏极或所述场效应管的源极之间断开或相 连。
6、 根据权利要求 5 所述的检测电路， 其特征在于： 所述开关模块为 M0S管或三极管。
7、 根据权利要求 1或 2所述的检测电路， 其特征在于： 所述电感模块 的电感量的值与所述场效应管的封装引线电感的电感量的值的比值大于或 等于 1 00 , 和 /或， 所述电阻模块的阻值大于或等于 5 0 Ω。
8、 根据权利要求 7所述的检测电路， 其特征在于： 所述电感模块的电 感量的值与所述场效应管的封装引线电感的电感量的值的比值为 8 00 ~ 1 200 , 和 /或， 所述电阻模块的阻值为 8 0 ~ 1 20 Ω。
9、 根据权利要求 1或 2所述的检测电路， 其特征在于： 所述电感模块 为一个电感或所述电感模块为多个电感并联和 /或串联而成，所述电阻模块 为一个电阻或所述电阻模块为多个电阻并联和 /或串联而成。
1 0、 一种同步整流电路， 其特征在于： 包括变压器、 场效应管以及检 测电路， 其中：
所述变压器的初级线圏用于获取交流电， 所述变压器的次级线圏用于 输出交流电； 所述场效应管的漏极与所述变压器的次级线圏的第一抽头相 连， 所述变压器的次级线圏的第二抽头以及所述场效应管的源极分别与功 耗器件相连；
所述功耗器件， 用于从所述第二抽头以及所述场效应管的源极获取直 流电形式的电能；
所述检测电路用于通过测量得出所述场效应管的源极与漏极之间的有 效电压值或流过所述场效应管的源极与漏极的电流的有效电流值。
1 1、 根据权利要求 1 0所述的同步整流电路， 其特征在于： 所述检测电 路包括电感模块、 电阻模块以及检测模块， 其中：
所述电感模块与所述电阻模块互相串联， 且互相串联的所述电感模块 与所述电阻模块连接于场效应管的源极与所述场效应管的漏极之间；
所述检测模块， 用于通过测量获得所述电感模块和所述电阻模块的连 接点到所述场效应管源极之间的电压值或流过所述电阻模块与所述场效应 管的源极的电流的电流值， 并根据所述电压值或电流值得出所述场效应管 的源极与漏极之间的有效电压值或流过所述场效应管的源极与漏极的有效 电流值。
12、 根据权利要求 11所述的同步整流电路， 其特征在于， 所述电感模 块的电感量的值与所述电阻模块的阻值的比值等于所述场效应管的引线电 量获得所述电感模块和所述电阻模块的连接点到所述场效应管源极之间的 电压值或流过所述电阻模块与所述场效应管的源极的电流的电流值为所述 场效应管的源极与漏极之间的有效电压值或流过所述场效应管的源极与漏 极的有效电流值。
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