WO2011134092A2

WO2011134092A2 - Circuit for a multilevel converter comprising thyristor switching

Info

Publication number: WO2011134092A2
Application number: PCT/CH2011/000083
Authority: WO
Inventors: Ralph Niederer
Original assignee: Ralph Niederer
Priority date: 2010-04-27
Filing date: 2011-04-18
Publication date: 2011-11-03
Also published as: CH703022A2; WO2011134092A3

Abstract

Disclosed is a circuit for a multilevel converter, consisting of individual cells formed by a DC link capacitor and by 2 semiconductor switches, 2 freewheeling diodes, and 2 thyristors for each phase. The DC links of the cells are connected in series, and those thyristors of all cells that are part of one phase are interconnected and form the phase output of the converter. In each phase, one thyristor is switched on, thus selecting the cell that is active for said phase. An additional voltage source is required to switch the thyristor.

Description

B E S C H R E I N C U Circuit for a multilevel inverter with thyristor switching

Technical area

The invention relates to the field of power electronics. Fields of application are, for example, converters in drive technology or in the power supply.

To increase the voltage and reduce the harmonics of the inverters, multi-level inverters (multilevel inverters) can be used.

State of the art

The circuit topologies commonly used in converters can be roughly divided into 3 categories, namely voltage source inverters, power source inverters, and cycloconverters.

The voltage source inverters can be subdivided into the number of states into which each converter phase can be switched. For a two-position inverter, each inverter phase can be switched to 2 different states (+ and -).

In the case of a multilevel inverter, each inverter phase can be switched to more than 2 different states, for example three different states (+, 0 and -) for the three-level inverter in 3.

Typical representatives of the multilevel inverters are the Neutral Point Clamped Inverter (NPC), the Flying Capacitor Inverter, the Cascaded H-Bridge Inverter (CHB) and the Modular Multilevel Inverter (M2C).

In these multilevel circuit topologies, the current of each inverter phase flows through a plurality of semiconductor switches (i.e., turn-off power semiconductors such as IGBT, IGCT, GTO, or MOSFET) or freewheeling diodes (i.e., fast-switching diodes).

In this case, the current flows through all the more semiconductor switches or free-wheeling diodes, the more levels a circuit has. An overview of the known multilevel inverters can be found, for example, in the publication "Diode-clamped Multilevel Voltage Source Converter for Medium Voltage Dynamic Voltage Restorer" by P. Boonchiam and N. Mithulananthan.

Presentation of the invention

The circuit according to this invention consists of at least 2 series-connected cells. Each cell may have one or more inverter phases connected in parallel to the same DC link capacitor.

Each cell consists of a DC link capacitor or a DC voltage source and per current direction and phase each consisting of a turn-off semiconductor, a freewheeling diode (fast diode) and a thyristor.

The cell active for each phase is switched to the phase connection of the inverter by the thyristor network.

The corresponding thyristors are switched only with the fundamental frequency of the phase current.

Since the thyristors can not be actively switched off, an additional voltage source, the commutation voltage source, is used to switch over the thyristors.

For a 3-point circuit, 2 such cells are switched in series, for a 5-point circuit 4 such cells are switched in series.

In the circuit according to this invention, the current of each converter phase flows only through a semiconductor switch (turn-off power semiconductor) or a freewheeling diode (fast diode) and through a thyristor.

The forward losses of the thyristors are significantly lower than those of the semiconductor switches or freewheeling diodes. For this reason, the circuit topology according to this invention has significantly lower forward losses than the previously known circuit topologies.

Since the switching losses remain unchanged compared with the previous circuit topologies, the circuit according to this invention has overall lower semiconductor losses. This improves the efficiency of the drive and reduces the cost of the semiconductors and their cooling.

Another advantage of the circuit according to this invention is that in the switching operations of the semiconductor switches in each case only a semiconductor switch and a

Freewheeling diode are involved within the same cell.

Therefore, only the phases within a cell need to be low-inductively configured, and not the complete circuit as in the Neutral Point Clamped Inverter (NPC) or Flying Capacitor inverter. This reduces the requirements for the mechanical structure of the circuit.

Brief description of the drawings

In the following the invention will be explained in more detail with reference to embodiments in conjunction with the drawings.

In all figures, the semiconductor switches are represented as IGBTs representative of any type of semiconductor device which can be turned off (IGBT, IGCT, GTO or MOSFET).

Show it:

1 shows the circuit diagram of a cell for a converter phase with two current directions for the circuit according to the invention;

Fig. 2 shows the schematic diagram of a cell for a converter phase with both current directions, wherein the terminals of the semiconductor switches are connected to each other for both current directions;

Fig. 3 shows the circuit diagram of an inventive three-point circuit for a

Converter phase with both current directions;

Fig. 4 shows the circuit diagram of an inventive three-point circuit for a

Converter phase with both current directions with additional auxiliary commutation circuits; Fig. 5 shows the circuit diagram of an inventive five-point circuit for a

Inverter phase with both current directions, with a star-shaped thyristor network;

Fig. 6 shows the circuit diagram of an inventive five-point circuit for a

Inverter phase with both current directions, with a chain-shaped thyristor network;

Fig. 7 shows the circuit diagram of an inventive three-point circuit for a

Inverter phase with a load current angle of 0 degrees;

Fig. 8 shows the circuit diagram of an inventive three-point circuit for a

Inverter phase with a load current angle of 180 degrees;

Embodiment of the invention

The circuit topology according to this invention consists of several cells. Each cell may have one or more inverter phases which are parallel to one another

DC link capacitor are connected.

A cell consists of a DC link capacitor (CZK), whose voltage can be considered to be substantially constant, and each converter phase and each of their current directions of a turn-off semiconductor (SP or SN), a freewheeling diode (DP or DN) and a thyristor (TP or TN).

The current direction which leads out of a cell is called positive.

A cell which is designed for one phase and both current directions is shown in FIG.

The cell according to FIG. 1 behaves as follows:

With positive phase current, TP conducts. TN is locked.

SP is clocking, i. is switched on and off, thus switching the phase connection AC to CZK + or CZK-. While SP is off, the phase current flows through DP.

With negative phase current, TN conducts. TP is locked. SN clocks, ie is switched on and off, and thus switches the phase connection AC to CZK + or CZK-. While SN is off, the current flows through DN.

Figure 2 shows a cell with the same characteristics as the cell according to Figure 1, wherein the terminals of the semiconductor switches for the two current directions are interconnected.

In order to obtain a multilevel circuit, now several such cells

connected together.

The DC link capacitors are connected in series, but not directly, but via the commutation voltage source (UK), which is opposite to the

DC link capacitors is poled. As a result, the DC link capacitors are offset by the voltage UK, thereby enabling the commutation (that is, the switching) of the thyristors. This is necessary because the thyristors do not have a

Control signal, but only by means of a negative anode-cathode voltage can be erased.

The commutation voltage source has a relatively low DC voltage (eg about 20V).

The thyristors of the same inverter phase of all cells are connected to each other directly or via other thyristors and thus provide the phase connection of the inverter for each phase.

For each inverter phase, the thyristor of a single cell is conductive in each case. Thus, the cell active for this inverter phase is selected. Depending on the state of the semiconductor switch of the active cell, either the negative or the positive potential of the intermediate circuit capacitor of the active cell is switched to the phase connection via the conductive thyristor.

FIG. 3 shows a corresponding arrangement with 2 cells for one phase.

This circuit corresponds to a 3-point circuit, since the phase connection can optionally be switched to the DC link potentials CZK1 +, CZK1-, CZK2 + or CZK2-, the potentials CZK1- and CZK2 + only a small difference (corresponding to the

Commutation auxiliary voltage).

For the operation of the circuit according to the invention, it is important that the thyristors can be switched from one active cell to an adjacent cell (commutated). In the following, therefore, these switching operations of the thyristors for selecting the active cell will be described in detail. These switching operations are different

Phase connections each independently.

4 possible switching operations are to be considered, the descriptions refer to the exemplary representation in FIG. 3:

Commutation of cell 1 to cell 2 with positive phase current:

Thyristor T1 P conducts, blocking all other thyristors.

The semiconductor switch S1 P is clocked.

S1 P turns off, the phase current then flows through the freewheeling diode D1 P.

The semiconductor switch S2P and the thyristor T2P are turned on.

Thyristor T1 P is commutated by the circuit S2P - T2P - T1 P - D1 P - UK1 and turns off.

Now, thyristor T2P conducts, blocking all other thyristors. Semiconductor switch S2P clocks.

Commutation of cell 1 to cell 2 with negative phase current:

Thyristor T1 N conducts, all other thyristors block.

The semiconductor switch S1 N clocks.

S1 N turns off, the phase current then flows through the freewheeling diode D1 N.

The thyristor T2N is turned on.

Thyristor T1 N is commutated by the circuit D1 N-T1 N-T2N-D2N-UK1-CZK1 and turns off.

Now, thyristor T2N conducts, blocking all other thyristors. Semiconductor switch S2N clocks.

Commutation of cell 2 to cell 1 with positive phase current:

Thyristor T2P conducts, all other thyristors block.

The semiconductor switch S2P is clocking.

S2P switches off, the phase current then flows through the freewheeling diode D2P.

The thyristor T1 P is turned on.

Thyristor T2P is commutated by the circuit D1 P - T1 P - T2P - D2P - CZK2 - UK1 and switches off.

Now, thyristor T1 is conducting P, all other thyristors are blocking. Semiconductor switch S1 P clocks. Commutation of cell 2 to cell 1 with negative phase current:

Thyristor T2N conducts, all other thyristors block.

The semiconductor switch S2N is clocking.

S2N switches off, the phase current then flows through the freewheeling diode D2N.

The semiconductor switch S1 N and the thyristor T1 N are turned on.

Thyristor T2N is connected through the circuit D2N-T2N-T1N-S1N-UK1

abkommutiert and switches off.

The commutation processes described so far have for the thyristors. 2

different commutation voltages. Depending on the commutation process, the commutation voltage is UK1 or (CZK1 - UK1) or (CZK2 - UK1).

Since the commutation voltage affects the switching behavior of the thyristors, it may be undesirable to use the voltage (CZK1 - UK1) (or CZK2 - UK1) as

Commutation voltage to use, because this is considerably higher than the actual commutation voltage UK1.

With two additional commutation auxiliary circuits can be achieved that for all commutation the same commutation voltage is effective.

The circuit with 2 cells and the two additional commutation auxiliary circuits is shown in FIG.

The two commutation auxiliary circuits are fed by the voltage sources UK11 and UK12, which usefully have approximately the same voltage as UK1.

The switches SK1 1 or SK12 are turn-off power semiconductors.

SK1 1 and SH2 are normally locked, they are only during the corresponding

Commutation briefly turned on.

The diodes DK1 1, DK12, DK13 and DK14 serve to limit the voltage stress of the semiconductor switches SK11 and SK12 to voltages corresponding to the voltage sources UK11 and UK12, respectively.

In the following, the switching operations of the thyristors are taking into account the

Commutation auxiliary circuits described. 4 possible switching operations are to be considered, the descriptions refer to the exemplary representation in FIG. 4:

Commutation of cell 1 to cell 2 with positive phase current:

SK11 and SK12 block during the entire commutation process, ie the commutation auxiliary circuits are not active. The commutation takes place as described above:

Thyristor T1 P conducts, blocking all other thyristors.

The semiconductor switch S1 P is clocked.

The semiconductor switch S2P and the thyristor T2P are turned on.

Commutation of cell 1 to cell 2 with negative phase current:

Thyristor T1 N conducts, all other thyristors block.

The semiconductor switch S1 N clocks.

Then S1 N remains on, causing the phase current to flow through S1 N.

Thyristor T2N and the commutation semiconductor switch SK12 are turned on.

Thyristor T1 N is connected through the circuit S1 N - T1 N - T2N - DK13 - SK12 - UK12 -

UK1 abkommutiert and switches off.

Now, thyristor T2N conducts, blocking all other thyristors.

Commutation semiconductor switch SK12 is turned off and semiconductor switch S2N is clocked.

Commutation of cell 2 to cell 1 with positive phase current:

Thyristor T2P conducts, all other thyristors block.

The semiconductor switch S2P is clocking.

Then S2P remains on, causing the phase current to flow through S2P.

Thyristor T1 P and the commutation semiconductor switch SK11 are turned on. Thyristor T2P is commutated by the circuit SK1 1 - DK1 1 - T1 P - T2P - S2P - UK11 and switches off.

Now, thyristor T1 is conducting P, all other thyristors are blocking. Commutation semiconductor switch SK1 1 is turned off and semiconductor switch S1 P is clocked.

Commutation of cell 2 to cell 1 with negative phase current:

SK11 and SK12 lock during the entire commutation process, i. the commutation auxiliary circuits are not active. The commutation takes place as described above:

Thyristor T2N conducts, all other thyristors block.

The semiconductor switch S2N is clocking.

The semiconductor switch S1 N and the thyristor T1 N are turned on.

Thyristor T2N is connected through the circuit D2N-T2N-T1N-S1N-UK1

abkommutiert and switches off.

Figures 2, 3 and 4 show the new circuit concept in an embodiment with 2 cells. This corresponds to the so-called three-point circuits. By analogy, circuits with any number of cells and phases can be executed in this way.

The interconnection of the phase connections of the individual cells can by

different thyristor networks can be realized. The choice of the suitable network depends above all on the voltage design. Basically, a star-shaped network or a chain-like network makes sense.

Figure 5 shows an example of a circuit with 4 cells, 3 phases and a star-shaped thyristor network. For the sake of clarity, the commutation auxiliary circuits according to FIG. 4 are not shown.

Figure 6 shows an example of a circuit with 4 cells, 3 phases and a chain-shaped thyristor network. For the sake of clarity, the commutation auxiliary circuits according to FIG. 4 are not shown.

In this arrangement, the thyristors are claimed only by the voltage corresponding to a single cell. Depending on the angle of the phase current with respect to the phase voltage (cos phi), not all semiconductors in all cells need to be populated.

FIG. 7 shows by way of example a circuit with 2 cells and 1 phase, for a phase current with an angle of 0 degrees to the phase voltage (cos phi = 1).

For the sake of clarity, the commutation auxiliary circuits according to FIG. 4 are not shown.

FIG. 8 exemplarily shows a circuit with 2 levels and 1 phase, for a phase current with an angle of 0 degrees to the phase voltage (cos phi = -1).

name list

CZK DC link capacitor of a cell

CZK1, CZK2, CZK3, CZK4 DC link capacitor of cell 1, cell 2, etc. DK11, DK12, DK13, DK14 Diodes of commutation auxiliary circuits

DN freewheeling diode for negative phase current

D1 N, D2N, D3N, D4N Freewheeling diode for negative phase current of cell 1, cell

2, etc.

D1 RN, D1SN, D1TN Freewheeling diode of cell 1 for negative phase current for

Phase R, Phase S, etc.

D2RN, D2SN, D2TN Cell 2 freewheeling diode for negative phase current for

Phase R, Phase S, etc.

DP freewheeling diode for positive phase current

D1 P, D2P, D3P, D4P freewheeling diode for positive phase current of cell 1, cell

2, etc.

D1 RP, D1 SP, D1TP Freewheeling diode of cell 1 for positive phase current for

Phase R, Phase S, etc.

D2RP, D2SP, D2TP Cell 2 freewheeling diode for positive phase current for

Phase R, Phase S, etc.

SK1 1, SK12 Semiconductor switch for the commutation auxiliary circuit

SN semiconductor switch for negative phase current S1 N, S2N, S3N, S4N negative phase current semiconductor switch of cell 1,

Cell 2, etc

S1 RN, S1SN, S1TN Semiconductor switch of cell 1 for negative phase current for phase R, phase S, etc.

S2RN, S2SN, S2TN cell 2 negative phase current switch for phase R, phase S, etc.

SP semiconductor switch for positive phase current

S1 P, S2P, S3P, S4P positive phase current semiconductor switch of cell 1,

Cell 2, etc.

S1 RP, S1SP, S1TP semiconductor cell of positive phase current cell 1 for phase R, phase S, etc.

S2RP, S2SP, S2TP cell 2 positive phase current switch for phase R, phase S, etc.

TN thyristor for negative phase current

T1 N, T2N, T3N, T4N thyristor for negative phase current of cell 1, cell 2, etc.

T1 1 N, T21 N, T31 N, T41 N Thyristor for negative phase current in a chain

Thyristor network

T1 RN, T1 SN, T1TN cell 1 thyristor for negative phase current for phase

R, phase S, etc.

T2RN, T2SN, T2TN cell phase 2 thyristor for phase negative phase current

R, phase S, etc.

TP thyristor for positive phase current

T1 P, T2P, T3P, T4P positive phase current thyristor of cell 1, cell 2, etc.

T1 1 P, T21 P, T31 P, T41 P Thyristor for positive phase current in a chain

Thyristor network

T1 RP, T1 SP, T1TP Cell 1 thyristor for phase positive phase current

R, phase S, etc.

T2RP, T2SP, T2TP Thyristor of cell 2 for positive phase current for phase

R, phase S, etc.

UK commutation voltage source

UK1, UK2, UK3 cell 1 commutation voltage source, cell 2, etc.

UK1 1, UK12 commutation auxiliary power sources

Claims

PATENT APPLICATIONS

1. Multilevel converter comprising a) at least 2 cells, consisting of the intermediate circuit capacitor (CZK1, CZK2); such as

b) at least one phase which, for each current direction in each cell, comprises a semiconductor switch (S1 P, S2P, S1N, S2N), a freewheeling diode (D1P, D2P, D1N, D2N) and a thyristor (T1P, T2P, T1 N, T2N);

characterized in that

c) the positive terminals of the semiconductor switches for the positive current direction (S1 P or S2P) with the positive terminals of

DC link capacitors (CZK1 or CZK2) and their negative terminals are connected to the anodes of the thyristors for the positive current direction (T1 P or T2P) of the respective cell;

d) the anodes of the freewheeling diodes for the positive current direction (D1 P or D2P) with the negative terminals of the DC link capacitors (CZK1 or CZK2) and their cathodes with the anodes of the thyristors for the positive current direction (T1 P or T2P) of the respective Cell are connected; e) the negative terminals of the semiconductor switches for the negative current direction (S1 N or S2N) with the negative terminals of

DC link capacitors (CZK1 or CZK2) and their positive terminals are connected to the cathodes of the thyristors for the negative current direction (T1 N or T2N) of the respective cell;

f) the cathodes of the freewheeling diodes for the negative current direction (D1 N or D2N) with the positive terminals of the DC link capacitors (CZK1 or CZK2) and their anodes with the cathodes of the thyristors for the negative current direction (T1 N or T2N) of the respective Cell are connected;

g) the DC link capacitors (CZK1, CZK2) are connected in series by means of a commutation voltage source (UK), the commutation voltage source (UK) having the opposite polarity of the

Having DC link capacitors (CZK1, CZK2);

h) the anodes of the thyristors for the positive current direction (T1 P, T2P) of one phase of all cells are connected to each other directly or via further thyristors with each other and with the phase connection of the inverter; i) the cathodes of the thyristors for the negative current direction (T1 N, T2N) of one phase of all cells are connected to each other directly or via further thyristors with each other and with the phase connection of the inverter;

2. Multilevel inverter according to claim 1, characterized in that the

Commutation of the thyristors is improved by additional commutation auxiliary circuits consisting of

a) an auxiliary voltage source (UK1 1) whose negative pole is connected to the positive pole of the commutation voltage source (UK);

b) an auxiliary voltage source (UK12) whose positive pole is connected to the negative pole of the commutation voltage source (UK);

c) a semiconductor switch (SK1 1) whose positive pole is connected to the positive pole of the auxiliary voltage source (UK1 1);

d) a semiconductor switch (SK12) whose negative pole is connected to the negative pole of the auxiliary voltage source (UK1 1);

e) a diode (DK11) whose anode is connected to the negative terminal of the

Semiconductor switch (SK1 1) and its cathode at the negative pole of

Semiconductor switch (S1 P) is connected;

f) a diode (DK12) whose anode is connected to the negative terminal of

Auxiliary voltage source (UK1 1) and its cathode at the negative pole of

Semiconductor switch (SK1 1) is connected;

g) a diode (DK13) whose anode is connected to the positive terminal of the

Semiconductor switch (S2N) and whose cathode is connected to the positive pole of the semiconductor switch (SK12); such as

h) a diode (DK14) whose anode is connected to the positive terminal of the

Semiconductor switch (SK12) and its cathode positive connection of

Auxiliary voltage source (UK12) is connected.

3. Multilevel converter according to claim 1, characterized in that the thyristor network is arranged in a star shape, i. the phase terminals of the respective phase of all cells are connected together, thus forming the inverter phase connection of this phase.

4. Multilevel inverter according to claim 1, characterized in that the thyristor network is arranged in a chain, ie between the phase terminals of In addition, additional thyristors may be connected in each phase of potential-adjacent cells and between the middle cells and the converter phase connection in order to reduce the voltage load of the individual thyristors.

5. Multilevel inverter according to claim 1, characterized in that within the cell, the semiconductor switches for both current directions are interconnected, i. the negative terminal of the semiconductor switch for the positive current (SP), the positive terminal of the semiconductor switch for the negative current (SN), the cathode of the freewheeling diode for the positive current (DP) and the anode of the freewheeling diode for the negative current (DN) connected with each other.