CH703022A2 - Circuit for a multilevel inverter with thyristor switch. - Google Patents

Abstract

This circuit for a multilevel inverter consists of individual cells, which consist of a DC link capacitor, and for each phase of 2 semiconductor switches (S1N, S1P, S2N, S2P), 2 freewheeling diodes (D1N, D1P, D2N, D2P) and 2 thyristors (T1P , T1N, T2P, T2N). The intermediate circuits of the cells are connected in series, the thyristors belonging to one phase of all cells are interconnected and form the phase output of the converter. For each phase, a thyristor is activated, which selects the cell active for this phase. To enable the switching of the thyristors, an additional voltage source is needed.

Description

Technical area

The invention relates to the field of power electronics. Fields of application are, for example, converters in drive technology or in the power supply. To increase the voltage and reduce the harmonics of the inverters, multi-level inverters (multilevel inverters) can be used.

State of the art

The circuit topologies commonly used in converters can be roughly divided into 3 categories, namely in voltage source inverter, power source inverter and cycloconverter.

The voltage source inverter can be divided into the number of states in which each inverter phase can be switched. For a two-position inverter, each inverter phase can be switched to 2 different states (+ and -). In the case of a multilevel inverter, each inverter phase can be switched to more than 2 different states, for example three different states (+, 0 and -) for the three-level inverter in 3.

Typical representatives of the multilevel inverters are the neutral-point-clamped inverter (NPC), the flying capacitor inverter, the cascaded H-bridge converter (CHB) and the modular multilevel inverter (M2C).

In these multilevel circuit topologies, the current of each inverter phase flows through a plurality of semiconductor switches (i.e., turn-off power semiconductors such as IGBT, IGCT, GTO, or MOSFET) or freewheeling diodes (i.e., fast-switching diodes).

In this case, the current flows through all the more semiconductor switches or freewheeling diodes, the more level has a circuit.

An overview of the known multilevel inverters can be found, for example, in the publication "Diode-clamped Multilevel Voltage Source Converter for Medium Voltage Dynamic Voltage Restorer" by P. Boonchiam and N. Mithulananthan.

Presentation of the invention

The circuit according to this invention consists of at least 2 series-connected cells. Each cell may have one or more inverter phases connected in parallel to the same DC link capacitor.

Each cell consists of an intermediate circuit capacitor or a DC voltage source and per current direction and phase of a turn-off semiconductor, a freewheeling diode (fast diode) and a thyristor.

The cell active for each phase is switched by the thyristor network to the phase connection of the inverter.

The corresponding thyristors are switched only with the fundamental frequency of the phase current.

Since the thyristors can not be switched off actively, an additional voltage source, the commutation voltage source is used to switch the thyristors.

For a 3-point circuit 2 such cells are connected in series, for a 5-point circuit 4 such cells are connected in series.

In the circuit according to this invention, the current of each converter phase flows only through a semiconductor switch (turn-off power semiconductor) or a freewheeling diode (fast diode) and through a thyristor.

The forward losses of the thyristors are significantly lower than those of the semiconductor switches or freewheeling diodes. For this reason, the circuit topology according to this invention has significantly lower forward losses than the previously known circuit topologies.

Since the switching losses remain unchanged compared to the previous circuit topologies, the circuit according to this invention has overall lower semiconductor losses.

This improves the efficiency of the inverter and the cost of the semiconductor and its cooling are reduced.

Another advantage of the circuit according to this invention is that in the switching operations of the semiconductor switches in each case only a semiconductor switch and a freewheeling diode are involved within the same cell.

Therefore, only the phases must be constructed within a cell low inductance, and not the complete circuit as in the neutral-point-clamped inverter (NPC) or the flying capacitor inverter. This reduces the requirements for the mechanical structure of the circuit.

Brief description of the drawings

In the following the invention will be explained in more detail with reference to embodiments in conjunction with the drawings.

In all the figures, the semiconductor switches are represented as IGBTs representative of any type of semiconductor switchable element (IGBT, IGCT, GTO or MOSFET).

Show: <Tb> FIG. 1 <sep> The circuit diagram of a cell for an inverter phase with two current directions for the circuit according to the invention; <Tb> FIG. 2 <sep> The circuit diagram of a cell for an inverter phase with both current directions, wherein the terminals of the semiconductor switches are connected to each other for both current directions; <Tb> FIG. 3 <sep> The circuit diagram of an inventive three-point circuit for a converter phase with two current directions; <Tb> FIG. 4 <sep> The circuit diagram of a three-point circuit according to the invention for a converter phase with both current directions with additional auxiliary commutation circuits; <Tb> FIG. 5 <sep> The circuit diagram of a five-point circuit according to the invention for a converter phase with both current directions, with a star-shaped thyristor network; <Tb> FIG. 6 <sep> The circuit diagram of a five-point circuit according to the invention for an inverter phase with two current directions, with a chain-type thyristor network; <Tb> FIG. 7 <sep> The circuit diagram of a three-point circuit according to the invention for a converter phase with a load current angle of 0 degrees; <Tb> FIG. 8 <sep> The circuit diagram of a three-point circuit according to the invention for a converter phase with a load current angle of 180 degrees;

Embodiment of the invention

The circuit topology according to this invention consists of several cells. Each cell may have one or more inverter phases connected in parallel to the same DC link capacitor.

A cell consists of a DC link capacitor (CZK), the voltage can be considered as substantially constant, and per converter phase and each of their current directions of a turn-off semiconductor (SP or SN), a freewheeling diode (DP or DN) and a Thyristor (TP or TN).

The current direction which leads out of a cell is called positive.

A cell designed for one phase and both current directions is shown in drawing 1.

The cell according to FIG. 1 behaves as follows:

For a positive phase current TP passes. TN is locked.

SP clocks, i. is switched on and off, thus switching the phase connection AC to CZK + or CZK-. While SP is off, the phase current flows through DP.

With a negative phase current, TN conducts. TP is locked.

SN clocks, i. is switched on and off, thus switching the phase connection AC to CZK + or CZK-. While SN is off, the current flows through DN.

Fig. 2 shows a cell with the same characteristics as the cell according to Fig. 1, wherein the terminals of the semiconductor switches for the two current directions are interconnected.

In order to obtain a multilevel circuit, several such cells are now interconnected.

The DC link capacitors are connected in series, but not directly, but via the commutation voltage source (UK), which is polarized opposite to the DC link capacitors. As a result, the DC link capacitors are offset by the voltage UK, thereby enabling the commutation (that is, the switching) of the thyristors. This is necessary because the thyristors can not be erased by a control signal, but only by using a negative anode-cathode voltage.

The commutation voltage source has a relatively low DC voltage (for example about 20 V).

The thyristors of the respective same inverter phase of all cells are connected to each other directly or via other thyristors and thus provide the phase connection of the inverter for each phase.

For each inverter phase, the thyristor of a single cell is in each case conductive. Thus, the cell active for this inverter phase is selected. Depending on the state of the semiconductor switch of the active cell, either the negative or the positive potential of the DC link capacitor of the active cell is switched to the phase connection via the conductive thyristor.

Fig. 3 shows a corresponding arrangement with 2 cells for one phase. This circuit corresponds to a 3-point circuit, since the phase connection can optionally be switched to the DC link potentials CZK1 +, CZK1-, CZK2 + or CZK2-, the potentials CZK1- and CZK2 + having only a small difference (corresponding to the commutation auxiliary voltage).

For the operation of the inventive circuit, it is important that the thyristors can be switched from one active cell to an adjacent cell (commutated) can be.

In the following, therefore, these switching operations of the thyristors for selecting the active cell are described in detail. These switching operations are independent of each other for different phase connections.

4 possible switching operations are to be considered, the descriptions refer to the exemplary representation in Fig. 3:

Commutation of cell 1 to cell 2 with positive phase current: thyristor T1P conducts, blocking all other thyristors. The semiconductor switch S1P clocks.

S1P turns off, the phase current then flows through the freewheeling diode D1P.

The semiconductor switch S2P and the thyristor T2P are turned on.

Thyristor T1P is commutated by the circuit S2P - T2P - T1P - D1P - UK1 and turns off.

Now directs thyristor T2P, lock all other thyristors. Semiconductor switch S2P clocks.

Commutation of cell 1 to cell 2 with negative phase current: thyristor T1N conducts, blocking all other thyristors. The semiconductor switch S1N is clocked.

S1N turns off, the phase current then flows through the freewheeling diode D1N. The thyristor T2N is turned on.

Thyristor T1N is commutated by the circuit D1N -T1N -T2N - D2N - UK1 - CZK1 and turns off.

Now directs thyristor T2N, lock all other thyristors. Semiconductor switch S2N clocks.

Commutation of cell 2 to cell 1 with positive phase current: thyristor T2P conducts, blocking all other thyristors. The semiconductor switch S2P is clocking.

S2P switches off, the phase current then flows through the freewheeling diode D2P. The thyristor T1P is switched on.

Thyristor T2P is commutated by the circuit D1P - T1P - T2P - D2P - CZK2 - UK1 and turns off.

Now directs thyristor T1P, lock all other thyristors. Semiconductor switch S1P clocks.

Commutation of cell 2 to cell 1 with negative phase current: thyristor T2N conducts, blocking all other thyristors. The semiconductor switch S2N is clocking.

S2N switches off, the phase current then flows through the freewheeling diode D2N. The semiconductor switch S1N and the thyristor T1N are turned on. Thyristor T2N is commutated by the circuit D2N-T2N-T1N-S1N-UK1 and turns off.

Now directs thyristor T2N, lock all other thyristors. Semiconductor switch S2N clocks.

The commutation processes described so far have different commutation voltages for the thyristors 2. Depending on the commutation process, the commutation voltage is UK1 or (CZK1 - UK1) or (CZK2 - UK1). Since the commutation voltage affects the switching behavior of the thyristors, it may be undesirable to use the voltage (CZK1 - UK1) (or CZK2 - UK1) as the commutation voltage, because this is considerably higher than the actual commutation voltage UK1.

With two additional commutation auxiliary circuits can be achieved that for all Kommutierungsvorgänge the same commutation voltage is effective. The circuit with 2 cells and the two additional commutation auxiliary circuits is shown in FIG.

The two commutation auxiliary circuits are fed by the voltage sources UK11 and UK12, which usefully have approximately the same voltage as UK1.

The switches SK11 and SK12 are turn-off power semiconductors.

SK11 and SH2 are normally disabled, they are only briefly turned on during the corresponding commutation.

The diodes DK11, DK12, DK13 and DK14 serve to limit the voltage stress of the semiconductor switches SK11 and SK12 to voltages corresponding to the voltage sources UK11 and UK12, respectively.

In the following, the switching operations of the thyristors are described in consideration of the commutation auxiliary circuits.

4 possible switching operations are to be considered, the descriptions refer to the exemplary representation in FIG. 4:

Commutation of cell 1 to cell 2 with positive phase current: SK11 and SK12 lock during the entire commutation process, that is, the commutation auxiliary circuits are not active. The commutation takes place as described above: Thyristor T1P conducts, all other thyristors block. The semiconductor switch S1P clocks.

S1P turns off, the phase current then flows through the freewheeling diode D1P.

The semiconductor switch S2P and the thyristor T2P are turned on.

Thyristor T1P is commutated by the circuit S2P - T2P - T1P - D1P - UK1 and turns off.

Now directs thyristor T2P, lock all other thyristors. Semiconductor switch S2P clocks.

Commutation of cell 1 to cell 2 with negative phase current: thyristor T1N conducts, blocking all other thyristors. The semiconductor switch S1N is clocked.

Then, S1N remains turned on, whereby the phase current flows through S1N.

Thyristor T2N and the commutation semiconductor switch SK12 are turned on.

The thyristor T1N is connected through the circuit S1N - T1N - T2N - DK13 - SK12 - UK12 -

UK1 abkommutiert and switches off.

Now directs thyristor T2N, lock all other thyristors.

Commutation semiconductor switch SK12 is turned off and semiconductor switch S2N is clocked.

Commutation of cell 2 to cell 1 with positive phase current: thyristor T2P conducts, blocking all other thyristors. The semiconductor switch S2P is clocking.

Then, S2P remains turned on, whereby the phase current flows through S2P. Thyristor T1P and the commutation semiconductor switch SK11 are turned on. Thyristor T2P is commutated by the circuit SK11 - DK11 - T1P - T2P - S2P - UK11 and switches off.

Now directs thyristor T1P, lock all other thyristors.

Commutation semiconductor switch SK11 is turned off and semiconductor switch S1P is clocked.

Commutation of cell 2 to cell 1 with negative phase current: SK11 and SK12 lock during the entire commutation process, i. the commutation auxiliary circuits are not active. The commutation takes place as described above: Thyristor T2N conducts, all other thyristors block. The semiconductor switch S2N is clocking.

S2N turns off, the phase current then flows through the freewheeling diode D2N. The semiconductor switch S1N and the thyristor T1N are turned on. Thyristor T2N is commutated by the circuit D2N-T2N-T1N-S1N-UK1 and turns off.

Now, thyristor T2N conducts, blocking all other thyristors. Semiconductor switch S2N clocks.

Figures 2, 3 and 4 show the new circuit concept in a 2 cell design. This corresponds to the so-called three-point circuits. By analogy, circuits with any number of cells and phases can be executed in this way.

The interconnection of the phase connections of the individual cells can be realized by different thyristor networks. The choice of the suitable network depends above all on the voltage design. Basically, a star-shaped network or a chain-like network makes sense.

By way of example, FIG. 5 shows a circuit with 4 cells, 3 phases and a star-shaped thyristor network. For better clarity, the commutation auxiliary circuits according to FIG. 4 are not shown.

Fig. 6 shows by way of example a circuit with 4 cells, 3 phases and a chain-shaped thyristor network. For better clarity, the commutation auxiliary circuits according to FIG. 4 are not shown.

In this arrangement, the thyristors are claimed only by the voltage corresponding to a single cell.

Depending on the angle of the phase current with respect to the phase voltage (cos phi), not all semiconductors in all cells need to be populated.

Fig. 7 shows an example of a circuit with 2 cells and 1 phase, for a phase current at an angle of 0 degrees to the phase voltage (cos phi = 1).

For better clarity, the commutation auxiliary circuits according to FIG. 4 are not drawn.

Fig. 8 shows by way of example a circuit with 2 levels and 1 phase, for a phase current with an angle of 0 degrees to the phase voltage (cos phi = -1). For better clarity, the commutation auxiliary circuits according to FIG. 4 are not drawn.

name list

[0094] <tb> CZK <sep> DC link capacitor of a cell <tb> CZK1, CZK2, CZK3, CZK4 <sep> DC link capacitor of cell 1, cell 2, etc. <tb> DK11, DK12, DK13, DK14 <sep> Diodes of the commutation auxiliary circuits <tb> DN <sep> Free-wheeling diode for negative phase current <tb> D1N, D2N, D3N, D4N <sep> Freewheeling diode for negative phase current of cell 1, cell 2, etc. <tb> D1RN, D1SN, D1TN <sep> Free-wheeling diode of cell 1 for negative phase current for phase R, phase S, etc. <tb> D2RN, D2SN, D2TN <sep> Free-wheeling diode of cell 2 for negative phase current for phase R, phase S, etc. <tb> DP <sep> Free-wheeling diode for positive phase current <tb> D1P, D2P, D3P, D4P <sep> Free-wheeling diode for positive phase current of cell 1, cell 2, etc. <tb> D1RP, D1SP, D1TP <sep> Free-wheeling diode of cell 1 for positive phase current for phase R, phase S, etc. <tb> D2RP, D2SP, D2TP <sep> Cell 2 freewheeling diode for positive phase current for phase R, phase S, etc. <tb> SK11, SK12 <sep> Semiconductor switch for the commutation auxiliary circuit <tb> SN <sep> semiconductor switch for negative phase current <S1>, S2N, S3N, S4N <sep> semiconductor negative phase current switch of cell 1, cell 2, etc <tb> S1RN, S1SN, S1TN <sep> Semiconductor switch of cell 1 for negative phase current for phase R, phase S, etc. <tb> S2RN, S2SN, S2TN <sep> Cell Phase 2 semiconductor switch for phase negative phase current, phase S, etc. <tb> SP <sep> semiconductor switch for positive phase current <tb> S1P, S2P, S3P, S4P <sep> Positive phase current semiconductor switch of cell 1, cell 2, etc. <tb> S1RP, S1SP, S1TP <sep> Solid state cell semiconductor switch 1 for phase R, phase S, etc. <S2> S2RP, S2SP, S2TP <sep> Positive phase current semiconductor cell switch for phase R, phase S, etc. <tb> TN <sep> thyristor for negative phase current <tb> T1N, T2N.T3N, T4N <sep> thyristor for negative phase current of cell 1, cell 2, etc. <tb> T11N, T21N, T31N, T41N <sep> Thyristor for negative phase current in a thyristor network <tb> T1RN, T1SN, T1TN <sep> thyristor of cell 1 for negative phase current for phase R, phase S, etc. <tb> T2RN, T2SN, T2TN <sep> Thyristor of cell 2 for negative phase current for phase R, phase S, etc. <tb> TP <sep> thyristor for positive phase current T1, T2P, T3P, T4P <sep> thyristor for positive phase current of cell 1, cell 2, etc. <tb> T11P, T21P, T31P, T41P <sep> Thyristor for positive phase current in a thyristor network <tb> T1RP, T1SP, T1TP <sep> Thyristor of cell 1 for positive phase current for phase R, phase S, etc. <T2> T2RP, T2SP, T2TP <thp> Thyristor of cell 2 for positive phase current for phase R, phase S, etc. <Tb> UK <sep> commutation voltage source <tb> UK1, UK2, UK3 <sep> cell 1 commutation voltage source, cell 2, etc. <tb> UK11, UK12 <sep> commutation auxiliary power sources

Claims (5)

1. Multilevel inverter comprising a) at least 2 cells, consisting of the DC link capacitor (CZK1, CZK2); such as b) at least one phase having a semiconductor switch (S1P, S2P, S1N, S2N), a freewheeling diode (D1P, D2P, D1N, D2N) and a thyristor (T1P, T2P, T1N, T2N) for each current direction in each cell ; characterized in that c) the positive terminals of the semiconductor switches for the positive current direction (S1P or S2P) with the positive terminals of the DC link capacitors (CZK1 or CZK2) and their negative terminals to the anodes of the thyristors for the positive current direction (T1P or T2P) of the respective Cell are connected; d) the anodes of the freewheeling diodes for the positive current direction (D1P or D2P) with the negative terminals of the DC link capacitors (CZK1 and CZK2) and their cathodes connected to the anodes of the thyristors for the positive current direction (T1P or T2P) of each cell are; e) the negative terminals of the semiconductor switches for the negative current direction (S1N or S2N) with the negative terminals of the DC link capacitors (CZK1 and CZK2) and their positive terminals to the cathodes of the thyristors for the negative current direction (T1N or T2N) of the respective Cell are connected; f) the cathodes of the freewheeling diodes for the negative current direction (D1N or D2N) to the positive terminals of the DC link capacitors (CZK1 and CZK2) and their anodes connected to the cathodes of the thyristors for the negative current direction (T1N or T2N) of each cell are; g) the DC link capacitors (CZK1, CZK2) are connected in series by means of a commutation voltage source (UK), the commutation voltage source (UK) having the opposite polarity of the DC link capacitors (CZK1, CZK2); h) the anodes of the thyristors for the positive current direction (T1P, T2P) of one phase of all cells are connected to each other directly or via further thyristors with each other and with the phase connection of the inverter; i) the cathodes of the thyristors for the negative current direction (T1N, T2N) of one phase of all cells are connected to each other directly or via further thyristors with each other and with the phase connection of the inverter; 2. Multilevel inverter according to claim 1, characterized in that the commutation of the thyristors is improved by additional commutation auxiliary circuits consisting of a) an auxiliary voltage source (UK11) whose negative pole is connected to the positive pole of the commutation voltage source (UK); b) an auxiliary voltage source (UK12) whose positive pole is connected to the negative pole of the commutation voltage source (UK); c) a semiconductor switch (SK11) whose positive pole is connected to the positive pole of the auxiliary voltage source (UK11); d) a semiconductor switch (SK12) whose negative pole is connected to the negative pole of the auxiliary voltage source (UK11); e) a diode (DK11) whose anode is connected to the negative terminal of the semiconductor switch (SK11) and whose cathode is connected to the negative pole of the semiconductor switch (S1P); f) a diode (DK12) whose anode is connected to the negative terminal of the auxiliary voltage source (UK11) and whose cathode is connected to the negative pole of the semiconductor switch (SK11); g) a diode (DK13) whose anode is connected to the positive terminal of the semiconductor switch (S2N) and whose cathode is connected to the positive pole of the semiconductor switch (SK12); such as h) a diode (DKM) whose anode is connected to the positive terminal of the semiconductor switch (SK12) and whose cathode positive terminal of the auxiliary voltage source (UK12). 3. Multilevel inverter according to claim 1, characterized in that the thyristor network is arranged in a star shape, i. the phase terminals of the respective phase of all cells are connected together, thus forming the inverter phase connection of this phase. 4. Multilevel converter according to claim 1, characterized in that the thyristor network is arranged in a chain, i. additional thyristors may be connected between the phase terminals of the respective phase of potential-adjacent cells and between the middle cells and the converter phase connection in order to reduce the voltage loading of the individual thyristors. 5. Multilevel inverter according to claim 1, characterized in that within the cell, the semiconductor switches for both current directions are interconnected, i. the negative terminal of the semiconductor switch for the positive current (SP), the positive terminal of the semiconductor switch for the negative current (SN), the cathode of the freewheeling diode for the positive current (DP) and the anode of the freewheeling diode for the negative current (DN) connected with each other.