WO2011118116A1 - Semiconductor device and method for producing same - Google Patents

Semiconductor device and method for producing same Download PDF

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Publication number
WO2011118116A1
WO2011118116A1 PCT/JP2011/000625 JP2011000625W WO2011118116A1 WO 2011118116 A1 WO2011118116 A1 WO 2011118116A1 JP 2011000625 W JP2011000625 W JP 2011000625W WO 2011118116 A1 WO2011118116 A1 WO 2011118116A1
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WO
WIPO (PCT)
Prior art keywords
adhesive layer
semiconductor element
adhesive
electrode
semiconductor
Prior art date
Application number
PCT/JP2011/000625
Other languages
French (fr)
Japanese (ja)
Inventor
井上大輔
藤井恭子
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パナソニック株式会社
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Publication of WO2011118116A1 publication Critical patent/WO2011118116A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures

Definitions

  • the present invention relates to a semiconductor device that detects light and a manufacturing method thereof.
  • the mainstream of semiconductor devices is the conventional chip structure, bare chip structure or CSP (chip size package). It has become to.
  • the wafer level CSP technology is attracting attention, and this technology is also employed in optical devices including solid-state imaging devices (for example, Patent Document 1).
  • the wafer level CSP technology is a technology for electrically connecting the light emitting / receiving region and the external electrode by forming a through electrode and a rewiring in an assembly process in a wafer state.
  • FIG. 14 is a cross-sectional view of a solid-state imaging device having a conventional wafer level CSP structure.
  • a conventional solid-state imaging device 900A includes a solid-state imaging device 900.
  • the solid-state imaging device 900 is formed on the periphery of the semiconductor element 901, the imaging region 902 formed on the main surface of the semiconductor element 901, the microlens 903 provided on the imaging region 902, and the imaging region 902.
  • a peripheral circuit region 904A and an electrode wiring 904B electrically connected to the peripheral circuit region 904A are included.
  • a light transmitting plate 906 (for example, made of optical glass) is provided on the main surface of the semiconductor element 901 with an adhesive layer 905 interposed therebetween.
  • a through electrode 907 that penetrates the semiconductor element 901 in the thickness direction is provided inside the semiconductor element 901.
  • a metal wiring 908 is formed on the back surface of the semiconductor element 901, and the metal wiring 908 is electrically connected to the through electrode 907.
  • the back surface of the semiconductor element 901 and the metal wiring 908 are covered with an insulating layer 909, and an opening 909 a is formed in the insulating layer 909. A part of the metal wiring 908 is exposed from each opening 909a, and an external electrode 910 made of solder or the like is connected to the metal wiring 908 in each opening 909a.
  • the imaging region 902 and the external electrode 910 are electrically connected via the peripheral circuit region 904A, the electrode wiring 904B, the through electrode 907, and the metal wiring 908. .
  • the received light signal can be taken out to a flip chip substrate (not shown) or the like.
  • an adhesive layer is provided over the entire main surface of the semiconductor element as in the above-described solid-state imaging device
  • an adhesive mainly composed of an epoxy resin or a silicone resin is used as an adhesive constituting the adhesive layer.
  • a light beam having a high power density for example, 0.4 ⁇ W / ⁇ m 2
  • the adhesive layer may contract and discolor. This causes a decrease in the reliability of the solid-state imaging device.
  • a highly light-resistant rubber may be used as an adhesive.
  • rubber with high light resistance often has a low elastic modulus.
  • the throughput decreases (in this specification, the number of wafers that can be diced per unit time decreases), the chipping of the semiconductor element and the dicing blade Causes damage and other problems. As a result, the yield of the solid-state imaging device is reduced.
  • an adhesive mainly composed of an epoxy resin or a silicone resin is used as an adhesive constituting the adhesive layer. Due to the thermal history of the subsequent manufacturing process and the heat generation of the drive circuit after mounting, outgas is generated from the adhesive layer and fills the cavity.
  • a light beam having a high power density 0.4 ⁇ W / ⁇ m 2
  • a low outgas discharge rubber may be used as an adhesive.
  • the same problem occurs not only in the solid-state imaging element but also in the adhesion between the semiconductor element and the substrate on which the semiconductor element is mounted. That is, when an adhesive is supplied between a silicon substrate on which a semiconductor element is to be formed and a mounting substrate and the two substrates are heat-treated to bond them, the thermal expansion coefficients thereof are different. In this case, a difference in stress occurs between the substrates. When the thermal expansion coefficients of the respective substrates are greatly different, the stress of each substrate can be relieved by using an adhesive having a low elastic modulus. However, in this case, the same problem as that of the above-described solid-state imaging device occurs in the collective dicing process.
  • the amount of warpage of each semiconductor substrate is integrated, so an adhesive having a low elastic modulus is applied as a buffer material to bond the semiconductor substrates together. Also in this case, the same problem as the above problem occurs in the batch dicing process.
  • the present invention is to solve the above-mentioned conventional problems, and to provide a semiconductor device that is excellent in electrical characteristics and image characteristics, can be manufactured with high reliability and at low cost, and a manufacturing method thereof.
  • a first semiconductor device includes a semiconductor element, an optical element, a first adhesive layer, a second adhesive layer, and a translucent plate.
  • the optical element is provided on the main surface of the semiconductor element.
  • the first adhesive layer covers the optical element.
  • the second adhesive layer has a hardness higher than that of the first adhesive layer and covers at least a part of a portion other than the optical element on the main surface of the semiconductor element.
  • the translucent plate is bonded to the semiconductor element via the first adhesive layer and the second adhesive layer.
  • the second adhesive layer is cut instead of the first adhesive layer.
  • the second adhesive layer has a higher hardness than the first adhesive layer. Therefore, since the dicing process can be performed smoothly, problems such as a decrease in throughput in the dicing process, chipping of semiconductor elements, and damage to the dicing blade can be prevented.
  • the hardness of the second adhesive layer is 65 or more in Shore D hardness.
  • the translucent plate only needs to have a first surface and a second surface located on opposite sides, and the first surface and the second surface of the translucent plate.
  • An antireflection film is preferably provided on at least one of the surfaces. Thereby, reflection of the light in the 1st surface or 2nd surface of a translucent board can be prevented.
  • the second adhesive layer is preferably black. Thereby, the second adhesive layer can absorb the incident light.
  • the first semiconductor device it is preferable that a region where the first adhesive layer and the second adhesive layer are stacked exists between the semiconductor element and the light transmitting plate. Thereby, the light-transmitting plate can be firmly adhered to the semiconductor element also in this region.
  • the first adhesive layer and the second adhesive layer may be spaced apart from each other on the main surface of the semiconductor element, and the first adhesive layer on the main surface of the semiconductor element.
  • a spacer may be provided between the adhesive layer and the second adhesive layer.
  • the first semiconductor device according to the present invention includes a spacer
  • a region where the first adhesive layer and the spacer are stacked exists between the semiconductor element and the light transmitting plate.
  • the light-transmitting plate can be firmly adhered to the semiconductor element also in this region.
  • the first semiconductor device includes an electrode, a through hole, a through electrode, a filling layer, an insulating layer, an opening, and an external electrode.
  • the electrode is provided outside the optical element on the main surface of the semiconductor element, and the through hole penetrates in the thickness direction of the semiconductor element so as to reach the electrode, and the through electrode is in contact with the electrode , Extending from the inner surface of the through hole to the back surface of the semiconductor element.
  • the filling layer is provided in the through hole portion through the through electrode.
  • the insulating layer is provided on the back surface of the semiconductor element and on the through electrode on the back surface of the semiconductor element, and the opening is formed in the insulating layer to expose the through electrode on the back surface of the semiconductor element.
  • the external electrode is provided in the opening and is connected to the through electrode.
  • a second semiconductor device includes a first semiconductor element, a circuit region provided on a main surface of the first semiconductor element, a first adhesive layer covering the circuit region, and a main surface of the first semiconductor element.
  • a second adhesive layer covering at least a part of a portion other than the circuit region and having a hardness higher than that of the first adhesive layer; and a second semiconductor element bonded to the first semiconductor element via the first adhesive layer and the second adhesive layer And.
  • a first manufacturing method of a semiconductor device includes a step (a) of preparing a semiconductor element having an optical element formed on a main surface, a step (b) of covering the optical element with a first adhesive, A step (c) of covering at least a part of the main surface of the semiconductor element other than the optical element with a second adhesive having a hardness after curing that is higher than that of the first adhesive; a first adhesive layer made of the first adhesive; And a step (d) of adhering the translucent plate to the semiconductor element through a second adhesive layer made of two adhesives.
  • the second adhesive layer having a relatively high hardness is cut. Therefore, since the dicing process can be performed smoothly, problems such as a decrease in throughput in the dicing process, chipping of semiconductor elements, and damage to the dicing blade can be prevented.
  • the step (d) in the step (d), at least one of a first surface facing the main surface of the semiconductor element and a second surface positioned on the opposite side of the first surface.
  • a light-transmitting plate provided with an antireflection film on the surface may be bonded to the semiconductor element. Thereby, reflection of the light in the 1st surface or 2nd surface of an antireflection film can be prevented.
  • the step (e) of blackening the second adhesive it is only necessary to include the step (e) of blackening the second adhesive. Thereby, the light incident on the second adhesive layer can be prevented from reaching the optical element.
  • the first method for manufacturing a semiconductor device according to the present invention preferably includes a step (f) of providing a spacer between the first adhesive layer and the second adhesive layer on the main surface of the semiconductor element. Thereby, the dispersion
  • the first method for manufacturing a semiconductor device according to the present invention includes the step (f), it is preferable to perform the step (f) before performing the step (b) and the step (c).
  • the first manufacturing method of the semiconductor device includes a step (g) of disposing the light transmitting plate on the first adhesive after the step (b) and before the step (c).
  • a part of the first adhesive flows along the lower surface of the translucent plate toward the peripheral portion of the lower surface of the translucent plate, or passes through the main surface of the semiconductor element to form the semiconductor. What is necessary is just to flow toward the peripheral part of the main surface of an element. Thereby, the area
  • an electrode is provided outside the optical element on the main surface of the semiconductor element prepared in step (a).
  • the semiconductor device according to the present invention includes a step of penetrating a through hole portion in the thickness direction of the semiconductor element so as to reach the electrode, and an inner surface of the through hole portion while being in contact with the electrode.
  • a second manufacturing method of a semiconductor device includes a step of preparing a semiconductor wafer in which a main surface is divided into a plurality of regions by dicing lines and an optical element is formed in each of the regions, A step of covering each with a first adhesive, a step of covering at least a part of the main surface of the semiconductor element other than the optical element with a second adhesive having a hardness after curing that is higher than that of the first adhesive, and a first adhesive A step of bonding the translucent plate to the semiconductor wafer via a first adhesive layer made of an agent and a second adhesive layer made of a second adhesive, and a step of dicing the semiconductor wafer along a dicing line.
  • the second adhesive layer having a relatively high hardness is cut. Therefore, since the dicing process can be performed smoothly, problems such as a decrease in throughput in the dicing process, chipping of semiconductor elements, and damage to the dicing blade can be prevented.
  • the present invention can provide a semiconductor device that is excellent in electrical characteristics and image characteristics, is highly reliable, and can be manufactured at low cost.
  • FIG. 1 is a sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 2 is an enlarged cross-sectional view showing the structure of the semiconductor device according to the first modification of the first embodiment of the present invention.
  • FIG. 3 is a sectional view showing a structure of a semiconductor device according to a second modification of the first embodiment of the present invention.
  • FIG. 4 is an enlarged cross-sectional view showing the structure of the semiconductor device according to the third modification of the first embodiment of the present invention.
  • FIG. 5 is a sectional view showing the structure of a semiconductor device according to the second embodiment of the present invention.
  • FIG. 6 is an enlarged cross-sectional view showing the structure of a semiconductor device according to a modification of the second embodiment of the present invention.
  • FIG. 7A to 7D are cross-sectional views showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.
  • 8A to 8C are cross-sectional views showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps.
  • FIG. 9 is a sectional view showing the structure of a semiconductor device according to the fifth embodiment of the present invention.
  • FIG. 10 is a sectional view showing the structure of a semiconductor device according to the fifth embodiment of the present invention.
  • FIG. 11 is a cross-sectional view showing the structure of a semiconductor device according to a modification of the fifth embodiment of the present invention.
  • FIG. 12A to 12C are cross-sectional views showing a method of manufacturing a semiconductor device according to the fifth embodiment of the present invention in the order of steps.
  • FIG. 13A to FIG. 13C are cross-sectional views showing a method of manufacturing a semiconductor device according to a modification of the fifth embodiment of the present invention in the order of steps.
  • FIG. 14 is a cross-sectional view showing the structure of a conventional solid-state imaging device.
  • FIG. 1 is a cross-sectional view showing the structure of a semiconductor device 10 according to this embodiment.
  • the semiconductor device 10 is provided on the outside of the semiconductor element 11, the light receiving unit 12 that is an optical element provided on the main surface 11 ⁇ / b> A of the semiconductor element 11, and the light receiving unit 12 on the main surface 11 ⁇ / b> A of the semiconductor element 11. Bonded to the semiconductor element 11 through the peripheral circuit region 13 formed, the electrode 14 provided on the outer surface of the light receiving portion 12 on the main surface 11A of the semiconductor element 11, and the first adhesive layer 15 and the second adhesive layer 16.
  • the translucent plate 17 is provided.
  • the semiconductor element 11 may have a thickness of 100 ⁇ m to 300 ⁇ m, for example.
  • the elastic modulus of the semiconductor element 11 is, for example, 130 GPa to 190 GPa.
  • the light receiving portion 12 is preferably formed at the center of the main surface 11A of the semiconductor element 11, and the peripheral circuit region 13 is outside the light receiving portion 12 on the main surface 11A of the semiconductor element 11 so as to surround the light receiving portion 12. Is formed.
  • the light receiving unit 12 and the peripheral circuit region 13 are electrically connected to each other, and are preferably in contact with each other as shown in FIG.
  • the light receiving unit 12 detects light (signal light) incident on the semiconductor device 10 according to the present embodiment, converts the light into an electrical signal, and transmits the electric signal to the peripheral circuit region 13. The electrical signal from is processed.
  • the electrode 14 is electrically connected to the peripheral circuit region 13 and is preferably in contact with the upper surface of the peripheral circuit region 13 as shown in FIG.
  • the electrodes 14 are preferably arranged on the main surface 11 ⁇ / b> A of the semiconductor element 11 so as to be spaced from each other.
  • Such an electrode 14 should just be formed in part by metal thin films, such as Al or Cu.
  • the translucent plate 17 only needs to be able to transmit signal light (for example, visible light), and may be made of, for example, optical glass.
  • the elastic modulus of the translucent plate 17 is, for example, 70 GPa to 80 GPa.
  • first adhesive layer 15 and the second adhesive layer 16 will be described.
  • the first adhesive layer 15 covers the light receiving unit 12.
  • the second adhesive layer 16 covers the main surface 11A of the semiconductor element 11 other than the light receiving portion 12, and is provided on the main surface 11A of the semiconductor element 11 outside the first adhesive layer 15. It is in contact with the first adhesive layer 15. Therefore, when the semiconductor device according to this embodiment is manufactured by dicing the semiconductor wafer, not the first adhesive layer 15 but the second adhesive layer 16 is cut.
  • the first adhesive layer 15 covers the light receiving unit 12, it may be made of a material that can transmit signal light.
  • the first adhesive layer 15 is preferably made of a highly light-resistant and thermosetting rubber adhesive. Thereby, even if the signal light is a light beam having a high power density (for example, 1 W / cm 3 or more), the first adhesive layer 15 can be prevented from being discolored and contracted, and light (wavelength is, for example, 400 nm) can be transmitted. It is preferable to select the material of the first adhesive layer 15 (thickness is, for example, 2 mm) so that the rate is 85% or more, preferably 90%.
  • a rubber adhesive it is preferable to use, for example, silicone rubber, dimethyl silicone rubber or phenyl silicone rubber.
  • the hardness of the 1st contact bonding layer 15 is 5 or more and less than 65 in Shore D hardness, Preferably it is 10 or more and 40 or less.
  • the hardness of the first adhesive layer 15 may be an elastic modulus of 800 kPa or more and less than 15 MPa, preferably 2 MPa or more and 10 MPa or less.
  • the second adhesive layer 16 only has to have a Shore D hardness of 65 or more in a room temperature environment (about 27 ° C.).
  • the second adhesive layer 16 has an elastic modulus of 15 MPa or more. Just do it. Since the hardness of the first adhesive layer 15 is 5 or more and less than 65 in Shore D hardness in a room temperature environment, the second adhesive layer 16 is larger in hardness than the first adhesive layer 15. Thereby, dicing with respect to a semiconductor wafer can be performed smoothly.
  • the second adhesive layer 16 may contain a main component different from that of the first adhesive layer 15, or may contain the same main component as the first adhesive layer 15.
  • the second adhesive layer 16 preferably includes the same main component as the first adhesive layer 15.
  • the affinity of the second adhesive layer 16 for the first adhesive layer 15 can be increased, and the affinity of the first adhesive layer 15 for the second adhesive layer 16 can be increased. Therefore, the first adhesive layer 15 and the second adhesive layer 16 can be satisfactorily bonded to each other at the interface between the first adhesive layer 15 and the second adhesive layer 16.
  • the second adhesive layer 16 only needs to have its hardness (or its elastic modulus) adjusted by mixing an inorganic substance (such as silica) into the main component of the first adhesive layer 15. . Therefore, the hardness difference between the substrate and the light transmitting plate 17 (glass) in the dicing lane is relaxed by the second adhesive layer 16 and is easily cut.
  • the second adhesive layer 16 includes a main component different from the first adhesive layer 15, for example, when the main component of the first adhesive layer 15 is silicone, the main component of the second adhesive layer 16 is the first Any component that does not inhibit the curing of the adhesive layer 15 may be used, and polyimide is preferable.
  • carbon may be mixed into the second adhesive layer 16.
  • Examples of carbon to be mixed include carbon black, channel black, furnace black, acetylene black, thermal black, and lamp black.
  • the average particle diameter of carbon black is preferably finer, for example, preferably 1 nm to 900 nm, and more preferably about 1 nm to 100 nm.
  • the second adhesive layer 16 can absorb the incident light. Therefore, it is possible to prevent the light (stray light) that has been reflected from the side surface of the translucent plate 17 and entered the second adhesive layer 16 from reaching the light receiving unit 12.
  • Such a semiconductor device preferably further includes a through electrode 18, a filling layer 19, an insulating layer 20, and an external electrode 21.
  • the semiconductor element 11 only needs to have a through-hole (through-hole portion) 11a that penetrates from the back surface 11B to the main surface 11A and reaches the electrode 14.
  • the through electrode 18 is provided on each inner surface of the through hole 11a, and is in contact with the electrode 14 inside each through hole 11a. As a result, the through electrode 18 is electrically connected to the peripheral circuit region 13 through the electrode 14.
  • the through electrode 18 extends from the inner side surface of each through hole 11 a toward the back surface 11 ⁇ / b> B of the semiconductor element 11.
  • Such a through electrode 18 is made of a metal such as Ti or Cu, for example.
  • the filling layer 19 is provided in the through hole 11a via each through electrode 18, and may be made of resin (for example, polyimide resin, silicone resin or epoxy resin), or may be made of metal.
  • resin for example, polyimide resin, silicone resin or epoxy resin
  • the insulating layer 20 is provided on the through electrode 18 on the back surface 11B of the semiconductor element 11 and on the back surface 11B of the semiconductor element 11, and is made of a photosensitive resin (for example, polyimide resin, silicone resin, or epoxy resin). It is preferable. Further, the filling layer 19 and the insulating layer 20 may be made of the same material. An opening (opening) 20 a is formed in the insulating layer 20, whereby the through electrode 18 on the back surface 11 ⁇ / b> B of the semiconductor element 11 is exposed.
  • a photosensitive resin for example, polyimide resin, silicone resin, or epoxy resin.
  • the external electrode 21 is provided in each opening 20a, and is connected to the through electrode 18 in each opening 20a. Thereby, the external electrode 21 is connected to the electrode 14 through the through electrode 18. Therefore, the electrical signal converted by the light receiving unit 12 can be taken out.
  • Such an external electrode 21 may be made of, for example, a lead-free solder material having a Sn—Ag—Cu composition.
  • the light receiving unit 12 is covered with the first adhesive layer 15. Therefore, even when the light receiving unit 12 receives a light beam having a high power density (for example, 1 W / cm 3 or more), the first adhesive layer 15 can be prevented from contracting and discoloring. Therefore, in the present embodiment, it is possible to realize the semiconductor device 10 having excellent reliability and performance (for example, image characteristics).
  • a high power density for example, 1 W / cm 3 or more
  • the semiconductor device 10 according to the present embodiment is separated into pieces as a result of the dicing performed on the second adhesive layer 16. Since the second adhesive layer 16 has relatively high hardness, dicing can be performed smoothly. Accordingly, it is possible to prevent a decrease in throughput in the dicing process, chipping of semiconductor elements, breakage of the dicing blade, and the like. Thereby, in this embodiment, the semiconductor device 10 that can be manufactured with a high yield and a low cost can be realized.
  • the light transmitting plate 17 is directly bonded to the light receiving unit 12. Therefore, in this embodiment, a small and low-profile semiconductor device can be realized.
  • the semiconductor device according to this embodiment may have the configuration shown in the first to third modifications.
  • FIG. 2 is an enlarged cross-sectional view of a semiconductor device 30 according to a first modification of the present embodiment.
  • the adhesive strength at the interface between the second adhesive layer 16 and the semiconductor element 11 and the light transmitting plate 17 may be reduced.
  • the optical plate 17 cannot be firmly bonded to the semiconductor element 11. Therefore, a region A3 in which the first adhesive layer 35 and the second adhesive layer 36 are laminated is present between the semiconductor element 11 and the light transmitting plate 17 in the present modification.
  • the translucent plate 17 is bonded to the semiconductor element 11 via the first adhesive layer 35 also in the region A3. Therefore, the translucent plate 17 can be firmly bonded to the semiconductor element 11 as compared with the first embodiment.
  • a region A1 composed of the first adhesive layer 35, a region B composed of the second adhesive layer 36, and the first adhesive layer 35 and the second adhesive.
  • a region A3 in which the layer 36 is laminated with each other.
  • the region A1 is located on the light receiving portion 12
  • the region A2 is located on the peripheral portion of the main surface 11A of the semiconductor element 11, and the region A3 is separated from the region A1 on the main surface 11A of the semiconductor element 11. It is sandwiched between the area A2.
  • the first adhesive layer 35 constituting the region A1 corresponds to the first adhesive layer 15 in the first embodiment. Therefore, the first adhesive layer 35 in the present modification is obtained by connecting the first adhesive layer 35 in the region A3 to the first adhesive layer 15 in the first embodiment.
  • the second adhesive layer 36 and the first adhesive layer 35 may be stacked in this order in the direction from the semiconductor element 11 to the light transmitting plate 17, and the first adhesive layer 35 and the second adhesive layer 36 may be stacked in this order.
  • the first adhesive layer 35, the second adhesive layer 36, and the first adhesive layer 35 may be stacked in this order.
  • the second adhesive layer 36 and the first adhesive layer 35 are preferably stacked in this order in the direction from the semiconductor element 11 to the light transmitting plate 17. .
  • FIG. 3 is a cross-sectional view of a semiconductor device 40 according to a second modification of the present embodiment.
  • an antireflection film 41 is formed on the main surface (second surface) 17A and the back surface (first surface) 17B of the translucent plate 17.
  • reflection of the light in the main surface 17A and the back surface 17B of the translucent plate 17 can be prevented. Therefore, since the signal light is incident on the light receiving unit 12 without being reflected on the main surface 17A and the back surface 17B of the translucent plate 17, the signal light is incident on the light receiving unit 12 without a decrease in intensity. Therefore, a semiconductor device with excellent performance can be realized.
  • stray light can be prevented from being reflected at the interface between the second adhesive layer 16 and the translucent plate 17 and reaching the light receiving unit 12. Therefore, a semiconductor device in which deterioration of image characteristics is prevented can be realized.
  • the antireflection film 41 is composed of, for example, Al 2 O 3 , Nb 2 O 5 , SiO 2 , Ta 2 O 5 , TiO 2 , Y 2 O 3, ZrO 2, etc. It is preferable to have a laminated structure.
  • the antireflection film 41 is formed on the main surface 17A and the back surface 17B of the light transmitting plate 17. Is preferred. However, if the antireflection film 41 is formed on one of the main surface 17A and the back surface 17B of the translucent plate 17, the antireflection film 41 is formed on the main surface 17A and the back surface 17B of the translucent plate 17. Compared to the case where the light is not formed on both surfaces (first embodiment), reflection of light on the main surface 17A and the back surface 17B of the translucent plate 17 can be prevented.
  • FIG. 4 is an enlarged cross-sectional view of a semiconductor device 50 according to a third modification of the present embodiment.
  • This modification is a combination of the first modification and the second modification.
  • the antireflection film 41 is formed on the main surface 17A and the back surface 17B of the translucent plate 17, and the region A3 (first adhesive in the region A3) is provided between the semiconductor element 11 and the translucent plate 17.
  • Layer 15 and second adhesive layer 16 are laminated to each other).
  • FIG. 5 is a cross-sectional view showing the structure of the semiconductor device 60 according to this embodiment.
  • a spacer 61 is provided in the semiconductor device 10 according to the first embodiment. Below, it demonstrates centering on difference with said 1st embodiment.
  • the first adhesive layer 15 and the second adhesive layer 16 are arranged on the main surface 11A of the semiconductor element 11 with a space therebetween.
  • the spacer 61 is provided between the first adhesive layer 15 and the second adhesive layer 16 on the main surface 11 ⁇ / b> A of the semiconductor element 11.
  • the spacer 61 may have a width of 30 ⁇ m to 300 ⁇ m, for example, and is preferably made of polyimide resin or epoxy resin.
  • the semiconductor device 60 according to the present embodiment includes the spacer 61, in the present embodiment, the following effects can be obtained in addition to the effects obtained in the first embodiment.
  • the translucent plate 17 is supported by the spacer 61. Therefore, when the translucent plate 17 is bonded to the semiconductor element 11 via the first adhesive layer 15 and the second adhesive layer 16, the translucent plate 17 and the semiconductor element 11 in the height direction (thickness direction) Alignment can be performed easily.
  • the variation in the thickness of the first adhesive layer 15 can be minimized, the optical path length difference of the light incident on the first adhesive layer 15 can be minimized. Therefore, variations in image formation at each pixel can be prevented.
  • the spacer 61 is refracted by coating a material having an antireflection function using, for example, porous silicon or Al 2 O 3 , Nb 2 O 5 , SiO 2 , Ta 2 O 5 , TiO 2 , Y 2 O 3 and ZrO 2.
  • a material having an antireflection function using, for example, porous silicon or Al 2 O 3 , Nb 2 O 5 , SiO 2 , Ta 2 O 5 , TiO 2 , Y 2 O 3 and ZrO 2.
  • a plurality of films having different rates may be stacked).
  • the semiconductor device according to this embodiment may have a configuration shown in the following modification.
  • FIG. 6 is an enlarged cross-sectional view of a semiconductor device 70 according to a modification of the second embodiment.
  • the spacer 61 is inferior to the first adhesive layer 15 and the second adhesive layer 16 in the adhesive ability, the connection between the semiconductor element 11 and the translucent plate 17 in the portion where the spacer 61 is provided. It is difficult to ensure strength. Therefore, in this modification, a region A4 where the first adhesive layer 35 and the spacer 61 are laminated is present between the semiconductor element 11 and the light transmitting plate 17. Thereby, in this modification, the translucent plate 17 is bonded to the semiconductor element 11 via the first adhesive layer 35 also in the region A4. Therefore, the translucent plate 17 can be firmly bonded to the semiconductor element 11 as compared with the second embodiment.
  • the spacer 61 and the first adhesive layer 35 may be stacked in this order in the direction from the semiconductor element 11 to the translucent plate 17, or the first adhesive layer 35 and the spacer 61 may be stacked in this order.
  • the first adhesive layer 35, the spacer 61, and the first adhesive layer 35 may be stacked in this order.
  • the spacer 61 and the first adhesive layer 35 are preferably stacked in this order in the direction from the semiconductor element 11 to the light transmitting plate 17.
  • FIGS. 7A to 7D are cross-sectional views illustrating the method for manufacturing the semiconductor device 10 according to the first embodiment in the order of steps.
  • a semiconductor wafer 111 having a main surface 111A partitioned into a plurality of regions (two regions in FIG. 7A) 110 by a scribe line L is prepared.
  • a light receiving portion 12 and a peripheral circuit region 13 are formed, and an electrode 14 is provided on each region 110.
  • the light receiving portion 12 in each region 110 is covered with the first adhesive 115 by, for example, a dispensing method, a spin coating method, a printing filling method, or the like, preferably by a dispensing method.
  • the first adhesive 115 When applying the first adhesive 115 by the dispensing method, the first adhesive 115 may be applied according to the following method.
  • a photosensitive liquid resist (not shown) is applied to the entire main surface 111A by using, for example, a dry film attaching method or a spin coating method.
  • the thickness of the resist may be determined according to the thickness of the first adhesive layer 15 and may be about 10 ⁇ m to 35 ⁇ m.
  • the resist is patterned so that only the light receiving portion 12 is exposed by exposure and development using a photolithography technique.
  • the resist 71 is formed with an opening 71 a that exposes each of the light receiving portions 12.
  • the first adhesive 115 is filled into the opening 71a of the resist 71 using a dispensing method.
  • the filling amount of the first adhesive 115 may be appropriately determined according to the volume of the opening 71 a of the resist 71.
  • the shape of the first adhesive 115 before curing can be maintained.
  • the first adhesive 115 may be applied by a dispensing method without forming the resist 71, it is difficult to maintain the shape of the first adhesive 115 before being cured. Therefore, it is preferable to fill the first adhesive 115 in the opening 71 a of the resist 71.
  • the first adhesive 115 When applying the first adhesive 115 by spin coating, the first adhesive 115 may be applied according to the following method.
  • a resist 71 is formed on the main surface 111A of the semiconductor wafer 111.
  • the first adhesive 115 is applied on the main surface 111A of the semiconductor wafer 111 and the resist 71 by using a spin coating method. At this time, the first adhesive 115 deposited on the resist 71 is removed by spin coating centrifugal force.
  • the rotational speed and time of spin coating may be appropriately changed depending on the degree of filling of the first adhesive 115 into the opening 71a of the resist 71 and the removability of the first adhesive 115 deposited on the resist 71.
  • a light transmitting plate 117 is prepared.
  • the semiconductor wafer 111 and the translucent plate 117 are bonded together with the first adhesive 115 interposed therebetween. Thereafter, heat treatment is performed to cure the first adhesive 115. Thereby, the first adhesive layer 15 is formed on each of the light receiving portions 12, and the translucent plate 117 is bonded to the semiconductor wafer 111.
  • the semiconductor device shown in FIG. 3 is manufactured.
  • the semiconductor wafer 111 and the light transmitting plate 117 are bonded together in a pressurized state, a part of the first adhesive 115 extends from the inside of the opening 71a of the resist 71 to the back surface 117B of the light transmitting plate 117 and outside the opening 71a.
  • the semiconductor device shown in FIG. 2 is manufactured.
  • the second adhesive is filled in the cavity (the portion where the resist 71 is provided) between the semiconductor element 11 and the light transmitting plate 117. Since the second adhesive is filled into the cavity using the capillary phenomenon, it is desirable that the second adhesive has a low viscosity. Further, in order to improve the penetration rate of the second adhesive into the cavity, the second adhesive may be filled in the cavity in a vacuum state (10 ⁇ 1 Pa to 10 Pa). When the filling of the cavity is completed, heat treatment is performed. As a result, the second adhesive is cured, and the second adhesive layer 16 is formed outside the first adhesive layer 15 in each region 110.
  • the semiconductor wafer 111 is back-ground so that the thickness becomes a desired value (generally, about 100 ⁇ m to 300 ⁇ m). Furthermore, it is desirable that the back surface 111B of the semiconductor wafer 111 be subjected to a mirror surface treatment such as CMP (chemical mechanical polishing).
  • CMP chemical mechanical polishing
  • a through hole 11 a is formed in the semiconductor wafer 111.
  • a mask such as a resist, a SiO 2 film, or a metal film is formed on the back surface 111B of the semiconductor wafer 111.
  • an opening (not shown) is formed in a portion of the mask facing the electrode 14.
  • dry etching or wet etching is performed.
  • the through hole 11 a is formed so as to reach the lower surface of the electrode 14 from the back surface 111 ⁇ / b> B of the semiconductor wafer 111.
  • the entire back surface 111B of the semiconductor wafer 111 and the light receiving unit 12 and a part of the peripheral circuit region 13 in the surface of the semiconductor wafer 111 are formed.
  • An insulating film such as SiO 2 (not shown. This insulating film is not shown in FIG. 1) is formed in the removed portion and inside each through hole 11a. Thereafter, dry etching or wet etching is performed to remove the insulating film formed on the lower surface of the electrode 14.
  • the through electrode 18 is formed in the semiconductor wafer 111.
  • a metal thin film (not shown) is formed on the entire surface of the semiconductor wafer 111 using a sputtering method or the like.
  • a Ti film, a TiW film, a Cr film, or a Cu film may be used as the metal thin film.
  • the resist is patterned by exposure and development using a photolithography technique. Note that the thickness of the resist may be determined according to the thickness of the through electrode 18 to be finally formed, and is generally about 5 ⁇ m to 30 ⁇ m.
  • electrolytic plating is performed, a metal such as Cu is deposited on a portion of the metal thin film that is not covered with the resist. Thereby, the through electrode 18 is formed.
  • a filling layer 19 is formed in the through hole 11a.
  • a resin is used as the filling material, a liquid photocurable resin or a liquid thermosetting resin may be filled into the through holes 11a by spin coating, or a resin paste may be filled by a printing filling method or dipping.
  • the through hole 11a may be filled.
  • the metal When a metal is used as the filling material, the metal may be filled into the through-hole 11a using an electrolytic plating method, or a metal paste may be filled mainly into the through-hole 11a using a printing filling method or a dipping method. It may be filled.
  • the through electrode 18 and the filling layer 19 may be formed at the same time, or the filling layer 19 may be formed after the through electrode 18 is formed. Good. In the former case, the through hole 11a may be completely embedded with metal. In the latter case, after the through electrode 18 is formed, a mask exposing only the through hole 11a is formed on the back surface 111B of the semiconductor wafer 111, and the through hole 11a is filled with metal by an electrolytic plating method.
  • the insulating layer 20 is formed on the back surface 111 ⁇ / b> B of the semiconductor wafer 111.
  • a photosensitive resin may be formed on the back surface 111B of the semiconductor wafer 111 by spin coating or dry film bonding.
  • the insulating layer 20 is selectively removed using a photolithography technique. Thereby, an opening 20a is formed in the insulating layer 20, and a part of the through electrode 18 is exposed from each opening 20a.
  • the external electrode 21 is formed in the opening 20a by a solder ball mounting method using a flux, a solder paste printing method, or an electroplating method.
  • a solder ball mounting method using a flux, a solder paste printing method, or an electroplating method.
  • a solder ball mounting method using a flux, a solder paste printing method, or an electroplating method.
  • a solder ball mounting method using a flux, a solder paste printing method, or an electroplating method.
  • a solder ball mounting method using a flux, a solder paste printing method, or an electroplating method.
  • the semiconductor wafer 111 is cut along the scribe line L using a cutting member 85 such as a dicing saw, for example, and the semiconductor devices 10 are separated into pieces.
  • the second adhesive layer 16 exists on the scribe line L. Therefore, compared to the case where a relatively soft adhesive layer (for example, the first adhesive layer 15) is present on the scribe line, dicing can be easily performed, and as a result, throughput can be improved. Moreover, the end face of each semiconductor device separated into pieces can be made flat.
  • the manufacturing method of the semiconductor device according to the present embodiment may include the following steps.
  • the first adhesive layer 15 may be formed after the second adhesive layer 16 is formed, and then the light-transmitting plate 117 may be bonded. That is, the second adhesive is applied on the main surface of the semiconductor wafer 111 on the outer side of the light receiving unit 12, and then the first adhesive 115 is applied by a dispensing method, a printing method, a spin coating method, or the like. Then, the light transmitting plate 117 may be attached to the semiconductor wafer 111 via the first adhesive 115 and the second adhesive.
  • the first adhesive 115 and the second adhesive may be applied on the back surface 117B of the translucent plate 117.
  • the first adhesive passes over the main surface 111 ⁇ / b> A of the semiconductor wafer 111 and oozes out to the outside of the light receiving unit 12.
  • the second adhesive may contain carbon (for example, carbon black, channel black, furnace black, acetylene black, thermal black, lamp black, etc.). Thereby, the second adhesive layer 16 becomes black in the visible light region.
  • carbon for example, carbon black, channel black, furnace black, acetylene black, thermal black, lamp black, etc.
  • a semiconductor wafer 111 on which the light receiving unit 12, the peripheral circuit region 13, and the electrode 14 are formed is prepared.
  • a spacer 61 is formed on the main surface 111 ⁇ / b> A of the semiconductor wafer 111.
  • a polyimide resin or an epoxy resin is applied on the main surface 111 ⁇ / b> A of the semiconductor wafer 111 by a spin coating method, a printing method, a dispensing method, or the like so as to surround the light receiving unit 12.
  • the width of the polyimide resin or epoxy resin on the main surface 111A of the semiconductor wafer 111 may be set to 30 ⁇ m to 300 ⁇ m, for example.
  • the translucent plate 117 is bonded to the main surface 111 ⁇ / b> A of the semiconductor wafer 111 through the first adhesive 115 and the second adhesive 116.
  • application of the first adhesive 115, adhesion of the light transmitting plate 117, and application of the second adhesive 116 may be performed in this order, or in the following order. May be.
  • the first adhesive 115 and the second adhesive 116 are applied using, for example, a dispensing method. Specifically, the first adhesive 115 is applied to a portion surrounded by the spacer 61, and the second adhesive 116 is applied to the side opposite to the first adhesive 115 with the spacer 61 interposed therebetween.
  • the light transmitting plate 117 is bonded to the main surface 111 ⁇ / b> A of the semiconductor wafer 111 through the first adhesive 115 and the second adhesive 116, and then the first adhesive 115. And the second adhesive 116 is cured.
  • the through electrode 18, the filling layer 19, the insulating layer 20, and the external electrode 21 are formed, and the semiconductor wafer 111 is cut along the scribe line L using a cutting member. To do. Thereby, the semiconductor device according to the second embodiment is obtained.
  • the liquid non-photosensitive first adhesive 115 and second adhesive 116 are applied to the main surface 111 ⁇ / b> A of the semiconductor wafer 111. Can be applied on top. Therefore, in this embodiment, since the selectivity of the material of the first adhesive and the second adhesive can be widened, a semiconductor device can be manufactured at low cost.
  • the semiconductor devices of the first to fourth embodiments may include a light emitting unit instead of the light receiving unit 12 as an optical element.
  • the first to fourth embodiments can be applied to a light emitting device.
  • FIG. 9 is a cross-sectional view showing the structure of the semiconductor device 80 according to this embodiment.
  • the semiconductor device according to the fifth embodiment is different from the semiconductor device according to the first embodiment in that a circuit region 83 ⁇ / b> A is formed in the first semiconductor element 81 instead of the light receiving unit 12 and the peripheral circuit region 13. Further, the second semiconductor element 82 is pasted on the main surface 81A of the first semiconductor element 81 instead of the light transmitting plate 17.
  • the semiconductor device according to the present embodiment includes a first semiconductor element 81, a circuit region 83 ⁇ / b> A provided on the main surface 81 ⁇ / b> A of the first semiconductor element 81, and a main surface 81 ⁇ / b> A of the first semiconductor element 81.
  • the electrode 14A is provided, and a second semiconductor element 82 bonded onto the main surface 81A of the first semiconductor element 81 by the first adhesive layer 15 and the second adhesive layer 16 is provided.
  • the first adhesive layer 15 is formed so as to cover the circuit region 83 ⁇ / b> A
  • the second adhesive layer 16 is formed so as not to cover the circuit region 83 ⁇ / b> A on the main surface 81 ⁇ / b> A of the first semiconductor element 81.
  • the second adhesive layer 16 is provided outside the first adhesive layer 15 on the main surface 81 ⁇ / b> A of the first semiconductor element 81 and is in contact with the first adhesive layer 15.
  • the first semiconductor element 81 is provided with a through electrode 18A and a filling layer 19A, and the through electrode 18A is in contact with the electrode 14A. Thereby, the through electrode 18A is electrically connected to the circuit region 83A through the electrode 14A.
  • An insulating layer 20A is formed on the back surface 81B of the first semiconductor element 81, and an opening 20a exposing the through electrode 18A is formed in the insulating layer 20A. In the opening 20a, an external electrode 21A is formed so as to be connected to the through electrode 18A.
  • the structure of the second semiconductor element 82 is the same as that of the first semiconductor element 81, and is provided with a circuit region 83B, an electrode 14B, and the like. Further, the through electrode 18B and the filling layer 19B are also formed in the second semiconductor element 82, and the external electrode 21B connected to the through electrode 18B is electrically connected to the electrode 14A provided on the first semiconductor element 81. It is connected.
  • the first semiconductor element 81 and the first semiconductor element 81 are formed by making the hardness of the second adhesive layer 16 larger than the hardness of the first adhesive layer 15. 2 Dicing is smoothly performed because the stress at the time of bonding to the semiconductor element 82 is absorbed by the first adhesive layer 15 and the second adhesive layer 16 is relatively harder than the first adhesive layer 15. Can do.
  • a plurality of second semiconductor elements 82 may be stacked on the first semiconductor element 81 as shown in FIG. Even if it does in this way, the stress which arises at the time of each bonding can fully be relieved.
  • the thickness of the first semiconductor element 81 and the second semiconductor element 82 is preferably 50 ⁇ m or less.
  • the hardness of the second adhesive layer 16 in this embodiment is 65 or more in Shore D hardness, in other words, the elastic modulus is desirably 15 MPa or more.
  • the elastic modulus of the first adhesive layer 15 in the present embodiment is not particularly limited as long as the first adhesive layer 15 is relatively softer than the second adhesive layer 16, and the thicknesses of the first semiconductor element 81 and the second semiconductor element 82 are not limited. What is necessary is just to change suitably according to thickness and the number of lamination
  • FIG. 11 is a cross-sectional view of a semiconductor device 80 according to a variation of the fifth embodiment.
  • circuit regions 83A and 83B in the first semiconductor element 81 and the second semiconductor element 82 are formed on the back surfaces 81B and 82B, respectively, and the second semiconductor element 82 is The difference is that the through electrode and the filling layer are not formed.
  • the first semiconductor element 81 includes a circuit region 83A formed on the back surface 81B side of the first semiconductor element 81, and a circuit region 83A formed on the back surface 81B side of the first semiconductor element 81 and electrically connected to the circuit region 83A.
  • An electrode 14A to be connected and an external electrode 21A formed on the back surface 81B side of the first semiconductor element 81 and electrically connected to the electrode 14A are provided.
  • the second semiconductor element 82 is formed on the back surface 82B side of the second semiconductor element 82, and is formed on the back surface 82B side of the second semiconductor element 82 and is electrically connected to the circuit region 83B.
  • An electrode 14B and an external electrode 21B formed on the back surface 82B of the second semiconductor element 82 and electrically connected to the electrode 14 are provided.
  • the second semiconductor element 82 does not include a through electrode, a filling layer, an insulating layer, and an opening.
  • the first semiconductor element 81 and the second semiconductor element 82 are electrically connected by the through electrode 18A of the first semiconductor element 81 and the external electrode 21B of the second semiconductor element 82.
  • the manufacturing process of the semiconductor device 80 can be simplified.
  • the semiconductor device 80 can be manufactured at a low cost.
  • a plurality of first semiconductor elements 81 may be stacked.
  • FIGS. 12A to 12C are cross-sectional views illustrating a method for manufacturing a semiconductor device 80 according to the fifth embodiment in the order of steps.
  • a first semiconductor wafer 121 having a main surface 121A divided into a plurality of chip regions 120 (two regions in FIG. 12A) by a scribe line L, and a plurality of main surfaces 122A corresponding to the plurality of chip regions 120. And the second semiconductor wafer 122 partitioned into the chip region 123 are prepared.
  • Each of the chip regions 120 is provided with a circuit region 83A, an electrode 14A, a through electrode 18A, a filling layer 19A, an insulating layer 20A, and an opening 20a.
  • Each of the chip regions 123 is provided with a circuit region 83B, an electrode 14B, a through electrode 18B, a filling layer 19B, an insulating layer 20B, an opening 20a, and an external electrode 21B.
  • the electrode 14A and the external electrode 21B are formed on the main surface 121A via the first adhesive 115 and the second adhesive 116 by the same method as in the third embodiment and the fourth embodiment.
  • the first semiconductor wafer 121 and the second semiconductor wafer 122 are bonded so as to be electrically connected.
  • the first semiconductor wafer 121 and the second semiconductor wafer 122 may be bonded together using ultrasonic waves.
  • the external electrode 21A of the first semiconductor wafer 121 is formed by the same method as in the third embodiment.
  • the plurality of first semiconductor wafers 121 and the plurality of second semiconductor wafers 122 are separated into pieces using a cutting member 85 such as a dicing saw.
  • a cutting member 85 such as a dicing saw.
  • 13A to 13C are cross-sectional views illustrating a method for manufacturing the semiconductor device 80 according to a modification of the fifth embodiment in the order of steps.
  • the first semiconductor wafer 121 is divided into a plurality of chip regions 120 (two regions in FIG. 13A) with a main surface 121A by a scribe line L, and the main surface 122A has a plurality of chips.
  • a second semiconductor wafer 122 partitioned into a plurality of chip regions 123 corresponding to the region 120 is prepared.
  • Each of the chip regions 120 is provided with a circuit region 83A, an electrode 14A, a through electrode 18A, a filling layer 19A, an insulating layer 20A, and an opening 20a
  • each of the chip regions 123 is provided with a circuit region 83B, an electrode 14B, and an external electrode 21B. ing.
  • the first electrode 115 ⁇ / b> A and the external electrode 21 ⁇ / b> B are electrically connected to the main surface 121 ⁇ / b> A via the first adhesive 115 and the second adhesive 116 by the same method as described above.
  • the semiconductor wafer 121 and the second semiconductor wafer 122 are bonded together.
  • the external electrode 21A of the first semiconductor wafer is formed by the same method as in the third embodiment.
  • the plurality of first semiconductor wafers 121 and the plurality of second semiconductor wafers 122 are separated into pieces using a cutting member 85 such as a dicing saw.
  • the semiconductor device of the present invention is particularly suitable for various semiconductor devices or various modules such as a solid-state imaging device, a photodiode or a laser module.

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Abstract

Disclosed is a semiconductor device (10) that is provided with a semiconductor element (11), an optical element (12) disposed on a principal surface (11A) of the semiconductor element (11), a first adhesion layer (15) for covering the optical element (12), a second adhesion layer (16) — which has greater hardness than the first adhesion layer (15) — for covering at least a part of the principal surface (11A) of the semiconductor element (11) other than where the optical element (12) is disposed, and a translucent plate (17) that is adhered to the semiconductor element (11) between the first adhesive layer (15) and the second adhesive layer (16).

Description

半導体装置及びその製造方法Semiconductor device and manufacturing method thereof
　本発明は、光を検知する半導体装置及びその製造方法に関するものである。 The present invention relates to a semiconductor device that detects light and a manufacturing method thereof.
　近年、電子機器の小型化、薄型化、軽量化及び高機能化の進展に伴い、半導体装置では、従来のパッケージ構造からベアチップ構造あるいはＣＳＰ（チップ・サイズ・パッケージ，chip size package）構造が主流になってきている。この中でも、ウェハレベルＣＳＰ技術が注目されており、固体撮像素子をはじめとする光学デバイスにおいてもこの技術が採用されている（例えば特許文献１）。ここで、ウェハレベルＣＳＰ技術とは、ウェハ状態での組立工程において貫通電極及び再配線を形成することにより、受発光領域と外部電極とを電気的に接続する技術である。 In recent years, with the progress of miniaturization, thinning, weight reduction, and high functionality of electronic devices, the mainstream of semiconductor devices is the conventional chip structure, bare chip structure or CSP (chip size package). It has become to. Among these, the wafer level CSP technology is attracting attention, and this technology is also employed in optical devices including solid-state imaging devices (for example, Patent Document 1). Here, the wafer level CSP technology is a technology for electrically connecting the light emitting / receiving region and the external electrode by forming a through electrode and a rewiring in an assembly process in a wafer state.
　図１４は、従来のウェハレベルＣＳＰ構造を有する固体撮像素子の断面図である。 FIG. 14 is a cross-sectional view of a solid-state imaging device having a conventional wafer level CSP structure.
　従来の固体撮像装置９００Ａは、固体撮像素子９００を備えている。この固体撮像素子９００は、半導体素子９０１と、半導体素子９０１の主面に形成された撮像領域９０２と、撮像領域９０２上に設けられたマイクロレンズ９０３と、撮像領域９０２よりも周縁に形成された周辺回路領域９０４Ａと、周辺回路領域９０４Ａに電気的に接続された電極配線９０４Ｂとを含んでいる。 A conventional solid-state imaging device 900A includes a solid-state imaging device 900. The solid-state imaging device 900 is formed on the periphery of the semiconductor element 901, the imaging region 902 formed on the main surface of the semiconductor element 901, the microlens 903 provided on the imaging region 902, and the imaging region 902. A peripheral circuit region 904A and an electrode wiring 904B electrically connected to the peripheral circuit region 904A are included.
　また、半導体素子９０１の主面上には、接着層９０５を介して透光板９０６（例えば光学ガラス製）が設けられている。半導体素子９０１の内部には、半導体素子９０１を厚さ方向に貫通する貫通電極９０７が設けられている。 Further, a light transmitting plate 906 (for example, made of optical glass) is provided on the main surface of the semiconductor element 901 with an adhesive layer 905 interposed therebetween. A through electrode 907 that penetrates the semiconductor element 901 in the thickness direction is provided inside the semiconductor element 901.
　加えて、半導体素子９０１の裏面上には金属配線９０８が形成されており、この金属配線９０８は貫通電極９０７と電気的に接続されている。半導体素子９０１の裏面及び金属配線９０８は絶縁層９０９で被覆されており、絶縁層９０９には開口９０９ａが形成されている。各開口９０９ａからは金属配線９０８の一部分が露出しており、各開口９０９ａ内では半田等からなる外部電極９１０が金属配線９０８に接続されている。 In addition, a metal wiring 908 is formed on the back surface of the semiconductor element 901, and the metal wiring 908 is electrically connected to the through electrode 907. The back surface of the semiconductor element 901 and the metal wiring 908 are covered with an insulating layer 909, and an opening 909 a is formed in the insulating layer 909. A part of the metal wiring 908 is exposed from each opening 909a, and an external electrode 910 made of solder or the like is connected to the metal wiring 908 in each opening 909a.
　以上のように、従来の固体撮像装置９００Ａでは、撮像領域９０２と外部電極９１０とは、周辺回路領域９０４Ａと電極配線９０４Ｂと貫通電極９０７と金属配線９０８とを介して電気的に接続されている。これにより、受光信号をフリップチップ用基板（不図示）等に取り出すことができる。 As described above, in the conventional solid-state imaging device 900A, the imaging region 902 and the external electrode 910 are electrically connected via the peripheral circuit region 904A, the electrode wiring 904B, the through electrode 907, and the metal wiring 908. . As a result, the received light signal can be taken out to a flip chip substrate (not shown) or the like.
特開２００４－２０７４６１号公報JP 2004-207461 A
　しかし、上述の固体撮像装置のように半導体素子の主面全面に亘って接着層を設ける場合、その接着層を構成する接着剤としてエポキシ樹脂又はシリコーン樹脂を主成分とする接着剤を用いると、パワー密度が高い光線（例えば０．４μＷ／μｍ２）を受光したときにその接着層が収縮及び変色する場合がある。これにより、固体撮像装置の信頼性の低下を引き起こす。この不具合を解決するためには、接着剤として高耐光性のゴムを用いればよい。ところが、耐光性が高いゴムは弾性率が低い場合が多い。そのため、透光板、接着層及び半導体ウェハの一括ダイシング工程において、スループットの低下（本明細書では、単位時間当たりにダイシング可能なウェハの枚数が減少すること）、半導体素子のチッピング及びダイシングブレードの破損等の問題を引き起こす。これにより、固体撮像装置の歩留まり低下を招来する。 However, when an adhesive layer is provided over the entire main surface of the semiconductor element as in the above-described solid-state imaging device, an adhesive mainly composed of an epoxy resin or a silicone resin is used as an adhesive constituting the adhesive layer. When a light beam having a high power density (for example, 0.4 μW / μm 2 ) is received, the adhesive layer may contract and discolor. This causes a decrease in the reliability of the solid-state imaging device. In order to solve this problem, a highly light-resistant rubber may be used as an adhesive. However, rubber with high light resistance often has a low elastic modulus. Therefore, in the collective dicing process of the translucent plate, the adhesive layer, and the semiconductor wafer, the throughput decreases (in this specification, the number of wafers that can be diced per unit time decreases), the chipping of the semiconductor element and the dicing blade Causes damage and other problems. As a result, the yield of the solid-state imaging device is reduced.
　また、受光部上にキャビティーを形成するように接着層を受光部上に選択的に設ける場合、その接着層を構成する接着剤としてエポキシ樹脂又はシリコーン樹脂を主成分とする接着剤を用いると、その後の製造工程の熱履歴及び実装後の駆動回路の発熱により、接着層からアウトガスが発生してキャビティー内に充満する。この状態でパワー密度が高い光線（０．４μＷ／μｍ２）を受光すると、光ピンセット効果によりアウトガス粒子が透光板の裏面上に析出して画像特性の劣化を引き起こすといった問題が生じる。これを解決するためには、接着剤として低アウトガス排出のゴムを用いればよい。ところが、接着剤として低アウトガス排出のゴムを用いると、接着剤として高耐光性のゴムを用いた場合と同じく、一括ダイシング工程において、スループットの低下、半導体素子のチッピング及びダイシングブレードの破損等の問題を引き起こす。これにより、固体撮像装置の歩留まりの低下を招来する。 Further, when an adhesive layer is selectively provided on the light receiving portion so as to form a cavity on the light receiving portion, an adhesive mainly composed of an epoxy resin or a silicone resin is used as an adhesive constituting the adhesive layer. Due to the thermal history of the subsequent manufacturing process and the heat generation of the drive circuit after mounting, outgas is generated from the adhesive layer and fills the cavity. When a light beam having a high power density (0.4 μW / μm 2 ) is received in this state, there arises a problem that outgas particles are deposited on the rear surface of the light-transmitting plate due to the optical tweezer effect and cause deterioration of image characteristics. In order to solve this, a low outgas discharge rubber may be used as an adhesive. However, when rubber with low outgassing is used as an adhesive, problems such as reduced throughput, chipping of semiconductor elements, and damage to the dicing blade, etc. in the batch dicing process, as in the case of using high light resistance rubber as the adhesive. cause. As a result, the yield of the solid-state imaging device is reduced.
　また、固体撮像素子に限らず、半導体素子と該半導体素子を実装する基板との接着においても、同様の問題が生じる。すなわち、半導体素子が形成されるシリコン基板と実装基板との間に接着剤を供給し、両基板に対して熱処理を行うことによりこれらを接着する際に、これらの熱膨張係数が異なるため、接着の際に各基板の応力の相違が生じる。各基板の熱膨張係数が大きく異なる場合、弾性率が低い接着剤を用いることにより各基板の応力を緩和できるが、その場合、一括ダイシング工程において前述の固体撮像素子と同様の問題が生じる。 Further, the same problem occurs not only in the solid-state imaging element but also in the adhesion between the semiconductor element and the substrate on which the semiconductor element is mounted. That is, when an adhesive is supplied between a silicon substrate on which a semiconductor element is to be formed and a mounting substrate and the two substrates are heat-treated to bond them, the thermal expansion coefficients thereof are different. In this case, a difference in stress occurs between the substrates. When the thermal expansion coefficients of the respective substrates are greatly different, the stress of each substrate can be relieved by using an adhesive having a low elastic modulus. However, in this case, the same problem as that of the above-described solid-state imaging device occurs in the collective dicing process.
　さらに、複数の薄い半導体基板を積層する際も、各半導体基板の反り量が積算されるため、緩衝材として弾性率が低い接着剤を塗布し、半導体基板同士の接着を行う。この場合も、一括ダイシング工程において前記の問題と同様の問題が生じる。 Furthermore, when laminating a plurality of thin semiconductor substrates, the amount of warpage of each semiconductor substrate is integrated, so an adhesive having a low elastic modulus is applied as a buffer material to bond the semiconductor substrates together. Also in this case, the same problem as the above problem occurs in the batch dicing process.
　本発明は、上記従来の問題点を解決し、電気特性及び画像特性に優れ、高信頼性で、且つ低コストで製造可能な半導体装置及びその製作方法を提供することである。 The present invention is to solve the above-mentioned conventional problems, and to provide a semiconductor device that is excellent in electrical characteristics and image characteristics, can be manufactured with high reliability and at low cost, and a manufacturing method thereof.
　本発明に係る第１の半導体装置は、半導体素子と、光学素子と、第１接着層と、第２接着層と、透光板とを備えている。光学素子は、半導体素子の主面に設けられている。第１接着層は、光学素子を覆っている。第２接着層は、第１接着層よりも硬度が大きく、半導体素子の主面における光学素子以外の部分の少なくとも一部分を覆っている。透光板は、第１接着層及び第２接着層を介して半導体素子に接着されている。 A first semiconductor device according to the present invention includes a semiconductor element, an optical element, a first adhesive layer, a second adhesive layer, and a translucent plate. The optical element is provided on the main surface of the semiconductor element. The first adhesive layer covers the optical element. The second adhesive layer has a hardness higher than that of the first adhesive layer and covers at least a part of a portion other than the optical element on the main surface of the semiconductor element. The translucent plate is bonded to the semiconductor element via the first adhesive layer and the second adhesive layer.
　半導体ウェハをダイシングしてこの第１の半導体装置を製造するとき、ダイシング工程では、第１接着層ではなく第２接着層を切断する。ここで、第２接着層は、第１接着層に比べて硬度が大きい。よって、ダイシング工程をスムーズに行うことができるので、ダイシング工程におけるスループットの低下、半導体素子のチッピング及びダイシングブレードの破損等の不具合を防止できる。 When manufacturing the first semiconductor device by dicing the semiconductor wafer, in the dicing process, the second adhesive layer is cut instead of the first adhesive layer. Here, the second adhesive layer has a higher hardness than the first adhesive layer. Therefore, since the dicing process can be performed smoothly, problems such as a decrease in throughput in the dicing process, chipping of semiconductor elements, and damage to the dicing blade can be prevented.
　後述の好ましい実施形態では、第２接着層の硬度は、ショアＤ硬度で６５以上である。 In a preferred embodiment described later, the hardness of the second adhesive layer is 65 or more in Shore D hardness.
　本発明に係る第１の半導体装置では、透光板は互いに反対側に位置する第１面と第２面とを有していれば良く、透光板の第１面及び第２面のうちの少なくとも一方の面の上には反射防止膜が設けられていることが好ましい。これにより、透光板の第１面又は第２面における光の反射を防止することができる。 In the first semiconductor device according to the present invention, the translucent plate only needs to have a first surface and a second surface located on opposite sides, and the first surface and the second surface of the translucent plate. An antireflection film is preferably provided on at least one of the surfaces. Thereby, reflection of the light in the 1st surface or 2nd surface of a translucent board can be prevented.
　本発明に係る第１の半導体装置では、第２接着層は黒色であることが好ましい。これにより、第２接着層は、入射された光を吸収することができる。 In the first semiconductor device according to the present invention, the second adhesive layer is preferably black. Thereby, the second adhesive layer can absorb the incident light.
　本発明に係る第１の半導体装置では、半導体素子と透光板との間には、第１接着層と第２接着層とが積層された領域が存在していることが好ましい。これにより、この領域においても透光板を半導体素子に強固に接着させることができる。 In the first semiconductor device according to the present invention, it is preferable that a region where the first adhesive layer and the second adhesive layer are stacked exists between the semiconductor element and the light transmitting plate. Thereby, the light-transmitting plate can be firmly adhered to the semiconductor element also in this region.
　本発明に係る第１の半導体装置では、第１接着層と第２接着層とは半導体素子の主面上において互いに間隔を開けて配置されていても良く、半導体素子の主面上における第１接着層と第２接着層との間にはスペーサが設けられていてもよい。これにより、第１接着層の厚みのバラツキを最小限に抑えることができる。 In the first semiconductor device according to the present invention, the first adhesive layer and the second adhesive layer may be spaced apart from each other on the main surface of the semiconductor element, and the first adhesive layer on the main surface of the semiconductor element. A spacer may be provided between the adhesive layer and the second adhesive layer. Thereby, the variation in the thickness of the first adhesive layer can be minimized.
　本発明に係る第１の半導体装置がスペーサを備えている場合には、半導体素子と透光板との間には、第１接着層とスペーサとが積層された領域が存在していることが好ましい。これにより、この領域においても透光板を半導体素子に強固に接着させることができる。 In the case where the first semiconductor device according to the present invention includes a spacer, a region where the first adhesive layer and the spacer are stacked exists between the semiconductor element and the light transmitting plate. preferable. Thereby, the light-transmitting plate can be firmly adhered to the semiconductor element also in this region.
　後述の好ましい実施形態では、第１の半導体装置は、電極と、貫通孔部と、貫通電極と、充填層と、絶縁層と、開口部と、外部電極とを備えている。電極は、半導体素子の主面における光学素子の外側に設けられており、貫通孔部は、電極に達するように半導体素子の厚さ方向に貫通しており、貫通電極は、電極と接しており、貫通孔部の内側面上から半導体素子の裏面上にまで延びている。充填層は、貫通電極を介して貫通孔部内に設けられている。絶縁層は、半導体素子の裏面上と半導体素子の裏面上における貫通電極の上とに設けられており、開口部は、絶縁層に形成され、半導体素子の裏面上における貫通電極を露出しており、外部電極は、開口部内に設けられており且つ貫通電極に接続されている。 In a preferred embodiment described later, the first semiconductor device includes an electrode, a through hole, a through electrode, a filling layer, an insulating layer, an opening, and an external electrode. The electrode is provided outside the optical element on the main surface of the semiconductor element, and the through hole penetrates in the thickness direction of the semiconductor element so as to reach the electrode, and the through electrode is in contact with the electrode , Extending from the inner surface of the through hole to the back surface of the semiconductor element. The filling layer is provided in the through hole portion through the through electrode. The insulating layer is provided on the back surface of the semiconductor element and on the through electrode on the back surface of the semiconductor element, and the opening is formed in the insulating layer to expose the through electrode on the back surface of the semiconductor element. The external electrode is provided in the opening and is connected to the through electrode.
　本発明に係る第２の半導体装置は、第１半導体素子と、第１半導体素子の主面に設けられた回路領域と、回路領域を覆う第１接着層と、第１半導体素子の主面における回路領域以外の部分の少なくとも一部分を覆い、第１接着層よりも硬度が大きい第２接着層と、第１接着層及び第２接着層を介して第１半導体素子に接着された第２半導体素子とを備えている。 A second semiconductor device according to the present invention includes a first semiconductor element, a circuit region provided on a main surface of the first semiconductor element, a first adhesive layer covering the circuit region, and a main surface of the first semiconductor element. A second adhesive layer covering at least a part of a portion other than the circuit region and having a hardness higher than that of the first adhesive layer; and a second semiconductor element bonded to the first semiconductor element via the first adhesive layer and the second adhesive layer And.
　本発明に係る半導体装置の第１の製造方法は、光学素子が主面に形成された半導体素子を準備する工程（ａ）と、第１接着剤で光学素子を覆う工程（ｂ）と、第１接着剤よりも硬化後の硬度が大きい第２接着剤で半導体素子の主面における光学素子以外の部分の少なくとも一部分を覆う工程（ｃ）と、第１接着剤からなる第１接着層及び第２接着剤からなる第２接着層を介して透光板を半導体素子に接着する工程（ｄ）とを備えている。 A first manufacturing method of a semiconductor device according to the present invention includes a step (a) of preparing a semiconductor element having an optical element formed on a main surface, a step (b) of covering the optical element with a first adhesive, A step (c) of covering at least a part of the main surface of the semiconductor element other than the optical element with a second adhesive having a hardness after curing that is higher than that of the first adhesive; a first adhesive layer made of the first adhesive; And a step (d) of adhering the translucent plate to the semiconductor element through a second adhesive layer made of two adhesives.
　ダイシング工程では、相対的に硬度が大きい第２接着層を切断する。よって、ダイシング工程をスムーズに行うことができるので、ダイシング工程におけるスループットの低下、半導体素子のチッピング及びダイシングブレードの破損等の不具合を防止できる。 In the dicing process, the second adhesive layer having a relatively high hardness is cut. Therefore, since the dicing process can be performed smoothly, problems such as a decrease in throughput in the dicing process, chipping of semiconductor elements, and damage to the dicing blade can be prevented.
　本発明に係る半導体装置の第１の製造方法では、工程（ｄ）では、半導体素子の主面に対向する第１面及び第１面とは反対側に位置する第２面のうちの少なくとも一方の面の上に反射防止膜が設けられた透光板を半導体素子に接着すればよい。これにより、反射防止膜の第１面又は第２面における光の反射を防止することができる。 In the first method for manufacturing a semiconductor device according to the present invention, in the step (d), at least one of a first surface facing the main surface of the semiconductor element and a second surface positioned on the opposite side of the first surface. A light-transmitting plate provided with an antireflection film on the surface may be bonded to the semiconductor element. Thereby, reflection of the light in the 1st surface or 2nd surface of an antireflection film can be prevented.
　本発明に係る半導体装置の第１の製造方法では、第２接着剤を黒色化させる工程（ｅ）を備えていればよい。これにより、第２接着層に入射された光が光学素子に到達することを防止できる。 In the first method for manufacturing a semiconductor device according to the present invention, it is only necessary to include the step (e) of blackening the second adhesive. Thereby, the light incident on the second adhesive layer can be prevented from reaching the optical element.
　本発明に係る半導体装置の第１の製造方法では、半導体素子の主面上における第１接着層と第２接着層との間にスペーサを設ける工程（ｆ）を備えていることが好ましい。これにより、厚さ方向における第１接着層のバラツキを最小限に抑えることができる。 The first method for manufacturing a semiconductor device according to the present invention preferably includes a step (f) of providing a spacer between the first adhesive layer and the second adhesive layer on the main surface of the semiconductor element. Thereby, the dispersion | variation in the 1st contact bonding layer in the thickness direction can be suppressed to the minimum.
　本発明に係る半導体装置の第１の製造方法が工程（ｆ）を備えている場合、工程（ｂ）及び工程（ｃ）を行う前に工程（ｆ）を行うことが好ましい。 When the first method for manufacturing a semiconductor device according to the present invention includes the step (f), it is preferable to perform the step (f) before performing the step (b) and the step (c).
　本発明に係る半導体装置の第１の製造方法では、工程（ｂ）の後であって工程（ｃ）の前に透光板を第１接着剤の上に配置する工程（ｇ）を備えていることが好ましく、工程（ｇ）では、第１接着剤の一部が透光板の下面をつたって透光板の下面の周縁部へ向かって流動する又は半導体素子の主面をつたって半導体素子の主面の周縁部へ向かって流動すればよい。これにより、半導体素子と透光板との間に、第１接着層と第２接着層とが互いに積層された領域を形成することができる。 The first manufacturing method of the semiconductor device according to the present invention includes a step (g) of disposing the light transmitting plate on the first adhesive after the step (b) and before the step (c). Preferably, in the step (g), a part of the first adhesive flows along the lower surface of the translucent plate toward the peripheral portion of the lower surface of the translucent plate, or passes through the main surface of the semiconductor element to form the semiconductor. What is necessary is just to flow toward the peripheral part of the main surface of an element. Thereby, the area | region where the 1st contact bonding layer and the 2nd contact bonding layer were mutually laminated | stacked can be formed between a semiconductor element and a translucent board.
　後述の好ましい実施形態では、工程（ａ）で準備する半導体素子の主面における光学素子の外側には、電極が設けられている。また、後述の好ましい実施形態では、本発明に係る半導体装置は、電極に達するように半導体素子の厚さ方向に貫通孔部を貫設させる工程と、電極に接するとともに貫通孔部の内側面上から半導体素子の裏面上にまで延びる貫通電極を形成する工程と、貫通孔部内に貫通電極を挟んで充填層を設ける工程と、半導体素子の裏面上と半導体素子の裏面上における貫通電極の上とに絶縁層を設ける工程と、半導体素子の裏面上における貫通電極が露出するように絶縁層に開口部を形成する工程と、外部電極を開口部内に設けて貫通電極に接続する工程とを備えている。 In a preferred embodiment described later, an electrode is provided outside the optical element on the main surface of the semiconductor element prepared in step (a). In a preferred embodiment described later, the semiconductor device according to the present invention includes a step of penetrating a through hole portion in the thickness direction of the semiconductor element so as to reach the electrode, and an inner surface of the through hole portion while being in contact with the electrode. Forming a through electrode extending from the semiconductor device to the back surface of the semiconductor element, providing a filling layer with the through electrode sandwiched in the through hole, and on the back surface of the semiconductor element and on the through electrode on the back surface of the semiconductor element A step of forming an insulating layer on the semiconductor element, a step of forming an opening in the insulating layer so that the through electrode on the back surface of the semiconductor element is exposed, and a step of providing an external electrode in the opening and connecting to the through electrode. Yes.
　本発明に係る半導体装置の第２の製造方法は、主面がダイシングラインにより複数の領域に区画されており、光学素子が領域のそれぞれに形成された半導体ウェハを準備する工程と、光学素子のそれぞれを第１接着剤で覆う工程と、第１接着剤よりも硬化後の硬度が大きい第２接着剤で半導体素子の主面における光学素子以外の部分の少なくとも一部分を覆う工程と、第１接着剤からなる第１接着層及び第２接着剤からなる第２接着層を介して透光板を半導体ウェハに接着する工程と、ダイシングラインに沿って半導体ウェハをダイシングする工程とを備えている。 A second manufacturing method of a semiconductor device according to the present invention includes a step of preparing a semiconductor wafer in which a main surface is divided into a plurality of regions by dicing lines and an optical element is formed in each of the regions, A step of covering each with a first adhesive, a step of covering at least a part of the main surface of the semiconductor element other than the optical element with a second adhesive having a hardness after curing that is higher than that of the first adhesive, and a first adhesive A step of bonding the translucent plate to the semiconductor wafer via a first adhesive layer made of an agent and a second adhesive layer made of a second adhesive, and a step of dicing the semiconductor wafer along a dicing line.
　ダイシング工程では、相対的に硬度が大きい第２接着層を切断する。よって、ダイシング工程をスムーズに行うことができるので、ダイシング工程におけるスループットの低下、半導体素子のチッピング及びダイシングブレードの破損等の不具合を防止できる。 In the dicing process, the second adhesive layer having a relatively high hardness is cut. Therefore, since the dicing process can be performed smoothly, problems such as a decrease in throughput in the dicing process, chipping of semiconductor elements, and damage to the dicing blade can be prevented.
　本発明では、電気特性及び画像特性に優れ、高信頼性で、低コストで製造可能な半導体装置を提供することができる。 The present invention can provide a semiconductor device that is excellent in electrical characteristics and image characteristics, is highly reliable, and can be manufactured at low cost.
図１は本発明の第一の実施形態に係る半導体装置の構造を示す断面図である。FIG. 1 is a sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention. 図２は本発明の第一の実施形態の第１の変形例に係る半導体装置の構造を示す拡大断面図である。FIG. 2 is an enlarged cross-sectional view showing the structure of the semiconductor device according to the first modification of the first embodiment of the present invention. 図３は本発明の第一の実施形態の第２の変形例に係る半導体装置の構造を示す断面図である。FIG. 3 is a sectional view showing a structure of a semiconductor device according to a second modification of the first embodiment of the present invention. 図４は本発明の第一の実施形態の第３の変形例に係る半導体装置の構造を示す拡大断面図である。FIG. 4 is an enlarged cross-sectional view showing the structure of the semiconductor device according to the third modification of the first embodiment of the present invention. 図５は本発明の第二の実施形態に係る半導体装置の構造を示す断面図である。FIG. 5 is a sectional view showing the structure of a semiconductor device according to the second embodiment of the present invention. 図６は本発明の第二の実施形態の変形例に係る半導体装置の構造を示す拡大断面図である。FIG. 6 is an enlarged cross-sectional view showing the structure of a semiconductor device according to a modification of the second embodiment of the present invention. 図７（ａ）～図７（ｄ）は本発明の第一の実施形態に係る半導体装置の製造方法を工程順に示す断面図である。7A to 7D are cross-sectional views showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps. 図８（ａ）～図８（ｃ）は本発明の第二の実施形態に係る半導体装置の製造方法を工程順に示す断面図である。8A to 8C are cross-sectional views showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps. 図９は本発明の第五の実施形態に係る半導体装置の構造を示す断面図である。FIG. 9 is a sectional view showing the structure of a semiconductor device according to the fifth embodiment of the present invention. 図１０は本発明の第五の実施形態に係る半導体装置の構造を示す断面図である。FIG. 10 is a sectional view showing the structure of a semiconductor device according to the fifth embodiment of the present invention. 図１１は本発明の第五の実施形態の一変形例に係る半導体装置の構造を示す断面図である。FIG. 11 is a cross-sectional view showing the structure of a semiconductor device according to a modification of the fifth embodiment of the present invention. 図１２（ａ）～図１２（ｃ）は本発明の第五の実施形態に係る半導体装置の製造方法を工程順に示す断面図である。12A to 12C are cross-sectional views showing a method of manufacturing a semiconductor device according to the fifth embodiment of the present invention in the order of steps. 図１３（ａ）～図１３（ｃ）は本発明の第五の実施形態の一変形例に係る半導体装置の製造方法を工程順に示す断面図である。FIG. 13A to FIG. 13C are cross-sectional views showing a method of manufacturing a semiconductor device according to a modification of the fifth embodiment of the present invention in the order of steps. 図１４は従来の固体撮像装置の構造を示す断面図である。FIG. 14 is a cross-sectional view showing the structure of a conventional solid-state imaging device.
　以下、図面を参照しながら本発明の実施形態を詳細に説明する。なお、本発明は、以下に示す実施形態に限定されない。また、以下では、同一の部材及び同一の機能を有する部材に対して同一の符号を付す場合がある。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited to embodiment shown below. Moreover, below, the same code | symbol may be attached | subjected with respect to the member which has the same member and the same function.
　（第一の実施形態）
　以下、本発明の第一の実施形態に係る半導体装置を説明する。図１は本実施形態に係る半導体装置１０の構造を示す断面図である。 (First embodiment)
The semiconductor device according to the first embodiment of the present invention will be described below. FIG. 1 is a cross-sectional view showing the structure of a semiconductor device 10 according to this embodiment.
　本実施形態に係る半導体装置１０は、半導体素子１１と、半導体素子１１の主面１１Ａに設けられた光学素子である受光部１２と、半導体素子１１の主面１１Ａにおける受光部１２の外側に設けられた周辺回路領域１３と、半導体素子１１の主面１１Ａにおける受光部１２の外側の上に設けられた電極１４と、第１接着層１５及び第２接着層１６を介して半導体素子１１に接着された透光板１７とを備えている。 The semiconductor device 10 according to this embodiment is provided on the outside of the semiconductor element 11, the light receiving unit 12 that is an optical element provided on the main surface 11 </ b> A of the semiconductor element 11, and the light receiving unit 12 on the main surface 11 </ b> A of the semiconductor element 11. Bonded to the semiconductor element 11 through the peripheral circuit region 13 formed, the electrode 14 provided on the outer surface of the light receiving portion 12 on the main surface 11A of the semiconductor element 11, and the first adhesive layer 15 and the second adhesive layer 16. The translucent plate 17 is provided.
　半導体素子１１は、例えば１００μｍ～３００μｍの厚みを有していればよい。なお、半導体素子１１の弾性率は、例えば１３０ＧＰａ～１９０ＧＰａである。 The semiconductor element 11 may have a thickness of 100 μm to 300 μm, for example. The elastic modulus of the semiconductor element 11 is, for example, 130 GPa to 190 GPa.
　受光部１２は、半導体素子１１の主面１１Ａの中央に形成されていることが好ましく、周辺回路領域１３は、受光部１２を囲むように半導体素子１１の主面１１Ａにおける受光部１２の外側に形成されている。受光部１２と周辺回路領域１３とは、互いに電気的に接続されており、図１に示すように互いに接触していることが好ましい。受光部１２は、本実施形態に係る半導体装置１０に入射された光（信号光）を検知して電気信号に変換してから周辺回路領域１３へ送信し、周辺回路領域１３は、受光部１２からの電気信号を処理する。 The light receiving portion 12 is preferably formed at the center of the main surface 11A of the semiconductor element 11, and the peripheral circuit region 13 is outside the light receiving portion 12 on the main surface 11A of the semiconductor element 11 so as to surround the light receiving portion 12. Is formed. The light receiving unit 12 and the peripheral circuit region 13 are electrically connected to each other, and are preferably in contact with each other as shown in FIG. The light receiving unit 12 detects light (signal light) incident on the semiconductor device 10 according to the present embodiment, converts the light into an electrical signal, and transmits the electric signal to the peripheral circuit region 13. The electrical signal from is processed.
　電極１４は、周辺回路領域１３に電気的に接続されており、図１に示すように周辺回路領域１３の上面に接触していることが好ましい。また、電極１４は、半導体素子１１の主面１１Ａ上では互いに間隔を開けて配置されていることが好ましい。このような電極１４は、一部分がＡｌ又はＣｕ等の金属薄膜で形成されていればよい。 The electrode 14 is electrically connected to the peripheral circuit region 13 and is preferably in contact with the upper surface of the peripheral circuit region 13 as shown in FIG. The electrodes 14 are preferably arranged on the main surface 11 </ b> A of the semiconductor element 11 so as to be spaced from each other. Such an electrode 14 should just be formed in part by metal thin films, such as Al or Cu.
　透光板１７は、信号光（例えば可視光）を透過できれば良く、例えば光学ガラスからなればよい。なお、透光板１７の弾性率は、例えば７０ＧＰａ～８０ＧＰａである。 The translucent plate 17 only needs to be able to transmit signal light (for example, visible light), and may be made of, for example, optical glass. The elastic modulus of the translucent plate 17 is, for example, 70 GPa to 80 GPa.
　では、第１接着層１５及び第２接着層１６について説明する。 Now, the first adhesive layer 15 and the second adhesive layer 16 will be described.
　第１接着層１５は、受光部１２を覆っている。一方、第２接着層１６は、半導体素子１１の主面１１Ａにおける受光部１２以外の部分を覆っており、半導体素子１１の主面１１Ａ上において第１接着層１５の外側に設けられているとともに第１接着層１５と接している。そのため、半導体ウェハをダイシングして本実施形態に係る半導体装置を製造する場合には、第１接着層１５ではなく第２接着層１６が切断されることとなる。 The first adhesive layer 15 covers the light receiving unit 12. On the other hand, the second adhesive layer 16 covers the main surface 11A of the semiconductor element 11 other than the light receiving portion 12, and is provided on the main surface 11A of the semiconductor element 11 outside the first adhesive layer 15. It is in contact with the first adhesive layer 15. Therefore, when the semiconductor device according to this embodiment is manufactured by dicing the semiconductor wafer, not the first adhesive layer 15 but the second adhesive layer 16 is cut.
　第１接着層１５は、受光部１２を覆っているため、信号光を透過可能な材料からなればよい。それだけでなく、第１接着層１５は、高耐光性で且つ熱硬化型のゴム接着剤からなることが好ましい。これにより、信号光がパワー密度が高い光線（例えば１Ｗ/ｃｍ３以上）であっても、第１接着層１５が変色及び収縮することを防止でき、また、光（波長が例えば４００ｎｍ）の透過率が８５％以上好ましくは９０％となるように第１接着層１５（厚みが例えば２ｍｍ）の材料を選択することが好ましい。このようなゴム接着剤としては、例えば、シリコーンゴム，ジメチルシリコーンゴム又はフェニルシリコーンゴム等を用いることが好ましい。なお、第１接着層１５の硬度は、ショアＤ硬度で５以上６５未満で、好ましくは１０以上４０以下である。別の言い方をすると、第１接着層１５の硬度は、８００ｋＰａ以上１５ＭＰａ未満で、好ましくは２ＭＰａ以上１０ＭＰａ以下の弾性率を有していればよい。 Since the first adhesive layer 15 covers the light receiving unit 12, it may be made of a material that can transmit signal light. In addition, the first adhesive layer 15 is preferably made of a highly light-resistant and thermosetting rubber adhesive. Thereby, even if the signal light is a light beam having a high power density (for example, 1 W / cm 3 or more), the first adhesive layer 15 can be prevented from being discolored and contracted, and light (wavelength is, for example, 400 nm) can be transmitted. It is preferable to select the material of the first adhesive layer 15 (thickness is, for example, 2 mm) so that the rate is 85% or more, preferably 90%. As such a rubber adhesive, it is preferable to use, for example, silicone rubber, dimethyl silicone rubber or phenyl silicone rubber. In addition, the hardness of the 1st contact bonding layer 15 is 5 or more and less than 65 in Shore D hardness, Preferably it is 10 or more and 40 or less. In other words, the hardness of the first adhesive layer 15 may be an elastic modulus of 800 kPa or more and less than 15 MPa, preferably 2 MPa or more and 10 MPa or less.
　第２接着層１６は、例えば、室温環境下（約２７℃）にてショアＤ硬度で６５以上の硬度を有していれば良く、別の言い方をすると、１５ＭＰａ以上の弾性率を有していればよい。第１接着層１５の硬度は室温環境下にてショアＤ硬度で５以上６５未満であるので、第２接着層１６は第１接着層１５よりも硬度が大きい。これにより、半導体ウェハに対するダイシングをスムーズに行うことができる。 For example, the second adhesive layer 16 only has to have a Shore D hardness of 65 or more in a room temperature environment (about 27 ° C.). In other words, the second adhesive layer 16 has an elastic modulus of 15 MPa or more. Just do it. Since the hardness of the first adhesive layer 15 is 5 or more and less than 65 in Shore D hardness in a room temperature environment, the second adhesive layer 16 is larger in hardness than the first adhesive layer 15. Thereby, dicing with respect to a semiconductor wafer can be performed smoothly.
　第２接着層１６は、第１接着層１５とは異なる主成分を含んでいてもよいし、第１接着層１５とは同一の主成分を含んでいてもよい。しかし、第２接着層１６は、第１接着層１５とは同一の主成分を含んでいることが好ましい。これにより、第１接着層１５に対する第２接着層１６の親和性を高めることができ、第２接着層１６に対する第１接着層１５の親和性を高めることができる。よって、第１接着層１５と第２接着層１６との界面において第１接着層１５と第２接着層１６とを互いに良好に接着させることができる。具体的には、第２接着層１６は、第１接着層１５の主成分に無機物質（例えばシリカ等）を混入することによりその硬度（又はその弾性率）が調整されたものであればよい。従って、ダイシングレーンにおける基板と透光板１７（ガラス）の硬度差が第２接着層１６によって緩和され切断しやすくなる。 The second adhesive layer 16 may contain a main component different from that of the first adhesive layer 15, or may contain the same main component as the first adhesive layer 15. However, the second adhesive layer 16 preferably includes the same main component as the first adhesive layer 15. Thereby, the affinity of the second adhesive layer 16 for the first adhesive layer 15 can be increased, and the affinity of the first adhesive layer 15 for the second adhesive layer 16 can be increased. Therefore, the first adhesive layer 15 and the second adhesive layer 16 can be satisfactorily bonded to each other at the interface between the first adhesive layer 15 and the second adhesive layer 16. Specifically, the second adhesive layer 16 only needs to have its hardness (or its elastic modulus) adjusted by mixing an inorganic substance (such as silica) into the main component of the first adhesive layer 15. . Therefore, the hardness difference between the substrate and the light transmitting plate 17 (glass) in the dicing lane is relaxed by the second adhesive layer 16 and is easily cut.
　第２接着層１６が第１接着層１５とは異なる主成分を含んでいる場合、例えば、第１接着層１５の主成分がシリコーンであるときには、第２接着層１６の主成分は、第１接着層１５の硬化を阻害しない成分であれば良く、好ましくはポリイミドである。 When the second adhesive layer 16 includes a main component different from the first adhesive layer 15, for example, when the main component of the first adhesive layer 15 is silicone, the main component of the second adhesive layer 16 is the first Any component that does not inhibit the curing of the adhesive layer 15 may be used, and polyimide is preferable.
　第２接着層１６は、可視光（λ＝３００ｎｍ～８００ｎｍ）領域において黒色であってもよい。第２接着層１６を黒色化するためには、第２接着層１６にカーボンを混入すればよい。混入するカーボンとしては、例えば、カーボンブラック、チャンネルブラック、ファーネスブラック、アセチレンブラック、サーマルブラック又はランブブラック等が挙げられる。カーボンブラックを選択した場合には、カーボンブラックの平均粒子径は、細かい方が好ましく、例えば１ｎｍ～９００ｎｍであることが好ましく、１ｎｍ～１００ｎｍ程度であればさらに好ましい。これにより、第２接着層１６は、入射された光を吸収することができる。よって、透光板１７の側面で反射して第２接着層１６に入射された光（迷光）が受光部１２に到達することを防止できる。 The second adhesive layer 16 may be black in the visible light (λ = 300 nm to 800 nm) region. In order to blacken the second adhesive layer 16, carbon may be mixed into the second adhesive layer 16. Examples of carbon to be mixed include carbon black, channel black, furnace black, acetylene black, thermal black, and lamp black. When carbon black is selected, the average particle diameter of carbon black is preferably finer, for example, preferably 1 nm to 900 nm, and more preferably about 1 nm to 100 nm. Thereby, the second adhesive layer 16 can absorb the incident light. Therefore, it is possible to prevent the light (stray light) that has been reflected from the side surface of the translucent plate 17 and entered the second adhesive layer 16 from reaching the light receiving unit 12.
　このような半導体装置は、さらに、貫通電極１８と、充填層１９と、絶縁層２０と、外部電極２１とを備えていることが好ましい。この場合には、半導体素子１１には、裏面１１Ｂから主面１１Ａへ貫通して電極１４に達する貫通孔（貫通孔部）１１ａが形成されていればよい。 Such a semiconductor device preferably further includes a through electrode 18, a filling layer 19, an insulating layer 20, and an external electrode 21. In this case, the semiconductor element 11 only needs to have a through-hole (through-hole portion) 11a that penetrates from the back surface 11B to the main surface 11A and reaches the electrode 14.
　貫通電極１８は、貫通孔１１ａのそれぞれの内側面上に設けられており、貫通孔１１ａのそれぞれの内部では電極１４と接している。これにより、貫通電極１８は、電極１４を介して周辺回路領域１３に電気的に接続される。また、貫通電極１８は、貫通孔１１ａのそれぞれの内側面上から半導体素子１１の裏面１１Ｂ上へ向かって延びている。このような貫通電極１８は、例えばＴｉ又はＣｕ等の金属からなる。 The through electrode 18 is provided on each inner surface of the through hole 11a, and is in contact with the electrode 14 inside each through hole 11a. As a result, the through electrode 18 is electrically connected to the peripheral circuit region 13 through the electrode 14. The through electrode 18 extends from the inner side surface of each through hole 11 a toward the back surface 11 </ b> B of the semiconductor element 11. Such a through electrode 18 is made of a metal such as Ti or Cu, for example.
　充填層１９は、各貫通電極１８を介して貫通孔１１ａ内に設けられており、樹脂（例えば、ポリイミド樹脂，シリコーン樹脂又はエポキシ樹脂）からなってもよいし、金属からなってもよい。充填層１９が貫通電極１８を構成する金属と同一の金属からなる場合には、貫通孔１１ａのそれぞれは貫通電極１８で満たされることとなる。 The filling layer 19 is provided in the through hole 11a via each through electrode 18, and may be made of resin (for example, polyimide resin, silicone resin or epoxy resin), or may be made of metal. When the filling layer 19 is made of the same metal as that of the through electrode 18, each of the through holes 11 a is filled with the through electrode 18.
　絶縁層２０は、半導体素子１１の裏面１１Ｂ上における貫通電極１８の上と半導体素子１１の裏面１１Ｂ上とに設けられており、感光性樹脂（例えば、ポリイミド樹脂，シリコーン樹脂又はエポキシ樹脂）からなることが好ましい。また、充填層１９と絶縁層２０とが同一の材料からなってもよい。この絶縁層２０には開口（開口部）２０ａが形成されており、これにより、半導体素子１１の裏面１１Ｂ上における貫通電極１８が露出する。 The insulating layer 20 is provided on the through electrode 18 on the back surface 11B of the semiconductor element 11 and on the back surface 11B of the semiconductor element 11, and is made of a photosensitive resin (for example, polyimide resin, silicone resin, or epoxy resin). It is preferable. Further, the filling layer 19 and the insulating layer 20 may be made of the same material. An opening (opening) 20 a is formed in the insulating layer 20, whereby the through electrode 18 on the back surface 11 </ b> B of the semiconductor element 11 is exposed.
　外部電極２１は、各開口２０ａ内に設けられており、各開口２０ａ内において貫通電極１８に接続されている。これにより、外部電極２１は貫通電極１８を介して電極１４に接続されている。よって、受光部１２で変換された電気信号を取り出すことができる。このような外部電極２１は、例えば、Ｓｎ－Ａｇ－Ｃｕ組成の鉛フリー半田材料からなればよい。 The external electrode 21 is provided in each opening 20a, and is connected to the through electrode 18 in each opening 20a. Thereby, the external electrode 21 is connected to the electrode 14 through the through electrode 18. Therefore, the electrical signal converted by the light receiving unit 12 can be taken out. Such an external electrode 21 may be made of, for example, a lead-free solder material having a Sn—Ag—Cu composition.
　以上説明したように、本実施形態に係る半導体装置１０では、受光部１２が第１接着層１５で覆われている。よって、受光部１２がパワー密度が高い光線（例えば１Ｗ/ｃｍ３以上）を受光した場合であっても、第１接着層１５が収縮及び変色することを防止できる。従って、本実施形態では、信頼性且つ性能（例えば画像特性）に優れた半導体装置１０を実現できる。 As described above, in the semiconductor device 10 according to this embodiment, the light receiving unit 12 is covered with the first adhesive layer 15. Therefore, even when the light receiving unit 12 receives a light beam having a high power density (for example, 1 W / cm 3 or more), the first adhesive layer 15 can be prevented from contracting and discoloring. Therefore, in the present embodiment, it is possible to realize the semiconductor device 10 having excellent reliability and performance (for example, image characteristics).
　また、本実施形態に係る半導体装置１０は、第２接着層１６においてダイシングが行われた結果、個片化されたものである。第２接着層１６は相対的に硬度が大きいため、ダイシングをスムーズに行うことができる。従って、ダイシング工程におけるスループットの低下、半導体素子のチッピング及びダイシングブレードの破損等を防止できる。これにより、本実施形態では、歩留まり良く且つ低コストで製造可能な半導体装置１０を実現できる。 In addition, the semiconductor device 10 according to the present embodiment is separated into pieces as a result of the dicing performed on the second adhesive layer 16. Since the second adhesive layer 16 has relatively high hardness, dicing can be performed smoothly. Accordingly, it is possible to prevent a decrease in throughput in the dicing process, chipping of semiconductor elements, breakage of the dicing blade, and the like. Thereby, in this embodiment, the semiconductor device 10 that can be manufactured with a high yield and a low cost can be realized.
　さらに、本実施形態に係る半導体装置１０では、透光板１７が受光部１２に直接貼り合わせられている。よって、本実施形態では、小型且つ低背な半導体装置を実現できる。 Furthermore, in the semiconductor device 10 according to the present embodiment, the light transmitting plate 17 is directly bonded to the light receiving unit 12. Therefore, in this embodiment, a small and low-profile semiconductor device can be realized.
　以上のことから、本実施形態では、信頼性且つ性能に優れ、小型且つ低背な半導体装置を歩留まり良く且つ低コストで製造することができる。 From the above, in this embodiment, a small and low-profile semiconductor device with excellent reliability and performance can be manufactured with high yield and low cost.
　本実施形態に係る半導体装置は、第１～第３の変形例に示す構成を有していてもよい。 The semiconductor device according to this embodiment may have the configuration shown in the first to third modifications.
　（第１の変形例）
　図２は、本実施形態の第１の変形例に係る半導体装置３０の拡大断面図である。 (First modification)
FIG. 2 is an enlarged cross-sectional view of a semiconductor device 30 according to a first modification of the present embodiment.
　第２接着層１６が無機物質（例えばシリカ）を含んでいると、第２接着層１６と半導体素子１１及び透光板１７との界面での接着強度が小さくなる場合があり、その結果、透光板１７を半導体素子１１に強固に接着できない場合がある。そこで、本変形例における半導体素子１１と透光板１７との間には、第１接着層３５と第２接着層３６とが互いに積層された領域Ａ３が存在している。これにより、本変形例では、領域Ａ３においても透光板１７は第１接着層３５を介して半導体素子１１に接着される。よって、第一の実施形態に比べて、透光板１７を半導体素子１１に強固に接着することができる。 If the second adhesive layer 16 contains an inorganic substance (for example, silica), the adhesive strength at the interface between the second adhesive layer 16 and the semiconductor element 11 and the light transmitting plate 17 may be reduced. In some cases, the optical plate 17 cannot be firmly bonded to the semiconductor element 11. Therefore, a region A3 in which the first adhesive layer 35 and the second adhesive layer 36 are laminated is present between the semiconductor element 11 and the light transmitting plate 17 in the present modification. Thereby, in this modification, the translucent plate 17 is bonded to the semiconductor element 11 via the first adhesive layer 35 also in the region A3. Therefore, the translucent plate 17 can be firmly bonded to the semiconductor element 11 as compared with the first embodiment.
　具体的には、半導体素子１１と透光板１７との間には、第１接着層３５からなる領域Ａ１と、第２接着層３６からなる領域Ｂと、第１接着層３５と第２接着層３６とが互いに積層された領域Ａ３とが存在している。領域Ａ１は受光部１２の上に位置しており、領域Ａ２は半導体素子１１の主面１１Ａの周縁部の上に位置しており、領域Ａ３は半導体素子１１の主面１１Ａ上において領域Ａ１と領域Ａ２とで挟まれている。 Specifically, between the semiconductor element 11 and the translucent plate 17, a region A1 composed of the first adhesive layer 35, a region B composed of the second adhesive layer 36, and the first adhesive layer 35 and the second adhesive. There is a region A3 in which the layer 36 is laminated with each other. The region A1 is located on the light receiving portion 12, the region A2 is located on the peripheral portion of the main surface 11A of the semiconductor element 11, and the region A3 is separated from the region A1 on the main surface 11A of the semiconductor element 11. It is sandwiched between the area A2.
　領域Ａ１を構成する第１接着層３５は、第一の実施形態における第１接着層１５に相当する。そのため、本変形例における第１接着層３５は、第一の実施形態における第１接着層１５に、領域Ａ３における第１接着層３５が接続されたものである。 The first adhesive layer 35 constituting the region A1 corresponds to the first adhesive layer 15 in the first embodiment. Therefore, the first adhesive layer 35 in the present modification is obtained by connecting the first adhesive layer 35 in the region A3 to the first adhesive layer 15 in the first embodiment.
　領域Ａ３では、半導体素子１１から透光板１７へ向かう方向において、第２接着層３６及び第１接着層３５の順に積層されていても良く、第１接着層３５及び第２接着層３６の順に積層されていても良く、第１接着層３５、第２接着層３６及び第１接着層３５の順に積層されていてもよい。なお、半導体装置の製造のし易さを考慮すると、領域Ａ３では、半導体素子１１から透光板１７へ向かう方向において第２接着層３６及び第１接着層３５の順に積層されていることが好ましい。 In the region A3, the second adhesive layer 36 and the first adhesive layer 35 may be stacked in this order in the direction from the semiconductor element 11 to the light transmitting plate 17, and the first adhesive layer 35 and the second adhesive layer 36 may be stacked in this order. The first adhesive layer 35, the second adhesive layer 36, and the first adhesive layer 35 may be stacked in this order. In consideration of the ease of manufacturing the semiconductor device, in the region A3, the second adhesive layer 36 and the first adhesive layer 35 are preferably stacked in this order in the direction from the semiconductor element 11 to the light transmitting plate 17. .
　（第２の変形例）
　図３は、本実施形態の第２の変形例に係る半導体装置４０の断面図である。 (Second modification)
FIG. 3 is a cross-sectional view of a semiconductor device 40 according to a second modification of the present embodiment.
　本変形例では、透光板１７の主面（第２面）１７Ａ及び裏面（第１面）１７Ｂには反射防止膜４１が形成されている。これにより、透光板１７の主面１７Ａ及び裏面１７Ｂにおける光の反射を防止することができる。よって、信号光は、透光板１７の主面１７Ａ及び裏面１７Ｂにおいて反射されることなく受光部１２へ入射されるため、強度低下を伴うことなく受光部１２へ入射される。従って、性能に優れた半導体装置を実現できる。 In this modification, an antireflection film 41 is formed on the main surface (second surface) 17A and the back surface (first surface) 17B of the translucent plate 17. Thereby, reflection of the light in the main surface 17A and the back surface 17B of the translucent plate 17 can be prevented. Therefore, since the signal light is incident on the light receiving unit 12 without being reflected on the main surface 17A and the back surface 17B of the translucent plate 17, the signal light is incident on the light receiving unit 12 without a decrease in intensity. Therefore, a semiconductor device with excellent performance can be realized.
　また、迷光が第２接着層１６と透光板１７との界面において反射して受光部１２へ到達することを防止できる。よって、画像特性の劣化が防止された半導体装置を実現できる。 Further, stray light can be prevented from being reflected at the interface between the second adhesive layer 16 and the translucent plate 17 and reaching the light receiving unit 12. Therefore, a semiconductor device in which deterioration of image characteristics is prevented can be realized.
　反射防止膜４１は、例えば、Ａｌ２Ｏ３，Ｎｂ２Ｏ５，ＳｉＯ２，Ｔａ２Ｏ５，ＴｉＯ２，Ｙ２Ｏ３及びＺｒＯ２等を用いて屈折率が互いに異なる複数の膜が交互に積層された構造とすることが好ましい。 The antireflection film 41 is composed of, for example, Al 2 O 3 , Nb 2 O 5 , SiO 2 , Ta 2 O 5 , TiO 2 , Y 2 O 3, ZrO 2, etc. It is preferable to have a laminated structure.
　透光板１７の主面１７Ａ及び裏面１７Ｂにおける光の反射を防止するという効果を有効に得るためには、反射防止膜４１は透光板１７の主面１７Ａ及び裏面１７Ｂに形成されていることが好ましい。しかし、反射防止膜４１が透光板１７の主面１７Ａ及び裏面１７Ｂのどちらか一方の面の上に形成されていれば、反射防止膜４１が透光板１７の主面１７Ａ及び裏面１７Ｂの両面上に形成されていない場合（第一の実施形態）に比べて、透光板１７の主面１７Ａ及び裏面１７Ｂにおける光の反射を防止できる。 In order to effectively obtain the effect of preventing light reflection on the main surface 17A and the back surface 17B of the light transmitting plate 17, the antireflection film 41 is formed on the main surface 17A and the back surface 17B of the light transmitting plate 17. Is preferred. However, if the antireflection film 41 is formed on one of the main surface 17A and the back surface 17B of the translucent plate 17, the antireflection film 41 is formed on the main surface 17A and the back surface 17B of the translucent plate 17. Compared to the case where the light is not formed on both surfaces (first embodiment), reflection of light on the main surface 17A and the back surface 17B of the translucent plate 17 can be prevented.
　（第３の変形例）
　図４は、本実施形態の第３の変形例に係る半導体装置５０の拡大断面図である。 (Third Modification)
FIG. 4 is an enlarged cross-sectional view of a semiconductor device 50 according to a third modification of the present embodiment.
　本変形例は、第１の変形例と第２の変形例とが組み合わさったものである。具体的には、反射防止膜４１が透光板１７の主面１７Ａ及び裏面１７Ｂ上に形成されており、半導体素子１１と透光板１７との間には領域Ａ３（領域Ａ３では第１接着層１５と第２接着層１６とが互いに積層されている）が存在している。これにより、本変形例では、第１の変形例で得られる効果と第２の変形例で得られる効果との両方を得ることができる。 This modification is a combination of the first modification and the second modification. Specifically, the antireflection film 41 is formed on the main surface 17A and the back surface 17B of the translucent plate 17, and the region A3 (first adhesive in the region A3) is provided between the semiconductor element 11 and the translucent plate 17. Layer 15 and second adhesive layer 16 are laminated to each other). Thereby, in this modification, both the effect obtained in the first modification and the effect obtained in the second modification can be obtained.
　（第二の実施形態）
　以下、本発明の第二の実施形態に係る半導体装置を説明する。図５は、本実施形態に係る半導体装置６０の構造を示す断面図である。本実施形態に係る半導体装置６０は、上記第一の実施形態に係る半導体装置１０にスペーサ６１が設けられたものである。以下では、上記第一の実施形態との相違点を中心に説明する。 (Second embodiment)
The semiconductor device according to the second embodiment of the present invention will be described below. FIG. 5 is a cross-sectional view showing the structure of the semiconductor device 60 according to this embodiment. In the semiconductor device 60 according to the present embodiment, a spacer 61 is provided in the semiconductor device 10 according to the first embodiment. Below, it demonstrates centering on difference with said 1st embodiment.
　本実施形態では、第１接着層１５と第２接着層１６とは、半導体素子１１の主面１１Ａ上において互いに間隔を開けて配置されている。スペーサ６１は、半導体素子１１の主面１１Ａにおける第１接着層１５と第２接着層１６との間に設けられている。 In the present embodiment, the first adhesive layer 15 and the second adhesive layer 16 are arranged on the main surface 11A of the semiconductor element 11 with a space therebetween. The spacer 61 is provided between the first adhesive layer 15 and the second adhesive layer 16 on the main surface 11 </ b> A of the semiconductor element 11.
　スペーサ６１は、例えば、３０μｍ～３００μｍの幅を有していれば良く、ポリイミド樹脂又はエポキシ樹脂からなることが好ましい。 The spacer 61 may have a width of 30 μm to 300 μm, for example, and is preferably made of polyimide resin or epoxy resin.
　このように本実施形態に係る半導体装置６０はスペーサ６１を備えているので、本実施形態では上記第一の実施形態において得られた効果に加えて次に示す効果を得ることができる。 As described above, since the semiconductor device 60 according to the present embodiment includes the spacer 61, in the present embodiment, the following effects can be obtained in addition to the effects obtained in the first embodiment.
　透光板１７はスペーサ６１に支持される。そのため、第１接着層１５と第２接着層１６とを介して透光板１７を半導体素子１１に接着する際に、高さ方向（厚さ方向）における透光板１７と半導体素子１１とのアライメントを容易に行うことができる。 The translucent plate 17 is supported by the spacer 61. Therefore, when the translucent plate 17 is bonded to the semiconductor element 11 via the first adhesive layer 15 and the second adhesive layer 16, the translucent plate 17 and the semiconductor element 11 in the height direction (thickness direction) Alignment can be performed easily.
　また、第１接着層１５の厚みのバラツキを最小限に抑えることができるので、第１接着層１５に入射した光の光路長差を最小限に抑えることができる。よって、各画素における結像のバラツキを防止することができる。 In addition, since the variation in the thickness of the first adhesive layer 15 can be minimized, the optical path length difference of the light incident on the first adhesive layer 15 can be minimized. Therefore, variations in image formation at each pixel can be prevented.
　なお、本実施形態は、次に示す構成を有していてもよい。 Note that the present embodiment may have the following configuration.
　スペーサ６１は、反射防止機能を有する材料をコーティング（例えばポーラスシリコン又はＡｌ２Ｏ３，Ｎｂ２Ｏ５，ＳｉＯ２，Ｔａ２Ｏ５，ＴｉＯ２，Ｙ２Ｏ３及びＺｒＯ２等を用いて屈折率が複数の異なる膜を積層）してもよい。これにより、透光板１７の側面で反射した光（迷光）がスペーサ６１の上面で反射することを防止できる。よって、この迷光が透光板１７の裏面１７Ｂで反射してから受光部１２に到達することを防止できる。 The spacer 61 is refracted by coating a material having an antireflection function using, for example, porous silicon or Al 2 O 3 , Nb 2 O 5 , SiO 2 , Ta 2 O 5 , TiO 2 , Y 2 O 3 and ZrO 2. A plurality of films having different rates may be stacked). Thereby, it is possible to prevent the light (stray light) reflected from the side surface of the translucent plate 17 from being reflected from the upper surface of the spacer 61. Therefore, the stray light can be prevented from reaching the light receiving unit 12 after being reflected by the back surface 17B of the translucent plate 17.
　本実施形態に係る半導体装置は、以下の変形例に示す構成を有していてもよい。 The semiconductor device according to this embodiment may have a configuration shown in the following modification.
　（変形例）
　図６は、上記第二の実施形態の変形例に係る半導体装置７０の拡大断面図である。 (Modification)
FIG. 6 is an enlarged cross-sectional view of a semiconductor device 70 according to a modification of the second embodiment.
　上記第二の実施形態では、スペーサ６１が第１接着層１５及び第２接着層１６に比べて接着能に劣るため、スペーサ６１が設けられた部分における半導体素子１１と透光板１７との接続強度を確保することは難しい。そこで、本変形例では、半導体素子１１と透光板１７との間には、第１接着層３５とスペーサ６１とが互いに積層された領域Ａ４が存在している。これにより、本変形例では、領域Ａ４においても透光板１７は第１接着層３５を介して半導体素子１１に接着される。よって、第二の実施形態に比べて、透光板１７を半導体素子１１に強固に接着することができる。 In the second embodiment, since the spacer 61 is inferior to the first adhesive layer 15 and the second adhesive layer 16 in the adhesive ability, the connection between the semiconductor element 11 and the translucent plate 17 in the portion where the spacer 61 is provided. It is difficult to ensure strength. Therefore, in this modification, a region A4 where the first adhesive layer 35 and the spacer 61 are laminated is present between the semiconductor element 11 and the light transmitting plate 17. Thereby, in this modification, the translucent plate 17 is bonded to the semiconductor element 11 via the first adhesive layer 35 also in the region A4. Therefore, the translucent plate 17 can be firmly bonded to the semiconductor element 11 as compared with the second embodiment.
　領域Ａ４では、半導体素子１１から透光板１７へ向かう方向において、スペーサ６１及び第１接着層３５の順に積層されていても良く、第１接着層３５及びスペーサ６１の順に積層されていても良く、第１接着層３５、スペーサ６１及び第１接着層３５の順に積層されていてもよい。なお、半導体装置の製造のし易さを考慮すると、領域Ａ４では、半導体素子１１から透光板１７へ向かう方向においてスペーサ６１及び第１接着層３５の順に積層されていることが好ましい。 In the region A4, the spacer 61 and the first adhesive layer 35 may be stacked in this order in the direction from the semiconductor element 11 to the translucent plate 17, or the first adhesive layer 35 and the spacer 61 may be stacked in this order. The first adhesive layer 35, the spacer 61, and the first adhesive layer 35 may be stacked in this order. In consideration of the ease of manufacturing the semiconductor device, in the region A4, the spacer 61 and the first adhesive layer 35 are preferably stacked in this order in the direction from the semiconductor element 11 to the light transmitting plate 17.
　（第三の実施形態）
　本発明の第三の実施形態では、上記第一の実施形態に係る半導体装置１０の製造方法を説明する。図７（ａ）～（ｄ）は、上記第一の実施形態に係る半導体装置１０の製造方法を工程順に説明する断面図である。 (Third embodiment)
In the third embodiment of the present invention, a method for manufacturing the semiconductor device 10 according to the first embodiment will be described. 7A to 7D are cross-sectional views illustrating the method for manufacturing the semiconductor device 10 according to the first embodiment in the order of steps.
　まず、主面１１１ＡがスクライブラインＬにより複数の領域（図７（ａ）では２つの領域）１１０に区画された半導体ウェハ１１１を準備する。各領域１１０には受光部１２と周辺回路領域１３とが形成されており、各領域１１０の上には電極１４が設けられている。 First, a semiconductor wafer 111 having a main surface 111A partitioned into a plurality of regions (two regions in FIG. 7A) 110 by a scribe line L is prepared. In each region 110, a light receiving portion 12 and a peripheral circuit region 13 are formed, and an electrode 14 is provided on each region 110.
　次に、例えばディスペンス法、スピンコート法又は印刷充填法等により、好ましくはディスペンス法により、第１接着剤１１５で各領域１１０内の受光部１２を覆う。 Next, the light receiving portion 12 in each region 110 is covered with the first adhesive 115 by, for example, a dispensing method, a spin coating method, a printing filling method, or the like, preferably by a dispensing method.
　ディスペンス法で第１接着剤１１５を塗布するときには、次に示す方法に従って第１接着剤１１５を塗布すればよい。 When applying the first adhesive 115 by the dispensing method, the first adhesive 115 may be applied according to the following method.
　まず、例えばドライフィルム貼り付け法又はスピンコート法を用いて、感光性の液状レジスト（不図示）を主面１１１Ａ全体に塗布する。なお、レジストの厚さは、第１接着層１５の厚さに応じて決めれば良く、１０μｍ～３５μｍ程度であればよい。 First, a photosensitive liquid resist (not shown) is applied to the entire main surface 111A by using, for example, a dry film attaching method or a spin coating method. The thickness of the resist may be determined according to the thickness of the first adhesive layer 15 and may be about 10 μm to 35 μm.
　次に、フォトリソグラフィ技術による露光及び現像により、受光部１２のみが露出するようにそのレジストをパターンニングする。これにより、図７（ａ）に示すように、レジスト７１には、受光部１２のそれぞれを露出する開口７１ａが形成される。 Next, the resist is patterned so that only the light receiving portion 12 is exposed by exposure and development using a photolithography technique. As a result, as shown in FIG. 7A, the resist 71 is formed with an opening 71 a that exposes each of the light receiving portions 12.
　続いて、ディスペンス法を用いて、第１接着剤１１５をレジスト７１の開口７１ａ内に充填する。第１接着剤１１５の充填量は、レジスト７１の開口７１ａの容積に応じて適宜決定すればよい。このとき、第１接着剤１１５がレジスト７１の開口７１ａの側壁により支持されるので、硬化前の第１接着剤１１５の形状を保持することができる。 Subsequently, the first adhesive 115 is filled into the opening 71a of the resist 71 using a dispensing method. The filling amount of the first adhesive 115 may be appropriately determined according to the volume of the opening 71 a of the resist 71. At this time, since the first adhesive 115 is supported by the side wall of the opening 71a of the resist 71, the shape of the first adhesive 115 before curing can be maintained.
　なお、レジスト７１を形成することなくディスペンス法により第１接着剤１１５を塗布してもよいが、硬化前の第１接着剤１１５の形状を保持することは難しい。そのため、レジスト７１の開口７１ａ内に第１接着剤１１５を充填させる方が好ましい。 Although the first adhesive 115 may be applied by a dispensing method without forming the resist 71, it is difficult to maintain the shape of the first adhesive 115 before being cured. Therefore, it is preferable to fill the first adhesive 115 in the opening 71 a of the resist 71.
　スピンコート法で第１接着剤１１５を塗布するときには、次に示す方法に従って第１接着剤１１５を塗布すればよい。 When applying the first adhesive 115 by spin coating, the first adhesive 115 may be applied according to the following method.
　まず、ディスペンス法と同様に、レジスト７１を半導体ウェハ１１１の主面１１１Ａ上に形成する。 First, similarly to the dispensing method, a resist 71 is formed on the main surface 111A of the semiconductor wafer 111.
　次に、スピンコート法を用いて、半導体ウェハ１１１の主面１１１Ａ上及びレジスト７１上に第１接着剤１１５を塗布する。このとき、レジスト７１上に堆積された第１接着剤１１５はスピンコートの遠心力で除去される。スピンコートの回転数及び時間は、レジスト７１の開口７１ａへの第１接着剤１１５の充填度と、レジスト７１上に堆積された第１接着剤１１５の除去性とで、適宜変更すればよい。 Next, the first adhesive 115 is applied on the main surface 111A of the semiconductor wafer 111 and the resist 71 by using a spin coating method. At this time, the first adhesive 115 deposited on the resist 71 is removed by spin coating centrifugal force. The rotational speed and time of spin coating may be appropriately changed depending on the degree of filling of the first adhesive 115 into the opening 71a of the resist 71 and the removability of the first adhesive 115 deposited on the resist 71.
　このようにして第１接着剤１１５で各受光部１２を被覆したら、透光板１１７を準備する。図７（ｂ）に示すように、第１接着剤１１５を介して半導体ウェハ１１１と透光板１１７とを貼り合わせる。その後、熱処理を行って第１接着剤１１５を硬化させる。これにより、受光部１２のそれぞれの上に第１接着層１５が形成されるとともに、透光板１１７が半導体ウェハ１１１に接着される。 When the respective light receiving portions 12 are covered with the first adhesive 115 in this way, a light transmitting plate 117 is prepared. As shown in FIG. 7B, the semiconductor wafer 111 and the translucent plate 117 are bonded together with the first adhesive 115 interposed therebetween. Thereafter, heat treatment is performed to cure the first adhesive 115. Thereby, the first adhesive layer 15 is formed on each of the light receiving portions 12, and the translucent plate 117 is bonded to the semiconductor wafer 111.
　このとき、透光板として主面及び裏面の少なくとも一方の面に反射防止膜が形成された透光板を準備すれば、図３に示す半導体装置が作製される。 At this time, if a light-transmitting plate having an antireflection film formed on at least one of the main surface and the back surface is prepared as the light-transmitting plate, the semiconductor device shown in FIG. 3 is manufactured.
　また、加圧した状態で半導体ウェハ１１１と透光板１１７とを貼り合わせれば、第１接着剤１１５の一部分がレジスト７１の開口７１ａ内から透光板１１７の裏面１１７Ｂをつたって開口７１ａの外へ染み出し、よって、図２に示す半導体装置が作製される。 Further, if the semiconductor wafer 111 and the light transmitting plate 117 are bonded together in a pressurized state, a part of the first adhesive 115 extends from the inside of the opening 71a of the resist 71 to the back surface 117B of the light transmitting plate 117 and outside the opening 71a. Thus, the semiconductor device shown in FIG. 2 is manufactured.
　続いて、レジスト７１を剥離剤で除去してから、半導体素子１１と透光板１１７との空洞部（レジスト７１が設けられていた部分）内に第２接着剤を充填させる。毛細血管現象を利用して第２接着剤を上記空洞部内に充填させるので、第２接着剤は低粘度であることが望ましい。また、上記空洞部への第２接着剤の浸透率を向上させるために、真空状態（１０－１Ｐａ～１０Ｐａ）で第２接着剤を上記空洞部に充填させてもよい。上記空洞部への充填が終了したら、熱処理を行う。これにより、第２接着剤が硬化して、第２接着層１６が各領域１１０内における第１接着層１５の外側に形成される。 Subsequently, after removing the resist 71 with a release agent, the second adhesive is filled in the cavity (the portion where the resist 71 is provided) between the semiconductor element 11 and the light transmitting plate 117. Since the second adhesive is filled into the cavity using the capillary phenomenon, it is desirable that the second adhesive has a low viscosity. Further, in order to improve the penetration rate of the second adhesive into the cavity, the second adhesive may be filled in the cavity in a vacuum state (10 −1 Pa to 10 Pa). When the filling of the cavity is completed, heat treatment is performed. As a result, the second adhesive is cured, and the second adhesive layer 16 is formed outside the first adhesive layer 15 in each region 110.
　続いて、厚さが所望の値（一般に、１００μｍ～３００μｍ程度）となるように半導体ウェハ１１１をバックグラインドする。更に、半導体ウェハ１１１の裏面１１１Ｂに対して、ＣＭＰ（chemical mechanical polishing ）等の鏡面処理を施しておくことが望ましい。 Subsequently, the semiconductor wafer 111 is back-ground so that the thickness becomes a desired value (generally, about 100 μm to 300 μm). Furthermore, it is desirable that the back surface 111B of the semiconductor wafer 111 be subjected to a mirror surface treatment such as CMP (chemical mechanical polishing).
　続いて、半導体ウェハ１１１に貫通孔１１ａを形成する。具体的には、レジスト、ＳｉＯ２膜又は金属膜等のマスク（不図示）を半導体ウェハ１１１の裏面１１１Ｂの上に形成する。このとき、このマスクのうち電極１４と対向する部分には、開口（不図示）が形成されている。その後、ドライエッチング又はウエットエッチング等を行う。すると、貫通孔１１ａが、半導体ウェハ１１１の裏面１１１Ｂから電極１４の下面に達するように形成される。 Subsequently, a through hole 11 a is formed in the semiconductor wafer 111. Specifically, a mask (not shown) such as a resist, a SiO 2 film, or a metal film is formed on the back surface 111B of the semiconductor wafer 111. At this time, an opening (not shown) is formed in a portion of the mask facing the electrode 14. Thereafter, dry etching or wet etching is performed. Then, the through hole 11 a is formed so as to reach the lower surface of the electrode 14 from the back surface 111 </ b> B of the semiconductor wafer 111.
　続いて、ＣＶＤ（chemical vapor deposition）法又は絶縁ペーストの印刷充填法等を用いて、半導体ウェハ１１１の裏面１１１Ｂ全体、半導体ウェハ１１１の表面のうち受光部１２と周辺回路領域１３の一部とを除く部分及び各貫通孔１１ａの内部にＳｉＯ２等の絶縁膜（不図示。なお、この絶縁膜は図１にも不図示）を形成する。その後、ドライエッチング又はウェットエッチングを行って、電極１４の下面上に形成された絶縁膜を除去する。 Subsequently, by using a chemical vapor deposition (CVD) method or a printing filling method of an insulating paste, the entire back surface 111B of the semiconductor wafer 111 and the light receiving unit 12 and a part of the peripheral circuit region 13 in the surface of the semiconductor wafer 111 are formed. An insulating film such as SiO 2 (not shown. This insulating film is not shown in FIG. 1) is formed in the removed portion and inside each through hole 11a. Thereafter, dry etching or wet etching is performed to remove the insulating film formed on the lower surface of the electrode 14.
　続いて、半導体ウェハ１１１に貫通電極１８を形成する。具体的には、まず、スパッタ法等を用いて、半導体ウェハ１１１の表面全体に金属薄膜（不図示）を形成する。金属薄膜としては、例えば、Ｔｉ膜、ＴｉＷ膜、Ｃｒ膜又はＣｕ膜等を用いればよい。次に、ドライフィルム貼り付け又はスピンコートにより感光性の液状レジストを金属薄膜に塗布した後、フォトリソグラフィ技術による露光及び現像によりそのレジストをパターニングする。なお、レジストの厚さは、最終的に形成したい貫通電極１８の厚さに応じて決定すれば良く、一般には、５μｍ～３０μｍ程度とすればよい。そして、電解めっきを行うと、金属薄膜のうちレジストで被覆されていない部分にＣｕ等の金属が析出する。これにより、貫通電極１８が形成される。 Subsequently, the through electrode 18 is formed in the semiconductor wafer 111. Specifically, first, a metal thin film (not shown) is formed on the entire surface of the semiconductor wafer 111 using a sputtering method or the like. For example, a Ti film, a TiW film, a Cr film, or a Cu film may be used as the metal thin film. Next, after applying a photosensitive liquid resist to the metal thin film by applying a dry film or by spin coating, the resist is patterned by exposure and development using a photolithography technique. Note that the thickness of the resist may be determined according to the thickness of the through electrode 18 to be finally formed, and is generally about 5 μm to 30 μm. When electrolytic plating is performed, a metal such as Cu is deposited on a portion of the metal thin film that is not covered with the resist. Thereby, the through electrode 18 is formed.
　続いて、貫通孔１１ａ内に充填層１９を形成する。充填材料として樹脂を用いる場合には、スピンコートにより液状の光硬化型樹脂又は液状の熱硬化型の樹脂を貫通孔１１ａ内に充填してもよいし、印刷充填法又はディッピング等により樹脂ペーストを貫通孔１１ａ内に充填してもよい。 Subsequently, a filling layer 19 is formed in the through hole 11a. When a resin is used as the filling material, a liquid photocurable resin or a liquid thermosetting resin may be filled into the through holes 11a by spin coating, or a resin paste may be filled by a printing filling method or dipping. The through hole 11a may be filled.
　充填材料として金属を用いる場合には、電解めっき法を用いて金属を貫通孔１１ａ内に充填してもよいし、印刷充填法又はディッピング法等を用いて主に金属ペーストを貫通孔１１ａ内に充填してもよい。 When a metal is used as the filling material, the metal may be filled into the through-hole 11a using an electrolytic plating method, or a metal paste may be filled mainly into the through-hole 11a using a printing filling method or a dipping method. It may be filled.
　電解めっき法により金属を貫通孔１１ａ内に充填する場合には、貫通電極１８と充填層１９とを同時に形成してもよいし、貫通電極１８を形成してから充填層１９を形成してもよい。前者の場合には、金属で貫通孔１１ａを完全に埋め込めばよい。後者の場合には、貫通電極１８を形成してから、貫通孔１１ａのみを露出するマスクを半導体ウェハ１１１の裏面１１１Ｂ上に形成し、電解めっき法により金属で貫通孔１１ａを充填すればよい。 When the metal is filled into the through hole 11a by the electrolytic plating method, the through electrode 18 and the filling layer 19 may be formed at the same time, or the filling layer 19 may be formed after the through electrode 18 is formed. Good. In the former case, the through hole 11a may be completely embedded with metal. In the latter case, after the through electrode 18 is formed, a mask exposing only the through hole 11a is formed on the back surface 111B of the semiconductor wafer 111, and the through hole 11a is filled with metal by an electrolytic plating method.
　続いて、絶縁層２０を半導体ウェハ１１１の裏面１１１Ｂ上に形成する。例えば、スピンコート又はドライフィルム貼り付けにより、感光性樹脂を半導体ウェハ１１１の裏面１１１Ｂ上に形成すればよい。その後、フォトリソグラフィ技術を用いて、絶縁層２０を選択的に除去する。これにより、絶縁層２０には開口２０ａが形成され、各開口２０ａからは貫通電極１８の一部分が露出する。 Subsequently, the insulating layer 20 is formed on the back surface 111 </ b> B of the semiconductor wafer 111. For example, a photosensitive resin may be formed on the back surface 111B of the semiconductor wafer 111 by spin coating or dry film bonding. Thereafter, the insulating layer 20 is selectively removed using a photolithography technique. Thereby, an opening 20a is formed in the insulating layer 20, and a part of the through electrode 18 is exposed from each opening 20a.
　続いて、フラックスを用いた半田ボール搭載法、半田ペースト印刷法又は電気めっき法により、開口２０ａ内に外部電極２１を形成する。外部電極２１の材料としては、例えば、Ｓｎ－Ａｇ－Ｃｕ組成の鉛フリー半田材料を用いることができる。 Subsequently, the external electrode 21 is formed in the opening 20a by a solder ball mounting method using a flux, a solder paste printing method, or an electroplating method. As the material of the external electrode 21, for example, a lead-free solder material having a Sn—Ag—Cu composition can be used.
　それから、例えばダイシングソー等の切削用部材８５を用いて、半導体ウェハ１１１をスクライブラインＬに沿って切削し、複数の半導体装置１０に個片化させる。このとき、スクライブラインＬ上には第２接着層１６が存在する。そのため、スクライブライン上に相対的に軟らかい接着層（例えば第１接着層１５）が存在する場合に比べて、ダイシングを行いやすく、その結果、スループットの向上を図ることができる。また、個片化された各半導体装置の端面を平坦な面とすることができる。 Then, the semiconductor wafer 111 is cut along the scribe line L using a cutting member 85 such as a dicing saw, for example, and the semiconductor devices 10 are separated into pieces. At this time, the second adhesive layer 16 exists on the scribe line L. Therefore, compared to the case where a relatively soft adhesive layer (for example, the first adhesive layer 15) is present on the scribe line, dicing can be easily performed, and as a result, throughput can be improved. Moreover, the end face of each semiconductor device separated into pieces can be made flat.
　なお、本実施形態に係る半導体装置の製造方法は以下に示す工程を有していてもよい。 In addition, the manufacturing method of the semiconductor device according to the present embodiment may include the following steps.
　第２接着層１６を形成してから、第１接着層１５を形成し、その後、透光板１１７の接着工程を行ってもよい。つまり、半導体ウェハ１１１の主面のうち受光部１２よりも外側の部分の上に第２接着剤を塗布し、その後、ディスペンス法、印刷法又はスピンコート法等により第１接着剤１１５を塗布し、それから、第１接着剤１１５及び第２接着剤を介して透光板１１７を半導体ウェハ１１１に貼り付けてもよい。 The first adhesive layer 15 may be formed after the second adhesive layer 16 is formed, and then the light-transmitting plate 117 may be bonded. That is, the second adhesive is applied on the main surface of the semiconductor wafer 111 on the outer side of the light receiving unit 12, and then the first adhesive 115 is applied by a dispensing method, a printing method, a spin coating method, or the like. Then, the light transmitting plate 117 may be attached to the semiconductor wafer 111 via the first adhesive 115 and the second adhesive.
　第１接着剤１１５及び第２接着剤を透光板１１７の裏面１１７Ｂ上に塗布してもよい。このとき、透光板１１７を半導体ウェハ１１１の主面１１１Ａ上に配置して加圧すると、第１接着剤は半導体ウェハ１１１の主面１１１Ａ上をつたって受光部１２の外側に染み出す。これにより、上記第一の実施形態における第１変形例で説明した半導体装置を製造することができる。 The first adhesive 115 and the second adhesive may be applied on the back surface 117B of the translucent plate 117. At this time, when the translucent plate 117 is placed on the main surface 111 </ b> A of the semiconductor wafer 111 and pressed, the first adhesive passes over the main surface 111 </ b> A of the semiconductor wafer 111 and oozes out to the outside of the light receiving unit 12. Thereby, the semiconductor device described in the first modification in the first embodiment can be manufactured.
　第２接着剤は、カーボン（例えば、カーボンブラック、チャンネルブラック、ファーネスブラック、アセチレンブラック、サーマルブラック及びランブブラック等）を含んでいてもよい。これにより、第２接着層１６は可視光領域において黒色となる。 The second adhesive may contain carbon (for example, carbon black, channel black, furnace black, acetylene black, thermal black, lamp black, etc.). Thereby, the second adhesive layer 16 becomes black in the visible light region.
　（第四の実施形態）
　本発明の第四の実施形態では、上記第二の実施形態に係る半導体装置６０の製造方法を説明する。図８（ａ）～（ｃ）は、上記第二の実施形態に係る半導体装置６０の製造方法を工程順に説明する断面図である。なお、以下では、上記第三の実施形態において説明した半導体装置の製造方法との相違点を主に説明する。 (Fourth embodiment)
In the fourth embodiment of the present invention, a method for manufacturing the semiconductor device 60 according to the second embodiment will be described. 8A to 8C are cross-sectional views illustrating a method for manufacturing the semiconductor device 60 according to the second embodiment in the order of steps. In the following description, differences from the semiconductor device manufacturing method described in the third embodiment will be mainly described.
　まず、受光部１２、周辺回路領域１３及び電極１４が形成された半導体ウェハ１１１を準備する。 First, a semiconductor wafer 111 on which the light receiving unit 12, the peripheral circuit region 13, and the electrode 14 are formed is prepared.
　次に、図８（ａ）に示すように、半導体ウェハ１１１の主面１１１Ａ上にスペーサ６１を形成する。例えば、受光部１２を囲むように、スピンコート法、印刷法又はディスペンス法等によりポリイミド樹脂又はエポキシ樹脂を半導体ウェハ１１１の主面１１１Ａ上に塗布する。このとき、半導体ウェハ１１１の主面１１１Ａ上におけるポリイミド樹脂又はエポキシ樹脂の幅を例えば３０μｍ～３００μｍとすればよい。この後、第１接着剤１１５及び第２接着剤１１６を介して透光板１１７を半導体ウェハ１１１の主面１１１Ａに接着させる。このとき、上記第三の実施形態で説明したように第１接着剤１１５の塗布、透光板１１７の接着及び第２接着剤１１６の塗布の順に行ってもよいし、次に示す順で行ってもよい。 Next, as shown in FIG. 8A, a spacer 61 is formed on the main surface 111 </ b> A of the semiconductor wafer 111. For example, a polyimide resin or an epoxy resin is applied on the main surface 111 </ b> A of the semiconductor wafer 111 by a spin coating method, a printing method, a dispensing method, or the like so as to surround the light receiving unit 12. At this time, the width of the polyimide resin or epoxy resin on the main surface 111A of the semiconductor wafer 111 may be set to 30 μm to 300 μm, for example. Thereafter, the translucent plate 117 is bonded to the main surface 111 </ b> A of the semiconductor wafer 111 through the first adhesive 115 and the second adhesive 116. At this time, as described in the third embodiment, application of the first adhesive 115, adhesion of the light transmitting plate 117, and application of the second adhesive 116 may be performed in this order, or in the following order. May be.
　図８（ｂ）に示すように、例えばディスペンス法を用いて第１接着剤１１５と第２接着剤１１６とを塗布する。具体的には、第１接着剤１１５をスペーサ６１で囲まれた部分に塗布し、第２接着剤１１６をスペーサ６１を挟んで第１接着剤１１５とは反対側に塗布する。 As shown in FIG. 8B, the first adhesive 115 and the second adhesive 116 are applied using, for example, a dispensing method. Specifically, the first adhesive 115 is applied to a portion surrounded by the spacer 61, and the second adhesive 116 is applied to the side opposite to the first adhesive 115 with the spacer 61 interposed therebetween.
　続いて、図８（ｃ）に示すように、第１接着剤１１５及び第２接着剤１１６を介して透光板１１７を半導体ウェハ１１１の主面１１１Ａに接着させた後、第１接着剤１１５及び第２接着剤１１６を硬化させる。 Subsequently, as illustrated in FIG. 8C, the light transmitting plate 117 is bonded to the main surface 111 </ b> A of the semiconductor wafer 111 through the first adhesive 115 and the second adhesive 116, and then the first adhesive 115. And the second adhesive 116 is cured.
　その後、上記第三の実施形態で説明した方法に従って、貫通電極１８、充填層１９、絶縁層２０及び外部電極２１を形成し、切削用部材を用いてスクライブラインＬに沿って半導体ウェハ１１１を切断する。これにより、上記第二の実施形態に係る半導体装置が得られる。 Thereafter, according to the method described in the third embodiment, the through electrode 18, the filling layer 19, the insulating layer 20, and the external electrode 21 are formed, and the semiconductor wafer 111 is cut along the scribe line L using a cutting member. To do. Thereby, the semiconductor device according to the second embodiment is obtained.
　本実施形態では、上記第三の実施形態において得られる効果だけでなく次に示す効果を得ることもできる。スペーサ６１の形成により、半導体ウェハ１１１の主面１１１Ａに透光板１１７を貼り合わせる前に、感光性を持たない液状の第１接着剤１１５及び第２接着剤１１６を半導体ウェハ１１１の主面１１１Ａ上に塗布することができる。よって、本実施形態では、第１接着剤及び第２接着剤の材料の選択性を広くすることができるので、低コストで半導体装置を製造できる。 In this embodiment, not only the effects obtained in the third embodiment but also the following effects can be obtained. Due to the formation of the spacer 61, before the light transmitting plate 117 is bonded to the main surface 111 </ b> A of the semiconductor wafer 111, the liquid non-photosensitive first adhesive 115 and second adhesive 116 are applied to the main surface 111 </ b> A of the semiconductor wafer 111. Can be applied on top. Therefore, in this embodiment, since the selectivity of the material of the first adhesive and the second adhesive can be widened, a semiconductor device can be manufactured at low cost.
　上記の第一の実施形態～第四の実施形態の半導体装置は、光学素子として受光部１２の代わりに発光部を備えていてもよい。別の言い方をすると、上記第一の実施形態～第四の実施形態は、発光装置にも適用することができる。 The semiconductor devices of the first to fourth embodiments may include a light emitting unit instead of the light receiving unit 12 as an optical element. In other words, the first to fourth embodiments can be applied to a light emitting device.
　（第五の実施形態）
　以下、本発明の第五の実施形態に係る半導体装置を説明する。図９は本実施形態に係る半導体装置８０の構造を示す断面図である。 (Fifth embodiment)
The semiconductor device according to the fifth embodiment of the present invention will be described below. FIG. 9 is a cross-sectional view showing the structure of the semiconductor device 80 according to this embodiment.
　第五の実施形態に係る半導体装置は、第一の実施形態に係る半導体装置と異なり、第１半導体素子８１に、受光部１２及び周辺回路領域１３ではなく回路領域８３Ａが形成されている。また、第１半導体素子８１の主面８１Ａの上には、透光板１７ではなく第２半導体素子８２が貼り付けられている。具体的に、本実施形態に係る半導体装置は、第１半導体素子８１と、第１半導体素子８１の主面８１Ａに設けられた回路領域８３Ａと、第１半導体素子８１の主面８１Ａの上に設けられた電極１４Ａと、第１接着層１５及び第２接着層１６により第１半導体素子８１の主面８１Ａの上に接着された第２半導体素子８２とを備えている。第１接着層１５は、回路領域８３Ａを覆うように形成され、一方、第２接着層１６は、第１半導体素子８１の主面８１Ａに回路領域８３Ａを覆わないように形成されている。また、第２接着層１６は、第１半導体素子８１の主面８１Ａの上において第１接着層１５の外側に設けられていると共に第１接着層１５と接している。また、第１半導体素子８１には、貫通電極１８Ａ及び充填層１９Ａが形成されており、貫通電極１８Ａは電極１４Ａと接している。これにより、貫通電極１８Ａは、電極１４Ａを介して回路領域８３Ａと電気的に接続される。第１半導体素子８１の裏面８１Ｂには絶縁層２０Ａが形成され、絶縁層２０Ａには貫通電極１８Ａを露出する開口２０ａが形成されている。開口２０ａにおいて、貫通電極１８Ａと接続するように外部電極２１Ａが形成されている。第２半導体素子８２の構造は、第１半導体素子８１と同等であり、回路領域８３Ｂ及び電極１４Ｂ等が設けられている。さらに、第２半導体素子８２にも、貫通電極１８Ｂ及び充填層１９Ｂが形成され、貫通電極１８Ｂと接続された外部電極２１Ｂは、第１半導体素子８１の上に設けられた電極１４Ａと電気的に接続されている。 The semiconductor device according to the fifth embodiment is different from the semiconductor device according to the first embodiment in that a circuit region 83 </ b> A is formed in the first semiconductor element 81 instead of the light receiving unit 12 and the peripheral circuit region 13. Further, the second semiconductor element 82 is pasted on the main surface 81A of the first semiconductor element 81 instead of the light transmitting plate 17. Specifically, the semiconductor device according to the present embodiment includes a first semiconductor element 81, a circuit region 83 </ b> A provided on the main surface 81 </ b> A of the first semiconductor element 81, and a main surface 81 </ b> A of the first semiconductor element 81. The electrode 14A is provided, and a second semiconductor element 82 bonded onto the main surface 81A of the first semiconductor element 81 by the first adhesive layer 15 and the second adhesive layer 16 is provided. The first adhesive layer 15 is formed so as to cover the circuit region 83 </ b> A, while the second adhesive layer 16 is formed so as not to cover the circuit region 83 </ b> A on the main surface 81 </ b> A of the first semiconductor element 81. The second adhesive layer 16 is provided outside the first adhesive layer 15 on the main surface 81 </ b> A of the first semiconductor element 81 and is in contact with the first adhesive layer 15. Further, the first semiconductor element 81 is provided with a through electrode 18A and a filling layer 19A, and the through electrode 18A is in contact with the electrode 14A. Thereby, the through electrode 18A is electrically connected to the circuit region 83A through the electrode 14A. An insulating layer 20A is formed on the back surface 81B of the first semiconductor element 81, and an opening 20a exposing the through electrode 18A is formed in the insulating layer 20A. In the opening 20a, an external electrode 21A is formed so as to be connected to the through electrode 18A. The structure of the second semiconductor element 82 is the same as that of the first semiconductor element 81, and is provided with a circuit region 83B, an electrode 14B, and the like. Further, the through electrode 18B and the filling layer 19B are also formed in the second semiconductor element 82, and the external electrode 21B connected to the through electrode 18B is electrically connected to the electrode 14A provided on the first semiconductor element 81. It is connected.
　第五の実施形態に係る半導体装置によると、第一の実施形態と同様に、第１接着層１５の硬度よりも第２接着層１６の硬度を大きくすることによって、第１半導体素子８１と第２半導体素子８２との貼り合わせ時の応力を第１接着層１５により吸収し、且つ、第２接着層１６が第１接着層１５よりも相対的に硬度が大きいため、ダイシングをスムーズに行うことができる。 According to the semiconductor device of the fifth embodiment, as in the first embodiment, the first semiconductor element 81 and the first semiconductor element 81 are formed by making the hardness of the second adhesive layer 16 larger than the hardness of the first adhesive layer 15. 2 Dicing is smoothly performed because the stress at the time of bonding to the semiconductor element 82 is absorbed by the first adhesive layer 15 and the second adhesive layer 16 is relatively harder than the first adhesive layer 15. Can do.
　また、本実施形態において、図１０に示すように、第１半導体素子８１の上に複数の第２半導体素子８２を積層してもよい。このようにしても、それぞれの貼り合わせの際に生じる応力を十分に緩和することができる。 In the present embodiment, a plurality of second semiconductor elements 82 may be stacked on the first semiconductor element 81 as shown in FIG. Even if it does in this way, the stress which arises at the time of each bonding can fully be relieved.
　ここで、第１半導体素子８１及び第２半導体素子８２の厚さは、５０μｍ以下であることが好ましい。また、本実施形態における第２接着層１６の硬度はショアＤ硬度で６５以上であり、言い換えると弾性率は１５ＭＰａ以上であることが望ましい。なお、本実施形態における第１接着層１５は第２接着層１６よりも相対的に柔らかければよくその弾性率は特に限定するものではなく、第１半導体素子８１及び第２半導体素子８２の厚さ及び積層数に応じて適宜変更すればよい。 Here, the thickness of the first semiconductor element 81 and the second semiconductor element 82 is preferably 50 μm or less. In addition, the hardness of the second adhesive layer 16 in this embodiment is 65 or more in Shore D hardness, in other words, the elastic modulus is desirably 15 MPa or more. Note that the elastic modulus of the first adhesive layer 15 in the present embodiment is not particularly limited as long as the first adhesive layer 15 is relatively softer than the second adhesive layer 16, and the thicknesses of the first semiconductor element 81 and the second semiconductor element 82 are not limited. What is necessary is just to change suitably according to thickness and the number of lamination | stacking.
　（一変形例）
　図１１は、第五の実施形態の一変化例に係る半導体装置８０の断面図である。 (One variation)
FIG. 11 is a cross-sectional view of a semiconductor device 80 according to a variation of the fifth embodiment.
　第五の実施形態と比較して、本変形例は、第１半導体素子８１及び第２半導体素子８２における回路領域８３Ａ、８３Ｂがそれぞれの裏面８１Ｂ、８２Ｂ側に形成され、第２半導体素子８２は、貫通電極及び充填層等が形成されていない点が異なる。 Compared with the fifth embodiment, in the present modification, circuit regions 83A and 83B in the first semiconductor element 81 and the second semiconductor element 82 are formed on the back surfaces 81B and 82B, respectively, and the second semiconductor element 82 is The difference is that the through electrode and the filling layer are not formed.
　具体的に、第１半導体素子８１は、該第１半導体素子８１の裏面８１Ｂ側に形成された回路領域８３Ａと、第１半導体素子８１の裏面８１Ｂ側に形成され且つ回路領域８３Ａと電気的に接続する電極１４Ａと、第１半導体素子８１の裏面８１Ｂ側に形成され且つ電極１４Ａと電気的に接続する外部電極２１Ａとを備えている。また、第２半導体素子８２は、該第２半導体素子８２の裏面８２Ｂ側に形成された回路領域８３Ｂと、第２半導体素子８２の裏面８２Ｂ側に形成され且つ回路領域８３Ｂと電気的に接続する電極１４Ｂと、第２半導体素子８２の裏面８２Ｂに形成され且つ電極１４と電気的に接続する外部電極２１Ｂとを備えている。しかしながら、第２半導体素子８２は、貫通電極、充填層、絶縁層及び開口を備えていない。 Specifically, the first semiconductor element 81 includes a circuit region 83A formed on the back surface 81B side of the first semiconductor element 81, and a circuit region 83A formed on the back surface 81B side of the first semiconductor element 81 and electrically connected to the circuit region 83A. An electrode 14A to be connected and an external electrode 21A formed on the back surface 81B side of the first semiconductor element 81 and electrically connected to the electrode 14A are provided. The second semiconductor element 82 is formed on the back surface 82B side of the second semiconductor element 82, and is formed on the back surface 82B side of the second semiconductor element 82 and is electrically connected to the circuit region 83B. An electrode 14B and an external electrode 21B formed on the back surface 82B of the second semiconductor element 82 and electrically connected to the electrode 14 are provided. However, the second semiconductor element 82 does not include a through electrode, a filling layer, an insulating layer, and an opening.
　第１半導体素子８１と第２半導体素子８２とは、第１半導体素子８１の貫通電極１８Ａと第２半導体素子８２の外部電極２１Ｂとにより電気的に接続されている。 The first semiconductor element 81 and the second semiconductor element 82 are electrically connected by the through electrode 18A of the first semiconductor element 81 and the external electrode 21B of the second semiconductor element 82.
　本変形例によると、第五の実施形態による効果に加え、以下の効果が期待できる。 According to this modification, the following effects can be expected in addition to the effects of the fifth embodiment.
　第１半導体素子８１に積層された第２半導体素子８２は、貫通電極１８と充填層１９と絶縁層２０と開口２０ａとを備えていないため、半導体装置８０の製造工程を簡略化することができ、低いコストにより半導体装置８０を製造することができる。 Since the second semiconductor element 82 stacked on the first semiconductor element 81 does not include the through electrode 18, the filling layer 19, the insulating layer 20, and the opening 20 a, the manufacturing process of the semiconductor device 80 can be simplified. The semiconductor device 80 can be manufactured at a low cost.
　なお、本変形例において、第１半導体素子８１を複数積層してもよい。 In this modification, a plurality of first semiconductor elements 81 may be stacked.
　（第六の実施形態）
　以下、本発明の第六の実施形態として、上記の第五の実施形態に係る半導体装置の製造方法を説明する。図１２（ａ）～（ｃ）は、第五の実施形態に係る半導体装置８０の製造方法を工程順に説明する断面図である。 (Sixth embodiment)
Hereinafter, a semiconductor device manufacturing method according to the fifth embodiment will be described as a sixth embodiment of the present invention. 12A to 12C are cross-sectional views illustrating a method for manufacturing a semiconductor device 80 according to the fifth embodiment in the order of steps.
　ここでは、第１半導体素子と第２半導体素子とを貼り合わせる工程を中心に説明する。 Here, the description will focus on the process of bonding the first semiconductor element and the second semiconductor element.
　まず、主面１２１ＡがスクライブラインＬにより複数のチップ領域１２０（図１２（ａ）では２つの領域）に区画された第１半導体ウェハ１２１と、主面１２２Ａが複数のチップ領域１２０と対応する複数のチップ領域１２３に区画された第２半導体ウェハ１２２とを準備する。チップ領域１２０の各々には、回路領域８３Ａ、電極１４Ａ、貫通電極１８Ａ、充填層１９Ａ、絶縁層２０Ａ及び開口２０ａが設けられている。チップ領域１２３の各々には、回路領域８３Ｂ、電極１４Ｂ、貫通電極１８Ｂ、充填層１９Ｂ、絶縁層２０Ｂ、開口２０ａ及び外部電極２１Ｂが設けられている。 First, a first semiconductor wafer 121 having a main surface 121A divided into a plurality of chip regions 120 (two regions in FIG. 12A) by a scribe line L, and a plurality of main surfaces 122A corresponding to the plurality of chip regions 120. And the second semiconductor wafer 122 partitioned into the chip region 123 are prepared. Each of the chip regions 120 is provided with a circuit region 83A, an electrode 14A, a through electrode 18A, a filling layer 19A, an insulating layer 20A, and an opening 20a. Each of the chip regions 123 is provided with a circuit region 83B, an electrode 14B, a through electrode 18B, a filling layer 19B, an insulating layer 20B, an opening 20a, and an external electrode 21B.
　次に、第三の実施形態及び第四の実施形態と同様の方法により、主面１２１Ａ上に、第１接着剤１１５と第２接着剤１１６とを介して、電極１４Ａと外部電極２１Ｂとが電気的に接続するように第１半導体ウェハ１２１と第２半導体ウェハ１２２との貼り合わせを行う。ここで、第三の実施形態及び第四の実施形態と異なる接着方法を用いてもよい。例えば、第１接着剤１１５及び第２接着剤１１６を塗布した後に、超音波を用いて第１半導体ウェハ１２１と第２半導体ウェハ１２２とを貼り合わせてもよい。 Next, the electrode 14A and the external electrode 21B are formed on the main surface 121A via the first adhesive 115 and the second adhesive 116 by the same method as in the third embodiment and the fourth embodiment. The first semiconductor wafer 121 and the second semiconductor wafer 122 are bonded so as to be electrically connected. Here, you may use the adhesion method different from 3rd embodiment and 4th embodiment. For example, after applying the first adhesive 115 and the second adhesive 116, the first semiconductor wafer 121 and the second semiconductor wafer 122 may be bonded together using ultrasonic waves.
　次に、第１半導体ウェハ１２１の外部電極２１Ａを第三の実施形態と同様の方法により形成する。 Next, the external electrode 21A of the first semiconductor wafer 121 is formed by the same method as in the third embodiment.
　その後、ダイシングソー等の切削用部材８５を用いて複数の第１半導体ウェハ１２１と複数の第２半導体ウェハ１２２とを個片化させる。このようにすることにより、スクライブラインＬ上に相対的に硬度が大きい接着層（例えば、第２接着層１６）が形成されているため、スクライブラインＬ上に相対的に軟らかい接着層（例えば、第１接着層１５）が形成されている場合と比べて、ダイシングが行いやすく、その結果、スループットの向上を図ることができる。 Thereafter, the plurality of first semiconductor wafers 121 and the plurality of second semiconductor wafers 122 are separated into pieces using a cutting member 85 such as a dicing saw. By doing in this way, since the adhesive layer (for example, the 2nd adhesion layer 16) with relatively large hardness is formed on scribe line L, the adhesive layer (for example, relatively soft) on scribe line L (for example, Compared with the case where the first adhesive layer 15) is formed, dicing can be easily performed, and as a result, the throughput can be improved.
　次に、第五の実施形態の一変形例に係る半導体装置８０の製造方法を説明する。図１３（ａ）～（ｃ）は、上記第五の実施形態の一変形例に係る半導体装置８０の製造方法を工程順に説明する断面図である。 Next, a method for manufacturing the semiconductor device 80 according to a modification of the fifth embodiment will be described. 13A to 13C are cross-sectional views illustrating a method for manufacturing the semiconductor device 80 according to a modification of the fifth embodiment in the order of steps.
　まず、第１半導体ウェハ１２１を主面１２１ＡがスクライブラインＬにより複数のチップ領域１２０（図１３（ａ）では２つの領域）に区画された第１半導体ウェハ１２１と、主面１２２Ａが複数のチップ領域１２０と対応する複数のチップ領域１２３に区画された第２半導体ウェハ１２２とを準備する。チップ領域１２０の各々には回路領域８３Ａ、電極１４Ａ、貫通電極１８Ａ、充填層１９Ａ、絶縁層２０Ａ及び開口２０ａが、チップ領域１２３の各々には回路領域８３Ｂ、電極１４Ｂ及び外部電極２１Ｂが設けられている。 First, the first semiconductor wafer 121 is divided into a plurality of chip regions 120 (two regions in FIG. 13A) with a main surface 121A by a scribe line L, and the main surface 122A has a plurality of chips. A second semiconductor wafer 122 partitioned into a plurality of chip regions 123 corresponding to the region 120 is prepared. Each of the chip regions 120 is provided with a circuit region 83A, an electrode 14A, a through electrode 18A, a filling layer 19A, an insulating layer 20A, and an opening 20a, and each of the chip regions 123 is provided with a circuit region 83B, an electrode 14B, and an external electrode 21B. ing.
　次に、上記の方法と同様の方法により主面１２１Ａ上に、第１接着剤１１５と第２接着剤１１６を介して、貫通電極１８Ａと外部電極２１Ｂとが電気的に接続できるように第１半導体ウェハ１２１と第２半導体ウェハ１２２との貼り合わせを行う。 Next, the first electrode 115 </ b> A and the external electrode 21 </ b> B are electrically connected to the main surface 121 </ b> A via the first adhesive 115 and the second adhesive 116 by the same method as described above. The semiconductor wafer 121 and the second semiconductor wafer 122 are bonded together.
　その後、第１半導体ウェハの外部電極２１Ａを第三の実施形態と同様な方法で形成する。 Thereafter, the external electrode 21A of the first semiconductor wafer is formed by the same method as in the third embodiment.
　最後に、ダイシングソー等の切削用部材８５を用いて複数の第１半導体ウェハ１２１と複数の第２半導体ウェハ１２２とを個片化させる。 Finally, the plurality of first semiconductor wafers 121 and the plurality of second semiconductor wafers 122 are separated into pieces using a cutting member 85 such as a dicing saw.
　以上、図面を参照して本発明の実施形態を説明したが、本発明は、図示した実施形態の構成に限定されない。図示した実施形態に対して、この発明と同一の範囲内において又は均等の範囲内において、種々の修正及び変形を加えることが可能である。 As mentioned above, although embodiment of this invention was described with reference to drawings, this invention is not limited to the structure of embodiment shown in figure. Various modifications and variations can be made to the illustrated embodiment within the same range or equivalent range as the present invention.
　本発明の半導体装置は、固体撮像素子をはじめ、フォトダイオード若しくはレーザーモジュール等の各種半導体装置又は各種モジュールに特に好適である。 The semiconductor device of the present invention is particularly suitable for various semiconductor devices or various modules such as a solid-state imaging device, a photodiode or a laser module.
１０　　　半導体装置
１１　　　半導体素子
１１Ａ　　主面
１１Ｂ　　裏面
１１ａ　　貫通孔（貫通孔部）
１２　　　受光部（光学素子）
１３　　　周辺回路領域
１４、１４Ａ、１４Ｂ　　　電極
１５　　　第１接着層
１６　　　第２接着層
１７　　　透光板
１７Ａ　　主面（第２面）
１７Ｂ　　裏面（第１面）
１８、１８Ａ、１８Ｂ　　　貫通電極
１９、１９Ａ、１９Ｂ　　　充填層
２０、２０Ａ、２０Ｂ　　　絶縁層
２０ａ　　開口（開口部）
２１、２１Ａ、２１Ｂ　　　外部電極
３０　　　半導体装置
３５　　　第１接着層
３６　　　第２接着層
４０　　　半導体装置
４１　　　反射防止膜
５０　　　半導体装置
６０　　　半導体装置
６１　　　スペーサ
７０　　　半導体装置
７１　　　レジスト
７１ａ　　開口
８０　　　半導体装置
８１ 　第１半導体素子
８１Ａ　　主面
８１Ｂ　　裏面
８２ 　第２半導体素子
８２Ｂ　　裏面
８３Ａ、８３Ｂ 　回路領域
８５　　　切削用部材
１１１　　半導体ウェハ
１１１Ａ　主面
１１１Ｂ　裏面
１１５　　第１接着剤
１１６　　第２接着剤
１１７　　透光板
１１７Ｂ　裏面
１２０　　チップ領域
１２１　　第１半導体ウェハ
１２１Ａ　主面
１２２　　第２半導体ウェハ
１２２Ａ　主面
１２３　　チップ領域 DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Semiconductor element 11A Main surface 11B Back surface 11a Through-hole (through-hole part)
12 Light receiving part (optical element)
13 Peripheral circuit region 14, 14A, 14B Electrode 15 First adhesive layer 16 Second adhesive layer 17 Translucent plate 17A Main surface (second surface)
17B Back side (first side)
18, 18A, 18B Through electrode 19, 19A, 19B Filling layer 20, 20A, 20B Insulating layer 20a Opening (opening)
21, 21A, 21B External electrode 30 Semiconductor device 35 First adhesive layer 36 Second adhesive layer 40 Semiconductor device 41 Antireflection film 50 Semiconductor device 60 Semiconductor device 61 Spacer 70 Semiconductor device 71 Resist 71a Opening 80 Semiconductor device 81 First semiconductor element 81A Main surface 81B Back surface 82 Second semiconductor element 82B Back surface 83A, 83B Circuit region 85 Cutting member 111 Semiconductor wafer 111A Main surface 111B Back surface 115 First adhesive 116 Second adhesive 117 Translucent plate 117B Back surface 120 Chip region 121 First 1 semiconductor wafer 121A main surface 122 second semiconductor wafer 122A main surface 123 chip region

Claims (21)

  1. 　半導体素子と、
    　前記半導体素子の主面に設けられた光学素子と、
    　前記光学素子を覆う第１接着層と、
    　前記半導体素子の前記主面における前記光学素子以外の部分の少なくとも一部分を覆い、前記第１接着層よりも硬度が大きい第２接着層と、
    　前記第１接着層及び前記第２接着層を介して前記半導体素子に接着された透光板とを備えている半導体装置。     A semiconductor element;
    An optical element provided on a main surface of the semiconductor element;
    A first adhesive layer covering the optical element;
    A second adhesive layer that covers at least a portion of the main surface of the semiconductor element other than the optical element and has a hardness higher than that of the first adhesive layer;
    A semiconductor device comprising: a translucent plate bonded to the semiconductor element through the first adhesive layer and the second adhesive layer.
  2. 　請求項１において、
    　前記第２接着層の硬度は、ショアＤ硬度で６５以上である半導体装置。     In claim 1,
    The second adhesive layer has a hardness of 65 or more in Shore D hardness.
  3. 　請求項１又は２において、
    　前記透光板は、前記第１接着層及び前記第２接着層に接着された第１面と、前記第１面とは反対側に位置する第２面とを有し、
    　前記透光板の前記第１面及び前記第２面のうちの少なくとも一方の面の上には、反射防止膜が設けられている半導体装置。     In claim 1 or 2,
    The translucent plate has a first surface bonded to the first adhesive layer and the second adhesive layer, and a second surface located on the opposite side of the first surface,
    A semiconductor device in which an antireflection film is provided on at least one of the first surface and the second surface of the translucent plate.
  4. 　請求項１～３のいずれか１項において、
    　前記第２接着層は黒色である半導体装置。     In any one of claims 1 to 3,
    The semiconductor device, wherein the second adhesive layer is black.
  5. 　請求項１～４のいずれか１項において、
    　前記半導体素子と前記透光板との間には、前記第１接着層と前記第２接着層とが積層された領域が存在している半導体装置。     In any one of claims 1 to 4,
    A semiconductor device in which a region where the first adhesive layer and the second adhesive layer are laminated exists between the semiconductor element and the light transmitting plate.
  6. 　請求項１～４のいずれか１項において、
    　前記第１接着層と前記第２接着層とは、前記半導体素子の前記主面上において互いに間隔を開けて配置されており、
    　前記半導体素子の前記主面上における前記第１接着層と前記第２接着層との間には、スペーサが設けられている半導体装置。     In any one of claims 1 to 4,
    The first adhesive layer and the second adhesive layer are arranged on the main surface of the semiconductor element with a space therebetween,
    A semiconductor device in which a spacer is provided between the first adhesive layer and the second adhesive layer on the main surface of the semiconductor element.
  7. 　請求項６において、
    　前記半導体素子と前記透光板との間には、前記第１接着層と前記スペーサとが積層された領域が存在している半導体装置。     In claim 6,
    A semiconductor device in which a region in which the first adhesive layer and the spacer are stacked exists between the semiconductor element and the translucent plate.
  8. 　請求項１～７の何れか１項において、
    　前記半導体素子の前記主面における前記光学素子の外側に設けられた電極と、
    　前記電極に達するように前記半導体素子の厚さ方向に貫通する貫通孔部と、
    　前記電極と接しており、前記貫通孔部の内側面上から前記半導体素子の裏面上にまで延びる貫通電極とを備えている半導体装置。     In any one of claims 1 to 7,
    An electrode provided outside the optical element on the main surface of the semiconductor element;
    A through-hole portion penetrating in the thickness direction of the semiconductor element to reach the electrode;
    A semiconductor device comprising: a through electrode in contact with the electrode and extending from an inner surface of the through hole portion to a back surface of the semiconductor element.
  9. 　請求項８において、
    　前記貫通孔部内には、前記貫通電極を介して充填層が設けられている半導体装置。     In claim 8,
    A semiconductor device in which a filling layer is provided in the through hole portion through the through electrode.
  10. 　請求項８において、
    　前記半導体素子の前記裏面上と前記半導体素子の前記裏面上における前記貫通電極の上とに設けられた絶縁層と、
    　前記絶縁層に形成され、前記半導体素子の前記裏面上における前記貫通電極を露出する開口部と、
    　前記開口部内に設けられ、前記貫通電極に接続された外部電極とを備えている半導体装置。     In claim 8,
    An insulating layer provided on the back surface of the semiconductor element and on the through electrode on the back surface of the semiconductor element;
    An opening formed in the insulating layer and exposing the through electrode on the back surface of the semiconductor element;
    A semiconductor device comprising: an external electrode provided in the opening and connected to the through electrode.
  11. 　第１半導体素子と、
    　前記第１半導体素子の主面に設けられた回路領域と、
    　前記回路領域を覆う第１接着層と、
    　前記第１半導体素子の前記主面における前記回路領域以外の部分の少なくとも一部分を覆い、前記第１接着層よりも硬度が大きい第２接着層と、
    　前記第１接着層及び前記第２接着層を介して前記第１半導体素子に接着された第２半導体素子とを備えている半導体装置。     A first semiconductor element;
    A circuit region provided on a main surface of the first semiconductor element;
    A first adhesive layer covering the circuit region;
    A second adhesive layer that covers at least a part of the main surface of the first semiconductor element other than the circuit region and has a hardness higher than that of the first adhesive layer;
    A semiconductor device comprising: a second semiconductor element bonded to the first semiconductor element via the first adhesive layer and the second adhesive layer.
  12. 　光学素子が主面に形成された半導体素子を準備する工程（ａ）と、
    　第１接着剤で前記光学素子を覆う工程（ｂ）と、
    　前記第１接着剤よりも硬化後の硬度が大きい第２接着剤で、前記半導体素子の前記主面における前記光学素子以外の部分の少なくとも一部分を覆う工程（ｃ）と、
    　前記第１接着剤からなる第１接着層及び前記第２接着剤からなる第２接着層を介して透光板を前記半導体素子に接着する工程（ｄ）とを備えている半導体装置の製造方法。     A step (a) of preparing a semiconductor element having an optical element formed on a main surface;
    Covering the optical element with a first adhesive (b);
    A step (c) of covering at least a part of the main surface of the semiconductor element other than the optical element with a second adhesive having a hardness after curing that is higher than that of the first adhesive;
    A method of manufacturing a semiconductor device, comprising: a step (d) of bonding a translucent plate to the semiconductor element via a first adhesive layer made of the first adhesive and a second adhesive layer made of the second adhesive. .
  13. 　請求項１２において、
    　前記工程（ｄ）では、前記半導体素子の前記主面に対向する第１面及び前記第１面とは反対側に位置する第２面のうちの少なくとも一方の面の上に反射防止膜が設けられた透光板を前記半導体素子に接着する半導体装置の製造方法。     In claim 12,
    In the step (d), an antireflection film is provided on at least one of the first surface facing the main surface of the semiconductor element and the second surface located on the opposite side of the first surface. A method for manufacturing a semiconductor device, comprising bonding a translucent plate to the semiconductor element.
  14. 　請求項１２又は１３において、
    　前記第２接着剤を黒色化させる工程（ｅ）を備えている半導体装置の製造方法。     In claim 12 or 13,
    A method for manufacturing a semiconductor device, comprising the step (e) of blackening the second adhesive.
  15. 　請求項１２～１４のいずれか１項において、
    　前記半導体素子の前記主面上における前記第１接着層と前記第２接着層との間にスペーサを設ける工程（ｆ）を備えている半導体装置の製造方法。     In any one of claims 12 to 14,
    A method of manufacturing a semiconductor device, comprising a step (f) of providing a spacer between the first adhesive layer and the second adhesive layer on the main surface of the semiconductor element.
  16. 　請求項１５において、
    　前記工程（ｂ）及び前記工程（ｃ）を行う前に、前記工程（ｆ）を行う半導体装置の製造方法。     In claim 15,
    A method of manufacturing a semiconductor device, wherein the step (f) is performed before the step (b) and the step (c).
  17. 　請求項１２～１６のいずれか１項において、
    　前記工程（ｂ）の後であって前記工程（ｃ）の前に、前記透光板を前記第１接着剤の上に配置する工程（ｇ）を備え、
    　前記工程（ｇ）では、前記第１接着剤の一部が前記透光板の下面をつたって前記透光板の前記下面の周縁部へ向かって流動する又は前記半導体素子の前記主面をつたって前記半導体素子の前記主面の周縁部へ向かって流動する半導体装置の製造方法。     In any one of claims 12 to 16,
    After the step (b) and before the step (c), the method includes a step (g) of disposing the translucent plate on the first adhesive,
    In the step (g), a part of the first adhesive flows along the lower surface of the translucent plate and flows toward the peripheral portion of the lower surface of the translucent plate or the main surface of the semiconductor element. Accordingly, a method of manufacturing a semiconductor device that flows toward a peripheral portion of the main surface of the semiconductor element.
  18. 　請求項１２～１７のいずれか１項において、
    　前記工程（ａ）で準備する前記半導体素子の前記主面における前記光学素子の外側には、電極が設けられており、
    　前記電極に達するように、前記半導体素子の厚さ方向に貫通孔部を貫設させる工程と、
    　前記電極に接するとともに前記貫通孔部の内側面上から前記半導体素子の裏面上にまで延びる貫通電極を形成する工程とを備えている半導体装置の製造方法。     In any one of claims 12 to 17,
    An electrode is provided outside the optical element on the main surface of the semiconductor element prepared in the step (a),
    A step of penetrating a through hole in the thickness direction of the semiconductor element so as to reach the electrode;
    Forming a through electrode in contact with the electrode and extending from an inner surface of the through hole portion to a back surface of the semiconductor element.
  19. 　請求項１８において、
    　前記貫通孔部内に前記貫通電極を挟んで充填層を設ける工程を備えている半導体装置の製造方法。     In claim 18,
    A method for manufacturing a semiconductor device, comprising: providing a filling layer in the through hole with the through electrode interposed therebetween.
  20. 　請求項１８において、
    　前記半導体素子の前記裏面上と前記半導体素子の前記裏面上における前記貫通電極の上とに絶縁層を設ける工程と、
    　前記半導体素子の前記裏面上における前記貫通電極が露出するように前記絶縁層に開口部を形成する工程と、
    　外部電極を前記開口部内に設けて前記貫通電極に接続する工程とを備えている半導体装置の製造方法。     In claim 18,
    Providing an insulating layer on the back surface of the semiconductor element and on the through electrode on the back surface of the semiconductor element;
    Forming an opening in the insulating layer so that the through electrode on the back surface of the semiconductor element is exposed;
    And a step of providing an external electrode in the opening and connecting to the through electrode.
  21. 　主面がダイシングラインにより複数の領域に区画されており、光学素子が領域のそれぞれに形成された半導体ウェハを準備する工程と、
    　前記光学素子のそれぞれを第１接着剤で覆う工程と、
    　前記第１接着剤よりも硬化後の硬度が大きい第２接着剤で、前記半導体素子の前記主面における前記光学素子以外の部分の少なくとも一部分を覆う工程と、
    　前記第１接着剤からなる第１接着層及び前記第２接着剤からなる第２接着層を介して透光板を前記半導体ウェハに接着する工程と、
    　前記ダイシングラインに沿って前記半導体ウェハをダイシングする工程とを備えている半導体装置の製造方法。     A step of preparing a semiconductor wafer in which a main surface is divided into a plurality of regions by a dicing line and an optical element is formed in each of the regions;
    Covering each of the optical elements with a first adhesive;
    A step of covering at least a part of a portion other than the optical element on the main surface of the semiconductor element with a second adhesive having a hardness after curing larger than that of the first adhesive;
    Bonding the light-transmitting plate to the semiconductor wafer via the first adhesive layer made of the first adhesive and the second adhesive layer made of the second adhesive;
    And a step of dicing the semiconductor wafer along the dicing line.
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