WO2011110129A2 - Procédé et système d'estimation de canal - Google Patents

Procédé et système d'estimation de canal Download PDF

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Publication number
WO2011110129A2
WO2011110129A2 PCT/CN2011/073249 CN2011073249W WO2011110129A2 WO 2011110129 A2 WO2011110129 A2 WO 2011110129A2 CN 2011073249 W CN2011073249 W CN 2011073249W WO 2011110129 A2 WO2011110129 A2 WO 2011110129A2
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WIPO (PCT)
Prior art keywords
matrix
inverse
channel estimation
training sequence
sub
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PCT/CN2011/073249
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English (en)
Chinese (zh)
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WO2011110129A3 (fr
Inventor
綦睿
袁佳杰
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华为技术有限公司
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Priority to CN201180000278.3A priority Critical patent/CN102246478B/zh
Priority to PCT/CN2011/073249 priority patent/WO2011110129A2/fr
Publication of WO2011110129A2 publication Critical patent/WO2011110129A2/fr
Publication of WO2011110129A3 publication Critical patent/WO2011110129A3/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0202—Channel estimation
    • H04L25/024—Channel estimation channel estimation algorithms
    • H04L25/0242—Channel estimation channel estimation algorithms using matrix methods
    • H04L25/0244—Channel estimation channel estimation algorithms using matrix methods with inversion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0202—Channel estimation
    • H04L25/0224—Channel estimation using sounding signals
    • H04L25/0228—Channel estimation using sounding signals with direct estimation from sounding signals

Definitions

  • the present invention relates to the field of communications, and in particular, to a channel estimation method and apparatus.
  • VAMOS Voice Service Over Adaptive Mul t i-user Orthogonal Sub Channels
  • the VAM0S technology two users are multiplexed on the same time slot by adding a new voice channel to the original voice channel, that is, if the first voice channel is occupied, one and the first voice channel are used.
  • the orthogonal subchannel will be used as another voice channel to achieve double the voice capacity.
  • the introduction of the new voice channel has the following principles:
  • the new voice channel has the lowest cross-correlation with the original voice channel.
  • the VAM0S two-user joint channel estimation algorithm is used to estimate the correlation between the new voice channel and the original voice channel, and the specific process includes: first, by using two users that can represent the new voice channel and the original voice channel.
  • the training sequence number obtains the channel estimation factor; then the channel estimation factor is used for the VAM0S two-user joint channel detection to obtain the channel detection result; finally, the result is used for the VAM0S strong and weak user joint channel detection and subsequent detection.
  • the channel estimation process is at the forefront of the two-user joint channel estimation algorithm of VAM0S, and its computational accuracy and implementation method have a great influence on the two-user joint channel estimation algorithm of VAM0S.
  • Embodiments of the present invention provide a channel estimation method and apparatus capable of storing a small amount of data to implement channel estimation.
  • a channel estimation apparatus including:
  • a matrix storage unit configured to store an intermediate inverse matrix
  • the matrix generated by the training sequence corresponding to the training sequence numbers of the two users is subjected to multiplication and addition logic operations to obtain a channel estimation factor
  • a channel estimation unit configured to complete a channel estimation process according to the channel estimation factor calculated by the logic calculation unit.
  • a channel estimation method including: acquiring a sub-inverse matrix corresponding to training sequence numbers of two users from a pre-stored intermediate inverse matrix; and training the sub-inverse matrix with the two users
  • the matrix generated by the training sequence corresponding to the serial number is subjected to multiplication and addition logic operations to obtain a channel estimation factor; and the channel estimation process is completed according to the calculated channel estimation factor.
  • the channel estimation method and apparatus provided by the embodiment of the present invention, the matrix generated by the training sequence corresponding to the training sequence number of the two users in the intermediate inverse matrix stored by the matrix storage unit by the logic calculation unit, and the matrix generated by the training sequence corresponding to the training sequence number
  • the multiplication and addition logic calculation is performed to obtain a channel estimation factor to complete channel estimation. Since only the intermediate inverse matrix needs to be stored,
  • the embodiment of the invention solves the problem that the data storage amount of the chip in the prior art is large.
  • FIG. 1 is a schematic structural diagram of a channel estimation apparatus according to Embodiment 1 of the present invention
  • FIG. 2 is a schematic structural diagram of a channel estimation apparatus according to Embodiment 2 of the present invention
  • FIG. 3 is a first matrix calculation in the channel estimation apparatus shown in FIG. Schematic diagram of the module
  • FIG. 4 is a schematic structural diagram of a second matrix calculation module in the channel estimation apparatus shown in FIG. 2;
  • FIG. 5 is a flowchart of a channel estimation method according to Embodiment 3 of the present invention.
  • FIG. 6 is a flowchart of a channel estimation method according to Embodiment 4 of the present invention.
  • FIG. 7 is a flowchart of a channel estimation method according to Embodiment 5 of the present invention.
  • a channel estimation apparatus includes: a matrix storage unit 101 for storing an intermediate inverse matrix.
  • the intermediate inverse matrix stored in the matrix storage unit 101 may store all the elements of each matrix in the intermediate inverse matrix; and may also store corresponding elements of each matrix according to the characteristics of each matrix in the intermediate inverse matrix. For example, when a matrix in the intermediate inverse matrix is a symmetric matrix, half of the elements of the matrix are stored, etc.; the intermediate inverse matrix may also be stored by other means, which is not repeated here.
  • the sub-inverse matrix corresponding to the training sequence number of the two users.
  • the sub-inverse matrix obtained by the matrix obtaining unit 102 may be obtained from the intermediate inverse matrix stored by the matrix storage unit 101 according to the mapping relationship between the training sequence number of the two users and the intermediate inverse matrix; It can also be from another matrix storage unit
  • the matrix generated by the training sequence corresponding to the training sequence number of the user performs a multiplication and addition logic operation to obtain a channel estimation factor.
  • the logical computing unit 1 0 3 performs a multiplication and addition logic operation on the matrix generated by the training matrix corresponding to the training sequence number of the two users, and may include the matrix inverse matrix and the training sequence generated.
  • the matrix performs multiplication logic operations, addition logic operations, and transpose operations, etc., and is not repeated here.
  • the channel estimation unit 104 is configured to complete the channel estimation process according to the channel estimation factor calculated by the logic calculation unit.
  • the channel estimation process is completed by the channel estimation unit 104, and
  • the channel estimation factor calculated by the logic calculation unit 103 is used for VAMOS two-user joint channel detection, and the detection result is obtained; and the detection result is used for the VAM0S strong and weak user joint channel detection and other subsequent detections, etc., - Narration.
  • the channel estimation apparatus multiplies the sub-inverse matrix corresponding to the training sequence number of the two users in the intermediate inverse matrix stored in the matrix storage unit by the logical calculation unit, and multiplies the matrix generated by the training sequence corresponding to the training sequence number. Add logic calculation to get the channel estimation factor to achieve channel estimation.
  • the embodiment of the invention solves the problem of large data storage capacity of the chip in the prior art.
  • the channel estimation apparatus provided in Embodiment 2 of the present invention includes: a d matrix storage module 201, configured to store a d matrix in an intermediate inverse matrix, where the d matrix is a (- ⁇ (4) -1 matrix.
  • d matrix storage module 201 stores the « ⁇ - ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ 1 matrix, A, ⁇ training sequence generated by the training sequence numbers corresponding to the two users 22 * 5 The matrix; since there are 16 possibilities for the training sequence corresponding to the training sequence number of the two users, there are 16 possibilities for each A and A.
  • the d matrix storage module 201 can store all elements of the d matrix through the first storage submodule; since ⁇ - ⁇ ⁇ ) - 1 ⁇ ) - 1 ) ⁇ /, that is, the d matrix is symmetric a matrix, so the d matrix storage module 201 can also store d through the second storage submodule 0010
  • the d matrix storage module 201 can also store the training sequence number of the user 1 in the two users through the third storage submodule is smaller than the training serial number of the user 2 in the two users.
  • the elements of the d matrix since the d matrix is both a symmetric matrix, and the impulse responses of A and B can be linearly transformed, the d matrix storage module 201 can store half of the elements of the d matrix through the fourth storage submodule, the users of the two users
  • the training sequence number of 1 is smaller than the element of the training sequence number of the user 2 of the two users; the d matrix storage module 201 can also store the elements of the d matrix by other means, which are not repeated here.
  • the d matrix storage module 201 stores the elements of the d matrix through the third storage submodule, since it is only necessary to store the elements of the d matrix of the training sequence number of the user 1 of the two users that are smaller than the training sequence number of the user 2 of the two users. And the training of user 1 and user 2 There are 16 possibilities for the training serial number.
  • the d matrix storage module 201 stores the data storage amount of the elements of the d matrix through the fourth storage submodule, which is similar to the above calculation process, and is not repeated here.
  • the inverse matrix storage module 202 is configured to store an inverse matrix in the intermediate inverse matrix, where the inverse matrix is a matrix.
  • the inverse matrix storage module 202 stores (a matrix, which is a 22*5 matrix generated by the training sequence corresponding to the training sequence numbers of the two users; corresponding to the training sequence numbers of the two users. There are 16 possibilities for the training sequence, so there are 16 possibilities for each and A.
  • the submodule stores the elements of the inverse matrix, since there are 16 possibilities for each A and A, and the inverse matrix is a matrix of 5*5, when storing the general elements, each needs to store 15 elements, so X-bit quantization is used.
  • the sub-inverse matrix obtaining module 203 is configured to obtain the sub-inverse matrices dj and m 1 corresponding to the training sequence numbers of the two users from the d matrix and the inverse matrix stored by the d matrix storage module and the inverse matrix storage module.
  • the inverse matrix d pn obtained by the sub-inverse matrix obtaining module 203 may be a mapping relationship between the d matrix and the inverse matrix stored by the d matrix storage module 201 and the inverse matrix storage module 202 according to the training sequence numbers of the two users. Obtained from the d matrix and the inverse matrix stored by the d matrix storage module 201 and the inverse matrix storage module 202; or may be the d matrix and the inverse matrix stored by the d matrix storage module 201 and the inverse matrix storage module 202 by other means. Obtained, no longer here - repeat.
  • the first matrix calculation module 204 is configured to perform multiplication and logical operations on the sub-inverse matrix d pn obtained by the sub-inverse matrix acquisition module and the matrix generated by the training sequence to obtain a b T +4 matrix.
  • the b matrix is The matrix generated by the training sequence may be A and A.
  • the first matrix calculation module 204 in this embodiment may further include:
  • the first calculation sub-module 2041 is configured to perform multiplication logic operations on A and A to obtain an A matrix.
  • the second calculation sub-module 2042 is configured to perform a multiplication logic operation on the A matrix and the sub-inverse matrix ⁇ to obtain a t matrix, where the t matrix is ⁇ ( ).
  • the third calculation sub-module 2043 is configured to perform a multiplication logic operation on the t matrix and the matrix to obtain a b matrix, where the b matrix is - ⁇ .
  • the fourth calculation sub-module 2044 is configured to perform a multiplication logic operation on the b matrix and A to obtain a matrix.
  • the fifth calculation sub-module 2045 is configured to perform a multiplication logic operation on the ⁇ matrix and A to obtain a ⁇ 4f matrix.
  • the logical operation is performed to obtain the matrix.
  • the second matrix calculation module 205 is configured to perform multiplication and logical calculation on the sub-inverse matrix d pn obtained by the sub-inverse matrix acquisition module and the matrix generated by the training sequence to obtain a matrix of + ⁇ .
  • the matrix is mi
  • the matrix generated by the training sequence may be a sum.
  • the second matrix calculation module 205 in this embodiment may further include:
  • the first calculation sub-module 2051 is configured to perform multiplication logic operations on ⁇ and , to obtain an A matrix.
  • the second calculation sub-module 2052 is configured to perform a multiplication logic operation on the A matrix and the sub-inverse matrix to obtain a t matrix, where the t matrix is ⁇ ( ).
  • the third calculation sub-module 2053 is configured to perform a multiplication logic operation on the t matrix and the matrix to obtain a b matrix, where the b matrix is - ⁇ .
  • the seventh calculation sub-module 2054 is configured to perform a multiplication logic operation on the b matrix and the t matrix to obtain a b*[] T matrix.
  • the eighth calculation sub-module 2055 is configured to perform a multiplication logic operation on the sub-inverse matrix ⁇ and the *[ ⁇ matrix to obtain a matrix, the matrix is! 3 ⁇ 4+ [ ⁇ .
  • the ninth calculation sub-module 2056 is configured to perform the multiplication logic operation on the matrix and the 4 to obtain a ⁇ matrix.
  • the tenth calculation sub-module 2057 is configured to perform multiplication logic operation on the b matrix and A to obtain a bAf matrix.
  • the eleventh calculation sub-module 2058 is configured to perform an addition logic operation on the ⁇ matrix and the b matrix to obtain a matrix.
  • the splicing module 206 is configured to splicing the b T + « matrix obtained by the first matrix calculation module and the ⁇ + ⁇ matrix obtained by the second matrix calculation module to obtain a channel estimation factor.
  • the channel estimation module 207 is configured to complete the channel estimation process according to the channel estimation factor calculated by the logical computing unit.
  • the channel estimation process is performed by the channel estimation module 207, and the channel estimation factor obtained by splicing the splicing module 206 is used for the joint channel detection of two users of the VAM0S, and the detection result is obtained; and the detection result is used for the VAM0S.
  • the joint channel detection and other subsequent detection of strong and weak users are not repeated here.
  • the embodiment of the invention solves the chip in the prior art The problem of large data storage.
  • the channel estimation method provided in Embodiment 3 of the present invention includes: a corresponding sub-inverse matrix.
  • the pre-stored intermediate inverse matrix may store all elements of each matrix in the intermediate inverse matrix; and may also store corresponding elements of each matrix according to characteristics of each matrix in the intermediate inverse matrix, for example, When a matrix in the intermediate inverse matrix is a symmetric matrix, half of the elements of the matrix are stored, etc.; the intermediate inverse matrix can also be stored by other means, which is not repeated here.
  • the sub-inverse matrix obtained by step 501 may be based on the mapping relationship between the training sequence numbers of the two users and the intermediate inverse matrix, and the intermediate inverse matrix stored in advance will not be further described herein.
  • Step 502 Perform a multiplication and logical operation on the matrix generated by the sub-inverse matrix and the training sequence corresponding to the training sequence numbers of the two users, to obtain a channel estimation factor.
  • the matrix generated by the training sequence corresponding to the training sequence number of the two users of the sub-inverse matrix is multiplied and logically operated, and may include multiplication logic operations and additions on the matrix generated by the sub-inverse matrix and the training sequence. Logical operations and transposition operations, etc., no longer here
  • Step 503 Complete a channel estimation process according to the calculated channel estimation factor.
  • the channel estimation process is completed in step 503, which may include using the channel estimation factor calculated in step 502 for the two-user joint channel detection of the VAM0S, and obtaining the detection result; and using the detection result for the VAM0S strength User joint channel detection and other subsequent detections are not repeated here.
  • a channel estimation method provided by an embodiment of the present invention by using a pre-stored intermediate inverse matrix
  • the sub-inverse matrix corresponding to the training sequence number of the two users is multiplied and logically calculated with the matrix generated by the training sequence corresponding to the training sequence number, thereby obtaining a channel estimation factor to implement channel estimation.
  • the embodiment of the invention solves the problem that the data storage amount of the chip in the prior art is large.
  • the channel estimation method provided in Embodiment 4 of the present invention includes: Step 601: Store a d matrix and an inverse matrix in an intermediate inverse matrix, where the d matrix is (A T A - ⁇ ⁇ ( ⁇ ) - 1 A ) - 1 matrix, the inverse matrix is the ( A ) - 1 matrix.
  • step 601 when the d matrix in the intermediate inverse matrix is stored, step 601 can store all the elements of the d matrix by method one; since ⁇ ( ⁇ " ⁇ ( ) - 1 ⁇ ) - 1 ) ⁇ is the d matrix Is a symmetric matrix, so step 601 can also store half of the elements of the d matrix by method two;
  • ⁇ ⁇ ⁇ and ⁇ can be linearly transformed, and the corresponding impulse response is also 1000
  • step 601 can also store, by method three, the elements of the d matrix of the user 1 whose training sequence number is smaller than the training sequence number of the user 2 of the two users; since the d matrix is both a symmetric matrix, and The impulse responses of A and B can be linearly transformed, so the step Step 601 may store half of the elements of the d matrix by method four, where the training sequence number of the user 1 of the two users is smaller than the element of the training sequence number of the user 2 of the two users; Step 601 may also store the elements of the d matrix by other methods. , no longer here - repeat.
  • step 601 stores the elements of the d matrix by method two, since each and A has 16 possibilities, and The d matrix is a 5*5 matrix.
  • step 601 stores the elements of the d matrix by method two, since each and A has 16 possibilities, and The d matrix is a 5*5 matrix.
  • Step 601 is stored by Method Three.For the elements of the d matrix, since only the elements of the d matrix of the user 1 whose training sequence number is smaller than the training sequence number of the user 2 of the two users are stored, and the training sequence numbers of the user 1 and the user 2 are 16 It is possible, therefore, when the training sequence number of user 1 is 0, 15 d matrices need to be stored; when the training sequence number of user 1 is 1, 14 d matrices need to be stored; when the training sequence number of user 1 is 2 , need to store 14 d matrices; ...; When user 1's training serial number is 15, you need to store 0 d matrices, so the d matrix has a total of 15 + 14 + 13 + ...
  • Step 601 stores the data storage amount of the elements of the d matrix by Method 4, which is similar to the above calculation process, and no longer - Narration.
  • step 601 may store all elements of the inverse matrix by method five; due to That is, the inverse matrix is a symmetric matrix, so step 601 can also store half of the elements of the inverse matrix by method six; step 601 can also store the elements of the inverse matrix by other methods, which are not repeated here.
  • the sub-inverse matrix in step 602 may be obtained from the pre-stored intermediate inverse matrix according to the mapping relationship between the training sequence numbers of the two users and the intermediate inverse matrix.
  • Step 603 Perform multiplication and addition logic on the matrix generated by the training matrix of the two inverse training matrices corresponding to the training sequence numbers of the two users to obtain a channel estimation factor.
  • the matrix generated by the corresponding training sequence performs multiplication and addition logic operations, and may include multiplication logic operations, addition logic operations, and transposition operations on the matrix generated by the sub-inverse matrix and the training sequence, and will not be repeated here.
  • Step 604 Complete a channel estimation process according to the calculated channel estimation factor.
  • the channel estimation process is completed by step 604, which may include
  • the channel estimation factor calculated in step 603 is used for two user joint channel detection of VAM0S, and the detection result is obtained; and the detection result is used for joint channel detection of VAM0S strong and weak users and other subsequent detections, etc., .
  • the channel estimation method provided by the embodiment of the present invention performs multiplication and addition logic calculation on a matrix generated by a training sequence corresponding to a training sequence number by using a sub-inverse matrix corresponding to training sequence numbers of two users in a pre-stored intermediate inverse matrix, thereby A channel estimation factor is obtained to achieve channel estimation.
  • the embodiment of the invention solves the problem that the data storage amount of the chip in the prior art is large.
  • the channel estimation method provided in Embodiment 5 of the present invention includes: Step 701: Store a d matrix and an inverse matrix in an intermediate inverse matrix, where the d matrix is (A T A - ⁇ ⁇ ( ⁇ ) - 1 A ) - 1 matrix, the inverse matrix is the ( A ) - 1 matrix.
  • 4 is a 22*5 matrix generated by the training sequence corresponding to the training sequence numbers of the two users; due to the training sequence of the two users There are 16 possibilities for the training sequence corresponding to the number, so there are 16 possibilities for each and A.
  • step 701 may store all the elements of the d matrix by method one; since ⁇ ( ⁇ " ⁇ ( ) - 1 ⁇ ) - 1 ) ⁇ is the d matrix Is a symmetric matrix, so step 701 can also store one of the d matrices by method two. Semi-element; due to A
  • P ie A and B can be linearly transformed, and the corresponding impulse response is also 1000
  • step 701 can also store, by method three, the elements of the d matrix of the user 1 whose training sequence number is smaller than the training sequence number of the user 2 of the two users; since the d matrix is both a symmetric matrix, and The impulse responses of A and B can be linearly transformed, so step 701 can store half of the elements of the d matrix by method four, wherein the training sequence number of user 1 of the two users is smaller than the element of the training sequence number of user 2 of the two users; 701 can also store the elements of the d matrix by other methods, no longer here - repeat.
  • the training sequence number of user 1 is smaller than the element of the d matrix of the training sequence number of user 2 of the two users, and the training sequence numbers of user 1 and user 2 have 16 possibilities, so when the training sequence number of user 1 is When 0, it is necessary to store 15 d matrices; When the training sequence number of the user 1 is 1, 14 d matrices need to be stored; when the training sequence number of the user 1 is 2, 14 d matrices need to be stored; ...; when the training serial number of the user 1 is When it is 15, it needs to store 0 d matrices, so the d matrix has 15 + 14+13+...
  • Step 701 stores the data storage amount of the elements of the d matrix by method four, which is similar to the above calculation process, and is not repeated here.
  • Step 702 Obtain sub-inverse matrices ⁇ and m corresponding to training sequence numbers of two users from the d matrix and the inverse matrix.
  • the inverse matrix d pn obtained in step 702 may be based on the mapping relationship between the training sequence numbers of the two users and the d matrix and the inverse matrix stored in step 701, from the d matrix and the inverse matrix stored in step 701.
  • the obtained data may also be obtained from the d matrix and the inverse matrix stored in step 701 by other means, and is not described here again.
  • Step 703 multiplying and adding the sub-inverse matrix d pn and the matrix generated by the training sequence The operation is calculated to obtain the bT ⁇ +A matrix.
  • the b matrix is -m x ( A )*d, and the matrix generated by the training sequence may be A and A.
  • the process of obtaining the matrix by step 703 may specifically include:
  • a and A are multiplied by logical operations to obtain an A matrix.
  • Step 704 Multiply and add the sub-inverse matrix d pn to the matrix generated by the training sequence to obtain a ⁇ + matrix.
  • the matrix in the ⁇ +b ⁇ matrix obtained by step 704, the matrix is m 1 + b* [m, ( A )] ⁇ , and the matrix generated by the training sequence may be ⁇ and A.
  • the process of the ⁇ + ⁇ matrix obtained in step 704 may specifically include:
  • the A matrix and the sub-inverse matrix ⁇ are multiplied by logical operations to obtain a t matrix, and the t matrix is! ! ⁇ ( 4).
  • the matrix and A are multiplied by logical operations to obtain an ⁇ matrix.
  • Step 705 splicing the matrix with the ⁇ matrix to obtain a channel estimation factor.
  • Step 706 Complete a channel estimation process according to the calculated channel estimation factor.
  • the channel estimation process is completed in step 706, which may include using the channel estimation factor calculated in step 705 for two user joint channel detection of VAM0S, and obtaining a detection result; and using the detection result for the VAM0S strength User joint channel detection and other subsequent detections are not repeated here.
  • the channel estimation method provided by the embodiment of the present invention performs multiplication and addition logic calculation on a matrix generated by a training sequence corresponding to a training sequence number by using a sub-inverse matrix corresponding to training sequence numbers of two users in a pre-stored intermediate inverse matrix, thereby A channel estimation factor is obtained to achieve channel estimation.
  • the embodiment of the invention solves the data storage of the chip in the prior art A large amount of problems.
  • the channel estimation method and apparatus provided by the embodiments of the present invention can be applied to the VAMO S technology to detect the correlation between a new voice channel and an original voice channel.
  • RAM random access memory
  • ROM read only memory
  • EEPROM electrically programmable ROM
  • EEPROM electrically erasable programmable ROM
  • registers hard disk, removable disk, CD-ROM, or technical field Any other form of storage medium known.

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Abstract

La présente invention se rapporte au domaine de la communication, et concerne un procédé et un système d'estimation de canal. L'invention résout le problème de la technique antérieure lié au fait que la quantité de données stockées dans une puce est très importante. Le système comprend: une mémoire matricielle (101) pour stocker des matrices intermédiaires inverses; une unité d'acquisition de matrices (102) pour acquérir des sous-matrices inverses correspondant à des numéros de séquences d'apprentissage de deux utilisateurs et provenant des matrices intermédiaires inverses stockées dans la mémoire matricielle; une unité de calcul logique (103) pour appliquer une opération logique de multiplication et d'addition aux sous-matrices inverses acquises par l'unité d'acquisition de matrices, et aux matrices générées des séquences d'apprentissage correspondant aux numéros de séquences d'apprentissage des deux utilisateurs, et pour acquérir des facteurs d'estimation de canal; une unité d'estimation de canal (104) pour réaliser un processus d'estimation de canal en fonction des facteurs d'estimation de canal calculés par l'unité de calcul logique.
PCT/CN2011/073249 2011-04-25 2011-04-25 Procédé et système d'estimation de canal WO2011110129A2 (fr)

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CN103427933B (zh) * 2012-05-15 2018-06-08 深圳市中兴微电子技术有限公司 矢量处理器及其生成扰码序列的方法

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WO2009124568A1 (fr) * 2008-04-11 2009-10-15 Trident Microsystems (Far East) Ltd. Procédé et dispositif à circuit permettant une estimation de canal basée sur une corrélation et une mise en forme du signal dans un récepteur dtmb

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