WO2011110129A2

WO2011110129A2 - Channel estimation method and apparatus

Info

Publication number: WO2011110129A2
Application number: PCT/CN2011/073249
Authority: WO
Inventors: 綦睿; 袁佳杰
Original assignee: 华为技术有限公司
Priority date: 2011-04-25
Filing date: 2011-04-25
Publication date: 2011-09-15
Also published as: CN102246478B; WO2011110129A3; CN102246478A

Abstract

The present invention relates to the field of communication, and discloses a channel estimation method and apparatus. The present invention resolves the problem that amount of data stored in a chip is very large in the prior art. The apparatus includes: a matrix storage unit (101) for storing intermediate inverse matrices; a matrix acquirement unit (102) for acquiring inverse submatrices corresponding to numbers of training sequences of two users from the intermediate inverse matrices stored in the matrix storage unit; a logic calculation unit (103) for implementing multiplication and addition logical operation to the inverse submatrices acquired by the matrix acquirement unit and matrices generated from the training sequences corresponding to the numbers of the training sequences of the two users, and acquiring channel estimation factors; a channel estimation unit (104) for completing channel estimation process according to the channel estimation factors calculated by the logic calculation unit.

Description

Channel estimation method and device

The present invention relates to the field of communications, and in particular, to a channel estimation method and apparatus.

Background technique

As the number of Global System for Mobile Communication (GSM) subscribers increases, so does the demand for voice services, putting tremendous pressure on existing networks. In order to alleviate the pressure on the existing network, Voice Service Over Adaptive Mul t i-user Orthogonal Sub Channels (VAMOS) technology is proposed, which multiplexes two users into the same time slot. The voice capacity of each base transceiver station (BTS) is improved, so that the existing network hardware resources can be more fully utilized, and the utilization of spectrum resources is improved.

In the VAM0S technology, two users are multiplexed on the same time slot by adding a new voice channel to the original voice channel, that is, if the first voice channel is occupied, one and the first voice channel are used. The orthogonal subchannel will be used as another voice channel to achieve double the voice capacity. In order to maximize the voice capacity of each BTS, the introduction of the new voice channel has the following principles: The new voice channel has the lowest cross-correlation with the original voice channel. In the prior art, the VAM0S two-user joint channel estimation algorithm is used to estimate the correlation between the new voice channel and the original voice channel, and the specific process includes: first, by using two users that can represent the new voice channel and the original voice channel. The training sequence number obtains the channel estimation factor; then the channel estimation factor is used for the VAM0S two-user joint channel detection to obtain the channel detection result; finally, the result is used for the VAM0S strong and weak user joint channel detection and subsequent detection. The process of obtaining a channel estimation factor by a training sequence number of two users that can represent a new voice channel and an original voice channel includes: estimating from a pre-stored channel In the factor, a channel estimation factor corresponding to the training sequence number of the two users is obtained, and the pre-stored channel estimation factor is: y = (A ^T A) - ^τ , where Α is a matrix of 44*20, having the following

0 0

Format: A , where A is a matrix of 22*5, j = 0, 1; A is

0 ⁰ A is generated by the training sequence corresponding to the training sequence numbers of the two users; since there are 16 possibilities for the training sequences corresponding to the training sequence numbers of the two users, there are 16 possibilities for each. It can be seen from the above process that the channel estimation process is at the forefront of the two-user joint channel estimation algorithm of VAM0S, and its computational accuracy and implementation method have a great influence on the two-user joint channel estimation algorithm of VAM0S. In the process of implementing the present invention, the inventors have found that since the channel estimation factor needs to be stored in advance so that the channel estimation factor is quantized by X bits, the data storage amount of the chip is 2*22*5*16*16*x=56320x bits. The chip has a large amount of data storage, which increases the cost of the chip.

Summary of the invention

Embodiments of the present invention provide a channel estimation method and apparatus capable of storing a small amount of data to implement channel estimation.

In one aspect, a channel estimation apparatus is provided, including:

a matrix storage unit, configured to store an intermediate inverse matrix;

Matrix acquisition unit,

Taking the sub-inverse matrix corresponding to the training sequence numbers of the two users;

Logical computing unit,

The matrix generated by the training sequence corresponding to the training sequence numbers of the two users is subjected to multiplication and addition logic operations to obtain a channel estimation factor;

And a channel estimation unit, configured to complete a channel estimation process according to the channel estimation factor calculated by the logic calculation unit.

In another aspect, a channel estimation method is provided, including: acquiring a sub-inverse matrix corresponding to training sequence numbers of two users from a pre-stored intermediate inverse matrix; and training the sub-inverse matrix with the two users The matrix generated by the training sequence corresponding to the serial number is subjected to multiplication and addition logic operations to obtain a channel estimation factor; and the channel estimation process is completed according to the calculated channel estimation factor. The channel estimation method and apparatus provided by the embodiment of the present invention, the matrix generated by the training sequence corresponding to the training sequence number of the two users in the intermediate inverse matrix stored by the matrix storage unit by the logic calculation unit, and the matrix generated by the training sequence corresponding to the training sequence number The multiplication and addition logic calculation is performed to obtain a channel estimation factor to complete channel estimation. Since only the intermediate inverse matrix needs to be stored,

When the X-bit quantization is performed, the maximum data storage amount is X*(16*25+16*16*25)=6800x bits, so that the technical solution provided by the embodiment of the present invention can reduce the data storage amount of the chip, thereby reducing the area of the chip. , effectively reduce the cost of the chip. The embodiment of the invention solves the problem that the data storage amount of the chip in the prior art is large.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings to be used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description It is merely some embodiments of the present invention, and those skilled in the art can obtain other drawings according to the drawings without any creative work.

1 is a schematic structural diagram of a channel estimation apparatus according to Embodiment 1 of the present invention; FIG. 2 is a schematic structural diagram of a channel estimation apparatus according to Embodiment 2 of the present invention; FIG. 3 is a first matrix calculation in the channel estimation apparatus shown in FIG. Schematic diagram of the module;

4 is a schematic structural diagram of a second matrix calculation module in the channel estimation apparatus shown in FIG. 2;

FIG. 5 is a flowchart of a channel estimation method according to Embodiment 3 of the present invention;

6 is a flowchart of a channel estimation method according to Embodiment 4 of the present invention;

FIG. 7 is a flowchart of a channel estimation method according to Embodiment 5 of the present invention.

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention. In order to solve the problem of large amount of data storage inside the chip in the prior art, a channel estimation method and apparatus are proposed.

As shown in FIG. 1, a channel estimation apparatus according to Embodiment 1 of the present invention includes: a matrix storage unit 101 for storing an intermediate inverse matrix.

In this embodiment, the intermediate inverse matrix stored in the matrix storage unit 101 may store all the elements of each matrix in the intermediate inverse matrix; and may also store corresponding elements of each matrix according to the characteristics of each matrix in the intermediate inverse matrix. For example, when a matrix in the intermediate inverse matrix is a symmetric matrix, half of the elements of the matrix are stored, etc.; the intermediate inverse matrix may also be stored by other means, which is not repeated here. The sub-inverse matrix corresponding to the training sequence number of the two users.

In this embodiment, the sub-inverse matrix obtained by the matrix obtaining unit 102 may be obtained from the intermediate inverse matrix stored by the matrix storage unit 101 according to the mapping relationship between the training sequence number of the two users and the intermediate inverse matrix; It can also be from another matrix storage unit

1 01 is stored in the intermediate inverse matrix, which is no longer mentioned here. The matrix generated by the training sequence corresponding to the training sequence number of the user performs a multiplication and addition logic operation to obtain a channel estimation factor.

In this embodiment, the logical computing unit 1 0 3 performs a multiplication and addition logic operation on the matrix generated by the training matrix corresponding to the training sequence number of the two users, and may include the matrix inverse matrix and the training sequence generated. The matrix performs multiplication logic operations, addition logic operations, and transpose operations, etc., and is not repeated here.

The channel estimation unit 104 is configured to complete the channel estimation process according to the channel estimation factor calculated by the logic calculation unit.

In this embodiment, the channel estimation process is completed by the channel estimation unit 104, and The channel estimation factor calculated by the logic calculation unit 103 is used for VAMOS two-user joint channel detection, and the detection result is obtained; and the detection result is used for the VAM0S strong and weak user joint channel detection and other subsequent detections, etc., - Narration.

The channel estimation apparatus provided by the embodiment of the present invention multiplies the sub-inverse matrix corresponding to the training sequence number of the two users in the intermediate inverse matrix stored in the matrix storage unit by the logical calculation unit, and multiplies the matrix generated by the training sequence corresponding to the training sequence number. Add logic calculation to get the channel estimation factor to achieve channel estimation. The maximum technical data storage capacity is X* (16*25 + 16*16*25)=6800x bits, so that the technical solution provided by the embodiment of the present invention can be used. Reduce the amount of data storage of the chip, thereby reducing the area of the chip and effectively reducing the cost of the chip. The embodiment of the invention solves the problem of large data storage capacity of the chip in the prior art.

As shown in FIG. 2, the channel estimation apparatus provided in Embodiment 2 of the present invention includes: a d matrix storage module 201, configured to store a d matrix in an intermediate inverse matrix, where the d matrix is a (-^(4) ^-1 matrix.

In the present embodiment, d matrix storage module 201 stores the «Α-Α ^ ^ Α ^^ ΑΓ 1 matrix, A, Α training sequence generated by the training sequence numbers corresponding to the two users 22 * 5 The matrix; since there are 16 possibilities for the training sequence corresponding to the training sequence number of the two users, there are 16 possibilities for each A and A.

In this embodiment, the d matrix storage module 201 can store all elements of the d matrix through the first storage submodule; since ^^^ -^ ^^ ) - ¹ ^^) - ¹ ) ^/, that is, the d matrix is symmetric a matrix, so the d matrix storage module 201 can also store d through the second storage submodule

0010

A 0 0 0001

When B = ^{^P,} τ = ΡΑ Ί, i.e. Α and Β be converted linearly OA ₁ 0 A 1000

0100, its corresponding impulse response can also be linearly transformed, so the d matrix storage module 201 can also store the training sequence number of the user 1 in the two users through the third storage submodule is smaller than the training serial number of the user 2 in the two users. The elements of the d matrix; since the d matrix is both a symmetric matrix, and the impulse responses of A and B can be linearly transformed, the d matrix storage module 201 can store half of the elements of the d matrix through the fourth storage submodule, the users of the two users The training sequence number of 1 is smaller than the element of the training sequence number of the user 2 of the two users; the d matrix storage module 201 can also store the elements of the d matrix by other means, which are not repeated here.

In this embodiment, the d matrix storage module 201 stores the elements of the d matrix through the first storage submodule, and when the X bit quantization is used, the data storage amount is 16*16*25*x=6656x bits; the d matrix storage module 201 passes The second storage submodule stores the elements of the d matrix. When the X bit quantization is used, the data storage amount is 16*16*15*x=3840x bits; the d matrix storage module 201 stores the elements of the d matrix through the third storage submodule, In the case of X-bit quantization, the data storage amount is 120*25*x=3000x bits; the d-matrix storage module 201 stores the elements of the d-matrix through the fourth storage sub-module, and when the X-bit quantization is used, the data storage amount is 120*15*x. =1800x bits. Wherein, when the d matrix storage module 201 stores the elements of the d matrix through the first storage submodule, since each and A has 16 possibilities, and the d matrix is a matrix of 5*5, when using X-bit quantization, data storage The quantity is 16*16*25*x=6656x bits; the d matrix storage module 201 stores the elements of the d matrix through the second storage submodule, since each 4

A has 16 possibilities, and the d matrix is a matrix of 5*5. When storing half of the elements, each needs to store 15 elements. Therefore, when using X-bit quantization, the data storage capacity is 16*16*15*x=3840x. The d matrix storage module 201 stores the elements of the d matrix through the third storage submodule, since it is only necessary to store the elements of the d matrix of the training sequence number of the user 1 of the two users that are smaller than the training sequence number of the user 2 of the two users. And the training of user 1 and user 2 There are 16 possibilities for the training serial number. Therefore, when the training sequence number of user 1 is 0, 15 d matrices need to be stored; when the training sequence number of user 1 is 1, 14 d matrices need to be stored; When the training serial number is 2, 14 d matrices need to be stored; ......; when the user

When the training sequence number of 1 is 15, it needs to store 0 d matrices, so the d matrix has 15 + 14+13+... +1 + 0=120, so when using x-bit quantization, the data storage capacity is 120*25. *x=3000x bits; The d matrix storage module 201 stores the data storage amount of the elements of the d matrix through the fourth storage submodule, which is similar to the above calculation process, and is not repeated here.

The inverse matrix storage module 202 is configured to store an inverse matrix in the intermediate inverse matrix, where the inverse matrix is a matrix.

In this embodiment, the inverse matrix storage module 202 stores (a matrix, which is a 22*5 matrix generated by the training sequence corresponding to the training sequence numbers of the two users; corresponding to the training sequence numbers of the two users. There are 16 possibilities for the training sequence, so there are 16 possibilities for each and A. In this embodiment, the inverse matrix storage module 202 can store all elements of the inverse matrix through the fifth storage submodule; since (=(() The inverse matrix is a symmetric matrix, so the inverse matrix storage module 202 can also store half of the elements of the inverse matrix through the sixth storage sub-module; the inverse matrix storage module 202 can also store the elements of the inverse matrix by other means, and will not be described herein. .

In this embodiment, the inverse matrix storage module 202 stores the elements of the inverse matrix through the fifth storage submodule, and when using X-bit quantization, the data storage amount is 15*25*x=400x bits; the inverse matrix storage module 202 passes the sixth The storage sub-module stores the elements of the inverse matrix. When X-bit quantization is used, the data storage amount is 16*15*x=240x bits. Wherein, the inverse matrix storage module 202 stores the elements of the inverse matrix through the fifth storage submodule, due to each

A has 16 possibilities, and the inverse matrix is a matrix of 5*5, so when using X-bit quantization, the data storage amount is 15*25*x=400x bits; the inverse matrix storage module 202 passes the sixth storage. When the submodule stores the elements of the inverse matrix, since there are 16 possibilities for each A and A, and the inverse matrix is a matrix of 5*5, when storing the general elements, each needs to store 15 elements, so X-bit quantization is used. At the time, the amount of data storage is 16*15*x=240x bits.

The sub-inverse matrix obtaining module 203 is configured to obtain the sub-inverse matrices dj and m ₁ corresponding to the training sequence numbers of the two users from the d matrix and the inverse matrix stored by the d matrix storage module and the inverse matrix storage module.

In this embodiment, the inverse matrix d pn obtained by the sub-inverse matrix obtaining module 203 may be a mapping relationship between the d matrix and the inverse matrix stored by the d matrix storage module 201 and the inverse matrix storage module 202 according to the training sequence numbers of the two users. Obtained from the d matrix and the inverse matrix stored by the d matrix storage module 201 and the inverse matrix storage module 202; or may be the d matrix and the inverse matrix stored by the d matrix storage module 201 and the inverse matrix storage module 202 by other means. Obtained, no longer here - repeat.

The first matrix calculation module 204 is configured to perform multiplication and logical operations on the sub-inverse matrix d pn obtained by the sub-inverse matrix acquisition module and the matrix generated by the training sequence to obtain a b ^T +4 matrix.

In this embodiment, in the bT^+A matrix obtained by the first matrix calculation module 204, the b matrix is

The matrix generated by the training sequence may be A and A.

Further, as shown in FIG. 3, the first matrix calculation module 204 in this embodiment may further include:

The first calculation sub-module 2041 is configured to perform multiplication logic operations on A and A to obtain an A matrix.

The second calculation sub-module 2042 is configured to perform a multiplication logic operation on the A matrix and the sub-inverse matrix ^ to obtain a t matrix, where the t matrix is ^( ).

The third calculation sub-module 2043 is configured to perform a multiplication logic operation on the t matrix and the matrix to obtain a b matrix, where the b matrix is -^. The fourth calculation sub-module 2044 is configured to perform a multiplication logic operation on the b matrix and A to obtain a matrix.

The fifth calculation sub-module 2045 is configured to perform a multiplication logic operation on the ^ matrix and A to obtain a ^4f matrix. The logical operation is performed to obtain the matrix.

The second matrix calculation module 205 is configured to perform multiplication and logical calculation on the sub-inverse matrix d pn obtained by the sub-inverse matrix acquisition module and the matrix generated by the training sequence to obtain a matrix of +^.

In this embodiment, in the ^+b matrix obtained by the second matrix calculation module 205, the matrix is _mi

The matrix generated by the training sequence may be a sum.

Further, as shown in FIG. 4, the second matrix calculation module 205 in this embodiment may further include:

The first calculation sub-module 2051 is configured to perform multiplication logic operations on Α and , to obtain an A matrix.

The second calculation sub-module 2052 is configured to perform a multiplication logic operation on the A matrix and the sub-inverse matrix to obtain a t matrix, where the t matrix is ^( ).

The third calculation sub-module 2053 is configured to perform a multiplication logic operation on the t matrix and the matrix to obtain a b matrix, where the b matrix is -^.

The seventh calculation sub-module 2054 is configured to perform a multiplication logic operation on the b matrix and the t matrix to obtain a b*[] ^T matrix.

The eighth calculation sub-module 2055 is configured to perform a multiplication logic operation on the sub-inverse matrix ^ and the *[^ matrix to obtain a matrix, the matrix is! 3⁄4+ [^.

The ninth calculation sub-module 2056 is configured to perform the multiplication logic operation on the matrix and the 4 to obtain a ^ matrix. The tenth calculation sub-module 2057 is configured to perform multiplication logic operation on the b matrix and A to obtain a bAf matrix.

The eleventh calculation sub-module 2058 is configured to perform an addition logic operation on the ^ matrix and the b matrix to obtain a matrix.

The splicing module 206 is configured to splicing the b ^T +« matrix obtained by the first matrix calculation module and the α^τ+Μ matrix obtained by the second matrix calculation module to obtain a channel estimation factor.

.

The channel estimation module 207 is configured to complete the channel estimation process according to the channel estimation factor calculated by the logical computing unit.

In this embodiment, the channel estimation process is performed by the channel estimation module 207, and the channel estimation factor obtained by splicing the splicing module 206 is used for the joint channel detection of two users of the VAM0S, and the detection result is obtained; and the detection result is used for the VAM0S. The joint channel detection and other subsequent detection of strong and weak users are not repeated here.

In the channel estimation apparatus provided by the embodiment of the present invention, when X-bit quantization is used, the maximum data storage amount is X* (16*25 + 16*16*25) = 6800x bits, which is only 6800x/56320x=12 of the original algorithm. 07%, can save a lot of storage space.

The channel estimation apparatus provided by the embodiment of the present invention multiplies the sub-inverse matrix corresponding to the training sequence number of two users in the intermediate inverse matrix stored in the matrix storage unit by the logic calculation unit, and multiplies the matrix generated by the training sequence corresponding to the training sequence number. Add logic calculation to get the channel estimation factor to achieve channel estimation. Since only the intermediate inverse matrix is stored, that is, when the X-bit quantization is used, the maximum data storage amount is X*(16*25+16*16*25)=6800x bits, so that the technical solution provided by the embodiment of the present invention can be reduced. The amount of data stored in the chip, thereby reducing the area of the chip, effectively reducing the cost of the chip. The embodiment of the invention solves the chip in the prior art The problem of large data storage.

As shown in FIG. 5, the channel estimation method provided in Embodiment 3 of the present invention includes: a corresponding sub-inverse matrix.

In this embodiment, the pre-stored intermediate inverse matrix may store all elements of each matrix in the intermediate inverse matrix; and may also store corresponding elements of each matrix according to characteristics of each matrix in the intermediate inverse matrix, for example, When a matrix in the intermediate inverse matrix is a symmetric matrix, half of the elements of the matrix are stored, etc.; the intermediate inverse matrix can also be stored by other means, which is not repeated here.

In this embodiment, the sub-inverse matrix obtained by step 501 may be based on the mapping relationship between the training sequence numbers of the two users and the intermediate inverse matrix, and the intermediate inverse matrix stored in advance will not be further described herein.

Step 502: Perform a multiplication and logical operation on the matrix generated by the sub-inverse matrix and the training sequence corresponding to the training sequence numbers of the two users, to obtain a channel estimation factor.

In this embodiment, the matrix generated by the training sequence corresponding to the training sequence number of the two users of the sub-inverse matrix is multiplied and logically operated, and may include multiplication logic operations and additions on the matrix generated by the sub-inverse matrix and the training sequence. Logical operations and transposition operations, etc., no longer here

"""" ' "Like.

Step 503: Complete a channel estimation process according to the calculated channel estimation factor. In this embodiment, the channel estimation process is completed in step 503, which may include using the channel estimation factor calculated in step 502 for the two-user joint channel detection of the VAM0S, and obtaining the detection result; and using the detection result for the VAM0S strength User joint channel detection and other subsequent detections are not repeated here.

A channel estimation method provided by an embodiment of the present invention, by using a pre-stored intermediate inverse matrix The sub-inverse matrix corresponding to the training sequence number of the two users is multiplied and logically calculated with the matrix generated by the training sequence corresponding to the training sequence number, thereby obtaining a channel estimation factor to implement channel estimation. The maximum amount of data storage is X* (16*25 + 16*16*25)=6800x bits, so that the technical solution provided by the embodiment of the present invention is provided. It can reduce the amount of data storage of the chip, thereby reducing the area of the chip and effectively reducing the cost of the chip. The embodiment of the invention solves the problem that the data storage amount of the chip in the prior art is large.

As shown in FIG. 6, the channel estimation method provided in Embodiment 4 of the present invention includes: Step 601: Store a d matrix and an inverse matrix in an intermediate inverse matrix, where the d matrix is (A ^T A - Α ^Τ ( ^Τ ) - ¹ A ) - ¹ matrix, the inverse matrix is the ( A ) - ¹ matrix.

In this embodiment, in the d matrix and the inverse matrix stored in step 601, a 22*5 matrix generated by the training sequence corresponding to the training sequence numbers of the two users; due to the training sequence numbers of the two users There are 16 possibilities for the corresponding training sequence, so each and A has 16 possibilities.

In this embodiment, when the d matrix in the intermediate inverse matrix is stored, step 601 can store all the elements of the d matrix by method one; since ^^( ^ " ^( ) - ¹ ^^) - ¹ ) ^ is the d matrix Is a symmetric matrix, so step 601 can also store half of the elements of the d matrix by method two;

0010

0001

Ρ Α Α and Β can be linearly transformed, and the corresponding impulse response is also 1000

0100 can be linearly transformed, so step 601 can also store, by method three, the elements of the d matrix of the user 1 whose training sequence number is smaller than the training sequence number of the user 2 of the two users; since the d matrix is both a symmetric matrix, and The impulse responses of A and B can be linearly transformed, so the step Step 601 may store half of the elements of the d matrix by method four, where the training sequence number of the user 1 of the two users is smaller than the element of the training sequence number of the user 2 of the two users; Step 601 may also store the elements of the d matrix by other methods. , no longer here - repeat.

In this embodiment, step 601 stores the elements of the d matrix by method one, and when the X bit is used for quantization, the data storage amount is 16*16*25*x=6656x bits; step 601 stores the elements of the d matrix by method two, adopting In the case of X-bit quantization, the data storage amount is 16*16*15*x=3840x bits; Step 601 stores the elements of the d matrix by Method 3, and when X-bit quantization is used, the data storage amount is 120*25*x=3000x bits; Step 601 stores the elements of the d matrix by method four, and when the X-bit quantization is used, when the first storage sub-module stores the elements of the d-matrix, there are 16 possibilities for each A and A, and the d matrix is 5*. 5 matrix, so when using X-bit quantization, the data storage amount is 16*16*25*x=6656x bits; when step 601 stores the elements of the d matrix by method two, since each and A has 16 possibilities, and The d matrix is a 5*5 matrix. When storing half of the elements, each of the 15 elements needs to be stored. Therefore, when using X-bit quantization, the data storage amount is 16*16*15*x=3840x bits; Step 601 is stored by Method Three.For the elements of the d matrix, since only the elements of the d matrix of the user 1 whose training sequence number is smaller than the training sequence number of the user 2 of the two users are stored, and the training sequence numbers of the user 1 and the user 2 are 16 It is possible, therefore, when the training sequence number of user 1 is 0, 15 d matrices need to be stored; when the training sequence number of user 1 is 1, 14 d matrices need to be stored; when the training sequence number of user 1 is 2 , need to store 14 d matrices; ...; When user 1's training serial number is 15, you need to store 0 d matrices, so the d matrix has a total of 15 + 14 + 13 + ... + 1 + 0 = 120, so when using X-bit quantization, the data storage amount is 120*25*x=3000x bits; Step 601 stores the data storage amount of the elements of the d matrix by Method 4, which is similar to the above calculation process, and no longer - Narration.

In this embodiment, step 601 may store all elements of the inverse matrix by method five; due to

That is, the inverse matrix is a symmetric matrix, so step 601 can also store half of the elements of the inverse matrix by method six; step 601 can also store the elements of the inverse matrix by other methods, which are not repeated here.

In this embodiment, step 601 stores the elements of the inverse matrix by method five, and when the X-bit quantization is used, the data storage amount is 15*25*χ=400χ bits; step 601 stores the elements of the inverse matrix by method six, adopts X bits. When quantizing, the amount of data stored is 16*15*χ=240χ bits. Wherein step 601 stores the elements of the inverse matrix by method five, since there are 16 possibilities for each Α and Α, and the inverse matrix is a matrix of 5*5, the X step 601 is used to store the elements of the inverse matrix by method six. Since, since each and A have 16 possibilities, and the inverse matrix is a matrix of 5*5, when storing general elements, each needs to store 15 elements, so when using X-bit quantization, the data storage amount is 16*. 15*x=240x bits. The corresponding sub-inverse matrix.

In this embodiment, the sub-inverse matrix in step 602 may be obtained from the pre-stored intermediate inverse matrix according to the mapping relationship between the training sequence numbers of the two users and the intermediate inverse matrix.

Step 603: Perform multiplication and addition logic on the matrix generated by the training matrix of the two inverse training matrices corresponding to the training sequence numbers of the two users to obtain a channel estimation factor. The matrix generated by the corresponding training sequence performs multiplication and addition logic operations, and may include multiplication logic operations, addition logic operations, and transposition operations on the matrix generated by the sub-inverse matrix and the training sequence, and will not be repeated here.

Step 604: Complete a channel estimation process according to the calculated channel estimation factor. In this embodiment, the channel estimation process is completed by step 604, which may include The channel estimation factor calculated in step 603 is used for two user joint channel detection of VAM0S, and the detection result is obtained; and the detection result is used for joint channel detection of VAM0S strong and weak users and other subsequent detections, etc., .

In the channel estimation method provided by the embodiment of the present invention, when X-bit quantization is used, the maximum data storage amount is X* (16*25 + 16*16*25) = 6800x bits, which is only 6800x/56320x=12 of the original algorithm. 07%, can save a lot of storage space.

The channel estimation method provided by the embodiment of the present invention performs multiplication and addition logic calculation on a matrix generated by a training sequence corresponding to a training sequence number by using a sub-inverse matrix corresponding to training sequence numbers of two users in a pre-stored intermediate inverse matrix, thereby A channel estimation factor is obtained to achieve channel estimation. The maximum amount of data storage is X* (16*25 + 16*16*25)=6800x bits, so that the technical solution provided by the embodiment of the present invention is provided. It can reduce the amount of data storage of the chip, thereby reducing the area of the chip and effectively reducing the cost of the chip. The embodiment of the invention solves the problem that the data storage amount of the chip in the prior art is large.

As shown in FIG. 7, the channel estimation method provided in Embodiment 5 of the present invention includes: Step 701: Store a d matrix and an inverse matrix in an intermediate inverse matrix, where the d matrix is (A ^T A - Α ^Τ ( ^Τ ) - ¹ A ) - ¹ matrix, the inverse matrix is the ( A ) - ¹ matrix.

In this embodiment, in the d matrix and the inverse matrix stored in step 701, 4 is a 22*5 matrix generated by the training sequence corresponding to the training sequence numbers of the two users; due to the training sequence of the two users There are 16 possibilities for the training sequence corresponding to the number, so there are 16 possibilities for each and A.

In this embodiment, when the d matrix in the intermediate inverse matrix is stored, step 701 may store all the elements of the d matrix by method one; since ^^( ^ " ^( ) - ¹ ^^) - ¹ ) ^ is the d matrix Is a symmetric matrix, so step 701 can also store one of the d matrices by method two. Semi-element; due to A

0010

0001

P ie A and B can be linearly transformed, and the corresponding impulse response is also 1000

0100 can be linearly transformed, so step 701 can also store, by method three, the elements of the d matrix of the user 1 whose training sequence number is smaller than the training sequence number of the user 2 of the two users; since the d matrix is both a symmetric matrix, and The impulse responses of A and B can be linearly transformed, so step 701 can store half of the elements of the d matrix by method four, wherein the training sequence number of user 1 of the two users is smaller than the element of the training sequence number of user 2 of the two users; 701 can also store the elements of the d matrix by other methods, no longer here - repeat.

In this embodiment, step 701 stores the elements of the d matrix by method 1, and when the X bit is used for quantization, the data storage amount is 16*16*25*x=6656x bits; step 701 stores the elements of the d matrix by method two, adopting In the case of X-bit quantization, the data storage amount is 16*16*15*x=3840x bits; Step 701 stores the elements of the d matrix by Method 3, and when X-bit quantization is used, the data storage amount is 120*25*x=3000x bits; Step 701 stores the elements of the d matrix by method four, and when the X-bit quantization is used, the data method-first storage sub-module stores the elements of the d-matrix, since each and A has 16 possibilities, and the d matrix is 5*5. The matrix, therefore, when X-bit quantization is used, the data storage amount is 16*16*25*x=6656x bits; when step 701 stores the elements of the d-matrix by method two, since each and A has 16 possibilities, and d The matrix is a 5*5 matrix. When storing half of the elements, each of the 15 elements needs to be stored. Therefore, when X-bit quantization is used, the data storage amount is 16*16*15*x=3840x bits; Step 701 is stored by method three. The elements of the matrix, since only storage The training sequence number of user 1 is smaller than the element of the d matrix of the training sequence number of user 2 of the two users, and the training sequence numbers of user 1 and user 2 have 16 possibilities, so when the training sequence number of user 1 is When 0, it is necessary to store 15 d matrices; When the training sequence number of the user 1 is 1, 14 d matrices need to be stored; when the training sequence number of the user 1 is 2, 14 d matrices need to be stored; ...; when the training serial number of the user 1 is When it is 15, it needs to store 0 d matrices, so the d matrix has 15 + 14+13+... + 1 + 0=120, so when using X-bit quantization, the data storage is 120*25*x=3000x bits. Step 701 stores the data storage amount of the elements of the d matrix by method four, which is similar to the above calculation process, and is not repeated here.

In this embodiment, step 701 may store all elements of the inverse matrix by method five; since 3⁄4 = ((4), ie, the inverse matrix is a symmetric matrix, step 701 may also store half of the elements of the inverse matrix by method six; step 701 It is also possible to store the elements of the inverse matrix by other methods, which are not repeated here.

In this embodiment, step 701 stores the elements of the inverse matrix by method five, and when the X-bit quantization is used, the data storage amount is 15*25*x=4QQx bits; step 701 stores the elements of the inverse matrix by method six, adopts X bits. When quantized, the amount of data stored is 16*15*x=240x bits. Wherein step 701 stores the elements of the inverse matrix by method five, since there are 16 possibilities for each A and A, and the inverse matrix is a matrix of 5*5, the X step 701 is used to store the elements of the inverse matrix by method six. Since, since each and A have 16 possibilities, and the inverse matrix is a matrix of 5*5, when storing general elements, each needs to store 15 elements, so when using X-bit quantization, the data storage amount is 16*. 15*x=240x bits.

Step 702: Obtain sub-inverse matrices ^ and m corresponding to training sequence numbers of two users from the d matrix and the inverse matrix.

In this embodiment, the inverse matrix d pn obtained in step 702 may be based on the mapping relationship between the training sequence numbers of the two users and the d matrix and the inverse matrix stored in step 701, from the d matrix and the inverse matrix stored in step 701. The obtained data may also be obtained from the d matrix and the inverse matrix stored in step 701 by other means, and is not described here again.

Step 703, multiplying and adding the sub-inverse matrix d pn and the matrix generated by the training sequence The operation is calculated to obtain the bT^+A matrix.

In this embodiment, in the matrix obtained in step 703, the b matrix is -m _x ( A )*d, and the matrix generated by the training sequence may be A and A.

In this embodiment, the process of obtaining the matrix by step 703 may specifically include:

First, A and A are multiplied by logical operations to obtain an A matrix.

Second, multiply the matrix and the sub-inverse matrix ^ to obtain the t matrix, and the t matrix is! !^( 4).

Third, multiply the t matrix and the ^ matrix to obtain a b matrix, and the b matrix is

-t*^.

4. Perform a multiplication logic operation on the b matrix and the matrix to obtain a matrix.

5. Multiply the logic between the ^ matrix and the matrix A to obtain a 4 matrix.

Sixth, the matrix and the 4 matrix are added to the logical operation to obtain the matrix. Step 704: Multiply and add the sub-inverse matrix d pn to the matrix generated by the training sequence to obtain a ^ + matrix.

In this embodiment, in the ^+b^ matrix obtained by step 704, the matrix is m _{1 +} b* [m, ( A )] ^τ , and the matrix generated by the training sequence may be Α and A.

In this embodiment, the process of the ^+Μ matrix obtained in step 704 may specifically include:

1. Perform multiplication logic operations on Α and , to obtain an A matrix.

Second, the A matrix and the sub-inverse matrix ^ are multiplied by logical operations to obtain a t matrix, and the t matrix is! !^( 4).

-t*^. 4. Perform a multiplication logic operation on the b matrix and the t matrix to obtain a b*w ^T matrix.

5. Multiply the sub-inverse matrix ^ with the ^^^ matrix to obtain a "matrix," and the matrix is n^+b ir.

6. The matrix and A are multiplied by logical operations to obtain an α matrix.

7. Perform a multiplication logic operation on the b matrix and Α to obtain an Mf matrix.

Eight, the ^ matrix and the fe matrix are added to the logical operation, resulting in a matrix. Step 705, splicing the matrix with the ^^^ matrix to obtain a channel estimation factor.

Step 706: Complete a channel estimation process according to the calculated channel estimation factor.

In this embodiment, the channel estimation process is completed in step 706, which may include using the channel estimation factor calculated in step 705 for two user joint channel detection of VAM0S, and obtaining a detection result; and using the detection result for the VAM0S strength User joint channel detection and other subsequent detections are not repeated here.

The channel estimation method provided by the embodiment of the present invention performs multiplication and addition logic calculation on a matrix generated by a training sequence corresponding to a training sequence number by using a sub-inverse matrix corresponding to training sequence numbers of two users in a pre-stored intermediate inverse matrix, thereby A channel estimation factor is obtained to achieve channel estimation. The maximum amount of data storage is X* (16*25 + 16*16*25)=6800x bits, so that the technical solution provided by the embodiment of the present invention is provided. It can reduce the amount of data storage of the chip, thereby reducing the area of the chip and effectively reducing the cost of the chip. The embodiment of the invention solves the data storage of the chip in the prior art A large amount of problems.

The channel estimation method and apparatus provided by the embodiments of the present invention can be applied to the VAMO S technology to detect the correlation between a new voice channel and an original voice channel.

The steps of a method or algorithm described in connection with the embodiments disclosed herein can be implemented directly in hardware, a software module executed by a processor, or a combination of both. Software modules can be placed in random access memory (RAM), memory, read only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or technical field Any other form of storage medium known.

The above is only the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope of the present invention. It should be covered by the scope of the present invention. Therefore, the scope of the invention should be determined by the scope of the claims.

Claims

Claim

A channel estimation apparatus, comprising:

a matrix storage unit, configured to store an intermediate inverse matrix;

Matrix acquisition unit,

Sub-inverse matrix corresponding to the training sequence number of two users

Logical computing unit,

The matrix generated by the training sequence corresponding to the training sequence number of the user performs multiplication and addition logic operations to obtain a channel estimation factor;

2. The channel estimation apparatus according to claim 1, wherein the matrix storage unit comprises:

a d matrix storage module, configured to store a d matrix in the intermediate inverse matrix, where the d matrix is a matrix of (-^()- ¹ ^^)- ¹ ;

An inverse matrix storage module, configured to store an inverse matrix in the intermediate inverse matrix, wherein the inverse matrix is a matrix;

Wherein A, A are a matrix of 22 * 5 generated by the training sequence.

The channel estimation apparatus according to claim 2, wherein the d matrix storage module comprises:

a first storage submodule for storing all the elements of the d matrix; or a second storage submodule for storing half of the elements of the d matrix; or a third storage submodule for storing the two The training sequence number of user 1 among the users is smaller than the element of the d matrix of the training sequence number of user 2 of the two users; or

And a fourth storage submodule, configured to store one of the two elements of the d matrix, wherein the training sequence number of the user 1 of the two users is smaller than the training sequence number of the user 2 of the two users.

The channel estimation apparatus according to claim 2, wherein the inverse matrix storage module comprises:

a fifth storage submodule, configured to store all elements of the inverse matrix; or

And a sixth storage submodule, configured to store half of the elements of the inverse matrix.

The channel estimation apparatus according to claim 2, wherein the matrix obtaining unit comprises:

And a sub-inverse matrix obtaining module, configured to obtain the sub-inverse matrices ^ and _mi corresponding to the training sequence numbers of the two users from the d matrix and the inverse matrix stored by the d matrix storage module and the inverse matrix storage module.

The channel estimation apparatus according to claim 5, wherein the logic calculation unit comprises:

a first matrix calculation module, configured to multiply and add a sub-inverse matrix ^ and _mi obtained by the sub-inverse matrix acquisition module, and a matrix generated by the training sequence to obtain a ^^^^ matrix;

a second matrix calculation module, configured to perform multiplication and logical calculation on the sub-inverse matrices ^ and n obtained by the sub-inverse matrix acquisition module and the matrix generated by the training sequence, to obtain

a Μ splicing module, configured to splicing the b ^T + matrix obtained by the first matrix calculation module and the _{α + Μ} τ matrix obtained by the second matrix calculation module to obtain the channel estimation factor

Wherein the b matrix is

.

The channel estimation apparatus according to claim 6, wherein the first matrix calculation module comprises:

a first calculation submodule, configured to perform multiplication logic operations on the A and A to obtain an A moment Array

a second calculation submodule, configured to perform a multiplication logic operation on the ^^ matrix and the sub-inverse matrix _mi to obtain a t matrix, where the t matrix is ^( );

a third calculation submodule, configured to perform multiplication logic operation on the t matrix and the matrix to obtain a b matrix, where the b matrix is

a fourth calculation submodule, configured to perform a multiplication logic operation on the b matrix and the A to obtain a matrix;

a fifth calculation submodule, configured to perform a multiplication logic operation on the ^ matrix and the A to obtain a matrix;

And a sixth calculation submodule, configured to perform an addition logic operation on the matrix and the matrix to obtain the matrix.

The channel estimation apparatus according to claim 6, wherein the third matrix calculation module comprises:

a first calculation sub-module, configured to perform multiplication logic operations on the A and the A to obtain an A matrix;

a second calculation submodule, configured to perform a multiplication logic operation on the A matrix and the sub inverse matrix to obtain a t matrix, where the t matrix is ^( );

a third calculation submodule, configured to perform multiplication logic operation on the t matrix and the matrix to obtain a b matrix, where the b matrix is - *^ ;

a seventh calculation submodule, configured to perform a multiplication logic operation on the b matrix and the t matrix to obtain a b*[ ] ^T matrix;

An eighth calculation submodule, configured to perform a multiplication logic operation on the sub-inverse matrix _mi and the b*w ^T matrix to obtain a matrix, wherein the matrix is _mi +b *[i] ^T ;

a ninth calculation sub-module, configured to perform the multiplication logic operation on the matrix To ^ matrix;

a tenth calculation submodule, configured to perform a multiplication logic operation on the b matrix and the A to obtain a b matrix;

The eleventh calculation submodule is configured to perform an addition logic operation on the _alpha matrix and the Mf matrix to obtain a matrix.

9. A channel estimation method, comprising: a matrix;

Performing multiplication and logical operations on the matrix generated by the training matrix corresponding to the training sequence number of the two users, to obtain a channel estimation factor;

The channel estimation process is completed according to the calculated channel estimation factor.

The channel estimation method according to claim 9, wherein the method further comprises: before acquiring the sub-inverse matrix corresponding to the training sequence number of the two users from the pre-stored intermediate inverse matrix, the method further includes:

Storing a d matrix and an inverse matrix in the intermediate inverse matrix, wherein the d matrix is

) - ¹ matrix, the inverse matrix is ^a matrix;

Wherein A, A are a matrix of 22 * 5 generated by the training sequence.

The channel estimation method according to claim 10, wherein the storing the d matrix in the intermediate inverse matrix comprises:

Storing all elements of the d matrix; or

Storing half of the elements of the d matrix; or

Storing an element of the d matrix of the user 1 whose training sequence number is smaller than the training sequence number of the user 2 of the two users; or

In storing half of the elements of the d matrix, the training sequence number of the user 1 of the two users is smaller than the element of the training sequence number of the user 2 of the two users.

The channel estimation method according to claim 10, wherein the storing the inverse matrix in the intermediate inverse matrix comprises:

Storing all elements of the inverse matrix; or

Stores half of the elements of the inverse matrix.

The channel estimation method according to claim 10, wherein the sub-inverse matrix corresponding to the training sequence numbers of the two users is obtained from the pre-stored intermediate inverse matrix, and includes:

Obtaining a sub-inverse matrix corresponding to the training sequence numbers of the two users from the d matrix and the inverse matrix

The channel estimation method according to claim 13, wherein the matrix generated by the training sequence corresponding to the training sequence number of the two users is multiplied and logically operated, including :

And multiplying and adding the sub-inverse matrix ^ and _mi to the matrix generated by the training sequence to obtain a matrix;

And multiplying and adding the sub-inverse matrix ^ and _mi to the matrix generated by the training sequence to obtain a ^T + ^ ^T matrix;

And splicing the b ^T + matrix with the + bA ^T matrix to obtain the channel estimation factor.

,

Wherein the b matrix is

.

The channel estimation method according to claim 14, wherein the multiply-adding logical operation of the sub-inverse matrix d P n and the matrix generated by the training sequence to obtain a matrix comprises:

Performing multiplication logic operations on the A and A to obtain an A matrix; Performing multiplication logic operation on the A matrix and the sub-inverse matrix _mi to obtain a t matrix, where the t matrix is ^( );

Performing multiplication logic operation on the t matrix and the ^ matrix to obtain a b matrix, where the b matrix is - *^;

Performing multiplication logic operation on the b matrix and the matrix A to obtain a matrix; performing multiplication logic operation on the matrix and the matrix A to obtain a ^ matrix; adding the b ^T matrix and the ^ matrix Logically, the b ^r +4 matrix is obtained.

The channel estimation method according to claim 14, wherein the multiply-adding logical operation of the sub-inverse matrix d pn and the matrix generated by the training sequence to obtain an a +b matrix comprises:

Performing multiplication logic operations on the A and A to obtain an A matrix;

Performing a multiplication logic operation on the A matrix and the sub-inverse matrix _mi to obtain a t matrix, the t matrix being !^(4);

Performing a multiplication logic operation on the b matrix and the t matrix to obtain a b*w ^T matrix; performing a multiplication logic operation on the sub inverse matrix ^ and the b*W ^T matrix to obtain a "matrix, the" matrix For _mi +b*[i] ^T ;

Performing a multiplication logic operation on the matrix and the A to obtain a matrix;

Performing a multiplication logic operation on the b matrix and the A to obtain an Mf matrix;

Adding the a matrix to the matrix to perform an additive logic operation to obtain the a + bA matrix.