WO2011108404A1

WO2011108404A1 - Electrophoretic display device and method for driving display panel

Info

Publication number: WO2011108404A1
Application number: PCT/JP2011/053870
Authority: WO
Inventors: 秀雄浜; 浩之本多; 康宏大木
Original assignee: 大日本印刷株式会社
Priority date: 2010-03-02
Filing date: 2011-02-22
Publication date: 2011-09-09
Also published as: JP2011180409A

Abstract

Provided is an electrophoretic display device which comprises: a display panel comprising a plurality of transistors, in which gate electrodes of each of the plurality of transistors are connected to any of a plurality of gate wires, and either a source electrode or a drain electrode is connected to any of a plurality of data wires, while the other of the source electrode and the drain electrode is connected to one of two pixel electrodes for holding an electrophoretic display material therebetween; and a control unit for applying, in one frame period, a voltage pulse between the pixel electrodes corresponding to pixels in an image to be displayed on the display panel, the voltage pulse being applied with a frequency that corresponds to the brightness level of the pixels.

Description

Electrophoretic display device and method of driving display panel

The present invention relates to an electrophoretic display using an electrophoretic display material, a method of driving a display panel using the electrophoretic display material, and the like. In particular, the present invention relates to an electrophoretic display device capable of halftone display using an electrophoretic display material, a driving method of a display panel using the electrophoretic display material, and the like.

There is known an electrophoretic display device which performs display by moving charged particles by causing an electric field to be generated by sandwiching an electrophoretic display material in which charged particles are dispersed in a solvent and generating an electric field between the electrodes. Patent Document 1).

Such an electrophoretic display can be used as a reflective display for electronic paper and the like. Such an electrophoretic display device has features such as wide viewing angle and stable memory performance and low power consumption as compared with a display device using liquid crystal. Using this feature, the electrophoretic display device is used, for example, for display devices such as electronic price tags, and for digital signage that displays information in places such as transportation facilities, stores, public facilities, etc., such as POP (Point of purchase advertising) advertisements. It is applied to an e-book reader etc. which takes in and displays the contents of a book as electronic contents using a display device, and a communication function whose market is rapidly expanding recently.

In general, books may include illustrations, photographs, and the like. In addition, when displaying an advertisement or the like, image information of a photo may be displayed. For this reason, the electrophoretic display device needs to display not only the display of a binary image of black and white such as characters but also the display of an image of intermediate gradation.

The display of intermediate gradations is an essential display mode as described above not only in the field of liquid crystal display devices but also in the field of electrophoretic display devices, but in general, a pulse width modulation method and a voltage modulation method are known. (See, for example, Non-Patent Document 1).

JP 2008-139738 A

In the case of performing active matrix driving using thin film transistors or the like in the electrophoretic display device, when the volume resistivity of the electrophoretic display material is small, the charge supplied with the thin film transistor in the on state turns the thin film transistor in the off state It has been found by the present inventors that there is a problem that good black-and-white contrast and half-tone image writing can not be performed sufficiently to cause leakage through the electrophoretic display material afterward. Therefore, there is a problem that the conventionally known gradation display method can not always be used effectively.

One object of the present invention is to solve the problem that the image can not be written sufficiently when the leak current of the electrophoretic display material is large, and to provide a novel gray scale display device and a method of driving a display panel. is there.

As one embodiment of the present invention, a plurality of transistors are provided, each gate electrode of the plurality of transistors is connected to any of a plurality of gate lines, and one of a source electrode and a drain electrode is connected to any of a plurality of data lines. A display panel connected and the other of the source electrode and the drain electrode being connected to one of two pixel electrodes for sandwiching an electrophoretic display material, and an image to be displayed on the display panel in one frame period And a control unit for applying voltage pulses of the number of times corresponding to the lightness level of the pixel between the pixel electrodes corresponding to the pixel.

In one embodiment of the present invention, a plurality of transistors are provided, each gate electrode of the plurality of transistors is connected to any of a plurality of gate lines, and one of a source electrode and a drain electrode is any of a plurality of data lines. A driving method of a display panel connected to the other, wherein the other of the source electrode and the drain electrode is connected to one of two pixel electrodes for sandwiching an electrophoretic display material, Disclosed is a method of driving a display panel, characterized in that a write voltage pulse is applied between the pixel electrodes corresponding to the pixels a number of times according to the lightness level of a pixel of an image to be displayed on the display panel. .

According to the present invention, using the electrophoretic display device, it is possible to perform display using middle gradation as well as display using black and white contrast. In particular, since the current leaked through the electrophoretic display material is large, the charge supplied from the drive power supply through the thin film transistor etc. is reduced, and it is not possible to obtain the halftone display without sufficient image writing conventionally. Even, good halftone display can be obtained.

FIG. 1 is a functional block diagram of an electrophoretic display device according to Embodiment 1 of the present invention. FIG. 6A is a schematic view and a cross-sectional view of a cross section of a gate line and a data line in the display panel of the electrophoretic display device according to the first embodiment of the present invention. It is a schematic diagram of the pixel in the display panel of the electrophoretic display concerning Embodiment 1 of the present invention. FIG. 6 is an equivalent circuit diagram of pixel elements in a display panel of the electrophoretic display device according to the embodiment of the present invention. It is a figure which shows the relationship of the volume resistivity of the electrophoresis display material of the electrophoresis display device concerning embodiment of this invention, and holding time. It is a graph which shows an example of the time change of the holding voltage in the display panel of the electrophoresis display concerning an embodiment of the present invention. It is a figure for demonstrating the process which calculates the frequency | count of applying a voltage according to the brightness of a pixel in the electrophoretic display which concerns on Embodiment 1 of this invention. It is a flowchart explaining the process of a drive of the electrophoresis display concerning a 1st embodiment of the present invention. 5 is a timing chart of pulses applied to gate lines and data lines in the display panel of the electrophoretic display device according to the first embodiment of the present invention. FIG. 6 is a functional block diagram of an electrophoretic display device according to Embodiment 2 of the present invention. 10 is a timing chart of pulses applied to gate lines and data lines in a display panel of an electrophoretic display device according to Embodiment 2 of the invention. It is a functional block diagram of the electrophoresis display concerning a 3rd embodiment of the present invention. 10 is a timing chart of pulses applied to gate lines and data lines in a display panel of an electrophoretic display device according to Embodiment 3 of the present invention. It is a graph which shows the change of the reflectance at the time of actually operating the electrophoretic display concerning one Embodiment of this invention, and contrast. FIG. 18 is a view showing the arrangement of gate lines, data lines and pixel elements in Embodiment 1-6 of the present invention. It is a figure which shows application of the voltage in Example 1 of this invention. It is a figure which shows application of the voltage in Example 2 of this invention. It is a figure which shows application of the voltage in Example 3 of this invention. It is a figure which shows application of the voltage in Example 4 of this invention. It is a figure which shows application of the voltage in Example 5 of this invention. It is a figure which shows application of the voltage in Example 6 of this invention.

Hereinafter, embodiments of the present invention will be described as embodiments and examples with reference to the drawings. The present invention is not limited to the embodiments and examples described below, and various modifications can be made without departing from the scope of the invention.

(Embodiment 1)
FIG. 1 shows an example of a functional block diagram of an electrophoretic display device according to Embodiment 1 of the present invention. The electrophoretic display device 100 includes a display panel 101 and a control unit 102.

The display panel 101 is an electrophoretic display panel in which an electrophoretic display material is held between a pair of substrates. 1, in the display panel 101, gate lines G1, G2,..., Gm and data lines D1, D2,..., Dl are arranged on a substrate on which the transistors 104 of the display panel 101 are formed. One end of the gate lines G1, G2,..., Gm is connected to the gate line drive circuit 1021, and the voltage applied to each is controlled by the gate line drive circuit 1021. Further, one end of each of the data lines D1, D2, ..., Dl is connected to the data line drive circuit 1022, and the voltage applied to each is controlled by the data line drive circuit 1022. On the other hand, an electrode is formed on the other substrate of the display panel 101 (not shown). Hereinafter, this electrode is referred to as a "substrate electrode" below. The substrate electrode is connected to the substrate electrode drive circuit 1023 via a bridge electrode (not shown), and the voltage applied to the substrate electrode is controlled by the substrate electrode drive circuit 1023. The number of substrate electrodes formed on one side of the substrate does not have to be one. One of the substrates can be divided, and a number of substrate electrodes can be appropriately formed according to the division.

The display panel 101 is provided with a plurality of transistors 104. The transistor 104 is disposed at the intersection of the gate line and the data line. For example, a thin film transistor (thin film transistor) or the like is used as the transistor 104. The gate electrode of the transistor 104 is connected to the gate line located at the cross position, and the pixel electrode of the pixel element 105 described later is connected to the data line through the transistor 104. In other words, one of the source electrode and the drain electrode is connected to the data line located at the crossing position. Further, the other of the source electrode and the drain electrode is connected to an electrode at one end of the pixel element 105. An electrode (substrate electrode) at the other end of the pixel element 105 is connected to a substrate electrode drive circuit 1023. Note that an electrode (pixel electrode) at one end of the pixel element 105 and an electrode (substrate electrode) at the other end facing the electrode are collectively referred to as “pixel electrode”. Each of the pair of pixel electrodes is formed on the facing surfaces of the pair of substrates, and the electrophoretic display material is sandwiched therebetween. Therefore, by applying a voltage between the pixel electrodes, a predetermined voltage is applied to the electrophoretic display material held by the pixel electrodes. Note that the pixel electrode need not be in direct contact with the electrophoretic display material. For example, the electrophoretic display material may be enclosed in a capsule, and the capsule may be disposed between the pixel electrodes.

FIG. 2A is an example of an enlarged schematic view of an intersecting portion between a gate line and a data line. One end of the pixel element 105 is connected to the transistor 104. The pixel element 105 is connected to one of the data lines D1, D2,. The voltage applied to the gate line is controlled by the gate line drive circuit 1021, and when the transistor 104 is turned on, the voltage applied to the data line by the data line drive circuit 1022 and the other end of the pixel element by the substrate electrode drive circuit 1023. The difference between the voltage applied to the pixel and the voltage applied to the pixel element (hereinafter referred to as the “write voltage”) is applied to the The period (hereinafter referred to as “gate selection time”) in which the transistor 104 is turned on can be set in consideration of the number (m) of gate lines G1, G2,..., Gm. On the other hand, the gate selection time is also limited by the carrier mobility of the transistor. This is because carriers can be injected from the transistor to the pixel electrode at higher speed as the carrier mobility is higher. Since the mobility of a general amorphous silicon transistor is 0.6 to 0.8 cm ² / (V · s), it is known that the gate selection time can be shortened to about 10 microseconds.

As shown in FIG. 2A, the pixel element 105 includes a pixel 201 and a storage capacitor 202. The pixel 201 and the auxiliary capacitance 202 are connected in parallel. The pixel 201 is configured using two pixel electrodes and an electrophoretic display material sandwiched between the pixel electrodes. The auxiliary capacitance 202 is a capacitor. In the auxiliary capacitance 202, a transistor connected to one end of the pixel element 105 is turned off, and a predetermined voltage can be continuously applied to the pixel 201 even when the voltage of the data line is not applied to the pixel element 105 Used for In the case where the pixel 201 also functions as a capacitor, the auxiliary capacitance 202 may not be used.

FIG. 2B illustrates an example of a cross section of the transistor 104 in the case where the display panel is cut in parallel to the data line. Source / drain electrodes 214 and drain / source electrodes 215 are formed on a substrate 211. "Source / drain electrode" and "drain / source electrode" mean that one electrode operates as a source electrode and the other operates as a drain electrode. The source / drain electrode 214 is connected to any of the plurality of data lines D1 to D1, and the drain / source electrode 215 is connected to one of the pixel electrodes.

The source / drain electrode 214 and the drain / source electrode 215 are formed separately, and a channel region is formed in the semiconductor thin film between them. An insulating film 212 is stacked on the source / drain electrode 214, the drain / source electrode 215, and the channel, and a gate electrode 216 is formed on the channel region. The gate electrode 216 is connected to any of the plurality of gate lines G1 to Gm.

An insulating protective layer 213 is formed on the source / drain electrode 214, the drain / source electrode 215, the channel region, and the gate electrode, and one of the pixel electrodes is formed thereon. Note that in FIG. 2B, the thin film transistor has a top gate type in which the gate electrode is disposed on the upper side with respect to the channel region. However, the structure of the thin film transistor is not limited to the top gate type, and may be a bottom gate type in which the gate electrode is disposed below the channel region. The thin film transistor may be a silicon thin film transistor such as amorphous silicon, an oxide thin film transistor, or an organic thin film transistor.

In addition, on the substrate 217 facing the substrate 211, a substrate electrode 218 which is the other of the pixel electrodes is formed. The substrate electrode 218 is connected to the substrate electrode drive circuit 1023. In addition, an electrophoretic display material is disposed and sealed between the pixel electrodes 219. Thus, the electrophoretic display material is sandwiched between the two pixel electrodes.

3A and 3B are schematic views of the cross section of the pixel 201. FIG. In FIGS. 3A and 3B, for example, the pixel electrode 301 is connected to the substrate electrode drive circuit 1023 and the pixel electrode 302 is connected to the drain / source electrode 215 of the transistor 104 (pixel electrode 301 may be connected to the drain / source electrode 215 of the transistor 104, and the pixel electrode 302 may be connected to the substrate electrode drive circuit 1023). In addition, an electrophoretic display material is held and held between the pixel electrode 301 and the pixel electrode 302. Further, at least one of the pixel electrode 301 and the pixel electrode 302 is a transparent electrode, and the electrophoretic display material can be visually recognized from the outside of the display panel 101. For example, the pixel electrode not connected to the drain / source electrode 215 and the substrate (not shown) on which it is formed become transparent.

The electrophoretic display material is one in which a plurality of charged particles are dispersed in a solvent such as a liquid. The plurality of charged particles have respective colors such as black and white, and charged particles of the same color are charged by charges of the same polarity. If other charged particles of different colors are present, those charged particles of different colors are charged by charges of different polarity. Therefore, when a write voltage is applied between the pixel electrode 301 and the pixel electrode 302 to generate an electric field between the pixel electrode 301 and the pixel electrode 302, charged particles of a certain color are generated by this electric field. Are migrated and moved to one side of the pixel electrode 301 and the pixel electrode 302. In addition, if charged particles of different colors are present, they migrate and move to the other side of the pixel electrode 301 and the pixel electrode 302. Also, when an electric field in the opposite direction is generated between the pixel electrode 301 and the pixel electrode 302, charged particles of a certain color migrate to the other side of the pixel electrode 301 and the pixel electrode 302. Moving. If charged particles of different colors are present, they migrate to one of the pixel electrode 301 and the pixel electrode 302 and move.

In FIGS. 3A and 3B, for example, it is assumed that the pixel electrode 301 and the substrate (not shown) on which the pixel electrode 301 is formed are transparent. It is assumed that the charged particle 303 has a black color and is charged by a positive charge. Further, it is assumed that the charged particle 304 has a white color and is charged by a negative charge. When a voltage is applied to the pixel electrode 301 and the pixel electrode 302 and the voltage of the pixel electrode 301 is made larger than the voltage of the pixel electrode 302, an electric field in the direction from the pixel electrode 301 to the pixel electrode 302 is generated. As shown in FIG. 3A, the charged particles 303 move to the side of the pixel electrode 302, and the charged particles 304 move to the side of the pixel electrode 301. Thus, when the electrophoretic display material is viewed from the side of the pixel electrode 301, it looks white. That is, the pixel displayed by the pixel electrode 301 looks white. On the other hand, when the potential of the pixel electrode 302 is higher than the potential of the pixel electrode 301, an electric field in the direction from the pixel electrode 302 to the pixel electrode 301 is generated, and as shown in FIG. Moves to the side of the pixel electrode 301, and the charged particles 304 move to the side of the pixel electrode 302. Thus, when the electrophoretic display material is viewed from the side of the pixel electrode 301, it looks black. That is, the pixel displayed by the pixel electrode 301 looks black.

In FIG. 3, when the black charged particles 303 are present on the pixel electrode 302 side, the white charged particles 304 are present on the pixel electrode 301 side, and the black charged particles 303 are present for the pixel electrode. When present on the side of 301, white charged particles 304 are shown to be present on the side of the pixel electrode 302. However, the mode of the presence of charged particles is not limited to these cases. For example, depending on the conditions for applying a voltage, black charged particles 303 and white charged particles 304 may be mixed on the same electrode side. For example, when the black charged particles 303 and the white charged particles 304 are positioned on the pixel electrode 301 side, the electrophoretic display material may appear gray when viewed from the pixel electrode 301 side.

In addition, according to the number of charged particles having white, for example, present on the side of the pixel electrode 301, it is determined how much white the electrophoretic display material is viewed from the side of the pixel electrode 301 . In other words, the reflectivity for white is determined. In general, the number of charged particles present on the side of the pixel electrode 301 is the distribution of charged particles before voltage is applied to the pixel electrode 301 and the pixel electrode 302, and the number of charged electrodes on the pixel electrode 301 and the pixel. It depends on the magnitude of the voltage applied to the electrode 302 and time. Therefore, the reflectance of the electrophoretic display material corresponding to the color of the charged particles is changed. Therefore, the “response time” of the electrophoretic display material is defined as follows. That is, a first DC voltage is applied between two electrodes sandwiching the electrophoretic display material, and the color displayed on the side of one of the electrodes is set to a first color (for example, white), and Shut off the first DC voltage. Then, after passing a state in which there is no voltage difference between the two electrodes for a predetermined time or more, a second DC voltage is applied between the two electrodes, and the color displayed on the side of one of the electrodes is Transition to the second color (eg, black). At this time, the time until the reflectance of the electrophoretic display material held between the two electrodes takes the maximum value or the minimum value by the application of the second DC voltage is referred to as “response time”. Here, the reflectance refers to the reflectance of the color displayed by the electrophoretic display material. In other words, the time until the color displayed by the electrophoretic display material transitions from the first color to the second color upon application of the second DC voltage is referred to as "response time".

FIG. 4 shows an equivalent circuit of the pixel element 105. That is, FIG. 4 shows the pixel 201 shown in FIG. 2 and FIG. 3 by a parallel circuit of a pixel capacity and an electric resistance by the electrophoretic display material. Therefore, when the transistor is turned off after applying the write voltage to the equivalent circuit of FIG. 4, the electrophoretic display material of the pixel 201 has a voltage due to charges accumulated in the pixel 201 or the auxiliary capacitance 202 (hereinafter referred to as “ It is called "holding voltage" and is expressed as "VH"), and the charged particles move to realize white or black color display. Such transient phenomena can be numerically analyzed using an equivalent circuit. According to this, the magnitude of the holding voltage varies depending on the magnitude of the electric resistance R. That is, the magnitude of the holding voltage is the sum of the auxiliary capacitance 202 (hereinafter referred to as "Cs") and the electric capacitance of the pixel (hereinafter referred to as "C") and the electric resistance of the pixel (hereinafter referred to as R). Decay time “TCR” which is the product of
TCR = (Cs + C) × R (Equation 1)
Using,
VH = VH0 × EXP (−t / TCR) (Equation 2)
It can be expressed as. In Equation 2, “VH0” is the magnitude of the holding voltage immediately after the transistor is turned off, and is approximately equal to the write voltage, and “t” is an elapsed time starting from the time when the transistor is turned off It is. Therefore, although both the write voltage and the hold voltage are voltages applied to the pixel 201, the write voltage is a voltage applied to the pixel 201 during the gate selection time, whereas the hold voltage is the transistor. Is an effective voltage applied to the pixel 201 when it is turned off. The decay time corresponds to the time when the charge of the pixel leaks in the electrophoretic display material and disappears due to the current (hereinafter referred to as "leakage current"). Therefore, as shown in Equation 2, the shorter the decay time, the shorter the holding voltage (VH) will be.

As shown in FIG. 5, when the elapsed time t is 0, VH / VH0 becomes 1 from Equation 2 and the holding voltage becomes an initial value. For example, when the elapsed time t is TCR, VH / VH0 is 0. 0. It becomes as small as 37 and becomes almost 0 when the elapsed time t is 5 × TCR, so the charged particles do not have any voltage due to the holding voltage in the time of 5 × TCR or more, and the electric field of the charged particles has been If the migration by the response is not completed, the image can not be sufficiently written on the electrophoretic display panel.

Therefore, the magnitude of the decay time (TCR) is a problem. In general, the electrical resistance R of equation 1 can be calculated using volume resistivity ρ
R = ×× d / S (Equation 3)
It can be expressed as. In

Equations

2 and 3, d is the thickness of the electrophoretic display material, and S is the area of the pixel electrode. From Equation 3, as the volume resistivity より is larger, the decay time is longer, so that a constant holding voltage can be continuously applied to the electrophoretic display material for a long time.

The relationship between the time for which the magnitude of the holding voltage holds a predetermined value (for example, 90% of the initial value) (hereinafter referred to as "holding time") and the volume resistivity can be calculated using Equations 1 to 3. The obtained result is shown in FIG.
As shown in FIG. 6, when the volume resistivity is a fixed value (for example, 10 ¹² Ωcm) or more, the response time (for example, 400 milliseconds) of the electrophoretic display material and the holding time become comparable. Therefore, since the holding voltage is maintained at a predetermined value or more during the response time, for example, if one frame period is taken as the response time, the gate lines G1, G2,. The conventional active matrix driving method of selectively scanning only and applying a voltage to each data line in synchronization therewith enables sufficient writing of an image on the electrophoretic display panel.

In this case, halftone display can be performed by controlling the amount of charge accumulated in the pixel capacitance and the storage capacitance. The control of the charge amount can be performed by the conventional voltage modulation method or pulse width modulation method.

On the other hand, when the size of the volume resistivity (10) is 10 ¹² Ωcm or less, particularly about 10 ⁹ Ωcm, the holding time is about 1 millisecond (FIG. 6). The hold voltage is nearly zero for most of the response time, as it is significantly smaller than the response time (eg, 400 ms). Therefore, even if one frame period is a response time (for example, 400 milliseconds), the gate selection time is shorter than the response time (for example, 100 microseconds), so gate lines G1, G2,. The conventional active matrix driving method of selectively scanning only once and synchronously applying a voltage to each data line can not sufficiently write an image on the electrophoretic display panel. Furthermore, since the volume resistivity is as small as, for example, 10 ¹² Ωcm or less, if the holding voltage is reduced within the response time, it becomes difficult to control the brightness level of the white display itself. For this reason, it is impossible to control the gradation by the voltage modulation method or the pulse width modulation method.

According to one embodiment of the present invention, the voltage pulse is applied several times in the order of the gate lines G1, G2,..., Gm for one frame period which is the time required to finish displaying the image of one screen If the voltage pulse is applied to the pixel 201 in synchronization with the selection of the gate lines G1, G2,..., Gm, the charge is applied to the pixel according to the number of times the voltage is applied to the pixel 201. As it is continuously supplied, the lightness level can be controlled. Therefore, even if the volume resistivity is small (for example, 10 ¹² Ωcm or less), the write voltage for the number of times corresponding to the lightness level of the pixel of the image to be displayed on the display panel is Since the brightness level can be controlled by applying between the electrodes, even when the volume resistivity is small (for example, 10 ¹² Ωcm or less), the gradation of the voltage modulation method or the pulse width modulation method is not used. It becomes possible to perform half tone display.

The volume resistivity of the electrophoretic display material according to the embodiment of the present invention is preferably 10 ⁷ Ωcm or more and 10 ¹² Ωcm or less. If the volume resistivity is less than 10 ⁷ Ωcm, the leakage current is large, and the holding time is short, so that sufficient black and white display contrast can not be obtained. Also, if the volume resistivity is larger than 10 ¹² Ωcm, as described above, since the leak current is small, the gradation control method of the normal voltage modulation method or pulse width modulation method can be effectively used.

In one embodiment of the present invention, for example, the reflectance of a predetermined color is set to a minimum or maximum state or a predetermined value, and the write voltage is applied between the pixel electrode 301 and the pixel electrode 302. Depending on the number of times of application, it is possible to control the reflectance of the color. One of the features of the present embodiment is to control, for example, the white reflectance and the like by controlling the number of repetitions of application of voltage for a shorter period of time than the response time. The change in voltage from the start of application of the write voltage to the end of application is referred to as a “write voltage pulse”. In general, the magnitude of the voltage with respect to the time of the write voltage pulse is preferably square, but depending on the operation of the voltage generation circuit or the like, it may not be a strictly square due to overshoot, undershoot or the like. The pulse width of the write voltage pulse is usually the above-described gate selection time.

In addition, if the reflectance of the color of each pixel is calculated using the history of the voltage applied between the pixel electrodes, the reflectance of the color, etc. is obtained by each pixel at the next time. The number of times the write voltage pulse should be applied between the pixel electrodes can be calculated using the reflectance of the color to be used, and the write voltage can also be applied.

Note that one of the pixel electrode 301 and the pixel electrode 302 is a pixel electrode corresponding to a pixel, and the other of the pixel electrode 301 and the pixel electrode 302 is a substrate electrode corresponding to the pixel. Generally, the substrate electrode is transparent, and the image can be viewed from above the substrate electrode. In addition, the pixel electrode is often connected to the transistor 104. In addition, the substrate electrode is often connected to the substrate electrode drive circuit 1023. Therefore, by controlling the voltages of the gate lines G1, G2, ..., Gm and the data lines D1, D2, ..., Dl, different voltages can be applied to the pixel electrodes for each individual pixel element. On the other hand, a common voltage is applied to the substrate electrode. Note that applying a common voltage to all the substrate electrodes is not essential. For example, when a plurality of substrate electrodes are formed individually, different voltages can be applied to each of the substrate electrodes.

The control unit 102 applies, during one frame period, write voltage pulses of the number of times corresponding to the lightness level of the pixel of the image to be displayed on the display panel 101 between the pixel electrodes corresponding to the pixel.

The “one frame period” is a period in which control for displaying one still image on the display panel 101 is performed. In one embodiment of the present invention, selection of the gate lines G1 to Gm is performed a predetermined number of times in order to display one still image. The time required for the selection of the gate lines G1 to Gm to be performed a predetermined number of times consecutively is one frame period. In other words, “one frame period” is a period from the start of the image writing process to the end thereof to display one image. That is, it is a period in which the gate lines G1, G2,..., Gm are selected a plurality of times each having a predetermined number of times (n). In other words, it is the time required for the total number of pulses applied to the gate lines G1, G2,..., Gm to turn on the transistor 104 to be m × n. It does not include the time for selecting the pixels almost simultaneously and performing the predetermined processing. The “one image” is an image to be displayed using the display panel 101. Usually, it is one still image.

The “brightness level of the pixel of the image” is a brightness level of each pixel position of the display panel 101 when the image is displayed on the display panel 101. For example, when the pixel information represents an image using 8-bit brightness for each pixel, levels of brightness from 0 to 255 exist.

“The number of times according to the lightness level of the pixel of the image” means that the color of the pixel of the display panel 101 is white at the start of one frame period when the electrophoretic display material can display, for example, the range from white to black. In some cases, the smaller the lightness of the pixels of the image, the more it will increase. In addition, when the color of the pixel of the display panel 101 is black at the start of one frame period, the larger the lightness of the pixel, the more it becomes. The "brightness of an image pixel" refers to the brightness of an image pixel. For example, it is lightness when the color of a pixel of an image is expressed by hue, lightness, and saturation.

As an example of the configuration of the control unit 102, there is an example configured by an applied voltage control circuit 1025 and an application number control circuit 1024 described next.

The applied voltage control circuit 1025 is a circuit that generates a voltage pulse from the plurality of gate lines and the plurality of data lines and applies the voltage pulse between the pixel electrodes.

The control unit 102 (applied voltage control circuit 1025) causes the substrate electrode drive circuit 1023 to set the voltage of the substrate electrode to, for example, 0 V, and the gate line drive circuit 1021 turns on the transistor 104 for the gate lines G1, G2,. To the data line driver circuit 1022 to apply a voltage pulse to the source electrode or the drain electrode of the transistor to which the pulse is applied by the gate line, and the pixel electrode 301 and the pixel electrode 302 A write voltage pulse of a predetermined magnitude is applied during the period. For example, one frame period can be taken as response time. At this time, the gate selection time is shorter than the response time. For example, the gate selection time can be greater than 0 and less than or equal to the time obtained by dividing the response time by the value of n × m. Here, n × m is the number of times the gate line is selected during one frame time. Also, one frame period can be longer or shorter than the response time. The voltage of the substrate electrode can be a constant value (for example, 0 V), or can change with time, such as an alternating voltage.

For example, when a black color or a similar color is to be displayed on a pixel at an intersection position of the gate line G1 and the data line D1 of an image to be displayed on the display panel 101 as viewed from the substrate electrode side, the gate line When a voltage pulse is applied to G1, the data line driving circuit 1022 applies a voltage pulse for moving black charged particles away from the pixel electrode of the pixel connected to the data line D1. If the black charged particles 303 are charged with positive charge, a high voltage is applied to the data line D1 so that a voltage higher than the voltage of the substrate electrode is applied to the pixel electrode. For example, when the voltage of the pixel electrode is 0 V, a positive voltage (for example, 15 V) is applied to the data line D1. If the color of the solvent is black and the charged particles are white, a voltage is applied to move the charged particles away from the substrate electrode.

The number-of-applications control circuit 1024 applies, during one frame period, the voltage pulse the number of times according to the lightness level of the pixel of the image to the pixel electrode corresponding to the pixel.

In the image, a color filter may be formed on the substrate on which the substrate electrode is formed by a predetermined method, and full color display may be performed using the halftone display. The charged particles are not limited to black charged particles, and charged particles of any color, such as red charged particles, may be used. By using charged particles of respective colors such as red, blue and green as the charged particles, area color or full color display can be performed by arranging the charged particles of each color for a part of a display panel or a part of pixels. It can also be done.

FIG. 7 shows an example in which the control unit 102 (application number control circuit 1024) calculates the number of times of applying a voltage pulse to the application voltage control circuit 1025 according to the lightness level of the pixel of the acquired image information. In the state before applying the voltage pulse, the reflectance of the predetermined color such as white is in the minimum state, and the reflectance of the color gradually increases by applying the voltage pulse a plurality of times. Therefore, for example, when the lightness level of the pixel is 0 or more and 63 or less, a voltage is not applied to the corresponding pixel using the applied voltage control circuit 1025. In addition, if it is 64 or more and 127 or less, a voltage is applied once to the corresponding pixel using the applied voltage control circuit 1025. If the voltage is 128 or more and 191 or less, two voltages are applied to the corresponding pixel using the applied voltage control circuit 1025. If the voltage is 192 or more and 225 or less, the corresponding voltage control circuit 1025 is used. The number of times of voltage application is calculated as in the case where voltage is applied three times to pixels to be selected. However, although "a voltage is not applied" is described, a voltage which does not substantially change the color reflectance may be applied as in the embodiment described later.

In the above example, the number of application of the voltage for obtaining the maximum lightness is set to three times for convenience of explanation, but may be several tens to several hundreds of times. The number of times of application of the voltage for obtaining the maximum lightness also varies depending on the magnitude of the write voltage or the length of the gate selection time. For example, assuming that the gate selection time is n times the number of repetitions of sequentially selecting the gate lines G1, G2,..., Gm and applying a voltage pulse, one frame period may be divided by m × n. it can. As an example, taking one frame period as a response time (for example, 400 milliseconds), the gate selection time is about 55 microseconds when the number (m) of gate lines is 240 and the number of repetitions n is 30. When one frame period is fixed to the response time or the like, the shorter the gate selection time, the more the number of gate lines can be increased. Generally, in an amorphous silicon transistor, the gate selection time can be shortened to about 10 microseconds as described above. The gate selection time can also be shortened by using a thin film transistor (for example, a polycrystalline silicon transistor, an oxide transistor, or the like) with higher mobility. Further, the number of repetitions (n) of applying the voltage pulse by sequentially selecting the gate lines G1, G2,..., Gm can be made equal to or larger than the number of application of the voltage for obtaining the maximum lightness. For example, when the number of times of application of the voltage for obtaining a predetermined brightness is 10 when the number of times of repetition is 30, the voltage is applied 10 times out of the 30 times of repetition, and the remaining 20 times The voltage may not be applied. Further, although four gradation levels are illustrated in the above example, the present invention can be applied to any gradation level.

When the color reflectance is not in the minimum state, the brightness level of the pixel may be smaller than the reflectance of the state. In this case, the number of negatives can be calculated according to the difference between the lightness level of the pixel and the level. In this case, when the absolute value of the negative number is large, the write voltage is applied between the pixel electrodes so that the reflectance of the color decreases. For example, the application frequency control circuit 1024 uses the application voltage control circuit 1025 to apply a positive voltage to the negative frequency, which is opposite to the potential difference between the pixel electrode and the substrate electrode. A write voltage is applied to the pixel electrode and the substrate electrode as follows. Further, it is conceivable that the number of times of application at that time is an absolute value of the number of negative times. As a specific example, it is assumed that the application frequency control circuit 1024 applies 15 V to the pixel electrode and applies 0 V to the substrate electrode using the application voltage control circuit 1025 for each positive frequency. When -3 is calculated as the number of negative times, 0 V is applied to the pixel electrode and 15 V is applied to the substrate electrode three times.

FIG. 8 is an example of a flowchart illustrating the flow of processing executed by the electrophoretic display device 100 according to the present embodiment. In step S501, image information representing an image is acquired. The image information may be transmitted from the outside of the electrophoretic display device 100 or read from a storage circuit (not shown) of the electrophoretic display device 100 or the like. In step S502, the lightness level of each pixel of the image represented by the acquired image information is calculated. In step S 503, the number of times of applying the write voltage pulse between the pixel electrode corresponding to each pixel and the substrate electrode is calculated using the calculated lightness level. In step S505, the application voltage control circuit 1025 is used to apply the number of write voltage pulses calculated in step S504 to the pixel electrode and the substrate electrode corresponding to each pixel.

FIG. 9 shows an example of a timing chart of voltages applied to the gate lines G1, G2, G3,..., Gm and the data lines D1, D2,. In FIG. 9, T corresponds to one frame period. During time T / n obtained by dividing T by n, the gate lines G1, G2, G3,..., Gm are sequentially selected once, and one write voltage pulse is applied. Therefore, each gate line is selected n times during one frame period, and the write voltage pulse is applied to the pixel electrode and the substrate electrode the number of times calculated according to the lightness level of the pixel.

Referring to FIG. 9, in the first application, pulses P11, P21, P31,..., Pm1 are applied to the gate lines G1, G2, G3,. Similarly, in the n-th application, pulses P1n, P2n, P3n,..., Pmn are applied to the gate lines G1, G2, G3,.

Furthermore, while P11 is applied to the gate line G1, voltages of d111, d121,..., D11 are applied to the data lines D1, D2, ..., Dl, and P21 is applied to the gate line G2, d211, d221,..., d21 1 are applied. Therefore, for example, when the number-of-applications control circuit 1024 calculates the number of times k times or -k times for the pixel at the intersection of the gate line G3 and the data line D2, d321, d322, d323,. Among them, k are voltages that change the reflectance of the pixel (for example, 15 V or -15 V according to the sign of k), and the remaining voltages do not substantially change the reflectance of the pixel (for example, 0 V) Become. The k pieces of voltage that changes the reflectance of the pixel may be the first k pieces of d 321, d 322, d 323,..., D 32 n. Alternatively, it may be the last k. Alternatively, k may be randomly selected from d321, d322, d323, ..., d32n.

Note that all of the gate lines G1, G2, G3,..., Gm may be selected once each, and then all of the gate lines G1, G2, G3,. After all of the gate lines G1, G2, G3,..., Gm have been selected once each and a predetermined time has elapsed, then all of the gate lines G1, G2, G3,. It may be done. A period in which all of the gate lines G1, G2, G3,..., Gm are selected once may be referred to as "one field period".

Referring to FIG. 9, each gate line is selected a plurality of times within the time of T which is one frame period. This is because the volume resistivity (for example, 10 ⁹ Ω cm) of the electrophoretic display material is small by selecting each gate line once in one frame period by the normal active matrix driving, and therefore the leakage current of the electrophoretic display material is When it becomes larger, the charges injected from the data line at the time of gate line selection decrease, and the effective voltage (the above-mentioned holding voltage) applied to the electrophoretic display material decreases. For this reason, the change in reflectance becomes insufficient.

As described above, the inventor of the present application applies the write voltage between the pixel electrode and the substrate electrode corresponding to each pixel, paying attention to the phenomenon that the reflectance of the electrophoretic display material changes in accordance with the holding voltage. In view of the fact that the holding voltage can be increased according to the number of times, it has been found that display of intermediate gradation can be performed.

In the present embodiment, the write voltage pulse is applied a number of times according to the lightness level of the pixel to be displayed between the pixel electrode and the substrate electrode (between the pixel electrodes). It becomes possible to display gradation brightness and various colors.

Second Embodiment
As a second embodiment of the present invention, an electrophoretic display device will be mainly described which applies a voltage for erasing a displayed image before application of a write voltage pulse by a control unit.

FIG. 10 shows an example of a functional block diagram of the electrophoretic display device according to the second embodiment of the present invention. The electrophoretic display device 700 includes a display panel 101 and a control unit 701. As an example of the configuration of the control unit 701, there is an example configured to include an image erasing circuit 702, and further to use an applied voltage control circuit 1025 and an application number control circuit 1024. In addition, the electrophoretic display device 700 may include an applied voltage control circuit 1025, a gate line drive circuit 1021, a data line drive circuit 1022, and a substrate electrode drive circuit 1023, as necessary. Therefore, the electrophoretic display device according to the present embodiment can be described as further including the image erasing circuit 702 in the electrophoretic display device according to the first embodiment.

In the present embodiment, before the application of the write voltage pulse by the control unit 701, the erase voltage of any polarity is applied between the pixel electrodes. In this case, the erase voltage may be applied almost simultaneously to all of the pixel electrodes. This is because the display contents of all the pixels can be erased at one time, and the application time of the erase voltage can be shortened.

When the image erasing circuit 702, the applied voltage control circuit 1025, and the application frequency control circuit 1024 are provided in the control unit 701, they correspond to a plurality of pixels before the application of voltage by the application frequency control circuit 1024. An erasing voltage is applied to generate a potential difference between the pixel electrode and the substrate electrode. The erase voltage causes a potential difference of either polarity to occur between the pixel electrode and the substrate electrode. The polarity, the magnitude, and the application time of the potential difference due to the erasing voltage are appropriately set depending on how to set the reflectance of the color in the whole pixel of the display panel 101 after the erasing voltage is applied.

For example, if it is desired to make the whole pixel black after applying the erasing voltage, if the black charged particles have a positive charge, the potentials of all the substrate electrodes are made lower than all the pixel electrodes. The gate line drive circuit 1021, the data line drive circuit 1022, and the substrate electrode drive circuit 1023 are operated. For example, the substrate electrode drive circuit 1023 applies 0 V, the data line drive circuit 1022 applies 15 V to all data lines, and the gate line drive circuit 1021 turns on the transistors 104 for all gate lines. Apply a voltage. As a result, the erase voltage is applied to all the pixel electrodes almost simultaneously. The length of time during which the gate line driver circuit 1021 applies a voltage to turn on the transistors 104 to all the gate lines is preferably equal to or longer than the response time. Usually, the charged particles can not move from one electrode (for example, the pixel electrode) to the other electrode unless the application time of the erasing voltage is equal to or longer than the response time. However, depending on the state of application of the voltage before the erase voltage is applied, the length of time for which the voltage for turning on the transistor 104 is applied may be shorter than the response time.

Further, the image erasing circuit 702 may apply the erasing voltage in one or more divided operations. For example, the application of the erase voltage is performed five times at intervals of 50 milliseconds at intervals of 100 milliseconds. Alternatively, when applying an erase voltage of 500 ms in length, there is a time in which an erase voltage of 250 ms is applied and a voltage of 100 ms is not applied, and even if an erase voltage of 250 ms is applied thereafter. Good. Alternatively, an erasing voltage of 200 milliseconds may be applied, and after a time when no voltage is applied, an erasing voltage of 300 milliseconds longer than 200 milliseconds may be applied. Alternatively, on the contrary, the erase voltage of 300 milliseconds is first applied, and after the time when no voltage is applied, the erase voltage of 200 milliseconds is applied. In addition, when the erase voltage is applied in one or a plurality of times, the sum of time lengths of application of the erase voltage depends on the condition of voltage application before applying the erase voltage or when the response time or more is preferable. Less than response time may be preferred. Note that the case where the erasing voltage is applied in a plurality of times by inserting a pause time during which voltage application is not performed during voltage application is referred to as "intermittently applying the erasing voltage".

Note that applying an erasing voltage that causes a potential difference between the pixel electrode corresponding to a plurality of pixels and the substrate electrode on the basis of the voltage of the substrate electrode means that the pixel electrode has any polarity. It can be paraphrased to apply the erase voltage.

FIG. 11 shows an example of a timing chart of voltages applied to the gate lines G1, G2, G3,..., Gm and the data lines D1, D2,. Before applying voltages to gate lines G1, G2, G3, ..., Gm and data lines D1, D2, ..., Dl according to the timing chart shown in Fig. 9, gate lines G1, G2, G3, ..., Gm, respectively. , Pulses pe1, pe2, pe3,..., Pem having a width of time Et are applied almost simultaneously. At the same time, pulses de1, de2, ..., del are applied to the data lines D1, D2, ..., Dl. By application of such pulses pe1, pe2, pe3, ..., pem, de1, de2, ..., del, the display panel 101 displays an image of only one predetermined color, and the pulses pe1, pe2, pe3, ..., pem , De 1, de 2,..., Del are erased. As described above, Et is preferably equal to or longer than the response time, but in certain cases, it may be preferable to be less than the response time.

After applying the pulses pe1, pe2, pe3, ..., pem, de1, de2, ..., del, the lightness level of the pixel of the acquired image information is calculated according to the flowchart of Fig. 8, and the pixel electrode and the substrate electrode are The number of times of applying the write voltage pulse is calculated, and the write voltage pulse is applied.

According to the present embodiment, prior to the display of the image, the image displayed on the display panel before that is erased and the display of a specific single color is performed, so the influence of the image displayed previously is eliminated. Thus, it is possible to easily display an image including intermediate gradations.

(Embodiment 3)
An electrophoretic display device in which an alternating voltage is applied between a pixel electrode and a substrate electrode before application of a write voltage pulse by a control unit will be described as Embodiment 3 of the present invention.

FIG. 12 shows an example of functional blocks of the electrophoretic display device according to the third embodiment of the present invention. The electrophoretic display device 900 includes a display panel 101 and a control unit 901. As an example of the configuration of the control unit 901, there is an example further including an alternating voltage application circuit 902, an applied voltage control circuit 1025, and an application number control circuit 1024. In addition, the electrophoretic display device 700 may include a gate line drive circuit 1021, a data line drive circuit 1022, and a substrate electrode drive circuit 1023, as necessary. Therefore, it can be described that the electrophoretic display device according to the present embodiment is configured to further include the alternating voltage application circuit 902 according to the first embodiment.

In the present embodiment, an alternating voltage is applied between the pixel electrodes prior to the application of the write voltage pulse. The alternating voltage is a voltage in which a positive voltage and a negative voltage alternate alternately at a predetermined frequency. Also, in general, the absolute values of the positive voltage and the negative voltage are approximately equal. However, the absolute values of the positive voltage and the negative voltage may be different. For example, at 10 Hz, 15 V and -15 V are alternately repeated. The alternating voltage may be applied to all of the pixel electrodes substantially simultaneously.

In the case where the control unit 901 includes the alternating voltage application circuit 902, the alternating voltage application circuit 902 is substantially arranged between the pixel electrodes corresponding to the respective pixels before application of the write voltage pulse by the application number control circuit 1024. The same voltage is applied to generate an alternating voltage.

In the present embodiment, for example, the substrate electrode drive circuit 1023 applies 0 V, the data line drive circuit 1022 applies an alternating voltage to all data lines, and the gate line drive circuit 1021 applies transistors to all gate lines. A voltage may be applied to turn on the switch 104. Thereby, an alternating voltage is applied substantially simultaneously between all the pixel electrodes.

Note that “applying a voltage that generates an alternating voltage to the pixel electrode and the substrate electrode” can be reworded by applying an alternating voltage to the pixel electrode, based on the voltage of the substrate electrode.

The magnitude, frequency, pulse width and application time of the positive voltage and the negative voltage of the alternating voltage determine how to reflect the color reflectance of the entire pixel of the display panel 101 after applying the alternating voltage, It is set appropriately depending on the

FIG. 13 shows an example of a timing chart of voltages applied to the gate lines G1, G2, G3,..., Gm and the data lines D1, D2,. Before applying voltages to gate lines G1, G2, G3, ..., Gm and data lines D1, D2, ..., Dl according to the timing chart shown in Fig. 9, gate lines G1, G2, G3, ..., Gm, respectively. The pulses pa1, pa2, pa3,..., Pam having a width of time Pt are applied almost simultaneously. At the same time, alternating voltages dp1, dp2,..., Dpl are applied to the data lines D1, D2,. The application of such pulses pa1, pa2, pa3,..., Pam, dp1, dp2,..., Dpl causes the display panel 101 to change the color reflectance at a predetermined frequency. After application of the alternating voltage, the display panel 101 displays the frequency of the alternating voltage, the maximum voltage, the minimum voltage, the application time, and the color of the reflectance in accordance with the potential of the last pulse.

The application time of the alternating voltage pulse is preferably equal to or less than the response time. However, when the application time of the pulse of the alternating voltage is equal to or less than the response time of the electrophoretic display material, even when the pixel is selected to be black, for example, as the polarity of the last pulse of the alternating voltage Since the response of the charged particles is insufficient and the migration distance of the charged particles is shortened, the black reflectance is higher than after applying the erasing voltage to make the pixels black as in the second embodiment. There is a case. Therefore, as described in the first embodiment, in the operation of the application frequency control circuit 1024, a negative frequency or the like needs to be used.

The application of the alternating voltage causes the charged particles and the ions present around the charged particles to respond to the alternating voltage. Therefore, the dispersibility of the charged particles and the like of the electrophoretic display material is enhanced, the aggregation of the charged particles is suppressed, and the movement of the charged particles between the pixel electrode and the substrate electrode becomes favorable.

In addition, the electrophoretic display device according to the present embodiment may have an image erasing circuit as in the electrophoretic display device according to the second embodiment. In this case, before the application of the write voltage pulse by the application number control circuit 1024, the application of the erase voltage and the application of the alternating voltage are performed. The application of the erase voltage may be performed after the application of the erase voltage, or the application of the erase voltage may be performed after the application of the alternating voltage. However, it is preferable to apply an alternating voltage before applying the erase voltage.

Alternatively, instead of using the image erasing circuit, the last pulse of the alternating voltage may be erased using the fact that the display histories of all the pixels can be erased by application to the first few voltage pulses of the alternating voltage. Can be applied as a pulse. The application of the alternating voltage and the erase voltage is such that the last pulse of the voltage pulse train is applied when a voltage pulse train in which a positive voltage and a negative voltage applied alternately before the application of the write voltage pulse are alternately applied. It can also be described that the voltage pulse train except for this is an alternating voltage and the last pulse of the voltage pulse train is a pulse of the erase voltage. Therefore, the polarity of the last pulse of the alternating voltage is opposite to the polarity of the erase voltage.

By applying the last pulse of the alternating voltage as a pulse serving as the erasing voltage, the application of the erasing voltage is included in the application of the alternating voltage, so that it is not necessary to further apply the erasing voltage exemplified in the second embodiment. It becomes possible to write an image to the display panel faster. Here, the absence of the display history means that the brightness of the pixel after application of the alternating voltage is not affected according to the brightness of the pixel immediately before applying the alternating voltage.

When the last voltage pulse of the alternating voltage is made to act as the pulse of the erasing voltage as described above, the application time of the erasing voltage is the same as the application time of the last voltage pulse of the alternating voltage. It may be present or long. Assuming that the application time of the erase voltage is the same as the application time of the last voltage pulse of the alternating voltage, the application of the erase voltage can be performed as the application of the alternating voltage, and the configuration of the circuit can be simplified. . In addition, since the dispersibility of the charged particles is improved due to the influence of the alternating voltage applied before the erasing voltage, the pixel is made black or white in the application time less than the response time as the application time of the erasing voltage. Therefore, it can be made equal to or less than the response time of the electrophoretic display material.

In the present embodiment, since an alternating voltage is applied, the movement of the charged particles between the pixel electrode and the substrate electrode is improved. Furthermore, since the last voltage pulse of the alternating voltage can be made to act as the erasing voltage, high-speed display such as halftone display of a higher quality image becomes possible.

(Example of measurement)
The changes in reflectance and contrast when the electrophoretic display device according to the embodiment described above was actually operated were actually measured. That is, a general electrophoretic display material is held and sealed so as to be held between the pixel electrode and the substrate electrode, black charged particles are present on the substrate electrode side, and white charged particles are pixel electrode The black charged particles and the white charged particles are moved so that the white charged particles are present on the substrate electrode side and the black charged particles are present on the pixel electrode side. A predetermined write voltage pulse was applied between the pixel electrode and the substrate electrode in order to cause the problem. That is, application of a voltage pulse having a gate selection time of 100 microseconds to the gate line is repeated a predetermined number of times with a time interval of 100 milliseconds, and a predetermined voltage is applied to the data line in synchronization with the selection of the gate line. The pulse was applied repeatedly.

FIG. 14 shows the black reflectance which is the black reflectance, the white reflectance which is the white reflectance, and the white reflectance with respect to the black reflectance with respect to the number of times that such a voltage pulse is applied to the gate line. Fig. 6 shows a graph of the change with the contrast, which is the magnitude.

As shown in the graph of FIG. 14, it can be seen that the white reflectance increases as the number of times of application of a voltage pulse having a gate selection time of 100 microseconds to the gate line increases. It can also be seen that the contrast is also rising.

(Example)
Various embodiments of the present invention will be described with reference to FIGS. 15-21.

FIG. 15 is a schematic view of a display panel commonly used in the embodiments of FIG. 16 to FIG. Referring to FIG. 15, three gate lines G1, G2 and G3 are disposed, and two data lines D1 and D2 are disposed substantially orthogonal to gate lines G1, G2 and G3. The

pixel elements

1, 2, 3, 4, 5, 6 are disposed at the intersections of G1 and D1, G2 and D1, G3 and D1, G1 and D2, G2 and D2, and G3 and D2, respectively. In the embodiments shown in FIGS. 16 to 21, one frame period T consists of nine of the field periods. Therefore, as for

pixel elements

1, 2, 3, 4, 5, 6, in the first scan of the gate line,

pixel elements

1 and 4,

pixel elements

2 and 5, and

pixel elements

3 and 6 are sequentially selected. The scan is repeated several times.

Therefore, in the embodiment described below, for example, the application frequency control circuit 1024 can apply up to nine write voltage pulses to each pixel element using the application voltage control circuit 1025. Also, before and after the application of the maximum of nine writing voltage pulses, the change in reflectance of the pixel element 1 is the largest for the predetermined color is large, and then the

pixel elements

2 and 5 are the next and the pixel element 3 and so on. The number of times of application of the write voltage pulse is controlled such that 4 continues. In addition, the pixel element 6 is controlled such that the reflectance does not change. For example, after application of a maximum of nine writing voltage pulses, pixel element 1 is white,

pixel elements

2 and 5 are slightly light gray,

pixel elements

3 and 4 are gray, and pixel element 6 is black. To be controlled. In the following example, the white charged particles are positively charged and the black charged particles are negatively charged. However, the same applies to the method of the present invention when the polarity of the charge is reversed. The method of applies.

Example 1
FIG. 16 is a diagram for explaining the case where the erase voltage is applied before applying the write voltage pulse of the number of times to each pixel element. That is, the second embodiment mainly corresponds to the second embodiment.

As shown in FIG. 16, an erase voltage (denoted as a reset pulse in FIG. 16) is applied prior to the application of a maximum of nine write voltage pulses. To apply the erase voltage, for example, as described above, a voltage pulse is simultaneously applied to all gate lines to apply a voltage pulse for turning on the transistor 104 between the pixel electrodes, and in synchronization with this, all data lines are applied. This is done by applying an erase voltage. If the period for applying the erase voltage is extended, the gate selection time can be extended accordingly. For example, if the time for applying the erase voltage is about the response time, the gate selection time can also be about the response time. The magnitude of the erase voltage is -V. By applying this erase voltage, all pixel elements become black. Preferably, the erase voltage is applied for a period of about response time. For example, the erase voltage is applied for the response time or more. By applying the erase voltage during the response time period, the reflectance is substantially minimized or substantially maximized. As a result, after application of the erase voltage, mid-gradation display can be favorably performed by application of the write voltage pulse by the control unit. However, depending on the state of voltage application before applying the erase voltage, the dispersibility of the charged particles is different, so the application period of the erase voltage may be less than the response time.

After application of the erase voltage, the gate lines G1, G2, G3 are sequentially scanned during T / 9, and in synchronization therewith, the desired voltages are applied to the respective pixel elements on the data lines D1, D2. , A predetermined write voltage pulse is applied, and this is repeated nine times. A write voltage pulse of V is applied to pixel element 1 each time, a write voltage pulse of 6 V is applied to

pixel elements

2 and 5, and V times of 3 times is applied to

pixel elements

3 and 4. Write voltage pulses are applied. Further, there are cases where 0 V is applied each time and -V is applied to the pixel element 6. Since the voltage of -V is applied as the erase voltage, substantial movement of the charged particles does not occur even if 0 V is applied or -V is applied.

As shown in FIG. 16, the average voltage value of the application of the write voltage pulse after the application of the erase voltage is V, 2V / 3, V / 3, V / 3 for pixel elements 1 to 6, respectively. , 2V / 3, 0 or -V. The lightness of each pixel element is the lightness corresponding to the average voltage value.

(Example 2)
FIG. 17 is a diagram for explaining the case where the control unit intermittently applies the erase voltage one or more times before applying the write voltage pulse of the number of times to each pixel element. That is, the second embodiment mainly corresponds to the second embodiment.

As shown in FIG. 17, the application of the erase voltage -V and the application of the erase voltage are alternately repeated prior to the application of the maximum of nine write voltage pulses. For the application of the erase voltage, for example, as described above, a voltage pulse for turning on the transistor 104 is applied to all the gate lines, and in synchronization with this, a voltage pulse is applied to all the data lines. The application of the erase voltage and the application of the erase voltage are alternately repeated. By applying a pulse-like erasing voltage (or intermittent erasing voltage), all pixel elements become black.

The reason for using the intermittent erasing voltage is that when a DC voltage is continuously applied for a long time, the contrast is lowered due to so-called burn-in of the display or convection of the solvent. The intermittent application of the erasing voltage makes it possible to shorten the application time of the DC voltage, to suppress the deterioration of the contrast due to the burn-in of the display and the convection of the solvent, and to improve the quality of the display.

Moreover, it is preferable that the total of the application time of the intermittent erase voltage be about the response time. For example, the application time of the intermittent erase voltage is set to the response time or more. This is because the reflectance is substantially minimized or substantially maximized by such intermittent application of the erasing voltage. As a result, by applying the voltage pulse by the application number control circuit 1024, it is possible to satisfactorily perform half tone display. However, depending on the state of voltage application before applying the erase voltage, the dispersibility of the charged particles is different, so the sum of the application periods of the erase voltage may be less than the response time.

After applying the erasing voltage intermittently one or more times, the gate lines G1, G2 and G3 are sequentially scanned during T / 9, and in synchronization therewith, the data lines D1 and D2 are desired for each pixel element. As a voltage is applied, a predetermined voltage pulse is applied, which is repeated nine times. A write voltage pulse of V is applied to pixel element 1 each time, a write voltage pulse of 6 V is applied to

pixel elements

2 and 5, and V times of 3 times is applied to

pixel elements

3 and 4. Write voltage pulses are applied. Further, there are cases where 0 V is applied each time and -V is applied to the pixel element 6.

(Example 3)
FIG. 18 is a diagram for explaining the case where an alternating voltage is applied before the control unit applies the write voltage pulse of the number of times to each pixel element. That is, this mainly corresponds to the third embodiment.

As shown in FIG. 18, voltages V and -V are alternately applied before the application of the voltage up to nine times. For the application of the alternating voltage, for example, as described above, a voltage pulse for turning on the transistor 104 is applied to all gate lines, and in synchronization with this, a voltage pulse is applied to all data lines to alternate between the pixel electrodes. It does by applying a voltage. Thereafter, the gate lines G1, G2 and G3 are sequentially scanned during T / 9, and in synchronization therewith, a predetermined voltage is applied to the data lines D1 and D2 so that a desired voltage is applied to each pixel element. A pulse is applied and this is repeated nine times. A write voltage pulse of V is applied to pixel element 1 each time, a write voltage pulse of 6 V is applied to

pixel elements

2 and 5, and V times of 3 times is applied to

pixel elements

Since the alternating voltage is a voltage pulse that alternates between positive and negative polarities, the charged particles of the electrophoretic display material react to the polarity of the alternating voltage, for example, white charged particles and black charged particles. Move towards each other in the direction of the electrodes. Thus, depending on the polarity of the last voltage pulse of the alternating voltage, the electrophoretic display material has a predetermined reflectivity. Since the reflectance of the electrophoretic display material realized by the voltage pulse of the last polarity of the alternating voltage has the same effect as the case where the erasing voltage is applied, the alternating voltage is applied prior to the application of the writing voltage pulse. The new erase voltage is selected by selecting the polarity of the last pulse of the alternating voltage as the polarity to erase the image, ie by setting the polarity of the last pulse of the alternating voltage to the polarity of the erase voltage. Can be omitted. For this reason, it is possible to perform halftone display in a short time.

The frequency of the alternating voltage is preferably in the range of 10 Hz to 200 Hz, and more preferably in the range of 20 Hz to 100 Hz. If the frequency of the alternating voltage is small, for example, less than 10 Hz, it may be recognized that flicker is displayed on the display panel, and the display quality may be impaired. In addition, since the ionic substance contained in the electrophoretic display material responds to a high frequency of several tens of kilohertz, if the frequency of the alternating voltage is high, for example, exceeding 200 Hz, the effect of improving the dispersibility of charged particles may be generated. However, the tracking of the charged particles to the alternating voltage is low. For this reason, the application of the write voltage pulse may make it impossible to satisfactorily perform intermediate gray scale display.

(Example 4)
FIG. 19 shows the case where the alternating voltage is applied and the erase voltage is applied in the order of the alternating voltage and the erase voltage before the control unit applies the write voltage pulse of the number of times to each pixel element. FIG. That is, this corresponds mainly to the third embodiment. For example, the electrophoretic display device according to the third embodiment has an image erasing circuit.

As shown in FIG. 19, before application of a maximum of nine write voltage pulses per pixel element, first, voltages of V and -V are alternately applied to apply an alternating voltage to erase -V. A voltage is applied. For the application of the alternating voltage and the erasing voltage, for example, as described above, a voltage pulse for turning on the transistor 104 is applied to all gate lines, and a voltage pulse is applied to all data lines in synchronization with this. An alternating voltage and an erase voltage are applied in this order in the meantime. Thereafter, the gate lines G1, G2 and G3 are sequentially scanned during T / 9, and in synchronization therewith, predetermined voltage pulses are applied to the data lines D1 and D2 so that a desired voltage is applied to each pixel element. Is applied, and this is repeated nine times. A write voltage pulse of V is applied to pixel element 1 each time, a write voltage pulse of 6 V is applied to

pixel elements

2 and 5, and V times of 3 times is applied to

pixel elements

In the present embodiment, the application time of the erase voltage of −V applied after the application of the alternating voltage is preferably smaller than the response time. Even if the erase voltage is not applied for about the response time, since the alternating voltage is applied before the application of the erase voltage, the uniform dispersion of the charged particles is enhanced. For this reason, it is considered that movement of the charged particles by application of the erase voltage of -V becomes good within one frame period immediately after application of the alternating voltage of -V, and the erase voltage is applied smaller than the response time. Even the reflectance can be made approximately minimum or approximately maximum. By applying the erase voltage by the application frequency control circuit 1024, it is possible to satisfactorily perform half tone display. If the application time of the erasing voltage is long, convection of the solvent of the electrophoretic display material occurs, and the reflectance may increase from the minimum reflectance or decrease from the maximum reflectance. Further, by making the application time of the erasing voltage smaller than the response time, it is possible to shorten the time required to display an image on the display panel.

(Example 5)
FIG. 20 shows that an alternating voltage is applied and a pulse-like erase voltage is applied in the order of the alternating voltage and the erase voltage before the control unit applies the write voltage pulse of the number of times to each pixel element. It is a figure explaining the case where it carries out. That is, this corresponds mainly to the third embodiment. For example, the electrophoretic display device according to the third embodiment has the image erasing circuit, and the image erasing circuit applies a pulse-like erasing voltage as a modification of the second embodiment. It corresponds to the case.

As shown in FIG. 20, voltages V and -V are alternately applied before application of a maximum of nine write voltage pulses per pixel element. Then, an erase voltage of -V is applied intermittently. In intermittent application of the alternating voltage and the erasing voltage, for example, as described above, voltage pulses for turning on the transistor 104 are applied to all gate lines, and voltage pulses are applied to all data lines in synchronization with this. This is performed by intermittently applying an alternating voltage and an erase voltage between the electrodes. Thereafter, the gate lines G1, G2 and G3 are sequentially scanned during T / 9, and in synchronization therewith, predetermined voltage pulses are applied to the data lines D1 and D2 so that a desired voltage is applied to each pixel element. Is applied, and this is repeated nine times. A write voltage pulse of V is applied to pixel element 1 each time, a write voltage pulse of 6 V is applied to

pixel elements

2 and 5, and V times of 3 times is applied to

pixel elements

Preferably, the total sum of the application time of the erasing voltage which is intermittent is smaller than the response time. Even if the intermittent erase voltage is not applied for about the response time, since the alternating voltage is applied before the application of the erase voltage, the uniform dispersion of the charged particles is enhanced. For this reason, it is considered that the movement of the charged particles due to the application of the erasing voltage is improved, and the reflectance can be substantially minimized or substantially maximized even if the erasing voltage is smaller than the response time. As a result, the application of the voltage pulse by the application frequency control circuit 1024 makes it possible to achieve good gray scale display. In addition, by shortening the application time of the erasing voltage which is intermittent, it is possible to shorten the time required to display an image on the display panel.

(Example 6)
FIG. 21 is a diagram for explaining a case where an alternating voltage is applied before the control unit applies the write voltage pulse of each number to each pixel element, and thereafter, a voltage pulse of -V is applied a predetermined number of times is there. That is, this corresponds mainly to the third embodiment. For example, the electrophoretic display device according to the third embodiment has an image erasing circuit.

As shown in FIG. 21, voltages V and -V are alternately applied before application of a maximum of nine write voltage pulses per pixel element. Then, a voltage pulse of -V is applied a predetermined number of times, and the application of the alternating voltage is performed, for example, as described above, by applying a voltage pulse that turns on the transistor 104 to all gate lines. This is performed by applying a voltage pulse to the data line and applying an alternating voltage between the pixel electrodes. Thereafter, the gate lines G1, G2 and G3 are sequentially scanned during T / 12, and in synchronization therewith, predetermined voltage pulses are applied to the data lines D1 and D2 so that a desired voltage is applied to each pixel element. Is applied, and this is repeated 11 times. A write voltage pulse of -V is applied to each pixel element a predetermined number of times (twice) in the first two scannings of the gate lines, and thereafter, a write voltage pulse of V is applied to pixel element 1 each time Thus, six write voltage pulses of V are applied to the

pixel elements

2 and 5, and three write voltage pulses of V are applied to the

pixel elements

3 and 4. In addition, there are cases where 0 V is applied each time and a write voltage pulse of -V is applied to the pixel element 6.

Voltage pulses of positive polarity and negative polarity are alternately applied by the alternating voltage. Thus, the electrophoretic display material responds to the polarity of the alternating voltage, and the white charged particles and the black charged particles move in opposite directions. Thus, depending on the polarity of the last voltage pulse of the alternating voltage, the electrophoretic display material will have a predetermined reflectivity. That is, the reflectance set by the last voltage pulse of the alternating voltage has the same effect as the application of the erase voltage, and the polarity of the plurality of voltage pulses applied by the application frequency control circuit 1024 is the alternating voltage. In the case where the polarity of the last voltage pulse is reversed, it is not necessary to apply a new erase voltage. Therefore, halftone display can be performed efficiently in a short time.

However, depending on the configuration of the electrophoretic display device, etc., the reflectance obtained by the last voltage pulse of the alternating voltage does not reach a predetermined reference, and for example, the last of the alternating voltage is desired to be blackened by the erase voltage. The voltage pulse may not provide the desired black state. Even in this case, according to the present embodiment, the first several times among the plurality of voltage pulses applied by the application frequency control circuit 1024 without newly applying the erase voltage to all the pixel elements substantially simultaneously. The polarity of the write voltage is made the same as that of the last voltage pulse of the alternating voltage, and the polarity of the subsequent voltage pulse is reversed to the polarity of the last voltage pulse of the alternating voltage. As a result, it is possible to display halftones efficiently. Since the alternating voltage is applied prior to application of a plurality of voltage pulses by the application frequency control circuit 1024, the dispersibility of the white charged particles of the electrophoretic display material and the black charged particles is enhanced, and the application frequency control circuit applies the voltage. The desired first black state is obtained by the first few voltage pulses.

In the present embodiment, since the alternating voltage is applied first, the movement of the charged particles between the pixel electrode and the substrate electrode occurs due to the phenomenon that ions existing around the charged particles are separated from the charged particles. It becomes good. Therefore, the time for applying the erase voltage is shorter than the response time. The same applies to other embodiments in which an alternating voltage is initially applied.

DESCRIPTION OF SYMBOLS 100 Electrophoretic display device, 101 display panel, 102 control part, 1021 gate line drive circuit, 1022 data line drive circuit, 1023 substrate electrode drive circuit, 103 application number control circuit, 1024 application number control circuit, 1025 applied voltage control circuit

Claims

A plurality of transistors are provided, the gate electrode of each of the plurality of transistors is connected to any of a plurality of gate lines, one of the source electrode and the drain electrode is connected to any of a plurality of data lines, the source electrode and the drain A display panel in which the other of the electrodes is connected to one of two pixel electrodes for sandwiching the electrophoretic display material;
An electrophoretic display device, comprising: a control unit that applies, during one frame period, voltage pulses of the number according to the lightness level of a pixel of an image to be displayed on the display panel between the pixel electrodes corresponding to the pixel.
The electrophoretic display device according to claim 1, wherein a volume resistivity of the electrophoretic display material is 10 12 Ωcm or less.
2. The electrophoretic display device according to claim 1, wherein an erasing voltage of any polarity is applied substantially simultaneously between all the pixel electrodes before the application of the voltage pulse by the control unit. .
The electrophoretic display device according to claim 3, wherein the erase voltage is applied as one voltage pulse or a plurality of intermittent voltage pulses of the same polarity.
5. The electrophoretic display device according to claim 4, wherein a sum of application times of the plurality of voltage pulses is equal to or less than a response time of the electrophoretic display material.
The electrophoretic display device according to claim 1, wherein an alternating voltage is applied substantially simultaneously between all the pixel electrodes before the application of the voltage pulse by the control unit.
The alternating voltage is applied between all the pixel electrodes substantially simultaneously before the application of the voltage pulse by the control unit, and then the erase voltage of any polarity is applied. Electrophoretic display device as described.
The erase voltage is applied as one voltage pulse or a plurality of intermittent voltage pulses of the same polarity, and a total of application times of the plurality of voltage pulses is equal to or less than a response time. The electrophoretic display device according to Item 7.
8. The electrophoretic display device according to claim 7, wherein the polarity of the erase voltage is opposite to the polarity of the last pulse of the alternating voltage.
8. The electrophoretic display according to claim 7, wherein the application time of the erasing voltage is equal to or more than the application time of the last pulse of the alternating voltage and equal to or less than the response time of the electrophoretic display material. apparatus.
A plurality of transistors are provided, the gate electrode of each of the plurality of transistors is connected to any of a plurality of gate lines, one of the source electrode and the drain electrode is connected to any of a plurality of data lines, the source electrode and the drain A method of driving a display panel in which the other of the electrodes is connected to one of two pixel electrodes for sandwiching an electrophoretic display material,
In the display panel, a write voltage pulse is applied between the pixel electrodes corresponding to the pixels a number of times according to the lightness level of the pixel of the image to be displayed on the display panel in one frame period. How to drive.
The method of driving a display panel according to claim 11, wherein a volume resistivity of the electrophoretic display material is 10 12 Ωcm or less.
12. The method of driving a display panel according to claim 11, wherein an erase voltage of any polarity is applied between all the pixel electrodes substantially simultaneously before the application of the write voltage pulse. .
The method of claim 13, wherein the erase voltage is applied as one voltage pulse or a plurality of intermittent voltage pulses of the same polarity.
The method according to claim 14, wherein a sum of application times of the plurality of voltage pulses is equal to or less than a response time of the electrophoretic display material.
12. The method according to claim 11, wherein an alternating voltage is applied substantially simultaneously between all the pixel electrodes before the application of the write voltage pulse.
The alternating voltage is applied between all the pixel electrodes substantially simultaneously before the application of the write voltage pulse, and then the erase voltage of any polarity is applied. , How to drive the display panel.
The erase voltage is applied as one voltage pulse or a plurality of intermittent voltage pulses of the same polarity, and a total of application times of the plurality of voltage pulses is equal to or less than a response time. Item 18. A method of driving a display panel according to item 17.
The method of claim 17, wherein the polarity of the erase voltage is opposite to the polarity of the last pulse of the alternating voltage.
The display panel according to claim 17, wherein the application time of the erase voltage is equal to or more than the application time of the last pulse of the alternating voltage and equal to or less than the response time of the electrophoretic display material. Driving method.