WO2011108313A1 - Solenoid drive circuit - Google Patents

Solenoid drive circuit Download PDF

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Publication number
WO2011108313A1
WO2011108313A1 PCT/JP2011/051659 JP2011051659W WO2011108313A1 WO 2011108313 A1 WO2011108313 A1 WO 2011108313A1 JP 2011051659 W JP2011051659 W JP 2011051659W WO 2011108313 A1 WO2011108313 A1 WO 2011108313A1
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WO
WIPO (PCT)
Prior art keywords
switching element
voltage
solenoid coil
terminal
solenoid
Prior art date
Application number
PCT/JP2011/051659
Other languages
French (fr)
Japanese (ja)
Inventor
菊池 宏
水野 博之
Original Assignee
シーケーディ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シーケーディ株式会社 filed Critical シーケーディ株式会社
Priority to KR1020127025939A priority Critical patent/KR101222315B1/en
Priority to CN201180011746.7A priority patent/CN102782779B/en
Publication of WO2011108313A1 publication Critical patent/WO2011108313A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F7/00Magnets
    • H01F7/06Electromagnets; Actuators including electromagnets
    • H01F7/08Electromagnets; Actuators including electromagnets with armatures
    • H01F7/18Circuit arrangements for obtaining desired operating characteristics, e.g. for slow operation, for sequential energisation of windings, for high-speed energisation of windings
    • H01F7/1805Circuit arrangements for holding the operation of electromagnets or for holding the armature in attracted position with reduced energising current
    • H01F7/1811Circuit arrangements for holding the operation of electromagnets or for holding the armature in attracted position with reduced energising current demagnetising upon switching off, removing residual magnetism
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F7/00Magnets
    • H01F7/06Electromagnets; Actuators including electromagnets
    • H01F7/08Electromagnets; Actuators including electromagnets with armatures
    • H01F7/18Circuit arrangements for obtaining desired operating characteristics, e.g. for slow operation, for sequential energisation of windings, for high-speed energisation of windings
    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F16ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
    • F16KVALVES; TAPS; COCKS; ACTUATING-FLOATS; DEVICES FOR VENTING OR AERATING
    • F16K31/00Actuating devices; Operating means; Releasing devices
    • F16K31/02Actuating devices; Operating means; Releasing devices electric; magnetic
    • F16K31/06Actuating devices; Operating means; Releasing devices electric; magnetic using a magnet, e.g. diaphragm valves, cutting off by means of a liquid

Definitions

  • the present invention relates to a solenoid drive circuit for driving a solenoid valve.
  • a solenoid valve driving circuit there is known a solenoid drive circuit that performs a plunger suction operation by energizing a solenoid coil.
  • a solenoid drive circuit as shown in Patent Document 1, a timer circuit including a capacitor, an adsorption transistor through which an adsorption current corresponding to a plunger adsorption operation flows by being turned on for a timer time defined by the timer circuit, And a holding transistor in which a holding current smaller than the attracting current flows by turning on after the timer time elapses is known.
  • the solenoid drive circuit of Patent Document 1 includes a diode reversely connected in parallel to the solenoid coil. Since the surge voltage is absorbed up to the threshold voltage in the forward direction of the diode, the influence of the surge voltage on other elements is reduced.
  • the present invention has been made in view of such circumstances, and has as its main object to provide a solenoid drive circuit that can be switched at high speed by suppressing a response delay caused by a surge voltage.
  • Means 1 A solenoid coil that generates a magnetic field when energized and drives an electromagnetic valve; and a switching element connected in series to the solenoid coil, the series connection body of the solenoid coil and the switching element being a power source
  • the solenoid coil is connected to a pair of power supply terminals to which a voltage is applied. When the power supply voltage is applied, the switching element is turned on to form an energization path for the solenoid coil.
  • a first switching element that is turned on until a predetermined time elapses after the power supply voltage is applied, and in parallel with the first switching element Connected and while the power supply voltage is applied And a second energization path through the first switching element and a second energization path through the second switching element as the energization path of the solenoid coil.
  • a limiting resistor is provided on the second energization path so that a current flowing on the second energization path is smaller than a current flowing on the first energization path.
  • a first input path connecting the input terminal of the first switching element and one of the pair of power supply terminals, and a first input path connecting the input terminal of the second switching element and the one power supply terminal.
  • Two input paths are provided in parallel, provided on the first input path, and the first switching element is in an ON state with respect to the first switching element over the specific time.
  • a zener diode or varistor and a surge voltage generated when the energization of the solenoid coil is stopped is absorbed up to a threshold voltage at which the zener diode or the varistor becomes conductive.
  • a solenoid drive circuit wherein a surge voltage absorbed up to the threshold voltage is applied to each switching element.
  • each switching element when the power supply voltage is applied, each switching element is turned on. In this case, since a limiting resistor is provided on the second energization path, current flows through the first energization path. Thereafter, the first switching element is turned off at a timing when a specific time elapses with respect to the application voltage application start timing, and a current flows through the second energization path. The current is smaller than the current flowing on the first energization path. As a result, a current corresponding to the plunger adsorption operation of the solenoid valve is caused to flow based on the start of application of the power supply voltage, and after completion of the plunger adsorption operation, a current smaller than that current is caused to flow to reduce power consumption. You can plan.
  • the threshold voltage maintaining time can be shortened compared to the configuration in which the diode is provided to absorb the surge voltage. it can.
  • the response delay time of the solenoid valve can be shortened, and high-speed switching can be handled. Therefore, it can respond to the high-speed switching of a solenoid valve.
  • the element when a surge voltage lowered to the threshold voltage is applied to an element having a relatively low withstand voltage in a situation where the threshold voltage is set high, the element may be destroyed.
  • the capacitor when a capacitor is provided as a timer circuit, the capacitor may be destroyed by a surge voltage.
  • the surge absorbing circuit is connected in parallel to the solenoid coil, and is connected in series to the switching elements, so that the surge voltage is not transmitted to the input paths.
  • the solenoid drive circuit according to means 1, wherein the path and each of the energization paths are independent.
  • the surge absorption circuit since the surge absorption circuit is provided in parallel with the solenoid coil, when a surge voltage is generated, a closed loop circuit is formed by the solenoid coil and the surge absorption circuit. The surge voltage is absorbed by the closed loop circuit until the surge voltage reaches the threshold voltage.
  • a diode may be provided in parallel to the solenoid drive circuit so as to be forward with respect to the surge voltage from the viewpoint of surge voltage protection.
  • a closed loop circuit is formed by the switching element, the diode, and the solenoid coil. Then, current continues to flow in the solenoid coil until the surge voltage becomes lower than the threshold voltage (threshold voltage in the forward direction of the diode). For this reason, the influence of the surge voltage on other elements can be reduced, while the response delay time of the solenoid valve becomes longer than the response delay time based on the threshold voltage of the Zener diode or varistor.
  • each switching element and each energization path for generating the surge voltage are independent from each other, the surge voltage is not transmitted to each input path. Thereby, each switching element is not turned on based on the surge voltage. Therefore, the inconvenience can be avoided.
  • Means 3 On the second input path, there is provided a defining resistor that defines driving power supplied to the input terminal of the second switching element, and the timer circuit is connected in series with the time constant resistor and the time constant resistor.
  • a closed loop including the specified resistor, the time constant resistor, and the capacitor is formed by connecting the input paths, and the closed loop is configured to store the charge accumulated in the capacitor.
  • the charge accumulated in the capacitor is discharged in a closed loop formed by connecting the input paths.
  • a time constant resistor and a capacitor are provided on the first input path, and a specified resistor is provided on the second input path, in order to define the drive power supplied to each switching element. ing. For this reason, it is not necessary to provide on each input path a semiconductor element that changes from a non-conductive state to a conductive state when a predetermined threshold voltage is applied. Thereby, by not providing the semiconductor element on the discharge path, the charge accumulated in the capacitor can be suitably discharged.
  • the charge corresponding to the threshold voltage necessary for these semiconductor elements to become conductive remains without being discharged. To do. Since this residual charge is released by natural discharge, the discharge time required until the charge accumulated in the capacitor is completely discharged becomes longer. Then, there is a case where electric charge remains in the capacitor at the timing when the application of the power supply voltage is started again after the application of the power supply voltage is stopped. In this case, since the specific time varies depending on the remaining charge amount, the first switching element may be turned off before the plunger adsorption operation is completed. However, if the specific time is set longer in response to the change in the on-time of the first switching element based on the residual charge amount, there is a concern that the power consumption increases.
  • the semiconductor element since the semiconductor element is not provided on the discharge path, the charge accumulated in the capacitor can be completely discharged without performing the natural discharge.
  • the discharge time can be shortened as compared with the case where the operation is performed. Thereby, specific time can be set short and reduction of power consumption can be aimed at.
  • the resistance value of the specified resistor is set so that the time required to complete the discharge of the charge accumulated in the capacitor is shorter than the time required for the surge voltage to be absorbed to the threshold voltage.
  • the means 4 when the application of the power supply voltage is stopped in a situation where the capacitor is provided as the timer circuit, a surge voltage is generated and the discharge of the capacitor is started.
  • the charge stored in the capacitor via the second input path is input to the input terminal of the second switching element, and the second switching element may be turned on.
  • the resistance value of the specified resistor is set so that the discharge of the capacitor charge is completed at a timing before the timing at which the surge voltage becomes the threshold voltage.
  • the second switching element is in the off state at the timing when the threshold voltage is reached.
  • the first switching element is an NPN-type first bipolar transistor
  • the second switching element is an NPN-type second bipolar transistor
  • each energization path has one end of the solenoid coil connected to the pair of power supply terminals. And the other end is connected to the collector terminal of each bipolar transistor, and the emitter terminal of each bipolar transistor is connected to the-terminal of the pair of power supply terminals.
  • the limiting resistor is provided between the collector of the second bipolar transistor and the other end of the solenoid coil, and the first input path constitutes the base terminal of the first bipolar transistor and constitutes the timer circuit Connected to the + terminal through a time constant resistor and capacitor, And the second input path connects the base terminal of the second bipolar transistor to the + terminal via a first specified resistor, and The zener diode or varistor is connected in parallel to the solenoid coil and connected to each of the bipolar transistors.
  • the solenoid drive circuit according to any one of means 1 to 4, wherein the solenoid drive circuit is connected in series.
  • an adsorption current corresponding to the plunger adsorption operation can be supplied to the solenoid coil, and when a specific time has elapsed, a holding current smaller than the adsorption current can be supplied. .
  • each bipolar transistor is turned off. In this case, a surge voltage is generated in the solenoid coil, but since the surge voltage is not input to the base of each bipolar transistor, the bipolar transistor is prevented from being turned on based on the surge voltage. Yes.
  • the circuit diagram of the solenoid drive circuit of 1st Embodiment The timing chart for demonstrating the electric current change which flows into a solenoid coil, and operation
  • FIG. 1 is a circuit diagram of a solenoid drive circuit 10 for driving a solenoid valve.
  • the solenoid drive circuit 10 includes a solenoid coil 11 that performs a plunger suction operation, and a suction transistor 12 (first switching element) connected in series to the solenoid coil 11.
  • the adsorption transistor 12 is an NPN bipolar transistor. In the following description, the bipolar transistor is simply referred to as a transistor.
  • One end of the solenoid coil 11 is connected via a switch 13 to a + terminal 14a corresponding to one of the pair of power terminals 14a and 14b.
  • the other end of the solenoid coil 11 is connected to the collector of the adsorption transistor 12.
  • the emitter of the adsorption transistor 12 is connected through a diode 15 to a negative terminal 14b corresponding to the other power supply terminal.
  • a + terminal 14 a is connected to the base of the adsorption transistor 12 through a switch 13 and a timer circuit 16.
  • a path connecting the base of the adsorption transistor 12 and the + terminal 14a corresponds to a first input path.
  • the timer circuit 16 has a driving current that turns on the adsorption transistor 12 with respect to the base of the adsorption transistor 12 for a specific time after the switch 13 is turned on (after the power supply voltage is applied).
  • Supply Specifically, the timer circuit 16 includes a capacitor 21 and a resistor 22 (time constant resistor) connected in series to the capacitor 21. Each element is connected so that the power supply voltage from the + terminal 14 a is applied to the base of the adsorption transistor 12 through a series connection body of the resistor 22 and the capacitor 21.
  • a predetermined current flows through the solenoid coil 11 via the adsorption transistor 12.
  • the energization path via the adsorption transistor 12 corresponds to the first energization path A.
  • the solenoid drive circuit 10 includes a resistor 23 connected in series to the timer circuit 16. One end of the resistor 23 is connected to the capacitor 21, and the other end is connected to the negative terminal 14 b via the diode 15.
  • the switch 13 is turned off (when application of the power supply voltage is stopped)
  • the electric charge accumulated in the capacitor 21 is discharged through the resistors 22 and 23. Therefore, it can be said that the resistors 22 and 23 form a discharge path of the capacitor 21.
  • the resistance values of the resistors 22 and 23 are set so that the drive current is supplied to the base of the adsorption transistor 12 when a power supply voltage is applied in a state where no charge is accumulated in the capacitor 21. Yes.
  • the solenoid drive circuit 10 is provided with a second energization path B through which a current smaller than a current flowing through the first energization path A flows in addition to the first energization path A as an energization path of the solenoid coil 11.
  • the solenoid drive circuit 10 includes a limiting resistor 31 and an NPN-type holding transistor 32 (second switching element) connected in series to the solenoid coil 11 and connected in parallel to the adsorption transistor 12. ).
  • the limiting resistor 31 and the holding transistor 32 are connected in series. Specifically, one end of the limiting resistor 31 is connected to the collector of the holding transistor 32. The other end of the limiting resistor 31 is connected to the other end of the solenoid coil 11, and the emitter of the holding transistor 32 is connected to the ⁇ terminal 14 b via the diode 15.
  • the base of the holding transistor 32 is configured to be supplied with a drive current that turns on the holding transistor 32 when the switch 13 is turned on.
  • the solenoid drive circuit 10 includes a base current supply circuit 33 having a resistor 33a and a resistor 33b connected in series to the resistor 33a.
  • the base current supply circuit 33 is configured such that a power supply voltage is applied.
  • one end of the resistor 33a is connected to the + terminal 14a via the switch 13, and the other end of the resistor 33b is connected to the diode 15. Is connected to the negative terminal 14b.
  • the base of the holding transistor 32 is connected in parallel to the resistor 33b.
  • the resistance values of the resistors 33a and 33b are set so that the drive current is supplied to the base of the holding transistor 32 when the switch 13 is on.
  • a path connecting the base of the holding transistor 32 and the + terminal 14a corresponds to the second input path, and the resistors 33a and 33b correspond to the specified resistance.
  • the drive current is supplied to the base of the holding transistor 32, and the holding transistor 32 is turned on.
  • the adsorption transistor 12 is turned off, a current flows through the solenoid coil 11 via the limiting resistor 31 and the holding transistor 32.
  • the energization path through the limiting resistor 31 and the holding transistor 32 corresponds to the second energization path B.
  • the current flowing through the second energization path B is smaller than the current flowing through the first energization path A by the amount provided with the limiting resistor 31.
  • the solenoid drive circuit 10 is provided with a bidirectional Zener diode 40 as a surge absorbing circuit.
  • the bidirectional Zener diode 40 is connected in parallel to the solenoid coil 11 and is connected in series to the series connection body including the limiting resistor 31 and the holding transistor 32 and the adsorption transistor 12.
  • the Zener voltage of the bidirectional Zener diode 40 is set to be smaller than the withstand voltage (for example, 50V) of the adsorption transistor 12 and the holding transistor 32, and is specifically set to 47V.
  • the bidirectional Zener diode 40 when a surge voltage equal to or higher than the Zener voltage is generated in the solenoid coil 11, the bidirectional Zener diode 40 becomes conductive, and a surge current flows through the solenoid coil 11 through the bidirectional Zener diode 40. Thereafter, when the surge voltage becomes smaller than the Zener voltage due to the voltage drop, the bidirectional Zener diode 40 becomes non-conductive. As a result, the surge voltage is absorbed up to the Zener voltage.
  • the Zener voltage is set higher than the power supply voltage (24V) applied to the solenoid drive circuit 10.
  • the bidirectional Zener diode 40 is in a non-conductive state in a situation where the power supply voltage is applied, and a predetermined current flows through the solenoid coil 11.
  • the solenoid drive circuit 10 is provided with a light emitting diode 50.
  • the light emitting diode 50 has an anode connected to the + terminal 14 a via the switch 13 and a cathode connected to the ⁇ terminal 14 b via the diode 15. Thereby, the light emitting diode 50 emits light in a situation where the power supply voltage is applied.
  • FIGS. 2A is a graph showing a change in current flowing through the solenoid coil 11
  • FIG. 2B is a timing chart showing ON / OFF of the switch 13
  • FIG. 2C is a timing chart showing ON / OFF of the adsorption transistor 12
  • FIG. (D) is a timing chart showing ON / OFF of the holding transistor 32.
  • FIG. 3A is an explanatory diagram for explaining how the surge voltage is absorbed
  • FIG. 3B is an explanatory diagram for explaining how the capacitor 21 is discharged.
  • the light emitting diode 50 emits light based on the application of the power supply voltage and the electromagnetic valve is driven.
  • the base current of the adsorption transistor 12 decreases as the amount of charge charged in the capacitor 21 increases.
  • the adsorption transistor 12 is turned off as shown in FIG. 2C, and the solenoid coil 11 is adsorbed via the adsorption transistor 12.
  • a current flows through the second energization path B, and the position of the plunger is maintained.
  • This current (current at which the position of the plunger is held) is referred to as holding current. That is, it can be said that the holding transistor 32 provided on the second energization path B is a switching element for flowing a holding current to the solenoid coil 11.
  • the holding current is smaller than the adsorption current by the amount that the limiting resistor 31 is provided on the second energization path B.
  • the attracting current flows to the solenoid coil 11 over a predetermined time (the time from when the power supply voltage is applied until the base current of the attracting transistor 12 becomes smaller than the threshold current).
  • time elapses the current flowing through the solenoid coil 11 is switched from the adsorption current to the holding current.
  • the adsorption time T1 (the time from the timing t0 to the timing t1) in which the adsorption current flows including the time of the transient phenomenon is determined by the resistance values of the resistors 22 and 23 and the capacitance of the capacitor 21. For this reason, the adsorption time T1 can be adjusted by adjusting the resistance value and the capacitance.
  • the surge voltage will be described.
  • the surge voltage generated in the solenoid coil 11 is applied to the bidirectional Zener diode 40, and the bidirectional Zener diode 40 and the solenoid coil 11 constitute a closed loop circuit. Is formed.
  • a surge current flows in the closed loop circuit until the surge voltage becomes a Zener voltage.
  • the closed loop circuit is maintained until the bidirectional Zener diode 40 is turned off when the surge voltage is reduced to the Zener voltage.
  • the closed loop circuit is not formed, and the surge current does not flow through the solenoid coil 11. That is, the time from when the supply voltage application is stopped (timing at t2) to when the surge voltage becomes smaller than the zener voltage (timing at t3) is the response delay time T2 of the solenoid valve.
  • the threshold voltage and Zener voltage of the diode are not formed.
  • the response delay time T2 of the solenoid valve can be shortened by the difference from the above.
  • the adsorption transistor 12 and the holding transistor 32 are off, so that a surge voltage corresponding to the Zener voltage is applied to each of the transistors 12 and 32. Thereby, application of the surge voltage to the capacitor 21 and the light emitting diode 50 is suppressed. Therefore, the Zener voltage can be set high while suppressing destruction of the capacitor 21 and the light emitting diode 50.
  • a threshold voltage (zener voltage) at which the closed loop circuit is not formed is shortened in order to shorten the response delay time T2 of the solenoid valve, when the surge voltage corresponding to the threshold voltage is applied to the element, the element There is a risk of being destroyed.
  • the capacitor 21 and the light emitting diode 50 are easily destroyed when a reverse voltage is applied.
  • the adsorption transistor 12 and the holding transistor 32 are off in a situation where a surge voltage is generated, that is, in a situation where application of the power supply voltage is stopped. Thereby, a surge voltage is applied to each of the transistors 12 and 32, and the application of the surge voltage to the capacitor 21 and the light emitting diode 50 is regulated. Therefore, the inconvenience of destruction of each element that can be caused by setting the Zener voltage high can be avoided.
  • the adsorption transistor 12 and the holding transistor 32 can be said to be surge regulation transistors that regulate the surge voltage from being applied to the capacitor 21 and the light emitting diode 50.
  • the Zener voltage is set to a voltage (47V) close to the withstand voltage (50V) of each transistor 12, 32 with respect to the reference potential (0V).
  • the response delay time T2 can be shortened within a range in which the transistors 12 and 32 are not destroyed.
  • the bases of the transistors 12 and 32 are formed so that no surge voltage is applied. Specifically, the bases of the transistors 12 and 32 are directly connected to the + terminal 14 a without passing through the energization paths A and B of the solenoid coil 11. In other words, the input paths connecting the bases of the transistors 12 and 32 and the + terminal 14a and the energization paths A and B of the solenoid coil 11 are independent. This suppresses the transistors 12 and 32 from being turned on by the surge voltage. Therefore, even if the diode D is reversely connected to the solenoid drive circuit 10, the response delay time T2 of the solenoid valve does not vary.
  • various circuits such as a controller circuit may be connected to the solenoid drive circuit 10.
  • the diode D in order to prevent the surge voltage generated from the solenoid coil 11 from being applied to the various circuits, the diode D may be reversely connected as shown in FIG.
  • the holding transistor 32 is turned on by the surge voltage, a closed loop circuit is formed by the holding transistor 32, the limiting resistor 31, the diode D, and the solenoid coil 11, and a surge current flows to the solenoid coil 11. It becomes.
  • a two-dot chain line Z1 in FIG. 2A there may be a disadvantage that the response delay time T2 of the electromagnetic valve becomes long although the bidirectional Zener diode 40 is provided.
  • the base of the holding transistor 32 is connected to the + terminal 14a without passing through the energization paths A and B of the solenoid coil 11, so Surge voltage is not applied.
  • the holding transistor 32 is turned on by the surge voltage, and the closed loop circuit is not formed. Therefore, the inconvenience can be avoided. That is, the response delay time T2 of the solenoid valve is constant regardless of other circuit configurations connected to the solenoid drive circuit 10.
  • FIG. 3B a plurality (specifically, three) of discharge paths 51, 52, and 53 are formed in the solenoid drive circuit 10. Each discharge path 51, 52, 53 will be described below.
  • the first discharge path 51 will be described. Charge accumulated in the capacitor 21 is discharged through the light emitting diode 50.
  • a drive current is temporarily supplied to the base of the holding transistor 32 by the electric charge accumulated in the capacitor 21. Therefore, as shown in FIG. 2D, the holding transistor 32 is turned on for a predetermined time even after the switch 13 is turned off. Thereby, the electric charge accumulated in the capacitor 21 is discharged via the solenoid coil 11 and the holding transistor 32.
  • semiconductor elements that require a predetermined threshold voltage to be turned on are provided on the two discharge paths 51 and 52.
  • the light emitting diode 50 is provided on the first discharge path 51, and the holding transistor 32 is provided on the second discharge path 52.
  • the electric charge corresponding to the threshold voltage required to turn on these semiconductor elements remains without being discharged.
  • a charge corresponding to about 1 V remains. Since this residual charge is released by natural discharge, the discharge time required until the charge accumulated in the capacitor 21 is completely discharged becomes longer. Then, the charge 21 may remain in the capacitor 21 at the timing when the switch 13 is turned on again after the switch 13 is turned off.
  • the adsorption transistor 12 since the ON time of the adsorption transistor 12 varies depending on the remaining charge amount, the adsorption transistor 12 may be turned off before the plunger adsorption operation is completed. For this reason, as indicated by a two-dot chain line Z2 in FIG. 2A, it is necessary to set the adsorption time T1 longer in accordance with the change in the on-time of the adsorption transistor 12 based on the residual charge amount, thereby increasing the power consumption. There is a concern about conversion.
  • the solenoid drive circuit 10 includes a closed loop circuit formed by the timer circuit 16, the resistor 23, and the base current supply circuit 33 as the third discharge path 53.
  • the electric charge accumulated in the capacitor 21 is discharged through the third discharge path 53 via the resistors 33a and 33b, as shown in FIG. 3B. That is, it can be said that the resistors 33a and 33b are discharging resistors 33a and 33b of the capacitor 21, respectively.
  • resistors specifically, the resistors 22, 23, 33a, and 33b are provided on the third discharge path 53, and no semiconductor element that requires a predetermined threshold voltage to be turned on is provided.
  • the discharge time of the capacitor 21 can be shortened compared with the case where natural discharge is performed. Therefore, since the fluctuation of the on-time of the adsorption transistor 12 based on the residual charge amount of the capacitor 21 can be reduced, it is possible to shorten the adsorption time T1 through which the adsorption current flows. Therefore, power consumption can be reduced.
  • the holding transistor 32 is turned on by the discharge of the capacitor 21, as already described, if the diode D is provided, a surge current based on the surge voltage may flow through the diode D.
  • the resistance values of the discharge resistors 33a and 33b are set (lower) so that the discharge time of the capacitor 21 is shorter than the time required for the surge voltage to become the Zener voltage.
  • FIG. 2D at the timing when the surge voltage becomes smaller than the Zener voltage (timing at t3), the holding transistor 32 is off, so that no surge current flows.
  • the bidirectional Zener diode 40 is provided in parallel with the solenoid coil 11, and the adsorption transistor 12 and the holding transistor 32 are provided in series with the solenoid coil 11 and the bidirectional Zener diode 40. Thereby, when the power supply voltage is not applied, the transistors 12 and 32 are turned off, so that the surge voltage lowered to the Zener voltage is not applied to other elements. Therefore, the Zener voltage can be set high while suppressing the destruction of the element due to the surge voltage.
  • the bases of the transistors 12 and 32 were connected to the + terminal 14a without going through the solenoid coil 11. Thus, since the surge voltage is not applied to the bases of the transistors 12 and 32, the transistors 12 and 32 are not turned on based on the surge voltage. Therefore, even if the diode D is provided for the solenoid drive circuit 10, the response delay time T2 of the solenoid valve does not increase.
  • a third discharge path 53 is formed as a discharge path of the capacitor 21, which is not provided with a semiconductor element that requires a predetermined threshold voltage to be turned on. Therefore, the charge accumulated in the capacitor 21 is completely discharged. Can be made. Therefore, fluctuations in the on-time of the adsorption transistor 12 can be suppressed. Accordingly, since it is not necessary to set the suction time T1 to be long in response to the fluctuation, the suction time T1 can be set to be short, and power consumption can be reduced.
  • FIG. 4 is a circuit diagram of the solenoid drive circuit 100 in the second embodiment.
  • the description is abbreviate
  • the bidirectional Zener diode 40 is connected in parallel to the solenoid coil 11, but instead, the Zener diode 101 is connected between the base and collector of the adsorption transistor 12. Specifically, the anode of the Zener diode 101 is connected to the base of the adsorption transistor 12 and the cathode is connected to the collector of the adsorption transistor 12. As a result, the base path that is input to the base terminal of the adsorption transistor 12 via the Zener diode 101 and the first energization path A are connected.
  • the Zener diode 101 becomes conductive when a surge voltage larger than the Zener voltage is generated. Then, a surge current based on the surge voltage is supplied to the base of the adsorption transistor 12, and the adsorption transistor 12 is turned on. As a result, a closed loop circuit is formed via the adsorption transistor 12 and the resistors 33a and 33b, and a surge current flows in the closed loop circuit until the surge voltage becomes a Zener voltage.
  • the Zener diode 101 transmits the surge voltage so that the surge current is supplied to the base of the adsorption transistor 12 in a situation where the surge voltage is larger than the Zener voltage, and the surge voltage is higher than the Zener voltage. In a small situation, it can be said that the transmission of the surge voltage is regulated.
  • the direction of the current flowing through the resistors 33a and 33b is opposite between that based on the closed loop circuit and that based on the charge discharge. Therefore, when a closed loop circuit is formed, electric charges are not discharged through the resistors 33a and 33b. For this reason, after the surge voltage becomes lower than the Zener voltage (after the closed loop circuit is no longer formed), the complete discharge of the capacitor 21 is completed after a predetermined period.
  • the Zener diode 101 may be reversely connected between the collector and emitter of the adsorption transistor 12. Specifically, the cathode of the Zener diode 101 is connected to the collector, and the cathode of the Zener diode 101 is connected to the emitter. In this case, a closed loop circuit through the Zener diode 101 and the resistors 33a and 33b is formed until the surge voltage becomes the Zener voltage without the adsorption transistor 12 being turned on.
  • the present invention is not limited to the description of the above embodiments, and may be implemented as follows, for example.
  • the bidirectional Zener diode 40 or the Zener diode 101 is provided to reduce the surge voltage to the Zener voltage.
  • the present invention is not limited to this, and a varistor may be provided instead. .
  • an NPN transistor is used as a switching element.
  • the present invention is not limited to this.
  • a PNP transistor may be used.
  • the connection relationship is set according to the PNP transistor.
  • the switching element is not limited to a transistor, and another switching element such as a MOSFET may be used.
  • a separate path for supplying current to the light emitting diode 50 is provided, but the present invention is not limited to this.
  • the resistor 33a or the resistor 33b may be replaced with the light emitting diode 50.
  • simplification of a structure can be achieved.
  • the configuration in which the resistor 33a or the resistor 33b is provided is superior.
  • SYMBOLS 10 Solenoid drive circuit, 11 ... Solenoid coil, 12 ... Adsorption transistor as a switching element, 14a ... + terminal as one power supply terminal, 14b ...-terminal as the other power supply terminal, 16 ... Timer circuit, 21 ... Capacitor 31 ... Limiting resistor, 32 ... Holding transistor as switching element, 33 ... Base current supply circuit, 40 ... Bidirectional Zener diode, 51-53 ... Discharge path, 101 ... Zener diode, A, B ... Discharge path.

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Abstract

Provided is a solenoid drive circuit for suppressing a response delay caused by a surge voltage. The solenoid drive circuit (10) is provided with: a solenoid coil (11) which performs a plunger suction-attachment operation; a bidirectional Zener diode (40) which is connected in parallel to the solenoid coil (11) and absorbs, up to a Zener voltage, the surge voltage generated when the power supplied to the solenoid coil (11) is stopped; and a holding transistor (32) which is connected in series to the solenoid coil (11) and the bidirectional Zener diode (40). When a power supply voltage is applied, the holding transistor (32) turns on and a conduction path for the solenoid coil (11) is thereby formed. In this structure, the surge voltage reduced to the Zener voltage by the bidirectional Zener diode (40) is applied to the holding transistor (32).

Description

ソレノイド駆動回路Solenoid drive circuit
 本発明は電磁弁を駆動するソレノイド駆動回路に関する。 The present invention relates to a solenoid drive circuit for driving a solenoid valve.
 電磁弁を駆動させるものとして、ソレノイドコイルに通電することでプランジャ吸着動作を行わせるソレノイド駆動回路が知られている。ソレノイド駆動回路としては、特許文献1に示すように、コンデンサを含むタイマ回路と、タイマ回路によって規定されるタイマ時間に亘ってオンとなることでプランジャ吸着動作に対応した吸着電流が流れる吸着トランジスタと、タイマ時間経過後にオンとなることで吸着電流よりも小さい保持電流が流れる保持トランジスタと、を備えているものが知られている。 As a solenoid valve driving circuit, there is known a solenoid drive circuit that performs a plunger suction operation by energizing a solenoid coil. As a solenoid drive circuit, as shown in Patent Document 1, a timer circuit including a capacitor, an adsorption transistor through which an adsorption current corresponding to a plunger adsorption operation flows by being turned on for a timer time defined by the timer circuit, And a holding transistor in which a holding current smaller than the attracting current flows by turning on after the timer time elapses is known.
 ここで、ソレノイドコイルへの通電が停止することによってサージ電圧が発生する。当該サージ電圧を吸収するために、特許文献1のソレノイド駆動回路は、ソレノイドコイルに対して並列に逆接続されたダイオードを備えている。サージ電圧はダイオードの順方向の閾値電圧まで吸収されるため、他の素子に対するサージ電圧の影響が低減されている。 Here, a surge voltage is generated when the energization of the solenoid coil is stopped. In order to absorb the surge voltage, the solenoid drive circuit of Patent Document 1 includes a diode reversely connected in parallel to the solenoid coil. Since the surge voltage is absorbed up to the threshold voltage in the forward direction of the diode, the influence of the surge voltage on other elements is reduced.
特開平10-184974号公報JP-A-10-184974
 しかしながら、サージ電圧が閾値電圧よりも小さくなるまでソレノイドコイルに電流が流れる。この場合、ダイオードの順方向の閾値電圧は低電圧(1V程度)であるため、サージ電圧に基づくソレノイドコイルの通電時間が長くなり、サージ電圧に起因する電磁弁の応答遅れ時間が長くなる。 However, current flows through the solenoid coil until the surge voltage becomes smaller than the threshold voltage. In this case, since the forward threshold voltage of the diode is a low voltage (about 1 V), the energization time of the solenoid coil based on the surge voltage becomes long, and the response delay time of the solenoid valve caused by the surge voltage becomes long.
 ここで、近年では高速切換可能な電磁弁が求められている。このため、上記サージ電圧による応答遅れ時間が長い場合、高速切換に対応できないといった不都合が生じ得る。 Here, in recent years, solenoid valves that can be switched at high speed have been demanded. For this reason, when the response delay time by the said surge voltage is long, the problem that it cannot respond to high-speed switching may arise.
 本発明は、こうした実情に鑑みてなされたものであり、サージ電圧に起因する応答遅れを抑制することにより高速切換可能なソレノイド駆動回路を提供することを主たる目的とするものである。 The present invention has been made in view of such circumstances, and has as its main object to provide a solenoid drive circuit that can be switched at high speed by suppressing a response delay caused by a surge voltage.
 以下、上記課題を解決するのに有効な手段等について効果等を示しつつ説明する。 Hereinafter, effective means for solving the above-mentioned problems will be described while showing effects.
 手段1.通電されることにより磁界を発生し、電磁弁を駆動させるソレノイドコイルと、前記ソレノイドコイルに対して直列に接続されたスイッチング素子と、を備え、前記ソレノイドコイル及び前記スイッチング素子の直列接続体は電源電圧を印加する一対の電源端子に接続されており、前記電源電圧が印加されている状況において前記スイッチング素子がオン状態となることにより前記ソレノイドコイルの通電経路が形成され、当該ソレノイドコイルの通電が行われるソレノイド駆動回路において、前記スイッチング素子として、前記電源電圧が印加されてからあらかじめ定められた特定時間が経過するまでオン状態となる第1スイッチング素子と、前記第1スイッチング素子に対して並列に接続され、前記電源電圧が印加されている間に亘ってオン状態となる第2スイッチング素子と、を備え、前記ソレノイドコイルの通電経路として、前記第1スイッチング素子を介した第1通電経路と、前記第2スイッチング素子を介した第2通電経路と、が設けられており、前記第2通電経路上には、当該第2通電経路上を流れる電流が前記第1通電経路上を流れる電流よりも小さくなるように制限抵抗が設けられており、前記各通電経路とは別に、前記第1スイッチング素子の入力端子と前記一対の電源端子の一方とを接続する第1入力経路と、前記第2スイッチング素子の入力端子と前記一方の電源端子とを接続する第2入力経路と、が並列に設けられており、前記第1入力経路上に設けられ、前記特定時間に亘って前記第1スイッチング素子に対して当該第1スイッチング素子がオン状態となる駆動電力を供給するタイマ回路と、ツェナダイオード又はバリスタを有し、前記ソレノイドコイルへの通電が停止した場合に発生するサージ電圧を前記ツェナダイオード又は前記バリスタが導通状態となる閾値電圧まで吸収するサージ吸収回路と、を備え、前記閾値電圧まで吸収されたサージ電圧が前記各スイッチング素子に印加されるように構成されていることを特徴とするソレノイド駆動回路。 Means 1. A solenoid coil that generates a magnetic field when energized and drives an electromagnetic valve; and a switching element connected in series to the solenoid coil, the series connection body of the solenoid coil and the switching element being a power source The solenoid coil is connected to a pair of power supply terminals to which a voltage is applied. When the power supply voltage is applied, the switching element is turned on to form an energization path for the solenoid coil. In the solenoid driving circuit to be performed, as the switching element, a first switching element that is turned on until a predetermined time elapses after the power supply voltage is applied, and in parallel with the first switching element Connected and while the power supply voltage is applied And a second energization path through the first switching element and a second energization path through the second switching element as the energization path of the solenoid coil. And a limiting resistor is provided on the second energization path so that a current flowing on the second energization path is smaller than a current flowing on the first energization path. Separately from the path, a first input path connecting the input terminal of the first switching element and one of the pair of power supply terminals, and a first input path connecting the input terminal of the second switching element and the one power supply terminal. Two input paths are provided in parallel, provided on the first input path, and the first switching element is in an ON state with respect to the first switching element over the specific time. And a zener diode or varistor, and a surge voltage generated when the energization of the solenoid coil is stopped is absorbed up to a threshold voltage at which the zener diode or the varistor becomes conductive. A solenoid drive circuit, wherein a surge voltage absorbed up to the threshold voltage is applied to each switching element.
 手段1によれば、電源電圧が印加されると各スイッチング素子がオン状態となる。この場合、第2通電経路上には制限抵抗が設けられているため、第1通電経路を電流が流れる。その後、電源電圧の印加開始タイミングに対して特定時間が経過したタイミングで、第1スイッチング素子がオフ状態となり、第2通電経路を電流が流れる。当該電流は、第1通電経路上を流れる電流よりも小さい。これにより、電源電圧の印加が開始されることに基づいて電磁弁のプランジャ吸着動作に対応した電流を流し、当該プランジャ吸着動作完了後はその電流よりも小さい電流を流すことにより消費電力の低減を図ることができる。 According to the means 1, when the power supply voltage is applied, each switching element is turned on. In this case, since a limiting resistor is provided on the second energization path, current flows through the first energization path. Thereafter, the first switching element is turned off at a timing when a specific time elapses with respect to the application voltage application start timing, and a current flows through the second energization path. The current is smaller than the current flowing on the first energization path. As a result, a current corresponding to the plunger adsorption operation of the solenoid valve is caused to flow based on the start of application of the power supply voltage, and after completion of the plunger adsorption operation, a current smaller than that current is caused to flow to reduce power consumption. You can plan.
 かかる構成において、サージ電圧が発生した場合、当該サージ電圧はツェナダイオード又はバリスタによって閾値電圧であるツェナ電圧又はバリスタ電圧まで吸収される。これらツェナ電圧又はバリスタ電圧は、ダイオードの順方向の閾値電圧よりも高く設定することができるため、サージ電圧を吸収するものとしてダイオードが設ける構成と比較して、閾値電圧維持時間を短くすることができる。これにより、電磁弁の応答遅れ時間の短縮化を図ることができ、高速切換に対応することができる。よって、電磁弁の高速切換に対応することができる。しかしながら、閾値電圧が高く設定されている状況において当該閾値電圧まで下げられたサージ電圧が比較的耐圧性の弱い素子に印加されると、当該素子が破壊するおそれがある。特にタイマ回路としてコンデンサを設ける場合にはサージ電圧によってコンデンサが破壊されるおそれがある。 In such a configuration, when a surge voltage is generated, the surge voltage is absorbed to a Zener voltage or a varistor voltage which is a threshold voltage by a Zener diode or a varistor. Since these Zener voltage or varistor voltage can be set higher than the threshold voltage in the forward direction of the diode, the threshold voltage maintaining time can be shortened compared to the configuration in which the diode is provided to absorb the surge voltage. it can. As a result, the response delay time of the solenoid valve can be shortened, and high-speed switching can be handled. Therefore, it can respond to the high-speed switching of a solenoid valve. However, when a surge voltage lowered to the threshold voltage is applied to an element having a relatively low withstand voltage in a situation where the threshold voltage is set high, the element may be destroyed. In particular, when a capacitor is provided as a timer circuit, the capacitor may be destroyed by a surge voltage.
 これに対して、本手段によれば、閾値電圧まで吸収されたサージ電圧が各スイッチング素子に印加されるため、当該サージ電圧が他の素子に印加されることが規制される。これにより、他の素子へのサージ電圧の影響を低減することができる。よって、他の素子の破壊等を抑制しつつ、電磁弁の応答遅れ時間の短縮化を図ることができる。 On the other hand, according to this means, since the surge voltage absorbed up to the threshold voltage is applied to each switching element, application of the surge voltage to other elements is restricted. Thereby, the influence of the surge voltage on other elements can be reduced. Therefore, the response delay time of the solenoid valve can be shortened while suppressing destruction of other elements.
 手段2.前記サージ吸収回路は、前記ソレノイドコイルに対して並列に接続されているとともに、前記各スイッチング素子に対して直列に接続されており、前記サージ電圧が前記各入力経路に伝送されないように前記各入力経路と前記各通電経路とが独立していることを特徴とする手段1に記載のソレノイド駆動回路。 Means 2. The surge absorbing circuit is connected in parallel to the solenoid coil, and is connected in series to the switching elements, so that the surge voltage is not transmitted to the input paths. The solenoid drive circuit according to means 1, wherein the path and each of the energization paths are independent.
 手段2によれば、ソレノイドコイルに対して並列にサージ吸収回路が設けられているため、サージ電圧が発生した場合には、ソレノイドコイルとサージ吸収回路とで閉ループ回路が形成される。そして、サージ電圧が閾値電圧となるまで閉ループ回路にてサージ電圧が吸収される。 According to the means 2, since the surge absorption circuit is provided in parallel with the solenoid coil, when a surge voltage is generated, a closed loop circuit is formed by the solenoid coil and the surge absorption circuit. The surge voltage is absorbed by the closed loop circuit until the surge voltage reaches the threshold voltage.
 かかる構成において、サージ電圧によって各スイッチング素子がオン状態となると、サージ電圧がスイッチング素子ではなく他の素子に印加され、当該他の素子が破壊されるおそれがある。 In such a configuration, when each switching element is turned on by a surge voltage, the surge voltage is applied to other elements instead of the switching element, and the other elements may be destroyed.
 また、ソレノイド駆動回路に対して並列に他の回路を設ける場合、サージ電圧保護の観点から、本ソレノイド駆動回路に対して並列にサージ電圧に対して順方向となるようにダイオードを設ける場合がある。この場合、サージ電圧によってスイッチング素子がオン状態となると、スイッチング素子、ダイオード及びソレノイドコイルによって閉ループ回路が形成される。すると、サージ電圧が閾値電圧よりも更に低い電圧(ダイオードの順方向の閾値電圧)になるまでソレノイドコイルにおいて電流が流れ続ける。このため、他の素子に対するサージ電圧の影響を低減することができる一方、電磁弁の応答遅れ時間がツェナダイオード又はバリスタの閾値電圧に基づく応答遅れ時間よりも長くなる。 In addition, when other circuits are provided in parallel to the solenoid drive circuit, a diode may be provided in parallel to the solenoid drive circuit so as to be forward with respect to the surge voltage from the viewpoint of surge voltage protection. . In this case, when the switching element is turned on by the surge voltage, a closed loop circuit is formed by the switching element, the diode, and the solenoid coil. Then, current continues to flow in the solenoid coil until the surge voltage becomes lower than the threshold voltage (threshold voltage in the forward direction of the diode). For this reason, the influence of the surge voltage on other elements can be reduced, while the response delay time of the solenoid valve becomes longer than the response delay time based on the threshold voltage of the Zener diode or varistor.
 これに対して、本手段によれば、各スイッチング素子の入力経路と、サージ電圧が発生する各通電経路とがそれぞれ独立しているため、サージ電圧が各入力経路に対して伝送されない。これにより、各スイッチング素子がサージ電圧に基づいてオン状態とならない。よって、上記不都合を回避することができる。 On the other hand, according to this means, since the input path of each switching element and each energization path for generating the surge voltage are independent from each other, the surge voltage is not transmitted to each input path. Thereby, each switching element is not turned on based on the surge voltage. Therefore, the inconvenience can be avoided.
 手段3.前記第2入力経路上には、前記第2スイッチング素子の入力端子に供給する駆動電力を規定する規定抵抗が設けられており、前記タイマ回路は、時定数抵抗及び当該時定数抵抗に対して直列に接続されたコンデンサを備え、前記各入力経路が接続されることで前記規定抵抗、前記時定数抵抗及び前記コンデンサを含む閉ループが形成されており、前記閉ループは、前記コンデンサに蓄積された電荷の放電が行われる放電経路を構成することを特徴とする手段1又は手段2に記載のソレノイド駆動回路。 Means 3. On the second input path, there is provided a defining resistor that defines driving power supplied to the input terminal of the second switching element, and the timer circuit is connected in series with the time constant resistor and the time constant resistor. A closed loop including the specified resistor, the time constant resistor, and the capacitor is formed by connecting the input paths, and the closed loop is configured to store the charge accumulated in the capacitor. 3. The solenoid drive circuit according to means 1 or 2, wherein a discharge path for discharging is formed.
 手段3によれば、電源電圧の印加が停止した場合、各入力経路を接続することで形成された閉ループにて、コンデンサに蓄積された電荷の放電が行われる。この場合、各スイッチング素子に対して供給される駆動電力を規定するものとして、第1入力経路上には時定数抵抗及びコンデンサが設けられており、第2入力経路上には規定抵抗が設けられている。このため、各入力経路上に、所定の閾値電圧が印加された場合に非導通状態から導通状態となる半導体素子を設ける必要がない。これにより、放電経路上に上記半導体素子を設けないようにすることにより、コンデンサに蓄積された電荷を好適に放電させることができる。 According to the means 3, when the application of the power supply voltage is stopped, the charge accumulated in the capacitor is discharged in a closed loop formed by connecting the input paths. In this case, a time constant resistor and a capacitor are provided on the first input path, and a specified resistor is provided on the second input path, in order to define the drive power supplied to each switching element. ing. For this reason, it is not necessary to provide on each input path a semiconductor element that changes from a non-conductive state to a conductive state when a predetermined threshold voltage is applied. Thereby, by not providing the semiconductor element on the discharge path, the charge accumulated in the capacitor can be suitably discharged.
 すなわち、仮にコンデンサの放電経路上に発光ダイオードやトランジスタ等の半導体素子が設けられている場合、これらの半導体素子が導通状態となるのに必要な閾値電圧に対応した電荷が放電されることなく残留する。この残留電荷は自然放電によって放出されることとなるため、コンデンサに蓄積された電荷が完全に放電するまでに要する放電時間が長くなる。すると、電源電圧の印加が停止してから再度電源電圧の印加が開始されたタイミングにおいて、コンデンサに電荷が残留している場合がある。この場合、残留している電荷量に応じて特定時間が変動するため、プランジャ吸着動作が完了する前に第1スイッチング素子がオフ状態となるおそれがある。かといって、上記残留電荷量に基づく第1スイッチング素子のオン時間の変動に対応させて特定時間を長く設定すると、消費電力の増大化が懸念される。 That is, if semiconductor elements such as light emitting diodes and transistors are provided on the discharge path of the capacitor, the charge corresponding to the threshold voltage necessary for these semiconductor elements to become conductive remains without being discharged. To do. Since this residual charge is released by natural discharge, the discharge time required until the charge accumulated in the capacitor is completely discharged becomes longer. Then, there is a case where electric charge remains in the capacitor at the timing when the application of the power supply voltage is started again after the application of the power supply voltage is stopped. In this case, since the specific time varies depending on the remaining charge amount, the first switching element may be turned off before the plunger adsorption operation is completed. However, if the specific time is set longer in response to the change in the on-time of the first switching element based on the residual charge amount, there is a concern that the power consumption increases.
 これに対して、本手段によれば、放電経路上に半導体素子を設けないようにすることによって、自然放電を行うことなくコンデンサに蓄積された電荷を完全に放電させることができるため、自然放電が行われる場合と比較して放電時間を短くすることができる。これにより、特定時間を短く設定することができ、消費電力の低減を図ることができる。 On the other hand, according to the present means, since the semiconductor element is not provided on the discharge path, the charge accumulated in the capacitor can be completely discharged without performing the natural discharge. The discharge time can be shortened as compared with the case where the operation is performed. Thereby, specific time can be set short and reduction of power consumption can be aimed at.
 手段4.前記コンデンサに蓄積された電荷の放電が完了するのに要する時間が、前記サージ電圧が前記閾値電圧まで吸収されるのに要する時間よりも短くなるように前記規定抵抗の抵抗値が設定されていることを特徴とする手段3に記載のソレノイド駆動回路。 Means 4. The resistance value of the specified resistor is set so that the time required to complete the discharge of the charge accumulated in the capacitor is shorter than the time required for the surge voltage to be absorbed to the threshold voltage. The solenoid drive circuit according to claim 3, wherein
 手段4によれば、タイマ回路としてコンデンサが設けられている状況において電源電圧の印加が停止すると、サージ電圧が発生するとともに、コンデンサの放電が開始される。この場合、第2入力経路を介してコンデンサに蓄積されている電荷が第2スイッチング素子の入力端子に対して入力され、第2スイッチング素子がオン状態となるおそれがある。 According to the means 4, when the application of the power supply voltage is stopped in a situation where the capacitor is provided as the timer circuit, a surge voltage is generated and the discharge of the capacitor is started. In this case, the charge stored in the capacitor via the second input path is input to the input terminal of the second switching element, and the second switching element may be turned on.
 これに対して、本手段によれば、サージ電圧が閾値電圧になるタイミングよりも前のタイミングでコンデンサの電荷の放電が完了するように規定抵抗の抵抗値が設定されているため、サージ電圧が閾値電圧となるタイミングにおいて第2スイッチング素子はオフ状態となっている。これにより、手段2にて説明した効果を確保しつつ、コンデンサに蓄積された電荷を好適に放電させることができる。 On the other hand, according to this means, the resistance value of the specified resistor is set so that the discharge of the capacitor charge is completed at a timing before the timing at which the surge voltage becomes the threshold voltage. The second switching element is in the off state at the timing when the threshold voltage is reached. Thereby, the electric charge accumulated in the capacitor can be suitably discharged while ensuring the effect described in the means 2.
 手段5.前記第1スイッチング素子はNPN型の第1バイポーラトランジスタであり、前記第2スイッチング素子はNPN型の第2バイポーラトランジスタであり、前記各通電経路は、前記ソレノイドコイルの一端を前記一対の電源端子の+端子に接続するとともに、他端を前記各バイポーラトランジスタのコレクタ端子に接続し、さらに前記各バイポーラトランジスタのエミッタ端子を前記一対の電源端子の-端子に接続することで形成されるものであり、前記制限抵抗は、前記第2バイポーラトランジスタのコレクタと前記ソレノイドコイルの他端との間に設けられており、前記第1入力経路は、前記第1バイポーラトランジスタのベース端子を、前記タイマ回路を構成する時定数抵抗及びコンデンサを介して前記+端子に接続するとともに、抵抗を介して前記-端子に接続することで形成されるものであり、前記第2入力経路は、前記第2バイポーラトランジスタのベース端子を、第1規定抵抗を介して前記+端子に接続するとともに、第2規定抵抗を介して前記-端子に対して接続することで形成されるものであり、前記ツェナダイオード又はバリスタは、前記ソレノイドコイルに対して並列に接続されるとともに前記各バイポーラトランジスタに対して直列に接続されていることを特徴とする手段1乃至4のいずれか1に記載のソレノイド駆動回路。 Means 5. The first switching element is an NPN-type first bipolar transistor, the second switching element is an NPN-type second bipolar transistor, and each energization path has one end of the solenoid coil connected to the pair of power supply terminals. And the other end is connected to the collector terminal of each bipolar transistor, and the emitter terminal of each bipolar transistor is connected to the-terminal of the pair of power supply terminals. The limiting resistor is provided between the collector of the second bipolar transistor and the other end of the solenoid coil, and the first input path constitutes the base terminal of the first bipolar transistor and constitutes the timer circuit Connected to the + terminal through a time constant resistor and capacitor, And the second input path connects the base terminal of the second bipolar transistor to the + terminal via a first specified resistor, and The zener diode or varistor is connected in parallel to the solenoid coil and connected to each of the bipolar transistors. The solenoid drive circuit according to any one of means 1 to 4, wherein the solenoid drive circuit is connected in series.
 手段5によれば、電源電圧が印加された場合にソレノイドコイルに対してプランジャ吸着動作に対応した吸着電流を流し、特定時間が経過した場合には吸着電流よりも小さい保持電流を流すことができる。そして、電源電圧の印加が停止した場合には各バイポーラトランジスタがオフ状態となる。この場合、ソレノイドコイルにおいてサージ電圧が発生するが、当該サージ電圧は各バイポーラトランジスタのベースに入力されないようになっているため、サージ電圧に基づいて各バイポーラトランジスタがオン状態となることが抑制されている。 According to the means 5, when a power supply voltage is applied, an adsorption current corresponding to the plunger adsorption operation can be supplied to the solenoid coil, and when a specific time has elapsed, a holding current smaller than the adsorption current can be supplied. . When the application of the power supply voltage is stopped, each bipolar transistor is turned off. In this case, a surge voltage is generated in the solenoid coil, but since the surge voltage is not input to the base of each bipolar transistor, the bipolar transistor is prevented from being turned on based on the surge voltage. Yes.
 また、電源電圧の印加が停止した場合には、コンデンサに蓄積された電荷は各入力経路を介して放電される。この場合、各入力経路上には導通状態となるために所定の閾値電圧を要する半導体素子が設けられていないため、コンデンサに蓄積された電荷が残留することなく放電される。これにより、吸着電流が流れる特定時間の変動を抑制することができ、特定時間の短縮化を図ることができる。よって、消費電力の低減を図ることができる。 Also, when the application of the power supply voltage is stopped, the electric charge accumulated in the capacitor is discharged through each input path. In this case, since no semiconductor element requiring a predetermined threshold voltage is provided on each input path to be in a conductive state, the charge accumulated in the capacitor is discharged without remaining. Thereby, the fluctuation | variation of the specific time through which adsorption current flows can be suppressed, and shortening of specific time can be aimed at. Therefore, power consumption can be reduced.
第1実施形態のソレノイド駆動回路の回路図。The circuit diagram of the solenoid drive circuit of 1st Embodiment. ソレノイドコイルに流れる電流変化及びソレノイド駆動回路の動作を説明するためのタイミングチャート。The timing chart for demonstrating the electric current change which flows into a solenoid coil, and operation | movement of a solenoid drive circuit. (a)サージ電圧の吸収の様子を説明するための説明図、(b)コンデンサの放電の様子を説明するための説明図。(A) Explanatory drawing for demonstrating the mode of absorption of a surge voltage, (b) Explanatory drawing for demonstrating the mode of discharge of a capacitor | condenser. 第2実施形態のソレノイド駆動回路の回路図。The circuit diagram of the solenoid drive circuit of 2nd Embodiment.
 <第1実施形態>
 以下、本発明の第1実施形態について図面を参照しつつ説明する。図1は電磁弁を駆動させるソレノイド駆動回路10の回路図である。
<First Embodiment>
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a solenoid drive circuit 10 for driving a solenoid valve.
 ソレノイド駆動回路10は、プランジャ吸着動作を行うソレノイドコイル11と、当該ソレノイドコイル11に対して直列に接続された吸着トランジスタ12(第1スイッチング素子)とを備えている。吸着トランジスタ12はNPN型のバイポーラトランジスタである。なお、以降の説明においてバイポーラトランジスタを単にトランジスタと言う。 The solenoid drive circuit 10 includes a solenoid coil 11 that performs a plunger suction operation, and a suction transistor 12 (first switching element) connected in series to the solenoid coil 11. The adsorption transistor 12 is an NPN bipolar transistor. In the following description, the bipolar transistor is simply referred to as a transistor.
 ソレノイドコイル11の一端はスイッチ13を介して一対の電源端子14a,14bのうちの一方の電源端子に対応する+端子14aに接続されている。ソレノイドコイル11の他端は吸着トランジスタ12のコレクタに接続されている。吸着トランジスタ12のエミッタはダイオード15を介して他方の電源端子に対応する-端子14bに接続されている。吸着トランジスタ12のベースには、スイッチ13及びタイマ回路16を介して+端子14aが接続されている。当該吸着トランジスタ12のベースと+端子14aとを接続する経路が第1入力経路に相当する。 One end of the solenoid coil 11 is connected via a switch 13 to a + terminal 14a corresponding to one of the pair of power terminals 14a and 14b. The other end of the solenoid coil 11 is connected to the collector of the adsorption transistor 12. The emitter of the adsorption transistor 12 is connected through a diode 15 to a negative terminal 14b corresponding to the other power supply terminal. A + terminal 14 a is connected to the base of the adsorption transistor 12 through a switch 13 and a timer circuit 16. A path connecting the base of the adsorption transistor 12 and the + terminal 14a corresponds to a first input path.
 タイマ回路16は、スイッチ13がオンとなってから(電源電圧が印加されてから)特定時間に亘って、吸着トランジスタ12のベースに対して当該吸着トランジスタ12がオン(導通状態)となる駆動電流を供給するものである。具体的には、タイマ回路16は、コンデンサ21と当該コンデンサ21に対して直列に接続された抵抗22(時定数抵抗)とを備えている。抵抗22及びコンデンサ21の直列接続体を介して+端子14aからの電源電圧が吸着トランジスタ12のベースに印加されるように各素子が接続されている。これにより、スイッチ13がオフからオンとなり+端子14aから電源電圧(例えば+24V)が印加された場合には、コンデンサ21に電荷が蓄積されるまで吸着トランジスタ12のベースに駆動電流が供給され、吸着トランジスタ12がオンとなる。 The timer circuit 16 has a driving current that turns on the adsorption transistor 12 with respect to the base of the adsorption transistor 12 for a specific time after the switch 13 is turned on (after the power supply voltage is applied). Supply. Specifically, the timer circuit 16 includes a capacitor 21 and a resistor 22 (time constant resistor) connected in series to the capacitor 21. Each element is connected so that the power supply voltage from the + terminal 14 a is applied to the base of the adsorption transistor 12 through a series connection body of the resistor 22 and the capacitor 21. As a result, when the switch 13 is turned on from off and a power supply voltage (for example, + 24V) is applied from the + terminal 14a, a drive current is supplied to the base of the adsorption transistor 12 until electric charge is accumulated in the capacitor 21, The transistor 12 is turned on.
 この場合、吸着トランジスタ12を介してソレノイドコイル11に所定の電流が流れる。吸着トランジスタ12を介した通電経路が第1通電経路Aに相当する。 In this case, a predetermined current flows through the solenoid coil 11 via the adsorption transistor 12. The energization path via the adsorption transistor 12 corresponds to the first energization path A.
 ちなみに、ソレノイド駆動回路10は、タイマ回路16に対して直列に接続された抵抗23を備えている。当該抵抗23の一端はコンデンサ21に接続されており、他端はダイオード15を介して-端子14bに接続されている。これにより、スイッチ13がオフとなった場合(電源電圧の印加が停止した場合)にはコンデンサ21に蓄積された電荷が抵抗22,23を介して放電される。このため、抵抗22,23はコンデンサ21の放電経路を形成するものであるとも言える。 Incidentally, the solenoid drive circuit 10 includes a resistor 23 connected in series to the timer circuit 16. One end of the resistor 23 is connected to the capacitor 21, and the other end is connected to the negative terminal 14 b via the diode 15. Thereby, when the switch 13 is turned off (when application of the power supply voltage is stopped), the electric charge accumulated in the capacitor 21 is discharged through the resistors 22 and 23. Therefore, it can be said that the resistors 22 and 23 form a discharge path of the capacitor 21.
 なお、コンデンサ21に電荷が蓄積されていない状況において電源電圧が印加された場合に、吸着トランジスタ12のベースに対して駆動電流が供給されるように各抵抗22,23の抵抗値が設定されている。 The resistance values of the resistors 22 and 23 are set so that the drive current is supplied to the base of the adsorption transistor 12 when a power supply voltage is applied in a state where no charge is accumulated in the capacitor 21. Yes.
 ソレノイド駆動回路10は、ソレノイドコイル11の通電経路として上記第1通電経路Aの他に、第1通電経路Aを流れる電流よりも小さい電流が流れる第2通電経路Bを備えている。具体的には、ソレノイド駆動回路10は、ソレノイドコイル11に対して直列に接続されているとともに吸着トランジスタ12に対して並列に接続された制限抵抗31及びNPN型の保持トランジスタ32(第2スイッチング素子)を備えている。これら制限抵抗31及び保持トランジスタ32は直列に接続されており、詳細には制限抵抗31の一端が保持トランジスタ32のコレクタに接続されている。制限抵抗31の他端はソレノイドコイル11の他端に接続されており、保持トランジスタ32のエミッタはダイオード15を介して-端子14bに接続されている。 The solenoid drive circuit 10 is provided with a second energization path B through which a current smaller than a current flowing through the first energization path A flows in addition to the first energization path A as an energization path of the solenoid coil 11. Specifically, the solenoid drive circuit 10 includes a limiting resistor 31 and an NPN-type holding transistor 32 (second switching element) connected in series to the solenoid coil 11 and connected in parallel to the adsorption transistor 12. ). The limiting resistor 31 and the holding transistor 32 are connected in series. Specifically, one end of the limiting resistor 31 is connected to the collector of the holding transistor 32. The other end of the limiting resistor 31 is connected to the other end of the solenoid coil 11, and the emitter of the holding transistor 32 is connected to the − terminal 14 b via the diode 15.
 保持トランジスタ32のベースには、スイッチ13がオンとなった場合に保持トランジスタ32がオンとなる駆動電流が供給されるように構成されている。詳細には、ソレノイド駆動回路10は、抵抗33a及び当該抵抗33aに対して直列に接続された抵抗33bを有するベース電流供給回路33を備えている。ベース電流供給回路33は電源電圧が印加されるように構成されており、具体的には抵抗33aの一端がスイッチ13を介して+端子14aに接続されており、抵抗33bの他端がダイオード15を介して-端子14bに接続されている。保持トランジスタ32のベースは抵抗33bに対して並列に接続されている。スイッチ13がオンの場合に保持トランジスタ32のベースに対して駆動電流が供給されるように各抵抗33a,33bの抵抗値が設定されている。保持トランジスタ32のベースと+端子14aとを接続する経路が第2入力経路に相当し、抵抗33a,33bが規定抵抗に相当する。 The base of the holding transistor 32 is configured to be supplied with a drive current that turns on the holding transistor 32 when the switch 13 is turned on. Specifically, the solenoid drive circuit 10 includes a base current supply circuit 33 having a resistor 33a and a resistor 33b connected in series to the resistor 33a. The base current supply circuit 33 is configured such that a power supply voltage is applied. Specifically, one end of the resistor 33a is connected to the + terminal 14a via the switch 13, and the other end of the resistor 33b is connected to the diode 15. Is connected to the negative terminal 14b. The base of the holding transistor 32 is connected in parallel to the resistor 33b. The resistance values of the resistors 33a and 33b are set so that the drive current is supplied to the base of the holding transistor 32 when the switch 13 is on. A path connecting the base of the holding transistor 32 and the + terminal 14a corresponds to the second input path, and the resistors 33a and 33b correspond to the specified resistance.
 かかる構成によれば、スイッチ13がオンである場合、保持トランジスタ32のベースに駆動電流が供給され、保持トランジスタ32がオンとなる。かかる状況において吸着トランジスタ12がオフとなると、制限抵抗31及び保持トランジスタ32を介してソレノイドコイル11にて電流が流れる。これら制限抵抗31及び保持トランジスタ32を介した通電経路が第2通電経路Bに相当する。第2通電経路Bを流れる電流は、制限抵抗31が設けられている分だけ、第1通電経路Aを流れる電流よりも小さくなっている。 According to this configuration, when the switch 13 is on, the drive current is supplied to the base of the holding transistor 32, and the holding transistor 32 is turned on. In this situation, when the adsorption transistor 12 is turned off, a current flows through the solenoid coil 11 via the limiting resistor 31 and the holding transistor 32. The energization path through the limiting resistor 31 and the holding transistor 32 corresponds to the second energization path B. The current flowing through the second energization path B is smaller than the current flowing through the first energization path A by the amount provided with the limiting resistor 31.
 ここで、ソレノイドコイル11への通電が停止した場合、当該ソレノイドコイル11において一時的に電源電圧よりも高いサージ電圧が発生する。当該サージ電圧に対して、本ソレノイド駆動回路10にはサージ吸収回路として双方向ツェナダイオード40が設けられている。 Here, when energization to the solenoid coil 11 is stopped, a surge voltage higher than the power supply voltage is temporarily generated in the solenoid coil 11. In response to the surge voltage, the solenoid drive circuit 10 is provided with a bidirectional Zener diode 40 as a surge absorbing circuit.
 双方向ツェナダイオード40は、ソレノイドコイル11に対して並列に接続されているとともに、制限抵抗31及び保持トランジスタ32からなる直列接続体並びに吸着トランジスタ12に対して直列に接続されている。双方向ツェナダイオード40のツェナ電圧は吸着トランジスタ12及び保持トランジスタ32の耐圧(例えば50V)よりも小さく設定されており、具体的には47Vに設定されている。 The bidirectional Zener diode 40 is connected in parallel to the solenoid coil 11 and is connected in series to the series connection body including the limiting resistor 31 and the holding transistor 32 and the adsorption transistor 12. The Zener voltage of the bidirectional Zener diode 40 is set to be smaller than the withstand voltage (for example, 50V) of the adsorption transistor 12 and the holding transistor 32, and is specifically set to 47V.
 かかる構成によれば、ソレノイドコイル11においてツェナ電圧以上のサージ電圧が発生した場合、双方向ツェナダイオード40が導通状態となり、双方向ツェナダイオード40を介してソレノイドコイル11にサージ電流が流れる。その後、電圧降下によってサージ電圧がツェナ電圧よりも小さくなると、双方向ツェナダイオード40が非導通状態となる。これにより、サージ電圧がツェナ電圧まで吸収されることとなる。 According to this configuration, when a surge voltage equal to or higher than the Zener voltage is generated in the solenoid coil 11, the bidirectional Zener diode 40 becomes conductive, and a surge current flows through the solenoid coil 11 through the bidirectional Zener diode 40. Thereafter, when the surge voltage becomes smaller than the Zener voltage due to the voltage drop, the bidirectional Zener diode 40 becomes non-conductive. As a result, the surge voltage is absorbed up to the Zener voltage.
 なお、ツェナ電圧は、ソレノイド駆動回路10に印加される電源電圧(24V)よりも高く設定されている。これにより、電源電圧が印加されている状況において双方向ツェナダイオード40は非導通状態であり、ソレノイドコイル11に所定の電流が流れるようになっている。 The Zener voltage is set higher than the power supply voltage (24V) applied to the solenoid drive circuit 10. As a result, the bidirectional Zener diode 40 is in a non-conductive state in a situation where the power supply voltage is applied, and a predetermined current flows through the solenoid coil 11.
 ソレノイド駆動回路10が駆動していることを報知するために、ソレノイド駆動回路10には発光ダイオード50が設けられている。当該発光ダイオード50は、アノードがスイッチ13を介して+端子14aに接続されており、カソードがダイオード15を介して-端子14bに接続されている。これにより、発光ダイオード50は電源電圧が印加されている状況において発光することとなる。 In order to notify that the solenoid drive circuit 10 is being driven, the solenoid drive circuit 10 is provided with a light emitting diode 50. The light emitting diode 50 has an anode connected to the + terminal 14 a via the switch 13 and a cathode connected to the − terminal 14 b via the diode 15. Thereby, the light emitting diode 50 emits light in a situation where the power supply voltage is applied.
 次に、本ソレノイド駆動回路10の動作について図2及び図3を用いて説明する。図2(a)はソレノイドコイル11に流れる電流変化を示すグラフ、図2(b)はスイッチ13のオンオフを示すタイミングチャート、図2(c)は吸着トランジスタ12のオンオフを示すタイミングチャート、図2(d)は保持トランジスタ32のオンオフを示すタイミングチャートである。図3(a)はサージ電圧の吸収の様子を説明するための説明図、図3(b)はコンデンサ21の放電の様子を説明するための説明図である。 Next, the operation of the solenoid drive circuit 10 will be described with reference to FIGS. 2A is a graph showing a change in current flowing through the solenoid coil 11, FIG. 2B is a timing chart showing ON / OFF of the switch 13, FIG. 2C is a timing chart showing ON / OFF of the adsorption transistor 12, and FIG. (D) is a timing chart showing ON / OFF of the holding transistor 32. FIG. 3A is an explanatory diagram for explaining how the surge voltage is absorbed, and FIG. 3B is an explanatory diagram for explaining how the capacitor 21 is discharged.
 先ず、スイッチ13がオフからオンとなった場合について説明し、その後スイッチ13がオンからオフとなった場合について説明する。 First, a case where the switch 13 is turned on from off will be described, and then a case where the switch 13 is turned off from on will be described.
 t0のタイミングにてスイッチ13がオンとなると、タイマ回路16のコンデンサ21の充電が開始される。この場合、吸着トランジスタ12のベースに対して駆動電流が供給され、吸着トランジスタ12がオンとなる(図2(c)参照)。これにより、第1通電経路Aを電流が流れる。当該電流によってプランジャ吸着動作が行われ、電磁弁が駆動する。当該電流(プランジャ吸着動作が行われる電流)を吸着電流という。すなわち、吸着トランジスタ12は、ソレノイドコイル11に対して吸着電流を流すためのスイッチング素子であるともいえる。 When the switch 13 is turned on at the timing t0, charging of the capacitor 21 of the timer circuit 16 is started. In this case, a drive current is supplied to the base of the adsorption transistor 12, and the adsorption transistor 12 is turned on (see FIG. 2C). Thereby, a current flows through the first energization path A. The plunger is attracted by the current, and the solenoid valve is driven. The current (current at which the plunger suction operation is performed) is referred to as a suction current. That is, it can be said that the adsorption transistor 12 is a switching element for flowing an adsorption current to the solenoid coil 11.
 なお、図2(d)に示すように、スイッチ13がオンとなると、保持トランジスタ32のベースに対して駆動電流が供給され、保持トランジスタ32がオンとなる。この場合、第2通電経路B上には制限抵抗31が設けられているため、第1通電経路Aを流れる吸着電流が支配的となる。 As shown in FIG. 2D, when the switch 13 is turned on, a drive current is supplied to the base of the holding transistor 32, and the holding transistor 32 is turned on. In this case, since the limiting resistor 31 is provided on the second energization path B, the adsorption current flowing through the first energization path A becomes dominant.
 また、上記電源電圧の印加に基づいて発光ダイオード50が発光し、電磁弁が駆動していることが報知される。 Further, it is notified that the light emitting diode 50 emits light based on the application of the power supply voltage and the electromagnetic valve is driven.
 その後、コンデンサ21に充電される電荷量が増加するに従って吸着トランジスタ12のベース電流が小さくなっていく。そして、t1のタイミングにてベース電流が吸着トランジスタ12の閾値電流よりも小さくなると、図2(c)に示すように、吸着トランジスタ12がオフとなり、ソレノイドコイル11には吸着トランジスタ12を介した吸着電流が流れなくなる。この場合、第2通電経路Bを電流が流れ、プランジャの位置が保持される。当該電流(プランジャの位置が保持される電流)を保持電流という。すなわち、第2通電経路B上に設けられた保持トランジスタ32は、ソレノイドコイル11に対して保持電流を流すためのスイッチング素子であるともいえる。保持電流は、図2(a)に示すように、第2通電経路B上に制限抵抗31が設けられている分だけ吸着電流よりも小さくなっている。 Thereafter, the base current of the adsorption transistor 12 decreases as the amount of charge charged in the capacitor 21 increases. When the base current becomes smaller than the threshold current of the adsorption transistor 12 at the timing t1, the adsorption transistor 12 is turned off as shown in FIG. 2C, and the solenoid coil 11 is adsorbed via the adsorption transistor 12. Current stops flowing. In this case, a current flows through the second energization path B, and the position of the plunger is maintained. This current (current at which the position of the plunger is held) is referred to as holding current. That is, it can be said that the holding transistor 32 provided on the second energization path B is a switching element for flowing a holding current to the solenoid coil 11. As shown in FIG. 2A, the holding current is smaller than the adsorption current by the amount that the limiting resistor 31 is provided on the second energization path B.
 以上のことから、所定の時間(電源電圧が印加されてから吸着トランジスタ12のベース電流が閾値電流よりも小さくなるまでの時間)に亘ってソレノイドコイル11に対して吸着電流が流れ、当該所定の時間が経過した場合にはソレノイドコイル11に流れる電流が吸着電流から保持電流に切り換わる。これにより、プランジャ吸着動作を行いつつ、電磁弁の駆動に係る消費電力の低減を図ることができる。 From the above, the attracting current flows to the solenoid coil 11 over a predetermined time (the time from when the power supply voltage is applied until the base current of the attracting transistor 12 becomes smaller than the threshold current). When time elapses, the current flowing through the solenoid coil 11 is switched from the adsorption current to the holding current. Thereby, reduction of the power consumption which concerns on the drive of a solenoid valve can be aimed at, performing plunger adsorption | suction operation | movement.
 ここで、過渡現象の時間を含めて吸着電流が流れる吸着時間T1(t0のタイミング~t1のタイミングまでの時間)は、各抵抗22,23の抵抗値及びコンデンサ21の静電容量によって決まる。このため、上記抵抗値及び静電容量を調整することによって、吸着時間T1を調整することができる。 Here, the adsorption time T1 (the time from the timing t0 to the timing t1) in which the adsorption current flows including the time of the transient phenomenon is determined by the resistance values of the resistors 22 and 23 and the capacitance of the capacitor 21. For this reason, the adsorption time T1 can be adjusted by adjusting the resistance value and the capacitance.
 次に、電源電圧の印加が停止した場合について説明する。 Next, the case where the application of the power supply voltage is stopped will be described.
 t2のタイミングにてスイッチ13がオフとなると、ソレノイドコイル11及びコンデンサ21への通電が停止する。これにより、ソレノイドコイル11においてサージ電圧が発生するとともに、コンデンサ21において放電が行われる。各現象に基づく動作について説明する。 When the switch 13 is turned off at the timing t2, the energization to the solenoid coil 11 and the capacitor 21 is stopped. As a result, a surge voltage is generated in the solenoid coil 11 and the capacitor 21 is discharged. An operation based on each phenomenon will be described.
 先ず、サージ電圧について説明すると、図3(a)に示すように、ソレノイドコイル11にて発生したサージ電圧は双方向ツェナダイオード40に印加され、双方向ツェナダイオード40とソレノイドコイル11とで閉ループ回路が形成される。これにより、サージ電圧がツェナ電圧になるまで当該閉ループ回路にてサージ電流が流れることとなる。当該閉ループ回路は、サージ電圧がツェナ電圧まで下がることによって双方向ツェナダイオード40がオフとなるまで維持される。 First, the surge voltage will be described. As shown in FIG. 3A, the surge voltage generated in the solenoid coil 11 is applied to the bidirectional Zener diode 40, and the bidirectional Zener diode 40 and the solenoid coil 11 constitute a closed loop circuit. Is formed. As a result, a surge current flows in the closed loop circuit until the surge voltage becomes a Zener voltage. The closed loop circuit is maintained until the bidirectional Zener diode 40 is turned off when the surge voltage is reduced to the Zener voltage.
 その後、サージ電圧がツェナ電圧よりも小さくなるt3のタイミングにて、上記閉ループ回路が形成されなくなり、ソレノイドコイル11にはサージ電流が流れなくなる。すなわち、電源電圧の印加の停止タイミング(t2のタイミング)からサージ電圧がツェナ電圧よりも小さくなるタイミング(t3のタイミング)までの時間が、電磁弁の応答遅れ時間T2となっている。 Thereafter, at the timing t3 when the surge voltage becomes smaller than the Zener voltage, the closed loop circuit is not formed, and the surge current does not flow through the solenoid coil 11. That is, the time from when the supply voltage application is stopped (timing at t2) to when the surge voltage becomes smaller than the zener voltage (timing at t3) is the response delay time T2 of the solenoid valve.
 ここで、サージ電圧を吸収する観点に着目すれば、双方向ツェナダイオード40に代えて、サージ電圧が順方向に印加されるようにダイオードを設ける構成も考えられる。しかしながら、この場合、サージ電圧がダイオードにおける順方向の閾値電圧(約1V程度)になるまでソレノイドコイル11にサージ電流が流れることとなるため、電磁弁の応答遅れ時間T2が双方向ツェナダイオード40を設けた場合と比較して長くなる。 Here, focusing on the viewpoint of absorbing the surge voltage, a configuration in which a diode is provided so that the surge voltage is applied in the forward direction instead of the bidirectional Zener diode 40 is also conceivable. However, in this case, since a surge current flows through the solenoid coil 11 until the surge voltage reaches a forward threshold voltage (about 1 V) in the diode, the response delay time T2 of the solenoid valve causes the bidirectional Zener diode 40 to It becomes longer compared to the case where it is provided.
 これに対して、本実施形態によれば、サージ電圧がダイオードにおける順方向の閾値電圧よりも高いツェナ電圧まで降下することに基づいて閉ループ回路が形成されなくなるため、上記ダイオードの閾値電圧とツェナ電圧との差分だけ、電磁弁の応答遅れ時間T2を短縮することができる。 On the other hand, according to the present embodiment, since the closed loop circuit is not formed based on the surge voltage dropping to a Zener voltage higher than the forward threshold voltage in the diode, the threshold voltage and Zener voltage of the diode are not formed. The response delay time T2 of the solenoid valve can be shortened by the difference from the above.
 また、閉ループ回路が形成されていない状況においては吸着トランジスタ12及び保持トランジスタ32はオフであるため、これら各トランジスタ12,32に対してツェナ電圧に対応したサージ電圧が印加される。これにより、コンデンサ21や発光ダイオード50に対するサージ電圧の印加が抑制されている。よって、コンデンサ21や発光ダイオード50が破壊されることを抑制しつつ、ツェナ電圧を高く設定することができる。 Further, in the situation where the closed loop circuit is not formed, the adsorption transistor 12 and the holding transistor 32 are off, so that a surge voltage corresponding to the Zener voltage is applied to each of the transistors 12 and 32. Thereby, application of the surge voltage to the capacitor 21 and the light emitting diode 50 is suppressed. Therefore, the Zener voltage can be set high while suppressing destruction of the capacitor 21 and the light emitting diode 50.
 すなわち、電磁弁の応答遅れ時間T2を短縮するために閉ループ回路が形成されなくなる閾値電圧(ツェナ電圧)を高く設定する場合、当該閾値電圧に相当するサージ電圧が素子に印加されると当該素子が破壊されるおそれがある。特に、コンデンサ21や発光ダイオード50は、逆電圧が印加されることによって破壊され易い。 That is, when a threshold voltage (zener voltage) at which the closed loop circuit is not formed is shortened in order to shorten the response delay time T2 of the solenoid valve, when the surge voltage corresponding to the threshold voltage is applied to the element, the element There is a risk of being destroyed. In particular, the capacitor 21 and the light emitting diode 50 are easily destroyed when a reverse voltage is applied.
 これに対して、本実施形態によれば、サージ電圧が発生している状況、すなわち電源電圧の印加が停止している状況において吸着トランジスタ12及び保持トランジスタ32がオフである。これにより、これら各トランジスタ12,32に対してサージ電圧が印加され、コンデンサ21及び発光ダイオード50に対するサージ電圧の印加が規制されている。よって、ツェナ電圧を高く設定したことによって生じ得る各素子の破壊という不都合を回避することができる。換言すれば、吸着トランジスタ12及び保持トランジスタ32は、サージ電圧がコンデンサ21及び発光ダイオード50に印加されないように規制するサージ規制トランジスタであるとも言える。 On the other hand, according to the present embodiment, the adsorption transistor 12 and the holding transistor 32 are off in a situation where a surge voltage is generated, that is, in a situation where application of the power supply voltage is stopped. Thereby, a surge voltage is applied to each of the transistors 12 and 32, and the application of the surge voltage to the capacitor 21 and the light emitting diode 50 is regulated. Therefore, the inconvenience of destruction of each element that can be caused by setting the Zener voltage high can be avoided. In other words, the adsorption transistor 12 and the holding transistor 32 can be said to be surge regulation transistors that regulate the surge voltage from being applied to the capacitor 21 and the light emitting diode 50.
 特に、ツェナ電圧は、基準電位(0V)に対して各トランジスタ12,32の耐圧(50V)寄りの電圧(47V)に設定されている。これにより、各トランジスタ12,32が破壊されない範囲内で応答遅れ時間T2の短縮化を図ることができる。 In particular, the Zener voltage is set to a voltage (47V) close to the withstand voltage (50V) of each transistor 12, 32 with respect to the reference potential (0V). As a result, the response delay time T2 can be shortened within a range in which the transistors 12 and 32 are not destroyed.
 また、各トランジスタ12,32のベースにはサージ電圧が印加されないように形成されている。具体的には、各トランジスタ12,32のベースはソレノイドコイル11の各通電経路A,Bを介することなく直接+端子14aに接続されている。換言すれば、各トランジスタ12,32のベースと+端子14aとを接続する各入力経路とソレノイドコイル11の通電経路A,Bとが独立している。これにより、各トランジスタ12,32がサージ電圧によってオンとなることが抑制されている。よって、仮に本ソレノイド駆動回路10に対してダイオードDが逆接続された場合であっても、電磁弁の応答遅れ時間T2が変動しない。 Also, the bases of the transistors 12 and 32 are formed so that no surge voltage is applied. Specifically, the bases of the transistors 12 and 32 are directly connected to the + terminal 14 a without passing through the energization paths A and B of the solenoid coil 11. In other words, the input paths connecting the bases of the transistors 12 and 32 and the + terminal 14a and the energization paths A and B of the solenoid coil 11 are independent. This suppresses the transistors 12 and 32 from being turned on by the surge voltage. Therefore, even if the diode D is reversely connected to the solenoid drive circuit 10, the response delay time T2 of the solenoid valve does not vary.
 すなわち、ソレノイド駆動回路10に対してコントローラ回路等の各種回路を接続する場合がある。この場合、ソレノイドコイル11から生じるサージ電圧が上記各種回路に印加されないようするために、図3(a)に示すように、ダイオードDを逆接続する場合がある。かかる構成において、仮に上記サージ電圧によって保持トランジスタ32がオンとなると、当該保持トランジスタ32、制限抵抗31、ダイオードD及びソレノイドコイル11によって閉ループ回路が形成され、ソレノイドコイル11に対してサージ電流が流れることとなる。このため、図2(a)の2点鎖線Z1に示すように、双方向ツェナダイオード40を設けたのにも関わらず、電磁弁の応答遅れ時間T2が長くなるという不都合が生じ得る。 That is, various circuits such as a controller circuit may be connected to the solenoid drive circuit 10. In this case, in order to prevent the surge voltage generated from the solenoid coil 11 from being applied to the various circuits, the diode D may be reversely connected as shown in FIG. In such a configuration, if the holding transistor 32 is turned on by the surge voltage, a closed loop circuit is formed by the holding transistor 32, the limiting resistor 31, the diode D, and the solenoid coil 11, and a surge current flows to the solenoid coil 11. It becomes. For this reason, as indicated by a two-dot chain line Z1 in FIG. 2A, there may be a disadvantage that the response delay time T2 of the electromagnetic valve becomes long although the bidirectional Zener diode 40 is provided.
 これに対して、本実施形態によれば、保持トランジスタ32のベースはソレノイドコイル11の各通電経路A,Bを介することなく+端子14aに接続されているため、当該保持トランジスタ32のベースに対してサージ電圧が印加されない。これにより、保持トランジスタ32がサージ電圧によってオンとなり、上記閉ループ回路が形成されることがない。よって、上記不都合を回避することができる。すなわち、本ソレノイド駆動回路10に対して接続される他の回路構成に関わらず電磁弁の応答遅れ時間T2は一定となる。 On the other hand, according to the present embodiment, the base of the holding transistor 32 is connected to the + terminal 14a without passing through the energization paths A and B of the solenoid coil 11, so Surge voltage is not applied. As a result, the holding transistor 32 is turned on by the surge voltage, and the closed loop circuit is not formed. Therefore, the inconvenience can be avoided. That is, the response delay time T2 of the solenoid valve is constant regardless of other circuit configurations connected to the solenoid drive circuit 10.
 次に、コンデンサ21の放電について説明すると、図3(b)に示すように、本ソレノイド駆動回路10において複数(具体的には3つ)の放電経路51,52,53が形成される。各放電経路51,52,53について以下に説明する。 Next, the discharge of the capacitor 21 will be described. As shown in FIG. 3B, a plurality (specifically, three) of discharge paths 51, 52, and 53 are formed in the solenoid drive circuit 10. Each discharge path 51, 52, 53 will be described below.
 先ず、第1放電経路51について説明すると、コンデンサ21に蓄積された電荷は発光ダイオード50を介して放電される。 First, the first discharge path 51 will be described. Charge accumulated in the capacitor 21 is discharged through the light emitting diode 50.
 次に、第2放電経路52について説明すると、コンデンサ21に蓄積された電荷によって保持トランジスタ32のベースに対して一時的に駆動電流が供給される。このため、図2(d)に示すように、スイッチ13のオフ後も保持トランジスタ32が所定時間だけオンとなる。これにより、コンデンサ21に蓄積された電荷はソレノイドコイル11及び保持トランジスタ32を介して放電される。 Next, the second discharge path 52 will be described. A drive current is temporarily supplied to the base of the holding transistor 32 by the electric charge accumulated in the capacitor 21. Therefore, as shown in FIG. 2D, the holding transistor 32 is turned on for a predetermined time even after the switch 13 is turned off. Thereby, the electric charge accumulated in the capacitor 21 is discharged via the solenoid coil 11 and the holding transistor 32.
 ここで、上記2つの放電経路51,52上には、オンとなるために所定の閾値電圧を要する半導体素子が設けられている。詳細には、第1放電経路51上には発光ダイオード50が設けられており、第2放電経路52上には保持トランジスタ32が設けられている。このため、これらの半導体素子がオンとなるのに必要な閾値電圧に対応した電荷が放電されることなく残留する。具体的には、約1Vに相当する電荷が残留する。この残留電荷は自然放電によって放出されることとなるため、コンデンサ21に蓄積された電荷が完全に放電するまでに要する放電時間が長くなる。すると、スイッチ13がオフとなってから再度スイッチ13がオンとなるタイミングにおいて、コンデンサ21に電荷が残留している場合がある。この場合、残留している電荷量に応じて吸着トランジスタ12のオン時間が変動するため、プランジャ吸着動作が完了する前に吸着トランジスタ12がオフとなるおそれがある。そのため、図2(a)の2点鎖線Z2に示すように、上記残留電荷量に基づく吸着トランジスタ12のオン時間の変動に対応させて吸着時間T1を長く設定する必要が生じ、消費電力の増大化が懸念される。 Here, semiconductor elements that require a predetermined threshold voltage to be turned on are provided on the two discharge paths 51 and 52. Specifically, the light emitting diode 50 is provided on the first discharge path 51, and the holding transistor 32 is provided on the second discharge path 52. For this reason, the electric charge corresponding to the threshold voltage required to turn on these semiconductor elements remains without being discharged. Specifically, a charge corresponding to about 1 V remains. Since this residual charge is released by natural discharge, the discharge time required until the charge accumulated in the capacitor 21 is completely discharged becomes longer. Then, the charge 21 may remain in the capacitor 21 at the timing when the switch 13 is turned on again after the switch 13 is turned off. In this case, since the ON time of the adsorption transistor 12 varies depending on the remaining charge amount, the adsorption transistor 12 may be turned off before the plunger adsorption operation is completed. For this reason, as indicated by a two-dot chain line Z2 in FIG. 2A, it is necessary to set the adsorption time T1 longer in accordance with the change in the on-time of the adsorption transistor 12 based on the residual charge amount, thereby increasing the power consumption. There is a concern about conversion.
 これに対して、本ソレノイド駆動回路10は、第3放電経路53としてタイマ回路16、抵抗23及びベース電流供給回路33により形成される閉ループ回路を備えている。これにより、コンデンサ21に蓄積された電荷は、図3(b)に示すように、各抵抗33a,33bを介した第3放電経路53にて放電される。すなわち、各抵抗33a,33bはコンデンサ21の放電用抵抗33a,33bであるとも言える。 In contrast, the solenoid drive circuit 10 includes a closed loop circuit formed by the timer circuit 16, the resistor 23, and the base current supply circuit 33 as the third discharge path 53. Thereby, the electric charge accumulated in the capacitor 21 is discharged through the third discharge path 53 via the resistors 33a and 33b, as shown in FIG. 3B. That is, it can be said that the resistors 33a and 33b are discharging resistors 33a and 33b of the capacitor 21, respectively.
 第3放電経路53上には抵抗(詳細には各抵抗22,23,33a,33b)のみが設けられており、オンとなるのに所定の閾値電圧を要する半導体素子が設けられていない。これにより、コンデンサ21に蓄積された電荷を完全に放電させることができるため、自然放電が行われる場合と比較してコンデンサ21の放電時間を短くすることができる。よって、コンデンサ21の残留電荷量に基づく吸着トランジスタ12のオン時間の変動を低減させることができるため、吸着電流を流す吸着時間T1の短縮化を図ることができる。したがって、消費電力の低減を図ることができる。 Only resistors (specifically, the resistors 22, 23, 33a, and 33b) are provided on the third discharge path 53, and no semiconductor element that requires a predetermined threshold voltage to be turned on is provided. Thereby, since the electric charge accumulated in the capacitor 21 can be completely discharged, the discharge time of the capacitor 21 can be shortened compared with the case where natural discharge is performed. Therefore, since the fluctuation of the on-time of the adsorption transistor 12 based on the residual charge amount of the capacitor 21 can be reduced, it is possible to shorten the adsorption time T1 through which the adsorption current flows. Therefore, power consumption can be reduced.
 ここで、コンデンサ21の放電によって保持トランジスタ32がオンとなるため、既に説明した通り、仮にダイオードDを設けた場合にサージ電圧に基づくサージ電流がダイオードDを介して流れるおそれがある。これに対して、サージ電圧がツェナ電圧になるまでに要する時間よりもコンデンサ21の放電時間が短くなるように各放電用抵抗33a,33bの抵抗値が(低く)設定されている。これにより、図2(d)に示すように、サージ電圧がツェナ電圧よりも小さくなるタイミング(t3のタイミング)では、保持トランジスタ32はオフであるため、サージ電流が流れない。よって、コンデンサ21に蓄積された電荷の放電を好適に行いつつ、当該コンデンサ21の放電に基づく不都合(保持トランジスタ32がオンとなることによって生じ得る電磁弁の応答遅れ時間T2の長時間化)を抑制することができる。 Here, since the holding transistor 32 is turned on by the discharge of the capacitor 21, as already described, if the diode D is provided, a surge current based on the surge voltage may flow through the diode D. On the other hand, the resistance values of the discharge resistors 33a and 33b are set (lower) so that the discharge time of the capacitor 21 is shorter than the time required for the surge voltage to become the Zener voltage. As a result, as shown in FIG. 2D, at the timing when the surge voltage becomes smaller than the Zener voltage (timing at t3), the holding transistor 32 is off, so that no surge current flows. Therefore, while suitably discharging the electric charge accumulated in the capacitor 21, the inconvenience due to the discharge of the capacitor 21 (longening of the response delay time T2 of the solenoid valve that may occur when the holding transistor 32 is turned on) is caused. Can be suppressed.
 以上詳述した本実施形態によれば以下の優れた効果を奏する。 According to the embodiment described above in detail, the following excellent effects are obtained.
 ソレノイドコイル11に対して並列に双方向ツェナダイオード40を設け、これらソレノイドコイル11及び双方向ツェナダイオード40に対して直列に吸着トランジスタ12及び保持トランジスタ32を設けた。これにより、電源電圧が印加されない場合には各トランジスタ12,32をオフとすることによって、ツェナ電圧まで下がったサージ電圧が他の素子に印加されないようになっている。よって、サージ電圧による素子の破壊を抑制しつつ、ツェナ電圧を高く設定することができる。 The bidirectional Zener diode 40 is provided in parallel with the solenoid coil 11, and the adsorption transistor 12 and the holding transistor 32 are provided in series with the solenoid coil 11 and the bidirectional Zener diode 40. Thereby, when the power supply voltage is not applied, the transistors 12 and 32 are turned off, so that the surge voltage lowered to the Zener voltage is not applied to other elements. Therefore, the Zener voltage can be set high while suppressing the destruction of the element due to the surge voltage.
 各トランジスタ12,32のベースを、ソレノイドコイル11を介することなく+端子14aに接続した。これにより、サージ電圧が各トランジスタ12,32のベースに印加されないようになっているため、サージ電圧に基づいて各トランジスタ12,32がオンとならないようになっている。よって、仮に本ソレノイド駆動回路10に対してダイオードDを設けた場合であっても電磁弁の応答遅れ時間T2が長くなることがない。 The bases of the transistors 12 and 32 were connected to the + terminal 14a without going through the solenoid coil 11. Thus, since the surge voltage is not applied to the bases of the transistors 12 and 32, the transistors 12 and 32 are not turned on based on the surge voltage. Therefore, even if the diode D is provided for the solenoid drive circuit 10, the response delay time T2 of the solenoid valve does not increase.
 さらに、各トランジスタ12,32のベース端子を-端子14bに接続した。これにより、コンデンサ21の放電経路として、オンとなるために所定の閾値電圧を要する半導体素子が設けられていない第3放電経路53が形成されるため、コンデンサ21に蓄積された電荷を完全に放電させることができる。よって、吸着トランジスタ12のオン時間の変動を抑制することができる。したがって、当該変動に対応させて吸着時間T1を長く設定する必要がなくなるため、上記吸着時間T1を短く設定することができ、消費電力の低減を図ることができる。 Furthermore, the base terminals of the transistors 12 and 32 were connected to the negative terminal 14b. As a result, a third discharge path 53 is formed as a discharge path of the capacitor 21, which is not provided with a semiconductor element that requires a predetermined threshold voltage to be turned on. Therefore, the charge accumulated in the capacitor 21 is completely discharged. Can be made. Therefore, fluctuations in the on-time of the adsorption transistor 12 can be suppressed. Accordingly, since it is not necessary to set the suction time T1 to be long in response to the fluctuation, the suction time T1 can be set to be short, and power consumption can be reduced.
 <第2実施形態>
 本実施形態では、サージ電圧を吸収する構成が第1実施形態と相違する。当該相違点について図4を用いて説明する。図4は、第2実施形態におけるソレノイド駆動回路100の回路図である。なお、上記第1実施形態と同様の構成については同一の符号を付すとともに、その説明を省略する。
Second Embodiment
In the present embodiment, the configuration for absorbing the surge voltage is different from that of the first embodiment. The difference will be described with reference to FIG. FIG. 4 is a circuit diagram of the solenoid drive circuit 100 in the second embodiment. In addition, about the structure similar to the said 1st Embodiment, while attaching | subjecting the same code | symbol, the description is abbreviate | omitted.
 上記第1実施形態では、双方向ツェナダイオード40をソレノイドコイル11に対して並列に接続したが、これに代えて、ツェナダイオード101を吸着トランジスタ12のベース・コレクタ間に接続する。具体的には、ツェナダイオード101のアノードを吸着トランジスタ12のベースに対して接続し、カソードを吸着トランジスタ12のコレクタに接続する。これにより、ツェナダイオード101を介して吸着トランジスタ12のベース端子に入力されるベース経路と、第1通電経路Aとが接続されることとなる。 In the first embodiment, the bidirectional Zener diode 40 is connected in parallel to the solenoid coil 11, but instead, the Zener diode 101 is connected between the base and collector of the adsorption transistor 12. Specifically, the anode of the Zener diode 101 is connected to the base of the adsorption transistor 12 and the cathode is connected to the collector of the adsorption transistor 12. As a result, the base path that is input to the base terminal of the adsorption transistor 12 via the Zener diode 101 and the first energization path A are connected.
 かかる構成によれば、ツェナ電圧よりも大きいサージ電圧が発生した場合、ツェナダイオード101が導通状態となる。すると、サージ電圧に基づくサージ電流が吸着トランジスタ12のベースに供給され、吸着トランジスタ12がオンとなる。これにより、吸着トランジスタ12及び抵抗33a,33bを介した閉ループ回路が形成され、サージ電圧がツェナ電圧となるまで閉ループ回路にてサージ電流が流れる。 According to such a configuration, the Zener diode 101 becomes conductive when a surge voltage larger than the Zener voltage is generated. Then, a surge current based on the surge voltage is supplied to the base of the adsorption transistor 12, and the adsorption transistor 12 is turned on. As a result, a closed loop circuit is formed via the adsorption transistor 12 and the resistors 33a and 33b, and a surge current flows in the closed loop circuit until the surge voltage becomes a Zener voltage.
 その後、サージ電圧がツェナ電圧よりも小さくなると、吸着トランジスタ12のベースに対してサージ電流が供給されなくなるため、吸着トランジスタ12がオフ状態となる。これにより、ソレノイドコイル11にサージ電流が流れなくなり、電磁弁の駆動が停止する。よって、電磁弁の応答遅れ時間T2の短縮化を図ることができる。換言すれば、ツェナダイオード101は、サージ電圧がツェナ電圧よりも大きい状況においてはサージ電流が吸着トランジスタ12のベースに対して供給されるように前記サージ電圧を伝送するとともに、サージ電圧がツェナ電圧よりも小さい状況においては上記サージ電圧の伝送を規制するものであると言える。 Thereafter, when the surge voltage becomes smaller than the Zener voltage, the surge current is not supplied to the base of the adsorption transistor 12, so that the adsorption transistor 12 is turned off. As a result, the surge current stops flowing through the solenoid coil 11, and the drive of the solenoid valve stops. Therefore, the response delay time T2 of the solenoid valve can be shortened. In other words, the Zener diode 101 transmits the surge voltage so that the surge current is supplied to the base of the adsorption transistor 12 in a situation where the surge voltage is larger than the Zener voltage, and the surge voltage is higher than the Zener voltage. In a small situation, it can be said that the transmission of the surge voltage is regulated.
 ちなみに、コンデンサ21に蓄積された電荷の放電について第1実施形態と異なる点について説明すると、各抵抗33a,33bを流れる電流方向が、上記閉ループ回路に基づくものと電荷の放電に基づくものとで逆向きとなるため、閉ループ回路が形成されている場合には、各抵抗33a,33bを介した電荷の放電は行われない。このため、サージ電圧がツェナ電圧よりも小さくなってから(閉ループ回路が形成されなくなってから)所定の期間経過後に、コンデンサ21の電荷の完全放電が完了する。 By the way, the difference between the first embodiment and the discharge of the charge accumulated in the capacitor 21 will be described. The direction of the current flowing through the resistors 33a and 33b is opposite between that based on the closed loop circuit and that based on the charge discharge. Therefore, when a closed loop circuit is formed, electric charges are not discharged through the resistors 33a and 33b. For this reason, after the surge voltage becomes lower than the Zener voltage (after the closed loop circuit is no longer formed), the complete discharge of the capacitor 21 is completed after a predetermined period.
 なお、ツェナダイオード101を吸着トランジスタ12のコレクタ・エミッタ間に逆接続する構成としてもよい。詳細には、コレクタにツェナダイオード101のカソードを接続し、エミッタにツェナダイオード101のカソードを接続する。この場合、吸着トランジスタ12がオンとなることなく、サージ電圧がツェナ電圧となるまでツェナダイオード101、抵抗33a,33bを介した閉ループ回路が形成される。 Note that the Zener diode 101 may be reversely connected between the collector and emitter of the adsorption transistor 12. Specifically, the cathode of the Zener diode 101 is connected to the collector, and the cathode of the Zener diode 101 is connected to the emitter. In this case, a closed loop circuit through the Zener diode 101 and the resistors 33a and 33b is formed until the surge voltage becomes the Zener voltage without the adsorption transistor 12 being turned on.
 本発明は上記各実施形態の記載内容に限定されず例えば次のように実施してもよい。 The present invention is not limited to the description of the above embodiments, and may be implemented as follows, for example.
 (1)上記各実施形態では、サージ電圧をツェナ電圧にまで下げるために双方向ツェナダイオード40又はツェナダイオード101を設けたが、これに限られず、これらに代えて、バリスタを設ける構成としてもよい。 (1) In each of the above embodiments, the bidirectional Zener diode 40 or the Zener diode 101 is provided to reduce the surge voltage to the Zener voltage. However, the present invention is not limited to this, and a varistor may be provided instead. .
 (2)上記各実施形態では、スイッチング素子としてNPN型のトランジスタを用いたが、これに限られず、例えばPNP型のトランジスタを用いてもよい。この場合、PNP型のトランジスタに合わせて接続関係を設定する。また、トランジスタに限られず、MOSFET等の他のスイッチング素子を用いてもよい。 (2) In each of the above embodiments, an NPN transistor is used as a switching element. However, the present invention is not limited to this. For example, a PNP transistor may be used. In this case, the connection relationship is set according to the PNP transistor. Further, the switching element is not limited to a transistor, and another switching element such as a MOSFET may be used.
 (3)上記各実施形態では、発光ダイオード50に対して電流を流す経路を別に設けたが、これに限られず、例えば抵抗33a又は抵抗33bを発光ダイオード50に置換してもよい。これにより、構成の簡素化を図ることができる。但し、コンデンサ21の放電を完全に行うことができる点に着目すれば、抵抗33a又は抵抗33bを設ける構成の方が優れている。 (3) In each of the above embodiments, a separate path for supplying current to the light emitting diode 50 is provided, but the present invention is not limited to this. For example, the resistor 33a or the resistor 33b may be replaced with the light emitting diode 50. Thereby, simplification of a structure can be achieved. However, if attention is paid to the fact that the capacitor 21 can be completely discharged, the configuration in which the resistor 33a or the resistor 33b is provided is superior.
 (4)本ソレノイド駆動回路10に対してさらに別のソレノイド駆動回路や他の周辺回路を並列接続させてもよい。このような場合であっても、他の回路の回路構成に関わらず電磁弁の応答遅れ時間T2は一定となる。 (4) Another solenoid drive circuit and other peripheral circuits may be connected in parallel to the solenoid drive circuit 10. Even in such a case, the response delay time T2 of the solenoid valve is constant regardless of the circuit configuration of other circuits.
 10…ソレノイド駆動回路、11…ソレノイドコイル、12…スイッチング素子としての吸着トランジスタ、14a…一方の電源端子としての+端子、14b…他方の電源端子としての-端子、16…タイマ回路、21…コンデンサ、31…制限抵抗、32…スイッチング素子としての保持トランジスタ、33…ベース電流供給回路、40…双方向ツェナダイオード、51~53…放電経路、101…ツェナダイオード、A,B…放電経路。 DESCRIPTION OF SYMBOLS 10 ... Solenoid drive circuit, 11 ... Solenoid coil, 12 ... Adsorption transistor as a switching element, 14a ... + terminal as one power supply terminal, 14b ...-terminal as the other power supply terminal, 16 ... Timer circuit, 21 ... Capacitor 31 ... Limiting resistor, 32 ... Holding transistor as switching element, 33 ... Base current supply circuit, 40 ... Bidirectional Zener diode, 51-53 ... Discharge path, 101 ... Zener diode, A, B ... Discharge path.

Claims (5)

  1.  通電されることにより磁界を発生し、電磁弁を駆動させるソレノイドコイルと、
     前記ソレノイドコイルに対して直列に接続されたスイッチング素子と、
    を備え、
     前記ソレノイドコイル及び前記スイッチング素子の直列接続体は電源電圧を印加する一対の電源端子に接続されており、
     前記電源電圧が印加されている状況において前記スイッチング素子がオン状態となることにより前記ソレノイドコイルの通電経路が形成され、当該ソレノイドコイルの通電が行われるソレノイド駆動回路において、
     前記スイッチング素子として、
     前記電源電圧が印加されてからあらかじめ定められた特定時間が経過するまでオン状態となる第1スイッチング素子と、
     前記第1スイッチング素子に対して並列に接続され、前記電源電圧が印加されている間に亘ってオン状態となる第2スイッチング素子と、
    を備え、
     前記ソレノイドコイルの通電経路として、
     前記第1スイッチング素子を介した第1通電経路と、
     前記第2スイッチング素子を介した第2通電経路と、
    が設けられており、
     前記第2通電経路上には、当該第2通電経路上を流れる電流が前記第1通電経路上を流れる電流よりも小さくなるように制限抵抗が設けられており、
     前記各通電経路とは別に、
     前記第1スイッチング素子の入力端子と前記一対の電源端子の一方とを接続する第1入力経路と、
     前記第2スイッチング素子の入力端子と前記一方の電源端子とを接続する第2入力経路と、
    が並列に設けられており、
     前記第1入力経路上に設けられ、前記特定時間に亘って前記第1スイッチング素子に対して当該第1スイッチング素子がオン状態となる駆動電力を供給するタイマ回路と、
     ツェナダイオード又はバリスタを有し、前記ソレノイドコイルへの通電が停止した場合に発生するサージ電圧を前記ツェナダイオード又は前記バリスタが導通状態となる閾値電圧まで吸収するサージ吸収回路と、
    を備え、
     前記閾値電圧まで吸収されたサージ電圧が前記各スイッチング素子に対して印加されるように構成されていることを特徴とするソレノイド駆動回路。
    A solenoid coil that generates a magnetic field when energized and drives a solenoid valve;
    A switching element connected in series to the solenoid coil;
    With
    The series connection body of the solenoid coil and the switching element is connected to a pair of power supply terminals for applying a power supply voltage,
    In the solenoid drive circuit in which the energization path of the solenoid coil is formed by turning on the switching element in a state where the power supply voltage is applied, and the solenoid coil is energized.
    As the switching element,
    A first switching element that is turned on until a predetermined time elapses after the power supply voltage is applied;
    A second switching element that is connected in parallel to the first switching element and is turned on while the power supply voltage is applied;
    With
    As the energization path of the solenoid coil,
    A first energization path through the first switching element;
    A second energization path through the second switching element;
    Is provided,
    On the second energization path, a limiting resistor is provided so that a current flowing on the second energization path is smaller than a current flowing on the first energization path,
    Apart from the energization paths,
    A first input path connecting the input terminal of the first switching element and one of the pair of power supply terminals;
    A second input path connecting the input terminal of the second switching element and the one power supply terminal;
    Are provided in parallel,
    A timer circuit that is provided on the first input path and supplies driving power for turning on the first switching element to the first switching element over the specific time;
    A surge absorption circuit that has a Zener diode or a varistor and absorbs a surge voltage generated when the energization to the solenoid coil is stopped to a threshold voltage at which the Zener diode or the varistor becomes conductive;
    With
    A solenoid drive circuit characterized in that a surge voltage absorbed up to the threshold voltage is applied to each of the switching elements.
  2.  前記サージ吸収回路は、前記ソレノイドコイルに対して並列に接続されているとともに、前記各スイッチング素子に対して直列に接続されており、
     前記サージ電圧が前記各入力経路に伝送されないように前記各入力経路と前記各通電経路とが独立していることを特徴とする請求項1に記載のソレノイド駆動回路。
    The surge absorbing circuit is connected in parallel to the solenoid coil, and is connected in series to the switching elements.
    2. The solenoid drive circuit according to claim 1, wherein the input paths and the energization paths are independent so that the surge voltage is not transmitted to the input paths.
  3.  前記第2入力経路上には、前記第2スイッチング素子の入力端子に供給する駆動電力を規定する規定抵抗が設けられており、
     前記タイマ回路は、時定数抵抗及び当該時定数抵抗に対して直列に接続されたコンデンサを備え、
     前記各入力経路が接続されることで前記規定抵抗、前記時定数抵抗及び前記コンデンサを含む閉ループが形成されており、
     前記閉ループは、前記コンデンサに蓄積された電荷の放電が行われる放電経路を構成することを特徴とする請求項1又は請求項2に記載のソレノイド駆動回路。
    On the second input path, a defining resistor that defines driving power supplied to the input terminal of the second switching element is provided,
    The timer circuit includes a time constant resistor and a capacitor connected in series to the time constant resistor,
    A closed loop including the specified resistor, the time constant resistor and the capacitor is formed by connecting the input paths,
    3. The solenoid drive circuit according to claim 1, wherein the closed loop constitutes a discharge path through which electric charges accumulated in the capacitor are discharged. 4.
  4.  前記コンデンサに蓄積された電荷の放電が完了するのに要する時間が、前記サージ電圧が前記閾値電圧まで吸収されるのに要する時間よりも短くなるように前記規定抵抗の抵抗値が設定されていることを特徴とする請求項3に記載のソレノイド駆動回路。 The resistance value of the specified resistor is set so that the time required to complete the discharge of the charge accumulated in the capacitor is shorter than the time required for the surge voltage to be absorbed to the threshold voltage. The solenoid drive circuit according to claim 3.
  5.  前記第1スイッチング素子はNPN型の第1バイポーラトランジスタであり、
     前記第2スイッチング素子はNPN型の第2バイポーラトランジスタであり、
     前記各通電経路は、前記ソレノイドコイルの一端を前記一対の電源端子の+端子に接続するとともに、他端を前記各バイポーラトランジスタのコレクタ端子に接続し、さらに前記各バイポーラトランジスタのエミッタ端子を前記一対の電源端子の-端子に接続することで形成されるものであり、
     前記制限抵抗は、前記第2バイポーラトランジスタのコレクタと前記ソレノイドコイルの他端との間に設けられており、
     前記第1入力経路は、前記第1バイポーラトランジスタのベース端子を、前記タイマ回路を構成する時定数抵抗及びコンデンサを介して前記+端子に接続するとともに、抵抗を介して前記-端子に接続することで形成されるものであり、
     前記第2入力経路は、前記第2バイポーラトランジスタのベース端子を、第1規定抵抗を介して前記+端子に接続するとともに、第2規定抵抗を介して前記-端子に対して接続することで形成されるものであり、
     前記ツェナダイオード又はバリスタは、前記ソレノイドコイルに対して並列に接続されるとともに前記各バイポーラトランジスタに対して直列に接続されていることを特徴とする請求項1乃至4のいずれか1に記載のソレノイド駆動回路。
    The first switching element is an NPN-type first bipolar transistor,
    The second switching element is an NPN-type second bipolar transistor;
    Each energization path has one end of the solenoid coil connected to the positive terminal of the pair of power supply terminals, the other end connected to the collector terminal of each bipolar transistor, and the emitter terminal of each bipolar transistor connected to the pair of power supply terminals. It is formed by connecting to the negative terminal of the power supply terminal of
    The limiting resistor is provided between the collector of the second bipolar transistor and the other end of the solenoid coil,
    The first input path connects the base terminal of the first bipolar transistor to the + terminal through a time constant resistor and a capacitor constituting the timer circuit and to the − terminal through a resistor. It is formed with
    The second input path is formed by connecting the base terminal of the second bipolar transistor to the + terminal via a first specified resistor and to the − terminal via a second specified resistor. Is,
    5. The solenoid according to claim 1, wherein the Zener diode or the varistor is connected in parallel to the solenoid coil and is connected in series to each of the bipolar transistors. Driving circuit.
PCT/JP2011/051659 2010-03-05 2011-01-27 Solenoid drive circuit WO2011108313A1 (en)

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KR20120124073A (en) 2012-11-12
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