WO2011102088A1 - Electronic component - Google Patents

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Publication number
WO2011102088A1
WO2011102088A1 PCT/JP2011/000559 JP2011000559W WO2011102088A1 WO 2011102088 A1 WO2011102088 A1 WO 2011102088A1 JP 2011000559 W JP2011000559 W JP 2011000559W WO 2011102088 A1 WO2011102088 A1 WO 2011102088A1
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WO
WIPO (PCT)
Prior art keywords
coil
layer
magnetic
resin layer
pattern
Prior art date
Application number
PCT/JP2011/000559
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French (fr)
Japanese (ja)
Inventor
溝口 直樹
正人 野宮
Original Assignee
株式会社村田製作所
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Filing date
Publication date
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Publication of WO2011102088A1 publication Critical patent/WO2011102088A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00Fixed inductances of the signal type 
    • H01F17/0006Printed inductances
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01Frequency selective two-port networks
    • H03H7/0115Frequency selective two-port networks comprising only inductors and capacitors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01Frequency selective two-port networks
    • H03H7/09Filters comprising mutual inductance
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01Frequency selective two-port networks
    • H03H7/17Structural details of sub-circuits of frequency selective networks
    • H03H7/1708Comprising bridging elements, i.e. elements in a series path without own reference to ground and spanning branching nodes of another series path
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01Frequency selective two-port networks
    • H03H7/17Structural details of sub-circuits of frequency selective networks
    • H03H7/1741Comprising typical LC combinations, irrespective of presence and location of additional resistors
    • H03H7/1758Series LC in shunt or branch path
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01Frequency selective two-port networks
    • H03H7/17Structural details of sub-circuits of frequency selective networks
    • H03H7/1741Comprising typical LC combinations, irrespective of presence and location of additional resistors
    • H03H7/1775Parallel LC in shunt or branch path
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00Fixed inductances of the signal type 
    • H01F17/0006Printed inductances
    • H01F2017/0066Printed inductances with a magnetic layer
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H03H2001/0021Constructional details
    • H03H2001/0071Constructional details comprising zig-zag inductor
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H03H2001/0021Constructional details
    • H03H2001/0078Constructional details comprising spiral inductor on a substrate
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H03H2001/0021Constructional details
    • H03H2001/0085Multilayer, e.g. LTCC, HTCC, green sheets

Definitions

  • the present invention relates to a multilayer electronic component in which a pattern for forming a capacitor or a coil is provided.
  • an electronic component as a multilayer filter formed by simultaneously firing a laminated magnetic ceramic layer and a dielectric ceramic layer is known (see, for example, Patent Document 1).
  • the coil layer 1504 by the conductor pattern 1513 is provided inside the magnetic ceramic layer 1501, and two or more internal electrodes 1505 to 1508 are inside.
  • Dielectric ceramic layers 1502 and 1503 in which capacitors are formed by being disposed are laminated on the upper and lower sides of the magnetic ceramic layer 1501, respectively.
  • a capacitor and inductor layer 1504 is connected to the external electrodes 1510 and 1511 to form a multilayer filter 1500.
  • a multilayer filter 1500 a plurality of magnetic ceramic green sheets for forming the magnetic ceramic layer 1501, a plurality of dielectric ceramic green sheets for forming the dielectric ceramic layers 1502 and 1503, and a predetermined wiring pattern are formed.
  • a multilayer substrate is configured by laminating green sheets.
  • a multilayer substrate composed of a plurality of laminated ceramic green sheets is fired at around 1000 ° C. to produce a multilayer filter 1500 (so-called LTCC (Low Temperature Co-fired Ceramic). Ceramic) substrate).
  • LTCC Low Temperature Co-fired Ceramic
  • Ceramic Ceramic
  • the magnetic ceramic layer 1501 and the dielectric ceramic layers 1502 and 1503 contract due to evaporation of the solvent and binder contained in each green sheet. Since the magnetic ceramic layer 1501 and the dielectric ceramic layers 1502 and 1503 which are different materials have different shrinkage amounts, stress is likely to be generated at the boundary between the layers 1501 to 1503. Accordingly, there is a possibility that warpage, undulation, distortion, cracking, etc. may occur in the multilayer substrate that has been co-fired. If warping, undulation, distortion, cracking, etc. occur in the multilayer filter 1500 during the manufacturing process, In this process, a defect occurs, or a mounting failure occurs when the manufactured multilayer filter 1500 is mounted.
  • the ceramic material constituting each of the layers 1501 to 1503 is selected so that the thermal contraction amounts of the magnetic ceramic layer 1501 and the dielectric ceramic layers 1502 and 1503 are substantially the same.
  • the ceramic composition material constituting each of the layers 1501 to 1503 is limited, the selection range of the magnetic permeability of the magnetic ceramic layer 1501 and the dielectric constant of the dielectric ceramic layers 1502 and 1503 is significantly narrowed. Therefore, there is a problem that the multilayer filter 1500 having desired characteristics cannot be obtained, or even if the desired characteristics are obtained, the size of the multilayer filter 1500 is increased.
  • the present invention has been made in view of the above problems, and provides an electronic component capable of suppressing the occurrence of defective products in the manufacturing process and easily adjusting the magnetic permeability and the dielectric constant. Objective.
  • an electronic component of the present invention includes a multilayer substrate formed by firing laminated ceramic green sheets, and a magnetic resin layer provided on at least one main surface of the multilayer substrate. (Claim 1).
  • the electronic component of the present invention may further include a coil pattern that forms a coil (claim 2).
  • the coil pattern may be formed in a helical shape in the stacking direction of the multilayer substrate.
  • the coil pattern may be provided in contact with the magnetic resin layer (claim 4).
  • At least a part of the coil pattern may be provided inside the magnetic resin layer (Claim 5).
  • a metal film layer provided on the main surface of the magnetic resin layer opposite to the multilayer substrate is further provided, and the metal film layer is provided so as to overlap at least a part of the coil pattern in a top view. (Claim 6).
  • the electronic component of the present invention may further include a resonator pattern that forms a resonator (claim 7).
  • a first resonator pattern that forms a first resonator having a first coil and a second resonator pattern that forms a second resonator having a second coil are formed on the upper surface.
  • the magnetic resin layer may be provided at least between the first coil pattern that forms the first coil and the second coil pattern that forms the second coil. Good (claim 8).
  • a cavity disposed between the first coil pattern and the second coil pattern may be provided in the multilayer substrate, and the cavity may be filled with a magnetic resin.
  • a mask layer provided on a main surface of the multilayer substrate provided with the magnetic resin layer may be further provided, and the mask layer may be provided so as to surround the magnetic resin layer ( Claim 10).
  • the magnetic resin layer may be formed of a plurality of layers having different magnetic permeability (claim 11).
  • the magnetic resin layer is provided on at least one main surface of the multilayer substrate formed by firing the laminated ceramic green sheets. That is, a multilayer substrate is formed by firing as a dielectric ceramic layer, and a magnetic resin layer is provided on at least one main surface of the formed multilayer substrate. Since there is no need to stack layers together and fire simultaneously, there may be warping, waviness, distortion, cracking, space, etc. due to heat during firing at the boundary between the multilayer substrate and the magnetic resin layer The generation of defective products in the manufacturing process can be suppressed. In addition, when a green sheet including a magnetic layer is fired, it is generally fired in an oxidizing atmosphere.
  • the dielectric constant of the multilayer substrate can be easily adjusted by laminating and firing ceramic green sheets having a desired dielectric constant to form a multilayer substrate, and various magnetic materials and resin materials can be mixed. Since the magnetic permeability of the magnetic resin layer can be easily adjusted, the magnetic permeability and the dielectric constant can be easily adjusted.
  • the electronic component of the present invention further includes a coil pattern forming a coil, and the coil pattern is formed so that a part of the magnetic field generated from the coil passes through the magnetic layer.
  • the inductance of the coil can be easily adjusted without changing the coil pattern by adjusting the magnetic permeability of the magnetic resin layer. Further, by adjusting the magnetic permeability of the magnetic resin layer, a large inductance can be obtained even if the coil pattern is reduced, so that the electronic component can be downsized.
  • the inductance of the coil increases in proportion to the square of the number of turns of the coil in the stacking direction. Since the magnetic flux generated by energizing the pattern is concentrated in the direction along the central axis of the coil, the magnetic resin layer is provided on at least one main surface of the multilayer substrate, so that the direction along the central axis of the coil Since the magnetic flux density of the magnetic flux generated in a concentrated manner can be increased efficiently, the coil inductance can be adjusted and increased more efficiently.
  • the coil pattern is provided in contact with the magnetic resin layer, and the coil inductance can be adjusted more effectively by adjusting the magnetic permeability of the magnetic resin layer.
  • At least a part of the coil pattern is provided inside the magnetic resin layer, and the inductance of the coil is adjusted more effectively by adjusting the magnetic permeability of the magnetic resin layer. can do.
  • the metal film layer is further provided on the main surface of the magnetic resin layer on the side opposite to the multilayer substrate, and the metal film layer overlaps at least a part of the coil pattern in a top view. Therefore, radiation and radiation generated from the coil can be suppressed by grounding the metal film layer.
  • the electronic component of the present invention further includes a resonator pattern that forms a resonator, and resonates without changing the resonator pattern by adjusting the magnetic permeability of the magnetic resin layer.
  • a resonator pattern that forms a resonator, and resonates without changing the resonator pattern by adjusting the magnetic permeability of the magnetic resin layer.
  • the first and second coil patterns forming the first coil and the second coil pattern are electromagnetically coupled to form various filter circuits. Can do.
  • magnetic flux generated in the first coil and the second coil by providing a magnetic resin layer between the first coil pattern forming the first coil and the second coil pattern forming the second coil. Are concentrated on the magnetic resin layer, so that the electromagnetic coupling due to the magnetic flux generated in each coil is inhibited, the electromagnetic coupling between the first coil and the second coil is weakened, and the coupling coefficient becomes small.
  • the coupling coefficient in the electromagnetic coupling between the first coil and the second coil can be easily adjusted only by providing the magnetic resin layer.
  • the cavity arrange
  • the coupling coefficient in the electromagnetic coupling between the first coil and the second coil can be further reduced.
  • the present invention further comprises a mask layer provided on the main surface of the multilayer substrate provided with the magnetic resin layer, and the mask layer is provided so as to surround the magnetic resin layer.
  • a magnetic resin layer is provided on the main surface of the multilayer substrate with a magnetic resin paste or a magnetic resin mold, a desired portion of the main surface of the multilayer substrate ( The magnetic resin layer can be formed at the position).
  • the magnetic resin layer is formed of a plurality of layers having different magnetic permeability, the magnetic permeability of the magnetic resin layer can be adjusted more efficiently. For example, if the magnetic resin layer is formed so that the magnetic permeability of the surface layer is maximized or the magnetic loss is increased, radiation and radiation from the coil can be suppressed. In addition, this effect can be achieved even when there is a single magnetic resin layer. If the magnetic resin layer to be applied is selected to have a high magnetic permeability or a magnetic loss, radiation and radiation from the coil can be achieved. Can be effectively suppressed.
  • FIG. 16 is a diagram showing an equivalent circuit of the multilayer chip type plate resonator element shown in FIG. 15. It is a figure which shows an example of the frequency characteristic of the multilayer chip type
  • FIG. It is a figure which shows the equivalent circuit of the multilayer chip type band pass filter element shown in FIG. It is a figure which shows an example of the frequency characteristic of the multilayer chip type band pass filter element shown in FIG. It is a figure which shows the modification of a coil pattern. It is a figure for demonstrating the effect by providing a magnetic body resin layer in a multilayer substrate. It is a figure which shows the equivalent circuit of the multilayer chip type band pass filter element which is 8th Embodiment of the electronic component of this invention. It is a figure which shows an example of the frequency characteristic of the multilayer chip type band pass filter element shown in FIG. It is a figure which shows the multilayer chip type
  • FIG. 1 is a diagram showing a multilayer chip resonator element 1 according to the first embodiment, in which (a) is a cross-sectional view, and (b) to (f) are respective layers 3 constituting the multilayer chip resonator element 1. 20 to 23 are plan views, and (g) is a bottom view of the wiring layer 24.
  • FIG. FIG. 2 is a diagram showing an equivalent circuit of the resonator circuit 4 provided in the multilayer chip resonator element 1 shown in FIG. 3 to 5 are diagrams showing examples of frequency characteristics of the multilayer chip resonator element 1 shown in FIG.
  • a multilayer chip resonator element 1 includes a multilayer substrate 2 formed by firing laminated ceramic green sheets, and a magnetic body provided on one main surface of the multilayer substrate 2.
  • a resonator circuit 4 (corresponding to the “resonator pattern” of the present invention) formed of a conductor pattern such as Ag or Cu is provided inside the element 1.
  • the multilayer chip resonator element 1 has a width ⁇ length ⁇ height of about 8 mm on top of the multilayer substrate 2 formed in a shape of width ⁇ length ⁇ height of about 8 mm ⁇ 6 mm ⁇ 0.5 mm.
  • a magnetic resin layer 3 formed in a shape of ⁇ 6 mm ⁇ 0.1 mm is laminated to form a so-called chip-type electronic component.
  • the multilayer substrate 2 includes a coil layer 20, a first capacitor layer 21, a second capacitor layer 22, a third capacitor layer 23, and a wiring layer 24, which are laminated and fired to form an integral dielectric ceramic. It is formed as a layer.
  • the ceramic green sheets forming the layers 20 to 24 are obtained by forming a slurry in which a mixed powder such as alumina and glass is mixed with an organic binder and a solvent into a sheet by a film forming apparatus, and the temperature is higher than about 1000 ° C. The so-called low temperature firing is possible at a low temperature.
  • the ceramic green sheets cut into a predetermined shape are subjected to via formation and various pattern printing using a conductor paste such as Ag or Cu to form the layers 20 to 24.
  • the coil layer 20 is provided with a spiral coil pattern 20a for forming the coil L1.
  • An interlayer connection conductor (via conductor) 20b formed by filling a conductive paste is provided at one end of the coil pattern 20a for connection to the ground electrode G.
  • an interlayer connection conductor 20c having a via structure is provided at the other end of the coil pattern 20a for connection to the electrode pattern 21a forming the capacitor C3.
  • the first capacitor layer 21 is provided with an electrode pattern 21a that forms one electrode of the capacitor C3, and an interlayer connection conductor 21b having a via structure is provided at a predetermined location.
  • the second capacitor layer 22 is provided with an electrode pattern 22a that forms the other electrode of the capacitor C3 and one electrode of the capacitors C1 and C2, and a predetermined location.
  • an interlayer connection conductor 22b having a via structure is provided.
  • the third capacitor layer 23 is provided with an electrode pattern 23a that forms the other electrode of the capacitor C1 and an electrode pattern 23b that forms the other electrode of the capacitor C2.
  • An interlayer connection conductor 23c having a via structure is provided at the location.
  • the third capacitor layer 23 is provided with an interlayer connection conductor 23d for connecting the electrode pattern 23a and the input electrode P1, and an interlayer connection conductor 23e for connecting the electrode pattern 23b and the output electrode P2. ing.
  • the wiring layer 24 is provided with an input electrode P1, an output electrode P2, and a ground electrode G.
  • One end of the coil pattern 20a of the coil layer 20 and the ground electrode G are connected via interlayer connection conductors 20b, 21b, 22b, and 23c.
  • the other end of the coil pattern 20a of the coil layer 20 and the electrode pattern 21a of the first capacitor layer 21 are connected via an interlayer connection conductor 20c.
  • the electrode pattern 23a of the third capacitor layer 23 and the input electrode P1 are connected via an interlayer connection conductor 23d, and the electrode pattern 23b of the third capacitor layer 23 and the output electrode P2 are connected via an interlayer connection conductor 23e.
  • a resonator circuit 4 is formed.
  • the magnetic resin layer 3 is formed of, for example, a thermosetting resin, and various magnetic materials are mixed into the resin so that the magnetic resin layer 3 is desired. Is formed so as to have a magnetic permeability ⁇ r.
  • the thermosetting resin include an epoxy resin, a phenol resin, and a cyanate resin.
  • the magnetic permeability ⁇ r represents the relative magnetic permeability
  • the dielectric constant ⁇ r represents the relative dielectric constant
  • the multilayer chip resonator element 1 of this embodiment is manufactured by first forming the multilayer substrate 2 by low-temperature firing, and providing the magnetic resin layer 3 on one main surface of the formed multilayer substrate 2.
  • via holes are formed in a green sheet formed in a predetermined shape with a laser or the like and filled with a conductive paste to form via holes (via conductors) for interlayer connection.
  • a conductive paste such as Ag or Cu
  • a predetermined pattern is printed, and five green sheets for forming the respective layers 20 to 24 constituting the multilayer substrate 2 are prepared.
  • Each green sheet is provided with a plurality of electrode patterns so that a large number of multilayer substrates 2 can be formed at a time.
  • the layers 20 to 24 are laminated to form a laminate.
  • grooves for dividing the individual multilayer substrates 2 after firing are formed so as to surround the regions of the individual multilayer substrates 2.
  • the multilayer body 2 is fired at a low temperature while being pressed to form an aggregate of the multilayer substrates 2.
  • the multilayer chip resonator element 1 is completed by being divided into individual electronic components.
  • the size of the inductance L is generally proportional to the size of the magnetic permeability ⁇ r. Therefore, if the magnetic permeability ⁇ r of the member around the coil is increased, the inductance L is increased, and thereby the resonance frequency of the resonance frequency f is decreased.
  • FIG. 3 is a diagram showing the frequency characteristics of the multilayer chip resonator element 1 and the frequency characteristics of the resonator circuit 4 formed by the multilayer substrate 2 in a state where the magnetic resin layer 3 is not provided.
  • the upper curve in the figure shows a reflection characteristic which is a power ratio between a signal input to the input electrode P1 and a reflected signal reflected inside the resonator circuit 4 and returning to the input electrode P1 (hereinafter referred to as “reflection”). Called “characteristics”).
  • the lower curve in the figure shows a pass characteristic that is a power ratio between the signal input to the input electrode P1 and the signal output from the output electrode P2 (hereinafter referred to as “pass characteristic”).
  • the dotted curve indicates the frequency characteristics of the resonator circuit 4 by the multilayer substrate 2 in the state where the magnetic resin layer 3 is not provided, and the solid curve indicates the multilayer chip resonator element 1.
  • the frequency characteristic is shown, and the peak in the pass characteristic is the resonance frequency of the multilayer chip resonator element 1.
  • the multilayer substrate 2 is formed so that the dielectric constant ⁇ r is 6 and the magnetic permeability ⁇ r of the magnetic resin layer 3 is 2.
  • the multilayer substrate 2 is configured so that the magnetic permeability ⁇ r is 1.
  • the resonance frequency f of the multilayer chip resonator element 1 provided with the magnetic resin layer 3 moves to the low frequency side.
  • FIG. 4 shows the frequency characteristics of the multilayer chip resonator element 1 when the magnetic permeability ⁇ r of the magnetic resin layer 3 is changed.
  • the upper curve shows the reflection characteristics and the lower curve passes. Show properties.
  • the rightmost curve in the figure shows an example when the magnetic permeability of the magnetic resin layer 3 is configured to be 1, and hereinafter, the permeability of the magnetic resin layer 3 in order toward the low frequency side.
  • An example is shown in which the magnetic susceptibility ⁇ r is configured to be 2, 4, 8, and 16.
  • the resonance frequency f of the multilayer chip resonator element 1 moves to the lower frequency side.
  • FIG. 5 shows the frequency characteristics of the multilayer chip resonator element 1 when the thickness of the magnetic resin layer 3 is changed.
  • the upper curve shows the reflection characteristics, and the lower curve shows the pass characteristics. Show.
  • the rightmost curve in the figure shows an example when the magnetic resin layer 3 is not provided.
  • the thickness of the magnetic resin layer 3 is 0.05 mm and 0.1 mm in order toward the low frequency side. , 0.2 mm, 0.4 mm, and 1.0 mm.
  • the amount of magnetic field generated in the coil L1 leaks outside the magnetic resin layer 3 as the thickness of the magnetic resin layer 3 increases, so that the multilayer chip resonator element
  • the resonance frequency f of 1 moves to the low frequency side.
  • the frequency characteristics of the multilayer chip resonator element 1 can be easily adjusted.
  • FIG. 6A and 6B are diagrams showing modifications of the shape of the coil pattern, in which FIG. 6A shows a meander-shaped coil pattern 20d, FIG. 6B shows a line-shaped coil pattern 20e, and FIG. 6C shows a spiral-shaped coil pattern.
  • the coil pattern 20f is shown.
  • the spiral coil pattern 20a is formed on one surface of the coil layer 20.
  • the coil pattern 20d may be formed in the meander shape shown in FIG.
  • the coil pattern 20e may be formed in the line shape shown, or the coil pattern may be formed in the spiral shape shown in FIG.
  • FIG. 7 is a view showing a modification of the structure of the coil pattern 20 d, wherein (a) is a cross-sectional view of the multilayer chip resonator element 1, and (b) is a plan view of the coil layer 20.
  • the magnetic resin layer 3 may be filled between the coil patterns 20a by forming the coil pattern 20d in a convex shape on one surface of the coil layer 20. .
  • FIG. 8A and 8B are views showing a modification of the structure of the coil pattern 20d, where FIG. 8A is a cross-sectional view of the multilayer chip resonator element 1, and FIG. 8B is a plan view of the coil layer 20.
  • FIG. 8A the coil pattern 20d is formed so as to be buried in one surface of the coil layer 20, so that a ceramic layer as a dielectric is filled between the coil patterns 20a. Also good.
  • FIG. 9 is a diagram showing an example in which a mask layer 5 is provided, where (a) is a cross-sectional view of the multilayer chip resonator element 1, (b) is a plan view of (a), and (c) is a mask layer.
  • FIG. 9 is a diagram showing an example in which a mask layer 5 is provided, where (a) is a cross-sectional view of the multilayer chip resonator element 1, (b) is a plan view of (a), and (c) is a mask layer.
  • a mask layer 5 may be provided on the main surface of the multilayer substrate 2 provided with the magnetic resin layer 3 so as to surround the magnetic resin layer 3.
  • the mask layer 5 may be formed of the same material as the ceramic constituting the multilayer substrate 2. That is, when the multilayer substrate 2 is formed, the mask layer 5 can be provided by further laminating and firing a green sheet processed as the mask layer 5.
  • the mask layer 5 is provided so that the main surface of the multilayer substrate 2 may surround the magnetic body resin layer 3, it is multilayered by the magnetic body resin paste which has fluidity
  • the magnetic resin layer 3 can be formed at a predetermined position on the main surface of the multilayer substrate 2 by filling the mask layer 5 with a paste or a mold. It is possible to prevent the dripping from the edge of the main surface.
  • the shape of the mask layer 5 may be any shape as long as it surrounds the coil pattern 20d in a top view.
  • the mask layer is formed as a mask layer 5a shown in FIG. It may be configured.
  • FIG. 10A is a sectional view of the multilayer chip resonator element 1, and FIG. The frequency characteristics of the multilayer chip resonator element 1 at this time are shown, with the upper curve showing the reflection characteristics and the lower curve showing the pass characteristics.
  • the coil pattern 20 d is provided in the vicinity of the interface between the multilayer substrate 2 and the magnetic resin layer 3 and inside the multilayer substrate 2.
  • the resonance frequency f of the multilayer chip resonator element 1 moves to the low frequency side.
  • the rightmost curve in the figure shows an example when the magnetic resin layer 3 is not provided.
  • the coil pattern 20d has a depth of 0.025 mm from the interface in order toward the low frequency side. An example in which the coil pattern 20d is provided at a depth of 0.0125 mm from the interface and an example in which the coil pattern 20d is provided at the interface are shown.
  • the environmental resistance (durability) of the coil pattern 20d is improved and the coil pattern 20d is arranged in the vicinity of the coil pattern 20d.
  • the resonance frequency can be finely adjusted by the magnetic resin layer 3.
  • FIG. 11 is a diagram showing an example in which the layer provided with the coil pattern 20d is different.
  • (A) is a cross-sectional view of the multilayer chip resonator element 1, and (b) the coil pattern 20d is placed inside the magnetic resin layer 3.
  • the frequency characteristic of the multilayer chip resonator element 1 when provided is shown, the upper curve shows the reflection characteristic, and the lower curve shows the pass characteristic.
  • the coil pattern 20 d is provided in the vicinity of the interface between the multilayer substrate 2 and the magnetic resin layer 3 and inside the magnetic resin layer 3.
  • the resonance frequency f of the multilayer chip resonator element 1 can be moved to the lower frequency side.
  • the rightmost curve in the figure shows an example when the magnetic resin layer 3 is not provided.
  • the coil pattern 20d is provided at the interface in the order toward the low frequency side, the coil An example in which the pattern 20d is provided at a height of 0.0125 mm from the interface is shown.
  • the multilayer substrate 2 is formed as a dielectric ceramic layer by firing the laminated ceramic green sheets, and the magnetic resin layer 3 is formed on one main surface of the formed multilayer substrate 2. Since the electronic component having the magnetic resin layer 3 provided on the main surface of the multilayer substrate 2 is formed, the dielectric ceramic layer and the magnetic ceramic layer are laminated and integrated as in the past. There is no need for simultaneous firing, and there is no possibility of warping, undulation, distortion, cracking, space, or the like caused by heat during firing at the boundary between the multilayer substrate 2 and the magnetic resin layer 3, so in the manufacturing process Generation of defective products can be suppressed.
  • the dielectric constant of the multilayer substrate 2 can be easily adjusted by laminating and firing ceramic green sheets having a desired dielectric constant to form the multilayer substrate 2, and various magnetic materials and resin materials can be mixed.
  • the magnetic permeability ⁇ r of the magnetic resin layer 3 can be easily adjusted, so that the magnetic permeability ⁇ r and the dielectric constant ⁇ r can be easily adjusted.
  • the inductance L of the coil can be easily adjusted without changing the coil patterns 20a, 20d, 20e, and 20f by adjusting the magnetic permeability ⁇ r of the magnetic resin layer 3. Further, by adjusting the magnetic permeability ⁇ r of the magnetic resin layer 3, a large inductance L can be obtained even if the coil patterns 20a, 20d, and 20e are reduced.
  • the electronic component can be downsized.
  • the magnetic permeability ⁇ r of the magnetic resin layer 3 is adjusted, so that the coil inductance L is more effectively adjusted. be able to.
  • the resonance frequency f of the resonator circuit 4 can be easily adjusted without changing the circuit pattern of the resonator circuit 4 by adjusting the magnetic permeability ⁇ r of the magnetic resin layer 3. Further, by adjusting the magnetic permeability ⁇ r of the magnetic resin layer 3, a desired resonance frequency f can be obtained even if the circuit pattern forming the resonator circuit 4 is reduced. 1 can be reduced in size.
  • the coil pattern when a coil having a large inductance L is required, in order to form a coil having a desired inductance L, the coil pattern must be formed in a necessary length and shape.
  • the inductance L of the coil can be increased by the magnetic resin layer 3, so that the coil having a large inductance L inside the electronic component can be obtained.
  • the height of the electronic component can be reduced.
  • FIGS. 12A and 12B are diagrams showing a multilayer chip type bandpass filter element 100 according to the second embodiment, in which FIG. 12A is a cross-sectional view, and FIGS. 12B to 10K are layers constituting the multilayer chip type bandpass filter element 100.
  • FIG. 3 is a plan view of 103, 120-128.
  • FIG. 13 is a diagram showing an equivalent circuit of the band pass filter circuit 104 provided in the multilayer chip type band pass filter element 100 shown in FIG.
  • FIG. 14 is a diagram showing an example of frequency characteristics of the multilayer chip type bandpass filter element 100 shown in FIG.
  • the second embodiment is different from the first embodiment in that the circuit configuration provided in the multilayer chip type bandpass filter (BPF) element 100 is different as shown in FIGS. . Since the other configuration is the same as that of the first embodiment, description of the configuration is omitted by assigning a corresponding symbol.
  • BPF bandpass filter
  • a multilayer chip type BPF element 100 includes a multilayer substrate 102 formed by firing laminated ceramic green sheets, and a magnetic resin provided on one main surface of the multilayer substrate 102. As shown in FIG. 13, a band pass filter circuit 104 formed of a conductor pattern such as Ag or Cu is provided therein.
  • the multilayer chip type BPF element 100 is formed as a so-called chip type electronic component having a width ⁇ length ⁇ height of about 1.0 mm ⁇ 0.5 mm ⁇ 0.3 mm.
  • the multilayer substrate 102 includes a first coil layer 120, a connection layer 121, a second coil layer 122, an insulator (dielectric) layer 123, a first capacitor layer 124, a second capacitor layer 125, and a third capacitor layer.
  • the capacitor layer 126, the wiring layer 127, and the dielectric layer 128 are laminated and fired to form a single body.
  • Each of the layers 120 to 128 is formed of a ceramic green sheet similar to the ceramic green sheet described in the first embodiment.
  • the multilayer substrate 102 has a dielectric constant ⁇ r of 60. Has been.
  • the first coil layer 120 is provided with a pair of left and right coil patterns 120a that form the coil L11.
  • the other end of each of the coil patterns 120a is connected to the one end 122b of each of the pair of left and right coil patterns 122a formed on the second coil layer 122 and the interlayer connection conductors 121a and 121b having a via structure provided symmetrically to the connection layer 121.
  • One end 120b of the left coil pattern 120a is connected to the input electrode P11 which is an external electrode
  • one end 120c of the right coil pattern 120a is connected to the output electrode P12 which is an external electrode.
  • connection layer 121 is connected to the other end of each of the two coil patterns 120 a of the first coil layer 120 and one end 122 b of the two coil patterns 122 a of the second coil layer 122.
  • Interlayer connection conductors 121a and 121b having a via structure are provided.
  • the second coil layer 122 is provided with line-shaped coil patterns 122a forming the coil L12 symmetrically.
  • One end 122b of the coil pattern 122a is connected to the other end of each coil pattern 120a formed on the left and right sides of the first coil layer 120 via the interlayer connection conductors 121a and 121b, and the other end of each coil pattern 122a.
  • 122c is connected to the ground electrode G of the wiring layer 127 via an external electrode.
  • the insulator layer 123 is provided to adjust the interval between the electrode patterns.
  • the first capacitor layer 124 is provided with an electrode pattern 124a, and the electrode pattern 124a and the electrode patterns 125a and 125b provided on the second capacitor layer 125 are used.
  • a capacitor C11 is formed.
  • the second capacitor layer 125 includes electrode patterns 125a and 125b for forming the capacitor C11, one electrode pattern 125a for forming one electrode of the capacitor C12, and one of the capacitor C13.
  • the electrode pattern 125b for forming the electrode is provided.
  • the electrode pattern 125a is connected to the input electrode P11 that is an external electrode
  • the electrode pattern 125b is connected to the output electrode P12 that is an external electrode.
  • the third capacitor layer 126 is provided with an electrode pattern 126a that forms the other electrode of the capacitor C12 and an electrode pattern 126b that forms the other electrode of the capacitor C13.
  • the electrode patterns 126a and 126b are connected to the ground electrode G of the wiring layer 127 via external electrodes, respectively.
  • the wiring layer 127 is provided with a ground electrode G. Then, the ground electrode G is connected to the other end 122c of the coil pattern 122a of the second coil layer 122 shown in FIG. 12 (e) via the external electrode and the electrode of the third capacitor layer 126 shown in FIG. 12 (i).
  • the band-pass filter circuit 104 is formed by connecting the patterns 126a and 126b. Further, as shown in FIG. 12 (k), the insulator layer 123 is provided to adjust the interval between the electrode patterns.
  • the magnetic resin layer 103 is formed of a magnetic resin similar to the magnetic resin described in the first embodiment.
  • the multilayer chip type BPF element 100 is manufactured by a method similar to the manufacturing method described in the first embodiment.
  • FIG. 14 is a diagram showing the frequency characteristics of the multilayer chip type BPF element 100.
  • the upper curve shows the reflection characteristics
  • the lower curve shows the pass characteristics.
  • the two curves on the right side indicate the frequency characteristics depending on the presence or absence of the magnetic resin layer 103
  • the two curves on the left side indicate the magnetic resin layer 3.
  • the frequency characteristic by the change of thickness is shown.
  • the magnetic resin layer 3 is configured such that the permeability ⁇ r is 1 and the thickness is 0.1 mm. Also, among the two curves on the right side of the figure, the right side shows an example when the magnetic resin layer 103 is not provided, and the left side shows an example when the magnetic resin layer 103 is provided. . As shown in the figure, the resonance frequency f of the multilayer chip type BPF element 100 provided with the magnetic resin layer 103 moves to the low frequency side.
  • the magnetic resin layer 103 having a permeability ⁇ r of 20 is provided on the multilayer substrate 102.
  • the right side shows an example when the thickness of the magnetic resin layer 103 is 0.05 mm
  • the left side shows an example when the thickness of the magnetic resin layer 103 is 0.1 mm. Indicates.
  • the resonance frequency f of the multilayer chip type BPF element 100 moves to the lower frequency side.
  • FIGS. 203 and 220 are plan views
  • (d) is a bottom view of the wiring layer 221.
  • FIG. FIG. 16 is a diagram showing an equivalent circuit of the resonator circuit 204 provided in the multilayer chip type plate resonator element 200 shown in FIG. 17 and 18 are diagrams showing an example of frequency characteristics of the multilayer chip type plate resonator element 200 shown in FIG.
  • the third embodiment differs from the first and second embodiments in that the circuit configuration provided inside the multilayer chip type plate resonator element 200 is different as shown in FIGS. .
  • the multilayer chip type plate resonator element 200 in this embodiment is configured as a distributed constant type resonator having a line length corresponding to a wavelength corresponding to a frequency of a signal to be blocked. Since other configurations are the same as those of the first and second embodiments, description of the configurations is omitted by assigning corresponding reference numerals.
  • a multilayer chip type plate resonator element 200 includes a multilayer substrate 202 formed by firing laminated ceramic green sheets, and a magnetic layer provided on one main surface of the multilayer substrate 202.
  • a resonator circuit 204 formed of a conductor pattern such as Ag or Cu is provided inside.
  • the multilayer chip type plate resonator element 200 has a width ⁇ length ⁇ height of about 8 mm ⁇ 6 mm ⁇ 0.5 mm formed on the top of the multilayer substrate 202 having a width ⁇ length ⁇ height of about 8 mm ⁇ 6 mm ⁇ 0.5 mm.
  • a magnetic resin layer 203 having a shape of 8 mm ⁇ 6 mm ⁇ 0.1 mm is laminated to form a so-called chip-type electronic component.
  • the multilayer substrate 202 is integrally formed as a dielectric ceramic layer by laminating and firing the resonator layer 220, the connection layer 222, and the wiring layer 221.
  • Each layer 220 to 222 is formed of a ceramic green sheet similar to the ceramic green sheet described in the first embodiment.
  • the multilayer substrate 202 has a dielectric constant ⁇ r of 60. Has been.
  • the resonator layer 220 is provided with a resonator pattern 220a and input / output coupling electrodes 220b and 220c.
  • the wiring layer 221 is provided with an input electrode P21, an output electrode P22, and a ground electrode G.
  • the connection layer 222 is provided with interlayer connection conductors 222a and 222b, the input / output coupling electrode 220b and the input electrode P21 are connected via the interlayer connection conductor 222a, and the input / output coupling electrode 220c and the input electrode P22.
  • a resonator circuit 204 having capacitors C21 and C22 and a resonator RF shown in FIG. 16 is formed.
  • the capacitor C21 is a capacitance determined by the interval between the input / output coupling electrode 220b and the resonator pattern 220a
  • the capacitor C22 is a capacitance determined by the interval between the input / output coupling electrode 220c and the resonator pattern 220a.
  • the magnetic resin layer 203 is formed of a magnetic resin similar to the magnetic resin described in the first embodiment.
  • the multilayer chip type plate resonator element 200 is manufactured by a method similar to the manufacturing method described in the first embodiment.
  • FIG. 17 is a diagram showing the frequency characteristics of the multilayer chip type plate resonator element 200 and the frequency characteristics of the resonator circuit 204 by the multilayer substrate 202 in a state where the magnetic resin layer 203 is not provided.
  • the upper curve in the figure shows the reflection characteristics
  • the lower curve in the figure shows the pass characteristics.
  • the dotted curve indicates the frequency characteristics of the resonator circuit 204 by the multilayer substrate 202 in the state where the magnetic resin layer 3 is not provided
  • the solid curve indicates the multilayer chip type plate resonator element 200.
  • the frequency characteristics of are shown.
  • the magnetic material resin layer 203 is configured so that the magnetic permeability ⁇ r is 8.
  • the resonance frequency f of the multilayer chip type plate resonator element 200 provided with the magnetic resin layer 203 moves to the low frequency side.
  • FIG. 18 shows the frequency characteristics of the multilayer chip type plate resonator element 200 when the magnetic permeability ⁇ r of the magnetic resin layer 203 is changed.
  • (A) shows the reflection characteristics
  • (b) shows the passage characteristics. Show properties.
  • the rightmost curve in FIGS. 18 (a) and 18 (b) shows an example when the magnetic permeability ⁇ r of the magnetic resin layer 203 is configured to be 8, and will be directed to the low frequency side hereinafter.
  • the magnetic resin layer 203 is configured so that the magnetic permeability ⁇ r is 16 and 32 in order.
  • the magnetic permeability ⁇ r of the magnetic resin layer 203 can be changed by changing the content of the magnetic powder contained in the magnetic resin layer 203, that is, the ratio between the so-called resin component and the magnetic powder. Therefore, even if the thickness of the magnetic resin layer 203 is the same, the frequency of the resonator can be finely adjusted by changing the magnetic permeability ⁇ r.
  • the resonance frequency f of the multilayer chip type plate resonator element 200 moves to the lower frequency side.
  • FIG. 19 shows a modification of the resonator pattern.
  • FIG. 19A shows a ⁇ / 2 resonator pattern 220d
  • FIG. 19B shows a ⁇ / 4 resonator pattern 220e with one end grounded.
  • FIG. 20 shows a modification of the resonator pattern, in which (a) shows a ring-shaped resonator pattern 220f, (b) shows a circular resonator pattern 220g, and (c) shows a rectangular shape.
  • a resonator pattern 220h is shown.
  • FIG. 21 is a modification of the resonator pattern, and shows a dual mode resonator pattern 220i that forms a band-pass filter by generating two resonance modes.
  • the resonator patterns 220a to 220c are formed in the resonator layer 220, but various resonator patterns shown as modified examples in FIGS. 19 to 21 may be formed instead.
  • FIG. 22A and 22B are views showing a multilayer chip resonator element 1a according to a fourth embodiment of the electronic component of the present invention, in which FIG. 22A is a cross-sectional view and FIG. 22B is a plan view.
  • the fourth embodiment is different from the first embodiment in that a metal film layer 6 is further provided on the upper surface of the magnetic resin layer 3 as shown in FIG. Since the other configuration is the same as that of the first embodiment, description of the configuration is omitted by attaching the same reference numerals.
  • the metal film layer 6 is provided so as to overlap with at least a part of the coil pattern 20a in a top view.
  • the metal film layer 6 and the ground electrode G are connected by an interlayer connection conductor 6a having a via structure.
  • the generated magnetic field is radiated to the outside of the electronic component, so that other electronic components arranged close to the electronic component There is a risk of interfering with an electronic component and changing the characteristics of the component.
  • the characteristics of the coil or resonator provided in the electronic component may change.
  • the metal film layer 6 is provided on the upper surface of the magnetic resin layer 3 so as to overlap at least a part of the coil pattern 20a in a top view, the metal film layer 6 is grounded. Thus, radiation and radiation generated from the coil can be suppressed. In addition, it is possible to suppress a change in circuit pattern characteristics caused by a magnetic field entering from the outside.
  • FIG. 23 is a view showing a fifth embodiment of the electronic component of the present invention.
  • the fifth embodiment is different from the first to fourth embodiments in that the magnetic resin layer 303 is formed of two layers having different magnetic permeability ⁇ r as shown in FIG. Since other configurations are the same as those of the first to fourth embodiments, description of the configurations will be omitted by attaching corresponding reference numerals.
  • the electronic component 300 of this embodiment includes a multilayer substrate 302 and a magnetic resin layer 303.
  • the magnetic resin layer 303 is composed of two layers 303b and 303a having different magnetic permeability ⁇ r.
  • the magnetic resin layer 303 is formed by a plurality of layers 303a and 303b having different magnetic permeability ⁇ r, thereby further improving the efficiency.
  • the magnetic permeability ⁇ r of the magnetic resin layer 303 can be adjusted well. For example, it is possible to suppress radiation and radiation from the coil by increasing the magnetic permeability ⁇ r of the layer 303b or increasing the magnetic loss.
  • the magnetic resin layer 303 is formed by the two layers 303a and 303b.
  • the magnetic resin layer 303 may be configured by increasing the number of layers having different magnetic permeability ⁇ r. Good.
  • FIG. 24 is an enlarged view of an essential part of the sixth embodiment of the electronic component of the present invention.
  • FIG. 25 is a diagram showing an example of the relationship between the number of turns of the helical coil and the inductance.
  • FIG. 26 is a diagram illustrating an example of the relationship between the number of turns of the helical coil and the Q value.
  • the sixth embodiment differs from the first embodiment in that coil patterns 420a to 422a forming a coil L41 are helical in the stacking direction of the multilayer substrate 402 forming the electronic component 400. It is the point formed in the shape. Since the other configuration is the same as that of the first embodiment, description of the configuration is omitted by assigning a corresponding symbol.
  • an electronic component 400 includes a multilayer substrate 402 formed by firing laminated ceramic green sheets, and various filter circuits (inside with a conductive pattern such as Ag or Cu) ( (Not shown) is provided.
  • the multilayer substrate 402 includes first to third coil layers 420 to 422, a first to third coil layers 420 to 422, a connection layer (not shown), an insulator (dielectric) layer, a capacitor layer, and a wiring.
  • the layers are integrally formed by laminating and firing.
  • Each layer forming the multilayer substrate 402 is formed of a ceramic green sheet similar to the ceramic green sheet described in the first embodiment.
  • the first to third coil layers 420 to 422 are provided with substantially U-shaped coil patterns 420a to 422a that form the coil L41.
  • the first to third coil layers 420 to 422 are laminated so that the directions of the openings of the substantially U-shaped coil patterns 420a to 422a provided in the first to third coil layers 420 to 422 are alternately opposite to each other.
  • one end 420b of the coil pattern 420a provided in the first coil layer and one end 421b of the coil pattern 421a provided in the second coil layer are connected by an interlayer connection conductor 420c having a via structure, and other than the coil pattern 421a.
  • the end 421c and the other end 422b of the coil pattern 422a provided on the third coil layer 422 are connected by an interlayer connection conductor 421d having a via structure, thereby forming a helical coil L41.
  • the electronic component 400 is manufactured by a method similar to the manufacturing method described in the first embodiment. Moreover, the coil L41 which has arbitrary turns can be easily formed by laminating
  • FIG. 25 is a diagram showing an example of the relationship between the number of turns of the coil L41 and the inductance
  • shows the relationship between the number of turns of the coil L41 and the inductance when the magnetic resin layer is not provided on the multilayer substrate.
  • the relationship between the number of turns of the coil L41 and the inductance when it is applied is shown.
  • the inductance of the coil L41 increases in proportion to the square of the number of turns of the coil L41. Further, if the magnetic permeability ⁇ r of the magnetic resin layer provided on the multilayer substrate is increased, the inductance of the coil L41 increases.
  • FIG. 26 is a diagram showing an example of the relationship between the number of turns of the coil L41 and the Q value, and ⁇ shows the relationship between the number of turns of the coil L41 and the Q value when the magnetic resin layer is not provided on the multilayer substrate.
  • the relationship between the number of turns of the coil L41 and the Q value when provided on the substrate is shown.
  • the Q value of the coil L41 increases. Further, if the magnetic permeability ⁇ r of the magnetic resin layer provided on the multilayer substrate is increased, the Q value of the coil L41 increases.
  • the same effects as in the first embodiment can be obtained.
  • the coil patterns 420a to 422a are formed in a helical shape in the stacking direction of the multilayer substrate 402, the inductance of the coil L41 increases in proportion to the square of the number of turns of the coil L41 in the stacking direction. Magnetic flux generated by energizing 420a to 422a is concentrated in the direction along the central axis of the coil L41. Therefore, by providing the magnetic resin layer on at least one main surface of the multilayer substrate 402, the magnetic flux density of the magnetic flux generated in a concentrated manner in the direction along the central axis of the coil L41 can be efficiently increased. The inductance of the coil L41 can be adjusted and increased more efficiently. Further, the Q value of the coil L41 can be efficiently increased by forming the magnetic resin layer with a material having a small magnetic loss.
  • the stray capacitance generated in the coil patterns 420a to 422a forming the coil L41 is affected by the dielectric constant ⁇ r of the magnetic resin layer. Since the coil patterns 420a to 422a are provided in the stacking direction on the multilayer substrate 402, the coil pattern 420a on the uppermost surface side or the coil pattern 422a on the lowermost surface side is most affected by the magnetic resin layer.
  • the magnetic resin layer is provided on one main surface of the multilayer substrate 402 formed so that the coil L41 has a predetermined characteristic, the floating generated in a part of the coil patterns 420a to 422a forming the coil L41. Since only the capacitance is affected only by the dielectric constant ⁇ r of the magnetic resin layer, the characteristics of the coil L41 are not greatly influenced by the dielectric constant ⁇ r of the magnetic resin layer, so the design range of the magnetic resin layer is expanded, The range of selection of materials such as magnetic powder and resin for forming the magnetic resin layer can be expanded.
  • various electronic circuits such as a resonator circuit, a filter circuit, a balun circuit, a directional coupler, and an antenna circuit are electronically converted using the helical coil L41. It may be formed in the part 400.
  • FIG. 27 is a view showing a multilayer chip type bandpass filter element 500 according to the seventh embodiment, wherein (a) is a cross-sectional view, and (b) to (j) are each layer constituting the multilayer chip type bandpass filter element 500.
  • 5 is a plan view of 503 and 520 to 527.
  • FIG. FIG. 28 is a diagram showing an equivalent circuit of the band-pass filter circuit 504 provided in the multilayer chip type band-pass filter element 500 shown in FIG.
  • the seventh embodiment is different from the first embodiment in that the circuit configuration provided in the multilayer chip type bandpass filter (BPF) element 500 is different as shown in FIGS. .
  • BPF bandpass filter
  • the first resonator pattern forming the first resonator circuit 504a having the first coil L51 and the second resonator circuit 504b having the second coil L52 are formed. Are arranged side by side on the multilayer substrate 502 in a top view.
  • the magnetic resin layer 503 is provided at least between the first coil pattern 520a that forms the first coil L51 and the second coil pattern 520b that forms the second coil L52. Since the other configuration is the same as that of the first embodiment, description of the configuration is omitted by assigning a corresponding symbol.
  • a multilayer chip type BPF element 500 includes a multilayer substrate 502 formed by firing laminated ceramic green sheets, and a magnetic resin provided on one main surface of the multilayer substrate 502. As shown in FIG. 28, a band-pass filter circuit 504 formed of a conductor pattern such as Ag or Cu is provided therein.
  • the band-pass filter circuit 504 of this embodiment includes a first coil pattern 520a of the first coil L51 and a second coil pattern 520b of the second coil L52 that the first resonator circuit 504a and the second resonator circuit 504b have, respectively. Are formed by electromagnetic coupling.
  • the multilayer substrate 502 includes a first coil layer 520, a first connection layer 521, a first capacitor layer 522, a second capacitor layer 523, a second connection layer 524, a third capacitor layer 525, and a wiring layer 526. And an insulating (dielectric) layer 527 are laminated and fired to form a single body.
  • Each of the layers 520 to 527 is formed of a ceramic green sheet similar to the ceramic green sheet described in the first embodiment.
  • the first coil layer 520 is provided with a substantially L-shaped first coil pattern 520a that forms the coil L51 and a second coil pattern 520b that forms the coil L52. It has been. Then, one end of the coil pattern 520a is provided with the electrode pattern 523a of the second capacitor layer 523 and the electrode pattern 525a of the third capacitor layer 525, and the first connection layer 521, the first capacitor layer 522, and the second connection layer 524.
  • An interlayer connection conductor 520c having a via structure is provided.
  • the coil pattern 520b has one end through the electrode pattern 523b of the second capacitor layer 523 and the electrode pattern 525b of the third capacitor layer 525, and the first connection layer 521, the first capacitor layer 522, and the second connection layer 524.
  • An interlayer connection conductor 520d having a via structure is provided. The other end of each of the coil pattern 520a and the coil pattern 520b is connected to a ground electrode that is an external electrode.
  • the first connection layer 521 includes one end of the first coil pattern 520a of the first coil layer 520, the electrode pattern 523a of the second capacitor layer 523, and the third capacitor layer 525.
  • An interlayer connection conductor 521a having a via structure for connecting to the electrode pattern 525a is provided.
  • one end of the second coil pattern 520b of the first coil layer 520, the electrode pattern 523b of the second capacitor layer 523, and the electrode pattern 525b of the third capacitor layer 525 are connected to the first connection layer 521.
  • An interlayer connection conductor 521b having a via structure is provided.
  • the first capacitor layer 522 is provided with an electrode pattern 522a that forms the other electrode of the capacitor C52.
  • the electrode pattern 522a and the second capacitor layer 523 are provided.
  • a capacitor C52 is formed by the electrode pattern 523a.
  • the first capacitor layer 522 is provided with an electrode pattern 522b that forms the other electrode of the capacitor C54.
  • the capacitor C54 is formed by the electrode pattern 522b and the electrode pattern 523b provided on the second capacitor layer 523. It is formed. Electrode pattern 522a and electrode pattern 522b are each connected to a ground electrode which is an external electrode.
  • the first capacitor layer 522 is connected to one end of the first coil pattern 520a of the first coil layer 520, the electrode pattern 523a of the second capacitor layer 523, and the electrode pattern 525a of the third capacitor layer 525.
  • An interlayer connection conductor 522c having a via structure is provided.
  • the first capacitor layer 522 is connected to one end of the second coil pattern 520b of the first coil layer 520, the electrode pattern 523b of the second capacitor layer 523, and the electrode pattern 525b of the third capacitor layer 525.
  • An interlayer connection conductor 522d having a via structure is provided.
  • the second capacitor layer 523 is provided with an electrode pattern 523a for forming one electrode of the capacitor C52 and an electrode pattern 523b for forming one electrode of the capacitor C54. ing.
  • the second connection layer 524 includes one end of the first coil pattern 520a of the first coil layer 520, the electrode pattern 523a of the second capacitor layer 523, and the third capacitor layer 525.
  • An interlayer connection conductor 524a having a via structure for connecting to the electrode pattern 525a is provided.
  • the second connection layer 524 is connected to one end of the second coil pattern 520b of the first coil layer 520, the electrode pattern 523b of the second capacitor layer 523, and the electrode pattern 525b of the third capacitor layer 525.
  • An interlayer connection conductor 524b having a via structure is provided.
  • the third capacitor layer 525 is provided with an electrode pattern 525a that forms one electrode of the capacitor C51, and is provided in the electrode pattern 525a and the wiring layer 526.
  • a capacitor C51 is formed by the electrode pattern 526a.
  • the third capacitor layer 525 is provided with an electrode pattern 525b that forms one electrode of the capacitor C53, and the capacitor C53 is formed by the electrode pattern 525b and the electrode pattern 526b provided on the wiring layer 526.
  • the wiring layer 526 is provided with an electrode pattern 526a that forms the other electrode of the capacitor C51 and an electrode pattern 526b that forms the other electrode of the capacitor C53.
  • the electrode pattern 526a is connected to the input electrode P51 which is an external electrode
  • the electrode pattern 526b is connected to the output electrode P52 which is an external electrode, thereby forming a band-pass filter circuit 504.
  • the insulator layer 527 is provided for adjusting the interval between the electrode patterns.
  • the magnetic resin layer 503 is formed of the same magnetic resin as the magnetic resin described in the first embodiment, and the first coil of the first coil layer 520 is formed. It arrange
  • the multilayer chip type BPF element 500 is manufactured by a method similar to the manufacturing method described in the first embodiment.
  • FIG. 29 is a diagram showing an example of frequency characteristics of the multilayer chip type BPF element 500 shown in FIG. 27.
  • c shows the frequency characteristic between the coil L51 and the coil L52.
  • the upper curve indicates the reflection characteristic
  • the lower curve indicates the transmission characteristic.
  • FIG. 30 is a view showing an example of a modification of the coil pattern.
  • FIG. 30A shows the coil patterns 520a and 520b in this embodiment
  • FIG. 30B shows a via structure formed in the stacking direction of the multilayer substrate 502. Coil patterns 520e and 520f are shown.
  • substantially L-shaped coil patterns 520a and 520b are provided side by side in a top view, and a magnetic resin layer is provided between the coil pattern 520a and the coil pattern 520b. 503 is provided.
  • coil patterns 520e and 520f having a via structure provided in the stacking direction of the multilayer substrate 502 may be formed side by side in a top view. And it is good to provide the magnetic body resin layer 503 between the coil pattern 520e and the coil pattern 520f.
  • FIG. 31A and 31B are diagrams for explaining the effect of providing the magnetic resin layer 503 on the multilayer substrate, wherein FIG. 31A is a diagram showing a state of the magnetic flux MF generated by the coil, and FIG. 31B is a magnetic resin layer.
  • FIG. 5C is a diagram illustrating a state in which a magnetic resin layer 503 is provided on a multilayer substrate, and FIG. 5C is a diagram illustrating a change in magnetic flux MF.
  • the magnetic flux MF is generated concentrically around the coil patterns 520e and 520f, and the coil pattern 520e is generated by the magnetic flux MF.
  • 520f is electromagnetically coupled.
  • the magnetic resin layer 503 is provided between the coil patterns 520e and 520f, the magnetic resin layer having a high magnetic permeability for the magnetic flux MF generated by both the coil patterns 520e and 520f. Concentrate on 503.
  • the magnetic flux MF generated between the two coil patterns 520e and 520f moves in the direction of the coil patterns 520e and 520f, respectively, as indicated by arrows in the figure. Therefore, the electromagnetic coupling between the coil patterns 520e and 520f is weakened. As a result, the concentration of the magnetic flux MF on the magnetic resin layer 503 depends on the magnetic permeability ⁇ r of the magnetic resin layer 503. Therefore, by providing the multilayer resin 502 with the magnetic resin layer 503 having different magnetic permeability ⁇ r, the coil The coupling coefficient in the electromagnetic coupling between the patterns 520e and 520f can be adjusted.
  • the same effects as in the first embodiment can be obtained and the following effects can be obtained. That is, as the resonator pattern, the first resonator pattern forming the first resonator circuit 504a having the first coil L51 and the second resonator forming the second resonator circuit 504b having the second coil L52.
  • the first coil pattern 520a that forms the first coil L51 and the second coil pattern 520b that forms the second coil L52 are electromagnetically coupled.
  • Various filter circuits (BPF circuit 504) can be formed.
  • the first coil L51 and the first coil L51 Since the magnetic flux MF generated in the two coils L52 concentrates on the magnetic resin layer 503 having a high permeability ⁇ r, electromagnetic coupling by the magnetic flux MF generated in the coils L51 and L52 is inhibited, and the first coil L51 and the second coil L52 The electromagnetic coupling with the coil L52 is weakened and the coupling coefficient K is reduced.
  • the degree of concentration of the magnetic flux MF on the magnetic resin layer 503 depends on the magnetic permeability ⁇ r of the magnetic resin layer 503, the coupling coefficient K in the electromagnetic coupling between the first coil L51 and the second coil L52 is determined by the magnetic permeability ⁇ r. Adjustment can be made simply by providing different magnetic resin layers 503 on the multilayer substrate 502.
  • the magnetic resin is applied to the multilayer substrate 502 without physically separating the first coil L51 and the second coil L52. Since the electromagnetic coupling can be weakened only by providing the layer 503, the multilayer chip BPF element 500 can be downsized.
  • the leakage current loss can be reduced and the Q value of the coil can be increased (for example, tan ⁇ ⁇ 0.1 of the magnetic resin layer).
  • FIG. 32 is a diagram showing an equivalent circuit of a band-pass filter circuit 604 provided in the multilayer chip type band-pass filter element according to the eighth embodiment of the electronic component of the present invention.
  • the eighth embodiment differs from the seventh embodiment in that the circuit configuration provided in the multilayer chip type bandpass filter (BPF) element is different as shown in FIG.
  • the first coil L61 forming the first resonator circuit 604a and the second coil L62 forming the second resonator circuit 604b are coupled by the capacitor C65. Since the other configuration is the same as that of the seventh embodiment, description of the configuration is omitted by assigning a corresponding symbol.
  • FIG. 33 is a diagram showing an example of frequency characteristics of the multilayer chip type bandpass filter element shown in FIG. 32.
  • c shows the frequency characteristic between the coil L61 and the coil L62.
  • the upper curve indicates the reflection characteristic
  • the lower curve indicates the transmission characteristic.
  • the frequency characteristic of the multilayer chip type BPF element 500 changes as the coupling coefficient K in the electromagnetic coupling of the coils L61 and L62 forming the multilayer chip type BPF element 500 changes.
  • this embodiment can achieve the same effects as those of the seventh embodiment.
  • FIG. 34A and 34B are diagrams showing a multilayer chip type bandpass filter element 600 according to the ninth embodiment of the electronic component of the present invention, wherein FIG. 34A is a plan view, FIG. 34B is a cross-sectional view, and FIG. FIG.
  • the ninth embodiment differs greatly from the seventh embodiment in that the first embodiment provided side by side on one main surface of the multilayer substrate 602 as shown in FIGS. 34 (a) and 34 (b).
  • a cavity 610 is provided between the coil pattern 620 a and the second coil pattern 620 b, and the magnetic resin layer 603 is filled in the cavity 610. Since the other configuration is the same as that of the seventh embodiment, description of the configuration is omitted by assigning a corresponding symbol.
  • FIG. 34C shows the frequency characteristics depending on the presence or absence of the magnetic resin layer 603, the upper curve shows the reflection characteristics, and the lower curve shows the pass characteristics.
  • a cavity 610 disposed between the first coil pattern 620a that forms the first coil and the second coil pattern 620b that forms the second coil is provided in the multilayer substrate 602, and the cavity 610 has a magnetic property. Since the body resin layer 603 is filled, the magnetic flux generated in the first coil and the second coil concentrates on the magnetic body resin layer 603 filled in the cavity 610, so that the magnetic body resin layer 603 serves as an electromagnetic shield. Since it functions, the coupling coefficient in the electromagnetic coupling between the first coil and the second coil can be further reduced. At this time, by increasing the magnetic permeability ⁇ r of the magnetic resin layer 603, the electromagnetic coupling between the first coil and the second coil can be substantially eliminated.
  • FIG. 35 to FIG. 39 are views showing modifications of the magnetic resin layer provided on the multilayer substrate, in which (a) of each figure shows a plan view and (b) of each figure shows a sectional view. .
  • the same components as those in the above embodiment are denoted by the same reference numerals, and the description of the components is omitted.
  • the magnetic resin layer 603a is filled by filling the cavity 610 provided on one main surface of the multilayer substrate 602 of the multilayer chip type BPF element 600 so as not to overflow the cavity 610. May be formed.
  • a mask layer 705 is provided on one main surface of the multilayer substrate 702 of the electronic component 700, and the first coil pattern 720a and the second coil pattern 720b are formed in the recess formed by the mask layer 705.
  • the magnetic resin layer 703 may be formed by filling a magnetic resin so that the whole is covered.
  • a mask layer 805 and a cavity 810 disposed between the first coil pattern 820a and the second coil pattern 820b are provided on one main surface of the multilayer substrate 802 of the electronic component 800, and the mask
  • the magnetic resin layer 803 may be formed by filling a concave portion formed by the layer 805 and the cavity 810 with a magnetic resin.
  • the magnetic layer 903 may be formed by providing a mask layer 905 on the main surface and filling a concave portion formed by the mask layer 905 with a magnetic resin.
  • the magnetic resin layer 1003 may be formed by providing a cavity 1010 between the first coil pattern 1020a and the second coil pattern 1020b on the main surface and filling the cavity 1010 with a magnetic resin.
  • the present invention is not limited to the above-described embodiment, and various modifications other than those described above can be made without departing from the spirit thereof, for example, a magnetic material that requires a large inductance. Only the coil pattern for which the effect of the resin layer is desired is placed inside the magnetic resin layer or near the boundary between the magnetic resin layer and the dielectric ceramic layer, and the other coil patterns are arranged on the multilayer substrate (dielectric ceramic layer). You may make it arrange
  • the magnetic resin layer it is desirable to configure the magnetic resin layer so that the magnetic permeability ⁇ r is greater than 1.
  • the particle diameter of the magnetic material constituting the magnetic resin layer may be any size, but in view of the use of electronic components in a higher frequency band, the particle diameter of the magnetic material is 2 ⁇ m or less. It is desirable that Further, by forming a magnetic resin layer with a small magnetic loss, the electronic component can be configured to be more suitable for high frequencies.
  • the magnetic resin layer of the electronic component is provided.
  • An external electrode or the like can be easily formed on the unexposed surface. Therefore, the present invention can be easily applied to surface mount chip components.
  • a magnetic resin layer may be provided on both main surfaces of the multilayer substrate.
  • the present invention can also be applied to a collective substrate such as a module.
  • a collective substrate such as a module.
  • the application of the present invention to a chip-type passive component improves the advantages of the manufacturing method.
  • the characteristics can be improved over the electrical characteristics when the electronic component is formed only of a dielectric layer.
  • a rectangular parallelepiped concave cavity is formed in the multilayer substrate.
  • the shape of the cavity is not limited to the above-described shape, and the cavity may be formed through the multilayer substrate.
  • a cavity may be formed.
  • the present invention can be widely applied to electronic components in which capacitors and coils are provided inside a multilayer substrate.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Filters And Equalizers (AREA)

Abstract

Disclosed is an electronic component with which generation of defective products in the manufacturing process can be suppressed and also with which magnetic permeability and dielectric constant can be readily adjusted. A magnetic resin layer (3) is provided on the main face of a multilayer substrate (2) formed by baking, and therefore there is no need for the unified simultaneous baking of a laminated dielectric ceramic layer and magnetic ceramic layer that is conventionally performed. Also, there is no risk at all of generation of defects at the interface between the multilayer substrate (2) and the magnetic resin layer (3), said defects being caused by heat when baking, and consequently generation of defective products in the manufacturing process can be suppressed. The dielectric constant of the multilayer substrate (2) can be readily adjusted by forming the multilayer substrate (2) by laminating and baking a ceramic green sheet having the desired dielectric constant. Furthermore, the magnetic permeability of the magnetic resin layer (3) can be readily adjusted by mixing various types of magnetic material and resin material, and consequently the magnetic permeability and dielectric constant can be readily adjusted.

Description

電子部品Electronic components
 本発明は、コンデンサやコイルを形成するパターンが内部に設けられた積層型の電子部品に関する。 The present invention relates to a multilayer electronic component in which a pattern for forming a capacitor or a coil is provided.
 従来、積層された磁性体セラミック層および誘電体セラミック層を同時焼成して形成された積層型フィルタとしての電子部品が知られている(例えば、特許文献1参照)。例えば、図40に電子部品の一例として示された積層型フィルタ1500では、導体パターン1513によるコイル層1504が磁性体セラミック層1501の内部に設けられ、2枚以上の内部電極1505~1508が内部に配置されることによりコンデンサが形成された誘電体セラミック層1502,1503が、磁性体セラミック層1501の上下にそれぞれ積層されている。そして、コンデンサとインダクター層1504が外部電極1510,1511に接続されて積層型フィルタ1500が構成されている。 Conventionally, an electronic component as a multilayer filter formed by simultaneously firing a laminated magnetic ceramic layer and a dielectric ceramic layer is known (see, for example, Patent Document 1). For example, in the multilayer filter 1500 shown as an example of the electronic component in FIG. 40, the coil layer 1504 by the conductor pattern 1513 is provided inside the magnetic ceramic layer 1501, and two or more internal electrodes 1505 to 1508 are inside. Dielectric ceramic layers 1502 and 1503 in which capacitors are formed by being disposed are laminated on the upper and lower sides of the magnetic ceramic layer 1501, respectively. A capacitor and inductor layer 1504 is connected to the external electrodes 1510 and 1511 to form a multilayer filter 1500.
 積層型フィルタ1500では、磁性体セラミック層1501を形成する複数の磁性体セラミックグリーンシートと、誘電体セラミック層1502,1503を形成する複数の誘電体セラミックグリーンシートと、所定の配線パターンが形成されたグリーンシートとが積層されることにより多層基板が構成されている。そして、複数のセラミックグリーンシートが積層されて構成された多層基板が1000℃前後で焼成されることにより、積層型フィルタ1500が製造される(所謂、LTCC(Low Temperature Co-fired Ceramic:低温同時焼結セラミック)基板)。なお、図40は従来の電子部品の一例である積層型フィルタ1500を示す図であって、(a)は積層型フィルタ1500の本体を透視して内部構成を示す斜視図であり、(b)は外観を示す斜視図である。 In the multilayer filter 1500, a plurality of magnetic ceramic green sheets for forming the magnetic ceramic layer 1501, a plurality of dielectric ceramic green sheets for forming the dielectric ceramic layers 1502 and 1503, and a predetermined wiring pattern are formed. A multilayer substrate is configured by laminating green sheets. A multilayer substrate composed of a plurality of laminated ceramic green sheets is fired at around 1000 ° C. to produce a multilayer filter 1500 (so-called LTCC (Low Temperature Co-fired Ceramic). Ceramic) substrate). 40 is a view showing a multilayer filter 1500 which is an example of a conventional electronic component, and FIG. 40A is a perspective view showing the internal configuration through the body of the multilayer filter 1500, and FIG. FIG. 2 is a perspective view showing an appearance.
特開2003-69358号公報(段落[0003],[0005]、図9,10など)Japanese Unexamined Patent Publication No. 2003-69358 (paragraphs [0003], [0005], FIGS. 9, 10 and the like)
 ところで、積層型フィルタ1500が同時焼成されるときに、各グリーンシート内に含まれている溶剤やバインダなどが蒸発することにより、磁性体セラミック層1501および誘電体セラミック層1502,1503は収縮するが、異種材料である磁性体セラミック層1501および誘電体セラミック層1502,1503それぞれの収縮量が異なるため、各層1501~1503の境界に応力が生じ易い。したがって、同時焼成された多層基板に反りやうねり、歪み、割れなどが生じるおそれがあり、積層型フィルタ1500の製造過程で、多層基板に反りやうねり、歪み、割れなどが生じると、焼成の後の工程で不具合が生じたり、製造された積層型フィルタ1500が実装されるときの実装不良を招来する。 By the way, when the multilayer filter 1500 is fired at the same time, the magnetic ceramic layer 1501 and the dielectric ceramic layers 1502 and 1503 contract due to evaporation of the solvent and binder contained in each green sheet. Since the magnetic ceramic layer 1501 and the dielectric ceramic layers 1502 and 1503 which are different materials have different shrinkage amounts, stress is likely to be generated at the boundary between the layers 1501 to 1503. Accordingly, there is a possibility that warpage, undulation, distortion, cracking, etc. may occur in the multilayer substrate that has been co-fired. If warping, undulation, distortion, cracking, etc. occur in the multilayer filter 1500 during the manufacturing process, In this process, a defect occurs, or a mounting failure occurs when the manufactured multilayer filter 1500 is mounted.
 また、磁性体セラミック層1501および誘電体セラミック層1502,1503それぞれの収縮量の違いにより、各層1501~1503の境界に空間が形成されて多層基板内部で剥離が生じれば、コイルおよびコンデンサの特性に影響を与える透磁率や誘電率が変化するおそれがある。各層1501~1503の透磁率や誘電率が変化すれば、所望のコイル特性およびコンデンサ特性を得ることができない。 Further, if a space is formed at the boundary between each of the layers 1501 to 1503 due to the difference in shrinkage between the magnetic ceramic layer 1501 and the dielectric ceramic layers 1502 and 1503 and peeling occurs inside the multilayer substrate, the characteristics of the coil and the capacitor There is a possibility that the magnetic permeability and the dielectric constant that affect the resistance change. If the magnetic permeability and dielectric constant of each of the layers 1501 to 1503 change, desired coil characteristics and capacitor characteristics cannot be obtained.
 これらの問題を解決するために、各層1501~1503を構成するセラミックの組成材料を選定して磁性体セラミック層1501および誘電体セラミック層1502,1503の熱収縮量をほぼ同じにすることも考えられる。しかし、この場合、各層1501~1503を構成するセラミックの組成材料が限定されるため、磁性体セラミック層1501の透磁率および誘電体セラミック層1502,1503の誘電率の選択範囲が大幅に狭くなる。したがって、所望の特性を有する積層型フィルタ1500が得られなかったり、所望の特性を得られたとしても、積層型フィルタ1500のサイズが大きくなるといった問題が生じていた。 In order to solve these problems, it is conceivable that the ceramic material constituting each of the layers 1501 to 1503 is selected so that the thermal contraction amounts of the magnetic ceramic layer 1501 and the dielectric ceramic layers 1502 and 1503 are substantially the same. . However, in this case, since the ceramic composition material constituting each of the layers 1501 to 1503 is limited, the selection range of the magnetic permeability of the magnetic ceramic layer 1501 and the dielectric constant of the dielectric ceramic layers 1502 and 1503 is significantly narrowed. Therefore, there is a problem that the multilayer filter 1500 having desired characteristics cannot be obtained, or even if the desired characteristics are obtained, the size of the multilayer filter 1500 is increased.
 本発明は、上記課題に鑑みてなされたものであり、製造過程における不良品の発生を抑制することができるとともに、透磁率および誘電率を容易に調整することのできる電子部品を提供することを目的とする。 The present invention has been made in view of the above problems, and provides an electronic component capable of suppressing the occurrence of defective products in the manufacturing process and easily adjusting the magnetic permeability and the dielectric constant. Objective.
 上記した目的を達成するために、本発明の電子部品は、積層したセラミックグリーンシートを焼成して形成された多層基板と、前記多層基板の少なくとも一方の主面に設けられた磁性体樹脂層とを備えることを特徴としている(請求項1)。 In order to achieve the above object, an electronic component of the present invention includes a multilayer substrate formed by firing laminated ceramic green sheets, and a magnetic resin layer provided on at least one main surface of the multilayer substrate. (Claim 1).
 また、本発明の電子部品は、コイルを形成するコイルパターンをさらに備えるようにしてもよい(請求項2)。 The electronic component of the present invention may further include a coil pattern that forms a coil (claim 2).
 また、前記コイルパターンは前記多層基板の積層方向にヘリカル状に形成されていてもよい(請求項3)。 The coil pattern may be formed in a helical shape in the stacking direction of the multilayer substrate.
 また、前記コイルパターンは前記磁性体樹脂層と接するように設けられていてもよい(請求項4)。 The coil pattern may be provided in contact with the magnetic resin layer (claim 4).
 また、前記コイルパターンの少なくとも一部は前記磁性体樹脂層の内部に設けらていてもよい(請求項5)。 Further, at least a part of the coil pattern may be provided inside the magnetic resin layer (Claim 5).
 また、前記多層基板と反対側の前記磁性体樹脂層の主面に設けられた金属膜層をさらに備え、前記金属膜層は、上面視において前記コイルパターンの少なくとも一部と重なるように設けられるようにしてもよい(請求項6)。 Further, a metal film layer provided on the main surface of the magnetic resin layer opposite to the multilayer substrate is further provided, and the metal film layer is provided so as to overlap at least a part of the coil pattern in a top view. (Claim 6).
 また、本発明の電子部品は、共振器を形成する共振器パターンをさらに備えるようにしてもよい(請求項7)。 The electronic component of the present invention may further include a resonator pattern that forms a resonator (claim 7).
 また、前記共振器パターンとして、第1コイルを有する第1共振器を形成する第1の共振器パターンと、第2コイルを有する第2共振器を形成する第2の共振器パターンとが、上面視において並べて設けられており、前記磁性体樹脂層は、少なくとも前記第1コイルを形成する第1のコイルパターンと前記第2コイルを形成する第2のコイルパターンとの間に設けられていてもよい(請求項8)。 Further, as the resonator pattern, a first resonator pattern that forms a first resonator having a first coil and a second resonator pattern that forms a second resonator having a second coil are formed on the upper surface. The magnetic resin layer may be provided at least between the first coil pattern that forms the first coil and the second coil pattern that forms the second coil. Good (claim 8).
 また、前記第1のコイルパターンと前記第2のコイルパターンとの間に配置されるキャビティが前記多層基板に設けられており、前記キャビティに磁性体樹脂が充填されていてもよい(請求項9)。 A cavity disposed between the first coil pattern and the second coil pattern may be provided in the multilayer substrate, and the cavity may be filled with a magnetic resin. ).
 また、前記磁性体樹脂層が設けられた前記多層基板の主面に設けられたマスク層をさらに備え、前記マスク層は、前記磁性体樹脂層を囲繞するように設けられるようにしてもよい(請求項10)。 Further, a mask layer provided on a main surface of the multilayer substrate provided with the magnetic resin layer may be further provided, and the mask layer may be provided so as to surround the magnetic resin layer ( Claim 10).
 また、前記磁性体樹脂層は、透磁率の異なる複数の層により形成されていてもよい(請求項11)。 The magnetic resin layer may be formed of a plurality of layers having different magnetic permeability (claim 11).
 請求項1の発明によれば、積層したセラミックグリーンシートを焼成して形成された多層基板の少なくとも一方の主面に磁性体樹脂層が設けられている。すなわち、誘電体セラミック層として多層基板が焼成により形成され、形成された多層基板の少なくとも一方の主面に磁性体樹脂層が設けられているため、従来のように誘電体セラミック層と磁性体セラミック層とを積層して一体的に同時焼成する必要がないため、多層基板と磁性体樹脂層との境界に、焼成するときの熱に起因した反りやうねり、歪み、割れ、空間などが生じるおそれが全くなく、製造過程における不良品の発生を抑制することができる。また、磁性層を含んだグリーンシートを焼成する場合、酸化雰囲気中で焼成することが一般的であるが、その場合、内部に使用する電極は銀等の酸化しにくい金属を使用する必要があるが、本構造においては、焼成後に磁性層を付与するため、内部パターンを形成したグリーンシートを還元雰囲気中でも焼成することができる。そのため、内部電極に銅電極等の酸化し易い金属を用いることも可能である。 According to the invention of claim 1, the magnetic resin layer is provided on at least one main surface of the multilayer substrate formed by firing the laminated ceramic green sheets. That is, a multilayer substrate is formed by firing as a dielectric ceramic layer, and a magnetic resin layer is provided on at least one main surface of the formed multilayer substrate. Since there is no need to stack layers together and fire simultaneously, there may be warping, waviness, distortion, cracking, space, etc. due to heat during firing at the boundary between the multilayer substrate and the magnetic resin layer The generation of defective products in the manufacturing process can be suppressed. In addition, when a green sheet including a magnetic layer is fired, it is generally fired in an oxidizing atmosphere. In this case, it is necessary to use a metal that is difficult to oxidize, such as silver, as an electrode used inside. However, in this structure, since the magnetic layer is provided after firing, the green sheet on which the internal pattern is formed can be fired even in a reducing atmosphere. Therefore, it is also possible to use a metal that is easily oxidized, such as a copper electrode, for the internal electrode.
 また、所望の誘電率を有するセラミックグリーンシートを積層し焼成して多層基板を形成することで多層基板の誘電率を容易に調整でき、また、種々の磁性体材料と樹脂材料とを混合することで磁性体樹脂層の透磁率を容易に調整できるため、透磁率および誘電率を容易に調整することができる。 Moreover, the dielectric constant of the multilayer substrate can be easily adjusted by laminating and firing ceramic green sheets having a desired dielectric constant to form a multilayer substrate, and various magnetic materials and resin materials can be mixed. Since the magnetic permeability of the magnetic resin layer can be easily adjusted, the magnetic permeability and the dielectric constant can be easily adjusted.
 請求項2の発明によれば、本発明の電子部品はコイルを形成するコイルパターンをさらに備えており、このコイルパターンは、コイルから発生する磁界の一部が磁性層中を通るように形成されたコイルパターンであり、磁性体樹脂層の透磁率を調整することでコイルパターンを変更しなくともコイルのインダクタンスを容易に調整できるため実用的である。また、磁性体樹脂層の透磁率を調整することで、コイルパターンを小さくしても、大きなインダクタンスを得ることができるため、電子部品の小型化を図ることができる。 According to the invention of claim 2, the electronic component of the present invention further includes a coil pattern forming a coil, and the coil pattern is formed so that a part of the magnetic field generated from the coil passes through the magnetic layer. This is practical because the inductance of the coil can be easily adjusted without changing the coil pattern by adjusting the magnetic permeability of the magnetic resin layer. Further, by adjusting the magnetic permeability of the magnetic resin layer, a large inductance can be obtained even if the coil pattern is reduced, so that the electronic component can be downsized.
 請求項3の発明によれば、コイルパターンは多層基板の積層方向にヘリカル状に形成されているため、コイルのインダクタンスは積層方向へのコイルの巻き数の二乗に比例して大きくなるが、コイルパターンに通電されることで発生する磁束はコイルの中心軸に沿った方向に集中するため、多層基板の少なくとも一方の主面に磁性体樹脂層を設けることで、コイルの中心軸に沿った方向に集中して発生する磁束の磁束密度を効率よく大きくすることができるので、コイルのインダクタンスをより効率よく調整して大きくすることができる。 According to the invention of claim 3, since the coil pattern is helically formed in the stacking direction of the multilayer substrate, the inductance of the coil increases in proportion to the square of the number of turns of the coil in the stacking direction. Since the magnetic flux generated by energizing the pattern is concentrated in the direction along the central axis of the coil, the magnetic resin layer is provided on at least one main surface of the multilayer substrate, so that the direction along the central axis of the coil Since the magnetic flux density of the magnetic flux generated in a concentrated manner can be increased efficiently, the coil inductance can be adjusted and increased more efficiently.
 請求項4の発明によれば、コイルパターンは磁性体樹脂層と接するように設けられており、磁性体樹脂層の透磁率を調整することでより効果的にコイルのインダクタンスを調整することができる。 According to the invention of claim 4, the coil pattern is provided in contact with the magnetic resin layer, and the coil inductance can be adjusted more effectively by adjusting the magnetic permeability of the magnetic resin layer. .
 請求項5の発明によれば、コイルパターンの少なくとも一部は磁性体樹脂層の内部に設けられており、磁性体樹脂層の透磁率を調整することで、より効果的にコイルのインダクタンスを調整することができる。 According to the invention of claim 5, at least a part of the coil pattern is provided inside the magnetic resin layer, and the inductance of the coil is adjusted more effectively by adjusting the magnetic permeability of the magnetic resin layer. can do.
 請求項6の発明によれば、多層基板と反対側の磁性体樹脂層の主面に設けられた金属膜層をさらに備え、金属膜層は、上面視においてコイルパターンの少なくとも一部と重なるように設けられているため、金属膜層を接地することで、コイルから生じる輻射や放射を抑制することができる。 According to the sixth aspect of the present invention, the metal film layer is further provided on the main surface of the magnetic resin layer on the side opposite to the multilayer substrate, and the metal film layer overlaps at least a part of the coil pattern in a top view. Therefore, radiation and radiation generated from the coil can be suppressed by grounding the metal film layer.
 請求項7の発明によれば、本発明の電子部品は共振器を形成する共振器パターンをさらに備えており、磁性体樹脂層の透磁率を調整することで共振器パターンを変更しなくとも共振器の共振周波数を容易に調整できるため実用的である。また、磁性体樹脂層の透磁率を調整することで、共振器パターンを小さくしても、所望の共振周波数を得ることができるため、電子部品の小型化を図ることができる。 According to the invention of claim 7, the electronic component of the present invention further includes a resonator pattern that forms a resonator, and resonates without changing the resonator pattern by adjusting the magnetic permeability of the magnetic resin layer. This is practical because the resonance frequency of the vessel can be easily adjusted. Further, by adjusting the magnetic permeability of the magnetic resin layer, a desired resonance frequency can be obtained even if the resonator pattern is reduced, and thus the electronic component can be reduced in size.
 請求項8の発明によれば、共振器パターンとして、第1コイルを有する第1共振器を形成する第1の共振器パターンと、第2コイルを有する第2共振器を形成する第2の共振器パターンとが、上面視において並べて設けられることにより、第1コイルを形成する第1のコイルパターンと第2コイルを形成する第2のコイルパターンとが電磁結合されて各種フィルタ回路を形成することができる。このとき、第1コイルを形成する第1のコイルパターンと第2コイルを形成する第2のコイルパターンとの間に磁性体樹脂層を設けることにより、第1コイルおよび第2コイルに発生する磁束が磁性体樹脂層に集中するため、互いのコイルで発生する磁束による電磁結合が阻害されて、第1コイルと第2コイルとの間の電磁結合が弱められて結合係数が小さくなるため、第1コイルおよび第2コイル間の電磁結合における結合係数を磁性体樹脂層を設けるだけで簡単に調整することができる。 According to the invention of claim 8, as the resonator pattern, the first resonator pattern forming the first resonator having the first coil and the second resonance forming the second resonator having the second coil. The first and second coil patterns forming the first coil and the second coil pattern are electromagnetically coupled to form various filter circuits. Can do. At this time, magnetic flux generated in the first coil and the second coil by providing a magnetic resin layer between the first coil pattern forming the first coil and the second coil pattern forming the second coil. Are concentrated on the magnetic resin layer, so that the electromagnetic coupling due to the magnetic flux generated in each coil is inhibited, the electromagnetic coupling between the first coil and the second coil is weakened, and the coupling coefficient becomes small. The coupling coefficient in the electromagnetic coupling between the first coil and the second coil can be easily adjusted only by providing the magnetic resin layer.
 請求項9の発明によれば、第1コイルを形成する第1のコイルパターンと第2コイルを形成する第2のコイルパターンとの間に配置されるキャビティが多層基板に設けられており、キャビティに磁性体樹脂が充填されているため、第1コイルおよび第2コイルで発生する磁束がキャビティに充填された磁性体樹脂に集中することにより、当該磁性体樹脂が電磁シールドとして機能するため、第1コイルと第2コイルとの間の電磁結合における結合係数をさらに小さくすることができる。 According to invention of Claim 9, the cavity arrange | positioned between the 1st coil pattern which forms a 1st coil, and the 2nd coil pattern which forms a 2nd coil is provided in the multilayer substrate, Since the magnetic resin is filled in the magnetic resin, the magnetic flux generated in the first coil and the second coil concentrates on the magnetic resin filled in the cavity, so that the magnetic resin functions as an electromagnetic shield. The coupling coefficient in the electromagnetic coupling between the first coil and the second coil can be further reduced.
 請求項10の発明によれば、磁性体樹脂層が設けられた多層基板の主面に設けられたマスク層をさらに備え、マスク層は、磁性体樹脂層を囲繞するように設けられているため、磁性体樹脂ペーストや磁性体樹脂モールドにより多層基板の主面に磁性体樹脂層を設けるときに、マスク層の内側にペーストやモールドを充填することで、多層基板の主面の所望の部分(位置)に磁性体樹脂層を形成できる。 According to the tenth aspect of the present invention, it further comprises a mask layer provided on the main surface of the multilayer substrate provided with the magnetic resin layer, and the mask layer is provided so as to surround the magnetic resin layer. When a magnetic resin layer is provided on the main surface of the multilayer substrate with a magnetic resin paste or a magnetic resin mold, a desired portion of the main surface of the multilayer substrate ( The magnetic resin layer can be formed at the position).
 請求項11の発明によれば、磁性体樹脂層は、透磁率の異なる複数の層により形成されているため、より効率よく磁性体樹脂層の透磁率を調整することができる。例えば、最も表層の透磁率を大きくしたり、磁性損失が大きくなるように磁性体樹脂層を形成すれば、コイルからの輻射や放射を抑制することができる。また、磁性体樹脂層が一層の場合でもこの効果を奏することができ、付与する磁性体樹脂層を、透磁率の大きなものや、磁性損失の大きなものを選択すれば、コイルからの輻射や放射を効果的に抑制することができる。 According to the invention of claim 11, since the magnetic resin layer is formed of a plurality of layers having different magnetic permeability, the magnetic permeability of the magnetic resin layer can be adjusted more efficiently. For example, if the magnetic resin layer is formed so that the magnetic permeability of the surface layer is maximized or the magnetic loss is increased, radiation and radiation from the coil can be suppressed. In addition, this effect can be achieved even when there is a single magnetic resin layer. If the magnetic resin layer to be applied is selected to have a high magnetic permeability or a magnetic loss, radiation and radiation from the coil can be achieved. Can be effectively suppressed.
本発明の電子部品の第1実施形態たる多層チップ型共振器素子を示す図である。It is a figure which shows the multilayer chip type | mold resonator element which is 1st Embodiment of the electronic component of this invention. 図1に示す多層チップ型共振器素子の等価回路を示す図である。It is a figure which shows the equivalent circuit of the multilayer chip | tip resonator element shown in FIG. 図1に示す多層チップ型共振器素子の周波数特性の一例を示す図である。It is a figure which shows an example of the frequency characteristic of the multilayer chip type | mold resonator element shown in FIG. 図1に示す多層チップ型共振器素子の周波数特性の一例を示す図である。It is a figure which shows an example of the frequency characteristic of the multilayer chip type | mold resonator element shown in FIG. 図1に示す多層チップ型共振器素子の周波数特性の一例を示す図である。It is a figure which shows an example of the frequency characteristic of the multilayer chip type | mold resonator element shown in FIG. コイルパターンの形状の変形例を示す図である。It is a figure which shows the modification of the shape of a coil pattern. コイルパターンの構造の変形例を示す図である。It is a figure which shows the modification of the structure of a coil pattern. コイルパターンの構造の変形例を示す図である。It is a figure which shows the modification of the structure of a coil pattern. マスク層が設けられた例を示す図である。It is a figure which shows the example in which the mask layer was provided. コイルパターンが設けられる層が異なる例を示す図である。It is a figure which shows the example from which the layer in which a coil pattern is provided differs. コイルパターンが設けられる層が異なる例を示す図である。It is a figure which shows the example from which the layer in which a coil pattern is provided differs. 本発明の電子部品の第2実施形態たる多層チップ型バンドパスフィルタ素子を示す図である。It is a figure which shows the multilayer chip type | mold band pass filter element which is 2nd Embodiment of the electronic component of this invention. 図12に示す多層チップ型バンドパスフィルタ素子の等価回路を示す図である。It is a figure which shows the equivalent circuit of the multilayer chip type band pass filter element shown in FIG. 図12に示す多層チップ型バンドパスフィルタ素子の周波数特性の一例を示す図である。It is a figure which shows an example of the frequency characteristic of the multilayer chip type band pass filter element shown in FIG. 本発明の電子部品の第3実施形態たる多層チップ型平板共振器素子を示す図である。It is a figure which shows the multilayer chip type | mold planar resonator element which is 3rd Embodiment of the electronic component of this invention. 図15に示す多層チップ型平板共振器素子の等価回路を示す図である。FIG. 16 is a diagram showing an equivalent circuit of the multilayer chip type plate resonator element shown in FIG. 15. 図15に示す多層チップ型平板共振器素子の周波数特性の一例を示す図である。It is a figure which shows an example of the frequency characteristic of the multilayer chip type | mold planar resonator element shown in FIG. 図15に示す多層チップ型平板共振器素子の周波数特性の一例を示す図である。It is a figure which shows an example of the frequency characteristic of the multilayer chip type | mold planar resonator element shown in FIG. 共振器パターンの変形例を示す図である。It is a figure which shows the modification of a resonator pattern. 共振器パターンの変形例を示す図である。It is a figure which shows the modification of a resonator pattern. 共振器パターンの変形例を示す図である。It is a figure which shows the modification of a resonator pattern. 本発明の電子部品の第4実施形態たる多層チップ型共振器素子を示す図である。It is a figure which shows the multilayer chip-type resonator element which is 4th Embodiment of the electronic component of this invention. 本発明の電子部品の第5実施形態を示す図である。It is a figure which shows 5th Embodiment of the electronic component of this invention. 本発明の電子部品の第6実施形態の要部拡大図である。It is a principal part enlarged view of 6th Embodiment of the electronic component of this invention. ヘリカル型コイルの巻数とインダクタンスとの関係の一例を示す図である。It is a figure which shows an example of the relationship between the number of turns of a helical coil, and an inductance. ヘリカル型コイルの巻数とQ値との関係の一例を示す図である。It is a figure which shows an example of the relationship between the number of turns of a helical type coil, and Q value. 本発明の電子部品の第7実施形態たる多層チップ型バンドパスフィルタ素子を示す図である。It is a figure which shows the multilayer chip type | mold band pass filter element which is 7th Embodiment of the electronic component of this invention. 図27に示す多層チップ型バンドパスフィルタ素子の等価回路を示す図である。It is a figure which shows the equivalent circuit of the multilayer chip type band pass filter element shown in FIG. 図27に示す多層チップ型バンドパスフィルタ素子の周波数特性の一例を示す図である。It is a figure which shows an example of the frequency characteristic of the multilayer chip type band pass filter element shown in FIG. コイルパターンの変形例を示す図である。It is a figure which shows the modification of a coil pattern. 多層基板に磁性体樹脂層を設けることによる効果を説明するための図である。It is a figure for demonstrating the effect by providing a magnetic body resin layer in a multilayer substrate. 本発明の電子部品の第8実施形態たる多層チップ型バンドパスフィルタ素子の等価回路を示す図である。It is a figure which shows the equivalent circuit of the multilayer chip type band pass filter element which is 8th Embodiment of the electronic component of this invention. 図32に示す多層チップ型バンドパスフィルタ素子の周波数特性の一例を示す図である。It is a figure which shows an example of the frequency characteristic of the multilayer chip type band pass filter element shown in FIG. 本発明の電子部品の第9実施形態たる多層チップ型バンドパスフィルタ素子を示す図である。It is a figure which shows the multilayer chip type | mold band pass filter element which is 9th Embodiment of the electronic component of this invention. 多層基板に設けられる磁性体樹脂層の変形例を示す図である。It is a figure which shows the modification of the magnetic body resin layer provided in a multilayer substrate. 多層基板に設けられる磁性体樹脂層の変形例を示す図である。It is a figure which shows the modification of the magnetic body resin layer provided in a multilayer substrate. 多層基板に設けられる磁性体樹脂層の変形例を示す図である。It is a figure which shows the modification of the magnetic body resin layer provided in a multilayer substrate. 多層基板に設けられる磁性体樹脂層の変形例を示す図である。It is a figure which shows the modification of the magnetic body resin layer provided in a multilayer substrate. 多層基板に設けられる磁性体樹脂層の変形例を示す図である。It is a figure which shows the modification of the magnetic body resin layer provided in a multilayer substrate. 従来の電子部品の一例である積層型フィルタを示す図である。It is a figure which shows the multilayer filter which is an example of the conventional electronic component.
 <第1実施形態>
 本発明の電子部品の第1実施形態たる多層チップ型共振器素子1について、図1~図5を参照して説明する。
<First Embodiment>
A multilayer chip resonator element 1 as a first embodiment of an electronic component of the present invention will be described with reference to FIGS.
 図1は第1実施形態の多層チップ型共振器素子1を示す図であって、(a)は断面図、(b)~(f)は多層チップ型共振器素子1を構成する各層3,20~23の平面図、(g)は配線層24の下面図である。図2は図1に示す多層チップ型共振器素子1に設けられた共振器回路4の等価回路を示す図である。図3~図5はそれぞれ図1に示す多層チップ型共振器素子1の周波数特性の一例を示す図である。 FIG. 1 is a diagram showing a multilayer chip resonator element 1 according to the first embodiment, in which (a) is a cross-sectional view, and (b) to (f) are respective layers 3 constituting the multilayer chip resonator element 1. 20 to 23 are plan views, and (g) is a bottom view of the wiring layer 24. FIG. FIG. 2 is a diagram showing an equivalent circuit of the resonator circuit 4 provided in the multilayer chip resonator element 1 shown in FIG. 3 to 5 are diagrams showing examples of frequency characteristics of the multilayer chip resonator element 1 shown in FIG.
 (構成)
 図1(a)に示すように、多層チップ型共振器素子1は、積層したセラミックグリーンシートを焼成して形成された多層基板2と、多層基板2の一方の主面に設けられた磁性体樹脂層3とを備え、図2に示すように、素子1の内部にはAgやCuなどの導体パターンにより形成された共振器回路4(本発明の「共振器パターン」に相当)が設けられている。また、多層チップ型共振器素子1は、幅×長さ×高さが約8mm×6mm×0.5mmの形状に形成された多層基板2の上部に、幅×長さ×高さが約8mm×6mm×0.1mmの形状に形成された磁性体樹脂層3が積層されて、所謂、チップ型の電子部品として形成されている。
(Constitution)
As shown in FIG. 1A, a multilayer chip resonator element 1 includes a multilayer substrate 2 formed by firing laminated ceramic green sheets, and a magnetic body provided on one main surface of the multilayer substrate 2. As shown in FIG. 2, a resonator circuit 4 (corresponding to the “resonator pattern” of the present invention) formed of a conductor pattern such as Ag or Cu is provided inside the element 1. ing. The multilayer chip resonator element 1 has a width × length × height of about 8 mm on top of the multilayer substrate 2 formed in a shape of width × length × height of about 8 mm × 6 mm × 0.5 mm. A magnetic resin layer 3 formed in a shape of × 6 mm × 0.1 mm is laminated to form a so-called chip-type electronic component.
 多層基板2は、コイル層20と、第1コンデンサ層21と、第2コンデンサ層22と、第3コンデンサ層23と、配線層24とが積層されて焼成されることにより一体的に誘電体セラミック層として形成されている。各層20~24を形成するセラミックグリーンシートは、アルミナおよびガラスなどの混合粉末が有機バインダおよび溶剤などと一緒に混合されたスラリーが成膜装置によりシート化されたものであり、約1000℃よりも低い温度で、所謂、低温焼成できるように構成されている。そして、所定形状に切り取られたセラミックグリーンシートに、ビア形成、AgやCuなどの導体ペーストによる種々のパターン印刷が行われて各層20~24が形成される。 The multilayer substrate 2 includes a coil layer 20, a first capacitor layer 21, a second capacitor layer 22, a third capacitor layer 23, and a wiring layer 24, which are laminated and fired to form an integral dielectric ceramic. It is formed as a layer. The ceramic green sheets forming the layers 20 to 24 are obtained by forming a slurry in which a mixed powder such as alumina and glass is mixed with an organic binder and a solvent into a sheet by a film forming apparatus, and the temperature is higher than about 1000 ° C. The so-called low temperature firing is possible at a low temperature. The ceramic green sheets cut into a predetermined shape are subjected to via formation and various pattern printing using a conductor paste such as Ag or Cu to form the layers 20 to 24.
 図1(c)に示すように、コイル層20にはコイルL1を形成するスパイラル形状のコイルパターン20aが設けられている。そして、コイルパターン20aの一端には、導電性ペーストの充填により形成された層間接続導体(ビア導体)20bが、接地電極Gとの接続のために設けられている。また、コイルパターン20aの他端には、ビア構造の層間接続導体20cが、コンデンサC3を形成する電極パターン21aとの接続のために設けられている。 As shown in FIG. 1C, the coil layer 20 is provided with a spiral coil pattern 20a for forming the coil L1. An interlayer connection conductor (via conductor) 20b formed by filling a conductive paste is provided at one end of the coil pattern 20a for connection to the ground electrode G. Further, an interlayer connection conductor 20c having a via structure is provided at the other end of the coil pattern 20a for connection to the electrode pattern 21a forming the capacitor C3.
 図1(d)に示すように、第1コンデンサ層21には、コンデンサC3の一方の電極を形成する電極パターン21aが設けられており、所定の箇所にビア構造の層間接続導体21bが設けられている。また、同図(e)に示すように、第2コンデンサ層22には、コンデンサC3の他方の電極およびコンデンサC1,C2の一方の電極を形成する電極パターン22aが設けられており、所定の箇所にビア構造の層間接続導体22bが設けられている。 As shown in FIG. 1D, the first capacitor layer 21 is provided with an electrode pattern 21a that forms one electrode of the capacitor C3, and an interlayer connection conductor 21b having a via structure is provided at a predetermined location. ing. Further, as shown in FIG. 5E, the second capacitor layer 22 is provided with an electrode pattern 22a that forms the other electrode of the capacitor C3 and one electrode of the capacitors C1 and C2, and a predetermined location. In addition, an interlayer connection conductor 22b having a via structure is provided.
 図1(f)に示すように、第3コンデンサ層23には、コンデンサC1の他方の電極を形成する電極パターン23aおよびコンデンサC2の他方の電極を形成する電極パターン23bが設けられており、所定の箇所にビア構造の層間接続導体23cが設けられている。また、第3コンデンサ層23には、電極パターン23aと入力電極P1とを接続するための層間接続導体23dと、電極パターン23bと出力電極P2とを接続するための層間接続導体23eとが設けられている。 As shown in FIG. 1 (f), the third capacitor layer 23 is provided with an electrode pattern 23a that forms the other electrode of the capacitor C1 and an electrode pattern 23b that forms the other electrode of the capacitor C2. An interlayer connection conductor 23c having a via structure is provided at the location. The third capacitor layer 23 is provided with an interlayer connection conductor 23d for connecting the electrode pattern 23a and the input electrode P1, and an interlayer connection conductor 23e for connecting the electrode pattern 23b and the output electrode P2. ing.
 図1(g)に示すように、配線層24には、入力電極P1と、出力電極P2と、接地電極Gとが設けられている。そして、コイル層20のコイルパターン20aの一端と、接地電極Gとが層間接続導体20b,21b,22b,23cを介して接続されている。また、コイル層20のコイルパターン20aの他端と、第1コンデンサ層21の電極パターン21aとが層間接続導体20cを介して接続されている。また、第3コンデンサ層23の電極パターン23aと、入力電極P1とが層間接続導体23dを介して接続され、第3コンデンサ層23の電極パターン23bと、出力電極P2とが層間接続導体23eを介して接続されて共振器回路4が形成されている。 As shown in FIG. 1 (g), the wiring layer 24 is provided with an input electrode P1, an output electrode P2, and a ground electrode G. One end of the coil pattern 20a of the coil layer 20 and the ground electrode G are connected via interlayer connection conductors 20b, 21b, 22b, and 23c. The other end of the coil pattern 20a of the coil layer 20 and the electrode pattern 21a of the first capacitor layer 21 are connected via an interlayer connection conductor 20c. The electrode pattern 23a of the third capacitor layer 23 and the input electrode P1 are connected via an interlayer connection conductor 23d, and the electrode pattern 23b of the third capacitor layer 23 and the output electrode P2 are connected via an interlayer connection conductor 23e. Thus, a resonator circuit 4 is formed.
 図1(b)に示すように、磁性体樹脂層3は、例えば、熱硬化性の樹脂により形成され、樹脂には種々の磁性体材料が混入されることにより、磁性体樹脂層3が所望の透磁率μrを有するように形成されている。なお、熱硬化性の樹脂としては、エポキシ樹脂、フェノール樹脂、シアネート樹脂などがある。 As shown in FIG. 1B, the magnetic resin layer 3 is formed of, for example, a thermosetting resin, and various magnetic materials are mixed into the resin so that the magnetic resin layer 3 is desired. Is formed so as to have a magnetic permeability μr. Examples of the thermosetting resin include an epoxy resin, a phenol resin, and a cyanate resin.
 なお、以下の説明において、透磁率μrは、比透磁率を表し、誘電率εrは比誘電率を表すものとする。 In the following description, the magnetic permeability μr represents the relative magnetic permeability, and the dielectric constant εr represents the relative dielectric constant.
 次に、図1の多層チップ型共振器素子1の製造方法の一例についてその概略を説明する。この実施形態の多層チップ型共振器素子1は、最初に多層基板2を低温焼成により形成し、形成された多層基板2の一方の主面に磁性体樹脂層3を設けることにより製造される。 Next, an outline of an example of a method for manufacturing the multilayer chip resonator element 1 of FIG. 1 will be described. The multilayer chip resonator element 1 of this embodiment is manufactured by first forming the multilayer substrate 2 by low-temperature firing, and providing the magnetic resin layer 3 on one main surface of the formed multilayer substrate 2.
 まず、所定形状に形成されたグリーンシートに、レーザなどでビアホールを形成し、内部に導体ペーストを充填することにより層間接続用のビア孔(ビア導体)が形成され、AgやCuなどの導体ペーストにより所定のパターンが印刷されて、多層基板2を構成する各層20~24を形成するための5枚のグリーンシートが準備される。なお、それぞれのグリーンシートには、一度に大量の多層基板2を形成できるように、複数の電極パターンが設けられている。 First, via holes are formed in a green sheet formed in a predetermined shape with a laser or the like and filled with a conductive paste to form via holes (via conductors) for interlayer connection. A conductive paste such as Ag or Cu Thus, a predetermined pattern is printed, and five green sheets for forming the respective layers 20 to 24 constituting the multilayer substrate 2 are prepared. Each green sheet is provided with a plurality of electrode patterns so that a large number of multilayer substrates 2 can be formed at a time.
 次に、各層20~24が積層されて積層体が形成される。そして、焼成後に個々の多層基板2に分割するための溝が、個々の多層基板2の領域を囲むように形成される。続いて、積層体が加圧されながら低温焼成されることにより多層基板2の集合体が形成される。 Next, the layers 20 to 24 are laminated to form a laminate. Then, grooves for dividing the individual multilayer substrates 2 after firing are formed so as to surround the regions of the individual multilayer substrates 2. Subsequently, the multilayer body 2 is fired at a low temperature while being pressed to form an aggregate of the multilayer substrates 2.
 次に、個々の多層基板2に分割される前に、多層基板2の集合体に樹脂シートが積層されて、これが加熱硬化されることにより磁性体樹脂層3が各多層基板2に設けられる。そして、個々の電子部品に分割されることにより多層チップ型共振器素子1が完成する。 Next, before being divided into individual multilayer substrates 2, a resin sheet is laminated on the aggregate of multilayer substrates 2, and this is heat-cured to provide the magnetic resin layer 3 on each multilayer substrate 2. Then, the multilayer chip resonator element 1 is completed by being divided into individual electronic components.
 (特性)
 次に、多層型チップ型共振器素子1の周波数特性について説明する。なお、共振器の共振周波数fは、
f=1/2π(L・C)1/2
L:インダクタンス
C:キャパシタンス
と表すことができるため、インダクタンスLまたはキャパシタンスCの増大に伴い、共振周波数fは小さくなる。
(Characteristic)
Next, the frequency characteristics of the multilayer chip resonator element 1 will be described. The resonance frequency f of the resonator is
f = 1 / 2π (L · C) 1/2
Since L can be expressed as inductance C: capacitance, the resonance frequency f decreases as the inductance L or capacitance C increases.
 また、インダクタンスLの大きさは一般的に透磁率μrの大きさに比例する。したがって、コイル周辺の部材の透磁率μrが大きくなれば、インダクタンスLが大きくなり、これにより共振周波数fの共振周波数は低くなる。 Also, the size of the inductance L is generally proportional to the size of the magnetic permeability μr. Therefore, if the magnetic permeability μr of the member around the coil is increased, the inductance L is increased, and thereby the resonance frequency of the resonance frequency f is decreased.
 (磁性体樹脂層3の有無による周波数特性)
 図3は多層チップ型共振器素子1の周波数特性と、磁性体樹脂層3が設けられていない状態の多層基板2による共振器回路4の周波数特性を示す図である。同図中の上側の曲線は、入力電極P1に入力した信号と、共振器回路4内部で反射して再度入力電極P1に帰る反射信号との電力比である反射特性を示す(以下、「反射特性」と称する)。また、同図中の下側の曲線は、入力電極P1に入力した信号と、出力電極P2から出力される信号との電力比である通過特性を示す(以下、「通過特性」と称する)。
(Frequency characteristics with and without magnetic resin layer 3)
FIG. 3 is a diagram showing the frequency characteristics of the multilayer chip resonator element 1 and the frequency characteristics of the resonator circuit 4 formed by the multilayer substrate 2 in a state where the magnetic resin layer 3 is not provided. The upper curve in the figure shows a reflection characteristic which is a power ratio between a signal input to the input electrode P1 and a reflected signal reflected inside the resonator circuit 4 and returning to the input electrode P1 (hereinafter referred to as “reflection”). Called "characteristics"). Also, the lower curve in the figure shows a pass characteristic that is a power ratio between the signal input to the input electrode P1 and the signal output from the output electrode P2 (hereinafter referred to as “pass characteristic”).
 また、図3において、点線の曲線が、磁性体樹脂層3が設けられていない状態の多層基板2による共振器回路4の周波数特性を示し、実線の曲線が、多層チップ型共振器素子1の周波数特性を示し、通過特性におけるピークが多層チップ型共振器素子1の共振周波数である。 In FIG. 3, the dotted curve indicates the frequency characteristics of the resonator circuit 4 by the multilayer substrate 2 in the state where the magnetic resin layer 3 is not provided, and the solid curve indicates the multilayer chip resonator element 1. The frequency characteristic is shown, and the peak in the pass characteristic is the resonance frequency of the multilayer chip resonator element 1.
 図3に示す例では、多層基板2は、誘電率εrが6となるように形成され、磁性体樹脂層3の透磁率μrが2となるように構成されている。なお、以下で説明する例において、多層基板2の透磁率μrは1となるように構成されている。 In the example shown in FIG. 3, the multilayer substrate 2 is formed so that the dielectric constant εr is 6 and the magnetic permeability μr of the magnetic resin layer 3 is 2. In the example described below, the multilayer substrate 2 is configured so that the magnetic permeability μr is 1.
 図3に示すように、磁性体樹脂層3が設けられた多層チップ型共振器素子1の共振周波数fは低周波側に移動する。 As shown in FIG. 3, the resonance frequency f of the multilayer chip resonator element 1 provided with the magnetic resin layer 3 moves to the low frequency side.
 (磁性体樹脂層3の透磁率μrの変化による周波数特性)
 図4は磁性体樹脂層3の透磁率μrを変化させたときの多層チップ型共振器素子1の周波数特性を示すものであって、上側の曲線は反射特性を示し、下側の曲線は通過特性を示す。同図中の一番右側の曲線は磁性体樹脂層3の透磁率μrが1となるように構成されたときの例を示し、以下、低周波側に向かう順に、磁性体樹脂層3の透磁率μrが2、4、8、16となるように構成されたときの例を示す。
(Frequency characteristics due to change of magnetic permeability μr of magnetic resin layer 3)
FIG. 4 shows the frequency characteristics of the multilayer chip resonator element 1 when the magnetic permeability μr of the magnetic resin layer 3 is changed. The upper curve shows the reflection characteristics and the lower curve passes. Show properties. The rightmost curve in the figure shows an example when the magnetic permeability of the magnetic resin layer 3 is configured to be 1, and hereinafter, the permeability of the magnetic resin layer 3 in order toward the low frequency side. An example is shown in which the magnetic susceptibility μr is configured to be 2, 4, 8, and 16.
 図4に示すように、磁性体樹脂層3の透磁率μrが大きくなるのに伴い、多層チップ型共振器素子1の共振周波数fは低周波側に移動する。 As shown in FIG. 4, as the magnetic permeability μr of the magnetic resin layer 3 increases, the resonance frequency f of the multilayer chip resonator element 1 moves to the lower frequency side.
 (磁性体樹脂層3の厚みの変化による周波数特性)
 図5は磁性体樹脂層3の厚みを変化させたときの多層チップ型共振器素子1の周波数特性を示すものであって、上側の曲線は反射特性を示し、下側の曲線は通過特性を示す。同図中の一番右側の曲線は磁性体樹脂層3が設けられていないときの例を示し、以下、低周波側に向かう順に、磁性体樹脂層3の厚みが0.05mm、0.1mm、0.2mm、0.4mm、1.0mmとなるように構成されたときの例を示す。
(Frequency characteristics due to change in thickness of magnetic resin layer 3)
FIG. 5 shows the frequency characteristics of the multilayer chip resonator element 1 when the thickness of the magnetic resin layer 3 is changed. The upper curve shows the reflection characteristics, and the lower curve shows the pass characteristics. Show. The rightmost curve in the figure shows an example when the magnetic resin layer 3 is not provided. Hereinafter, the thickness of the magnetic resin layer 3 is 0.05 mm and 0.1 mm in order toward the low frequency side. , 0.2 mm, 0.4 mm, and 1.0 mm.
 図5に示すように、磁性体樹脂層3の厚みが厚くなるのに伴いコイルL1で発生する磁界のうち、磁性体樹脂層3の外部に漏れる量が少なくなるので、多層チップ型共振器素子1の共振周波数fは低周波側に移動する。このように、磁性体樹脂層3の厚みを調整することにより、容易に多層チップ型共振器素子1の周波数特性を調整することができる。 As shown in FIG. 5, the amount of magnetic field generated in the coil L1 leaks outside the magnetic resin layer 3 as the thickness of the magnetic resin layer 3 increases, so that the multilayer chip resonator element The resonance frequency f of 1 moves to the low frequency side. Thus, by adjusting the thickness of the magnetic resin layer 3, the frequency characteristics of the multilayer chip resonator element 1 can be easily adjusted.
 (コイルパターンの形状の変形例)
 図6はコイルパターンの形状の変形例を示す図であって、(a)はミアンダ形状のコイルパターン20dを示し、(b)はライン形状のコイルパターン20eを示し、(c)はスパイラル形状のコイルパターン20fを示す。上記した例では、コイル層20の一方面にスパイラル形状のコイルパターン20aを形成したが、図6(a)に示すミアンダ形状でコイルパターン20dを形成してもよいし、同図(b)に示すライン形状でコイルパターン20eを形成してもよく、同図(c)に示すスパイラル形状でコイルパターンを形成してもよい。
(Modification of coil pattern shape)
6A and 6B are diagrams showing modifications of the shape of the coil pattern, in which FIG. 6A shows a meander-shaped coil pattern 20d, FIG. 6B shows a line-shaped coil pattern 20e, and FIG. 6C shows a spiral-shaped coil pattern. The coil pattern 20f is shown. In the above example, the spiral coil pattern 20a is formed on one surface of the coil layer 20. However, the coil pattern 20d may be formed in the meander shape shown in FIG. The coil pattern 20e may be formed in the line shape shown, or the coil pattern may be formed in the spiral shape shown in FIG.
 (コイルパターンの構造の変形例)
 図7はコイルパターン20dの構造の変形例を示す図であって、(a)は多層チップ型共振器素子1の断面図、(b)はコイル層20の平面図である。図7(a)に示すように、コイルパターン20dをコイル層20の一方面に凸状に形成することにより、コイルパターン20a間に磁性体樹脂層3が充填されるように構成してもよい。
(Modified example of coil pattern structure)
FIG. 7 is a view showing a modification of the structure of the coil pattern 20 d, wherein (a) is a cross-sectional view of the multilayer chip resonator element 1, and (b) is a plan view of the coil layer 20. As shown in FIG. 7A, the magnetic resin layer 3 may be filled between the coil patterns 20a by forming the coil pattern 20d in a convex shape on one surface of the coil layer 20. .
 図8はコイルパターン20dの構造の変形例を示す図であって、(a)は多層チップ型共振器素子1の断面図、(b)はコイル層20の平面図である。図8(a)に示すように、コイルパターン20dをコイル層20の一方面に埋没するように形成することにより、コイルパターン20a間に誘電体としてのセラミック層が充填されるように構成してもよい。 8A and 8B are views showing a modification of the structure of the coil pattern 20d, where FIG. 8A is a cross-sectional view of the multilayer chip resonator element 1, and FIG. 8B is a plan view of the coil layer 20. FIG. As shown in FIG. 8A, the coil pattern 20d is formed so as to be buried in one surface of the coil layer 20, so that a ceramic layer as a dielectric is filled between the coil patterns 20a. Also good.
 (マスク層5が設けられた例)
 図9はマスク層5が設けられた例を示す図であって、(a)は多層チップ型共振器素子1の断面図、(b)は(a)の平面図、(c)はマスク層の変形例を示す図である。
(Example in which mask layer 5 is provided)
FIG. 9 is a diagram showing an example in which a mask layer 5 is provided, where (a) is a cross-sectional view of the multilayer chip resonator element 1, (b) is a plan view of (a), and (c) is a mask layer. FIG.
 図9(a),(b)に示すように、磁性体樹脂層3が設けられた多層基板2の主面に、磁性体樹脂層3を囲繞するようにマスク層5を設けてもよい。マスク層5は、多層基板2を構成するセラミックと同じ材質で形成すればよい。すなわち、多層基板2を形成する際に、マスク層5として加工が施されたグリーンシートをさらに積層して焼成することによりマスク層5を設けることができる。 9A and 9B, a mask layer 5 may be provided on the main surface of the multilayer substrate 2 provided with the magnetic resin layer 3 so as to surround the magnetic resin layer 3. The mask layer 5 may be formed of the same material as the ceramic constituting the multilayer substrate 2. That is, when the multilayer substrate 2 is formed, the mask layer 5 can be provided by further laminating and firing a green sheet processed as the mask layer 5.
 このように構成すれば、マスク層5は、多層基板2の主面に磁性体樹脂層3を囲繞するように設けられているため、流動性を有する磁性体樹脂ペーストや磁性体樹脂モールドにより多層基板2の主面に磁性体樹脂層3を設けるときに、マスク層5の内側にペーストやモールドを充填することで、多層基板2の主面の所定箇所に磁性体樹脂層3を形成できるとともに、主面端縁部からの液だれが生じるのを防止できる。 If comprised in this way, since the mask layer 5 is provided so that the main surface of the multilayer substrate 2 may surround the magnetic body resin layer 3, it is multilayered by the magnetic body resin paste which has fluidity | liquidity, or a magnetic body resin mold. When the magnetic resin layer 3 is provided on the main surface of the substrate 2, the magnetic resin layer 3 can be formed at a predetermined position on the main surface of the multilayer substrate 2 by filling the mask layer 5 with a paste or a mold. It is possible to prevent the dripping from the edge of the main surface.
 なお、マスク層5の形状はコイルパターン20dを上面視において囲むように設ければどのような形状であってもよく、例えば、マスク層を、図9(c)に示すマスク層5aのように構成してもよい。 The shape of the mask layer 5 may be any shape as long as it surrounds the coil pattern 20d in a top view. For example, the mask layer is formed as a mask layer 5a shown in FIG. It may be configured.
 (コイルパターン20dが多層基板2の内部に設けられている例)
 図10はコイルパターン20dが設けられる層が異なる例を示す図であって、(a)は多層チップ型共振器素子1の断面図、(b)コイルパターン20dが多層基板2の内部に設けられたときの多層チップ型共振器素子1の周波数特性を示すものであり、上側の曲線は反射特性を示し、下側の曲線は通過特性を示す。図10(a)に示すように、この例では、コイルパターン20dが、多層基板2および磁性体樹脂層3の界面の近傍であって、多層基板2の内部に設けられている。
(Example in which the coil pattern 20d is provided inside the multilayer substrate 2)
10A and 10B are diagrams showing examples in which the layers on which the coil pattern 20d is provided are different. FIG. 10A is a sectional view of the multilayer chip resonator element 1, and FIG. The frequency characteristics of the multilayer chip resonator element 1 at this time are shown, with the upper curve showing the reflection characteristics and the lower curve showing the pass characteristics. As shown in FIG. 10A, in this example, the coil pattern 20 d is provided in the vicinity of the interface between the multilayer substrate 2 and the magnetic resin layer 3 and inside the multilayer substrate 2.
 このように構成しても、図10(b)に示すように、多層チップ型共振器素子1の共振周波数fは低周波側に移動する。なお、同図中の一番右側の曲線が磁性体樹脂層3が設けられていないときの例を示し、以下、低周波側に向かう順番に、コイルパターン20dが界面から0.025mmの深さに設けられた例、コイルパターン20dが界面から0.0125mmの深さに設けられた例、コイルパターン20dが界面に設けられた例を示す。 Even with this configuration, as shown in FIG. 10B, the resonance frequency f of the multilayer chip resonator element 1 moves to the low frequency side. The rightmost curve in the figure shows an example when the magnetic resin layer 3 is not provided. Hereinafter, the coil pattern 20d has a depth of 0.025 mm from the interface in order toward the low frequency side. An example in which the coil pattern 20d is provided at a depth of 0.0125 mm from the interface and an example in which the coil pattern 20d is provided at the interface are shown.
 また、図10に示す構成では、コイルパターン20dが、多層基板2の内部に形成されているため、コイルパターン20dの耐環境性(耐久性)が向上するとともに、コイルパターン20dの近傍に配置された磁性体樹脂層3により、共振周波数を微調整することができる。 Further, in the configuration shown in FIG. 10, since the coil pattern 20d is formed inside the multilayer substrate 2, the environmental resistance (durability) of the coil pattern 20d is improved and the coil pattern 20d is arranged in the vicinity of the coil pattern 20d. The resonance frequency can be finely adjusted by the magnetic resin layer 3.
 (コイルパターン20dが磁性体樹脂層3の内部に設けられている例)
 図11はコイルパターン20dが設けられる層が異なる例を示す図であって、(a)は多層チップ型共振器素子1の断面図、(b)コイルパターン20dが磁性体樹脂層3の内部に設けられたときの多層チップ型共振器素子1の周波数特性を示すものであり、上側の曲線は反射特性を示し、下側の曲線は通過特性を示す。図11(a)に示すように、この例では、コイルパターン20dが、多層基板2および磁性体樹脂層3の界面の近傍であって、磁性体樹脂層3の内部に設けられている。
(Example in which the coil pattern 20d is provided inside the magnetic resin layer 3)
FIG. 11 is a diagram showing an example in which the layer provided with the coil pattern 20d is different. (A) is a cross-sectional view of the multilayer chip resonator element 1, and (b) the coil pattern 20d is placed inside the magnetic resin layer 3. The frequency characteristic of the multilayer chip resonator element 1 when provided is shown, the upper curve shows the reflection characteristic, and the lower curve shows the pass characteristic. As shown in FIG. 11A, in this example, the coil pattern 20 d is provided in the vicinity of the interface between the multilayer substrate 2 and the magnetic resin layer 3 and inside the magnetic resin layer 3.
 このように構成すれば、図11(b)に示すように、多層チップ型共振器素子1の共振周波数fをより大きく低周波側に移動することができる。なお、同図中の一番右側の曲線が磁性体樹脂層3が設けられていないときの例を示し、以下、低周波側に向かう順番に、コイルパターン20dが界面に設けられた例、コイルパターン20dが界面から0.0125mmの高さに設けられた例を示す。 With this configuration, as shown in FIG. 11B, the resonance frequency f of the multilayer chip resonator element 1 can be moved to the lower frequency side. The rightmost curve in the figure shows an example when the magnetic resin layer 3 is not provided. Hereinafter, an example in which the coil pattern 20d is provided at the interface in the order toward the low frequency side, the coil An example in which the pattern 20d is provided at a height of 0.0125 mm from the interface is shown.
 したがって、この実施形態によれば、多層基板2を、積層したセラミックグリーンシートを焼成することにより誘電体セラミック層として形成し、形成された多層基板2の一方の主面に磁性体樹脂層3を設けることで、多層基板2の主面に磁性体樹脂層3が設けられた電子部品を形成しているため、従来のように誘電体セラミック層と磁性体セラミック層とを積層して一体的に同時焼成する必要がなく、多層基板2と磁性体樹脂層3との境界に、焼成の際の熱に起因した反りやうねり、歪み、割れ、空間などが生じるおそれが全くないため、製造過程における不良品の発生を抑制することができる。 Therefore, according to this embodiment, the multilayer substrate 2 is formed as a dielectric ceramic layer by firing the laminated ceramic green sheets, and the magnetic resin layer 3 is formed on one main surface of the formed multilayer substrate 2. Since the electronic component having the magnetic resin layer 3 provided on the main surface of the multilayer substrate 2 is formed, the dielectric ceramic layer and the magnetic ceramic layer are laminated and integrated as in the past. There is no need for simultaneous firing, and there is no possibility of warping, undulation, distortion, cracking, space, or the like caused by heat during firing at the boundary between the multilayer substrate 2 and the magnetic resin layer 3, so in the manufacturing process Generation of defective products can be suppressed.
 また、所望の誘電率を有するセラミックグリーンシートを積層し焼成して多層基板2を形成することで多層基板2の誘電率を容易に調整でき、また、種々の磁性体材料と樹脂材料とを混合することで磁性体樹脂層3の透磁率μrを容易に調整できるため、透磁率μrおよび誘電率εrを容易に調整することができる。 In addition, the dielectric constant of the multilayer substrate 2 can be easily adjusted by laminating and firing ceramic green sheets having a desired dielectric constant to form the multilayer substrate 2, and various magnetic materials and resin materials can be mixed. By doing so, the magnetic permeability μr of the magnetic resin layer 3 can be easily adjusted, so that the magnetic permeability μr and the dielectric constant εr can be easily adjusted.
 また、磁性体樹脂層3の透磁率μrを調整することでコイルパターン20a,20d,20e,20fを変更しなくともコイルのインダクタンスLを容易に調整できるため実用的である。また、磁性体樹脂層3の透磁率μrを調整することで、コイルパターン20a,20d,20eを小さくしても、大きなインダクタンスLを得ることができるため、多層チップ型共振器素子1に代表される電子部品の小型化を図ることができる。 Further, it is practical because the inductance L of the coil can be easily adjusted without changing the coil patterns 20a, 20d, 20e, and 20f by adjusting the magnetic permeability μr of the magnetic resin layer 3. Further, by adjusting the magnetic permeability μr of the magnetic resin layer 3, a large inductance L can be obtained even if the coil patterns 20a, 20d, and 20e are reduced. The electronic component can be downsized.
 また、コイルパターン20a,20d,20e,20fを磁性体樹脂層3の内部に設けることにより、磁性体樹脂層3の透磁率μrを調整することで、より効果的にコイルのインダクタンスLを調整することができる。 Further, by providing the coil patterns 20a, 20d, 20e, and 20f in the magnetic resin layer 3, the magnetic permeability μr of the magnetic resin layer 3 is adjusted, so that the coil inductance L is more effectively adjusted. be able to.
 また、磁性体樹脂層3の透磁率μrを調整することで共振器回路4の回路パターンを変更しなくとも共振器回路4の共振周波数fを容易に調整できるため実用的である。また、磁性体樹脂層3の透磁率μrを調整することで、共振器回路4を形成する回路パターンを小さくしても、所望の共振周波数fを得ることができるため、多層チップ型共振器素子1に代表される電子部品の小型化を図ることができる。 Further, it is practical because the resonance frequency f of the resonator circuit 4 can be easily adjusted without changing the circuit pattern of the resonator circuit 4 by adjusting the magnetic permeability μr of the magnetic resin layer 3. Further, by adjusting the magnetic permeability μr of the magnetic resin layer 3, a desired resonance frequency f can be obtained even if the circuit pattern forming the resonator circuit 4 is reduced. 1 can be reduced in size.
 また、従来では、大きなインダクタンスLを有するコイルが必要なときは、所望のインダクタンスLを有するコイルを形成するために、コイルパターンを必要な長さ、形状に形成しなければならず、コイルパターン(コイル)のサイズが大きく、高さも高くなったが、上記した構成によれば、磁性体樹脂層3によりコイルのインダクタンスLを増大させることができるため、電子部品の内部に大きなインダクタンスLを有するコイルを形成でき、電子部品の低背化を図ることができる。 Conventionally, when a coil having a large inductance L is required, in order to form a coil having a desired inductance L, the coil pattern must be formed in a necessary length and shape. However, according to the configuration described above, the inductance L of the coil can be increased by the magnetic resin layer 3, so that the coil having a large inductance L inside the electronic component can be obtained. The height of the electronic component can be reduced.
 <第2実施形態>
 次に、本発明の電子部品の第2実施形態たる多層チップ型バンドパスフィルタ素子100について、図12~図14を参照して説明する。
Second Embodiment
Next, a multilayer chip type bandpass filter element 100 as a second embodiment of the electronic component of the present invention will be described with reference to FIGS.
 図12は第2実施形態の多層チップ型バンドパスフィルタ素子100を示す図であって、(a)は断面図、(b)~(k)は多層チップ型バンドパスフィルタ素子100を構成する各層103,120~128の平面図である。図13は図12に示す多層チップ型バンドパスフィルタ素子100に設けられたバンドパスフィルタ回路104の等価回路を示す図である。図14は図12に示す多層チップ型バンドパスフィルタ素子100の周波数特性の一例を示す図である。 12A and 12B are diagrams showing a multilayer chip type bandpass filter element 100 according to the second embodiment, in which FIG. 12A is a cross-sectional view, and FIGS. 12B to 10K are layers constituting the multilayer chip type bandpass filter element 100. FIG. 3 is a plan view of 103, 120-128. FIG. 13 is a diagram showing an equivalent circuit of the band pass filter circuit 104 provided in the multilayer chip type band pass filter element 100 shown in FIG. FIG. 14 is a diagram showing an example of frequency characteristics of the multilayer chip type bandpass filter element 100 shown in FIG.
 この第2実施形態が、上記第1実施形態と異なる点は、図12,13に示すように、多層チップ型バンドパスフィルタ(BPF)素子100の内部に設けられた回路構成が異なる点である。その他の構成は上記第1実施形態と同様であるため、その構成の説明は相当符号を付すことにより省略する。 The second embodiment is different from the first embodiment in that the circuit configuration provided in the multilayer chip type bandpass filter (BPF) element 100 is different as shown in FIGS. . Since the other configuration is the same as that of the first embodiment, description of the configuration is omitted by assigning a corresponding symbol.
 (構成)
 図12(a)に示すように、多層チップ型BPF素子100は、積層したセラミックグリーンシートを焼成して形成された多層基板102と、多層基板102の一方の主面に設けられた磁性体樹脂層103とを備え、図13に示すように、内部にはAgやCuなどの導体パターンにより形成されたバンドパスフィルタ回路104が設けられている。また、多層チップ型BPF素子100は、幅×長さ×高さが約1.0mm×0.5mm×0.3mmの形状に形成されて、所謂、チップ型の電子部品として形成されている。
(Constitution)
As shown in FIG. 12A, a multilayer chip type BPF element 100 includes a multilayer substrate 102 formed by firing laminated ceramic green sheets, and a magnetic resin provided on one main surface of the multilayer substrate 102. As shown in FIG. 13, a band pass filter circuit 104 formed of a conductor pattern such as Ag or Cu is provided therein. The multilayer chip type BPF element 100 is formed as a so-called chip type electronic component having a width × length × height of about 1.0 mm × 0.5 mm × 0.3 mm.
 多層基板102は、第1コイル層120と、接続層121と、第2コイル層122と、絶縁体(誘電体)層123と、第1コンデンサ層124と、第2コンデンサ層125と、第3コンデンサ層126と、配線層127と、誘電体層128とが積層されて焼成されることにより一体的に形成されている。また、各層120~128は、上記第1実施形態で説明したセラミックグリーンシートと同様のセラミックグリーンシートにより形成されており、この実施形態では、多層基板102の誘電率εrが60となるように構成されている。 The multilayer substrate 102 includes a first coil layer 120, a connection layer 121, a second coil layer 122, an insulator (dielectric) layer 123, a first capacitor layer 124, a second capacitor layer 125, and a third capacitor layer. The capacitor layer 126, the wiring layer 127, and the dielectric layer 128 are laminated and fired to form a single body. Each of the layers 120 to 128 is formed of a ceramic green sheet similar to the ceramic green sheet described in the first embodiment. In this embodiment, the multilayer substrate 102 has a dielectric constant εr of 60. Has been.
 図12(c)に示すように、第1コイル層120にはコイルL11を形成する左右一対のコイルパターン120aが設けられている。そして、コイルパターン120aそれぞれの他端は、第2コイル層122に形成された左右一対のコイルパターン122aそれぞれの一端122bと接続層121に左右対称に設けられたビア構造の層間接続導体121a,121bを介して接続されている。左側のコイルパターン120aの一端120bは、外部電極である入力電極P11に接続され、右側のコイルパターン120aの一端120cは、外部電極である出力電極P12に接続される。 As shown in FIG. 12C, the first coil layer 120 is provided with a pair of left and right coil patterns 120a that form the coil L11. The other end of each of the coil patterns 120a is connected to the one end 122b of each of the pair of left and right coil patterns 122a formed on the second coil layer 122 and the interlayer connection conductors 121a and 121b having a via structure provided symmetrically to the connection layer 121. Connected through. One end 120b of the left coil pattern 120a is connected to the input electrode P11 which is an external electrode, and one end 120c of the right coil pattern 120a is connected to the output electrode P12 which is an external electrode.
 図12(d)に示すように、接続層121には、第1コイル層120の2つのコイルパターン120aそれぞれの他端と、第2コイル層122の2つのコイルパターン122aの一端122bとを接続するためのビア構造の層間接続導体121a,121bが設けられている。また、図12(e)に示すように、第2コイル層122にはコイルL12を形成するライン形状のコイルパターン122aが左右対称に設けられている。そして、コイルパターン122aの一端122bが、第1コイル層120の左右に形成されたコイルパターン120aそれぞれの他端と層間接続導体121a,121bを介して接続されており、コイルパターン122aそれぞれの他端122cは、配線層127の接地電極Gと外部電極を介して接続されている。 As shown in FIG. 12D, the connection layer 121 is connected to the other end of each of the two coil patterns 120 a of the first coil layer 120 and one end 122 b of the two coil patterns 122 a of the second coil layer 122. Interlayer connection conductors 121a and 121b having a via structure are provided. Further, as shown in FIG. 12E, the second coil layer 122 is provided with line-shaped coil patterns 122a forming the coil L12 symmetrically. One end 122b of the coil pattern 122a is connected to the other end of each coil pattern 120a formed on the left and right sides of the first coil layer 120 via the interlayer connection conductors 121a and 121b, and the other end of each coil pattern 122a. 122c is connected to the ground electrode G of the wiring layer 127 via an external electrode.
 図12(f)に示すように、絶縁体層123は、各電極パターンの間隔を調整するために設けられている。また、図12(g)に示すように、第1コンデンサ層124には、電極パターン124aが設けられており、電極パターン124aと、第2コンデンサ層125に設けられた電極パターン125a,125bとによりコンデンサC11が形成される。 As shown in FIG. 12 (f), the insulator layer 123 is provided to adjust the interval between the electrode patterns. Also, as shown in FIG. 12G, the first capacitor layer 124 is provided with an electrode pattern 124a, and the electrode pattern 124a and the electrode patterns 125a and 125b provided on the second capacitor layer 125 are used. A capacitor C11 is formed.
 図12(h)に示すように、第2コンデンサ層125には、コンデンサC11を形成する電極パターン125a,125bであって、コンデンサC12の一方の電極を形成する電極パターン125aと、コンデンサC13の一方の電極を形成する電極パターン125bとが設けられている。また、電極パターン125aは外部電極である入力電極P11に接続され、電極パターン125bは外部電極である出力電極P12に接続される。 As shown in FIG. 12 (h), the second capacitor layer 125 includes electrode patterns 125a and 125b for forming the capacitor C11, one electrode pattern 125a for forming one electrode of the capacitor C12, and one of the capacitor C13. The electrode pattern 125b for forming the electrode is provided. The electrode pattern 125a is connected to the input electrode P11 that is an external electrode, and the electrode pattern 125b is connected to the output electrode P12 that is an external electrode.
 図12(i)に示すように、第3コンデンサ層126には、コンデンサC12の他方の電極を形成する電極パターン126aおよびコンデンサC13の他方の電極を形成する電極パターン126bが設けられている。また、電極パターン126a,126bは、それぞれ配線層127の接地電極Gと外部電極を介して接続されている。 As shown in FIG. 12 (i), the third capacitor layer 126 is provided with an electrode pattern 126a that forms the other electrode of the capacitor C12 and an electrode pattern 126b that forms the other electrode of the capacitor C13. The electrode patterns 126a and 126b are connected to the ground electrode G of the wiring layer 127 via external electrodes, respectively.
 図12(j)に示すように、配線層127には、接地電極Gが設けられている。そして、接地電極Gが、外部電極を介して、図12(e)に示す第2コイル層122のコイルパターン122aそれぞれの他端122cと、図12(i)に示す第3コンデンサ層126の電極パターン126a,126bとが接続されて、バンドパスフィルタ回路104が形成されている。また、図12(k)に示すように、絶縁体層123は、各電極パターンの間隔を調整するために設けられている。 As shown in FIG. 12 (j), the wiring layer 127 is provided with a ground electrode G. Then, the ground electrode G is connected to the other end 122c of the coil pattern 122a of the second coil layer 122 shown in FIG. 12 (e) via the external electrode and the electrode of the third capacitor layer 126 shown in FIG. 12 (i). The band-pass filter circuit 104 is formed by connecting the patterns 126a and 126b. Further, as shown in FIG. 12 (k), the insulator layer 123 is provided to adjust the interval between the electrode patterns.
 図12(b)に示すように、磁性体樹脂層103は、上記第1実施形態で説明した磁性体樹脂と同様の磁性体樹脂により形成されている。 As shown in FIG. 12B, the magnetic resin layer 103 is formed of a magnetic resin similar to the magnetic resin described in the first embodiment.
 なお、多層チップ型BPF素子100は、上記第1実施形態で説明した製造方法と同様の方法で製造される。 The multilayer chip type BPF element 100 is manufactured by a method similar to the manufacturing method described in the first embodiment.
 (バンドパスフィルタの周波数特性)
 次に、多層チップ型BPF素子100の周波数特性について説明する。図14は多層チップ型BPF素子100の周波数特性を示す図であって、上側の曲線は反射特性を示し、下側の曲線は通過特性を示す。また、同図中の反射特性および通過特性のそれぞれは、右側の2本の曲線が、磁性体樹脂層103の有無による周波数特性を示し、左側の2本の曲線が、磁性体樹脂層3の厚みの変化による周波数特性を示す。
(Frequency characteristics of bandpass filter)
Next, frequency characteristics of the multilayer chip type BPF element 100 will be described. FIG. 14 is a diagram showing the frequency characteristics of the multilayer chip type BPF element 100. The upper curve shows the reflection characteristics, and the lower curve shows the pass characteristics. Further, in each of the reflection characteristics and the transmission characteristics in the figure, the two curves on the right side indicate the frequency characteristics depending on the presence or absence of the magnetic resin layer 103, and the two curves on the left side indicate the magnetic resin layer 3. The frequency characteristic by the change of thickness is shown.
 (1)磁性体樹脂層103の有無による周波数特性
 図14に示す例では、磁性体樹脂層3は透磁率μrが1、厚みが0.1mmとなるように構成されている。また、同図中の右側の2本の曲線のうち、右側が磁性体樹脂層103が設けられていないときの例を示し、左側が磁性体樹脂層103が設けられているときの例を示す。同図に示すように、磁性体樹脂層103が設けられた多層チップ型BPF素子100の共振周波数fは低周波側に移動する。
(1) Frequency characteristics depending on presence / absence of magnetic resin layer 103 In the example shown in FIG. 14, the magnetic resin layer 3 is configured such that the permeability μr is 1 and the thickness is 0.1 mm. Also, among the two curves on the right side of the figure, the right side shows an example when the magnetic resin layer 103 is not provided, and the left side shows an example when the magnetic resin layer 103 is provided. . As shown in the figure, the resonance frequency f of the multilayer chip type BPF element 100 provided with the magnetic resin layer 103 moves to the low frequency side.
 (2)磁性体樹脂層103の厚みの変化による周波数特性
 図14に示す例では、透磁率μrが20である磁性体樹脂層103が多層基板102の上部に設けられている。同図中の左側の2本の曲線のうち、右側が磁性体樹脂層103の厚みが0.05mmのときの例を示し、左側が磁性体樹脂層103の厚みが0.1mmのときの例を示す。同図に示すように、磁性体樹脂層103の厚みを厚くすれば、多層チップ型BPF素子100の共振周波数fは低周波側に移動する。
(2) Frequency characteristics due to change in thickness of magnetic resin layer 103 In the example shown in FIG. 14, the magnetic resin layer 103 having a permeability μr of 20 is provided on the multilayer substrate 102. Of the two curves on the left side of the figure, the right side shows an example when the thickness of the magnetic resin layer 103 is 0.05 mm, and the left side shows an example when the thickness of the magnetic resin layer 103 is 0.1 mm. Indicates. As shown in the figure, when the thickness of the magnetic resin layer 103 is increased, the resonance frequency f of the multilayer chip type BPF element 100 moves to the lower frequency side.
 以上のように、この実施形態においても、上記第1実施形態と同様の効果を奏することができる。 As described above, also in this embodiment, the same effects as in the first embodiment can be obtained.
 <第3実施形態>
 次に、本発明の電子部品の第3実施形態たる多層チップ型平板共振器素子200について、図15~図18を参照して説明する。
<Third Embodiment>
Next, a multilayer chip type plate resonator element 200 according to a third embodiment of the electronic component of the present invention will be described with reference to FIGS.
 図15は第3実施形態の多層チップ型平板共振器素子200を示す図であって、(a)は断面図、(b),(c)は多層チップ型平板共振器素子200を構成する各層203,220の平面図、(d)は配線層221の下面図ある。図16は図15に示す多層チップ型平板共振器素子200に設けられた共振器回路204の等価回路を示す図である。図17,18は図15に示す多層チップ型平板共振器素子200の周波数特性の一例を示す図である。 15A and 15B are diagrams showing a multilayer chip type plate resonator element 200 according to the third embodiment. FIG. 15A is a cross-sectional view, and FIGS. 203 and 220 are plan views, and (d) is a bottom view of the wiring layer 221. FIG. FIG. 16 is a diagram showing an equivalent circuit of the resonator circuit 204 provided in the multilayer chip type plate resonator element 200 shown in FIG. 17 and 18 are diagrams showing an example of frequency characteristics of the multilayer chip type plate resonator element 200 shown in FIG.
 この第3実施形態が、上記第1および第2実施形態と異なる点は、図15,16に示すように、多層チップ型平板共振器素子200の内部に設けられた回路構成が異なる点である。この実施形態における多層チップ型平板共振器素子200は、阻止したい信号の周波数に対応する波長に相当する長さを線路長とする分布定数型の共振器として構成されている。その他の構成は上記第1および第2実施形態と同様であるため、その構成の説明は相当符号を付すことにより省略する。 The third embodiment differs from the first and second embodiments in that the circuit configuration provided inside the multilayer chip type plate resonator element 200 is different as shown in FIGS. . The multilayer chip type plate resonator element 200 in this embodiment is configured as a distributed constant type resonator having a line length corresponding to a wavelength corresponding to a frequency of a signal to be blocked. Since other configurations are the same as those of the first and second embodiments, description of the configurations is omitted by assigning corresponding reference numerals.
 (構成)
 図15(a)に示すように、多層チップ型平板共振器素子200は、積層したセラミックグリーンシートを焼成して形成された多層基板202と、多層基板202の一方の主面に設けられた磁性体樹脂層203とを備え、図16に示すように、内部にはAgやCuなどの導体パターンにより形成された共振器回路204が設けられている。また、多層チップ型平板共振器素子200は、幅×長さ×高さが約8mm×6mm×0.5mmの形状に形成された多層基板202の上部に、幅×長さ×高さが約8mm×6mm×0.1mmの形状に形成された磁性体樹脂層203が積層されて、所謂、チップ型の電子部品として形成されている。
(Constitution)
As shown in FIG. 15A, a multilayer chip type plate resonator element 200 includes a multilayer substrate 202 formed by firing laminated ceramic green sheets, and a magnetic layer provided on one main surface of the multilayer substrate 202. As shown in FIG. 16, a resonator circuit 204 formed of a conductor pattern such as Ag or Cu is provided inside. Further, the multilayer chip type plate resonator element 200 has a width × length × height of about 8 mm × 6 mm × 0.5 mm formed on the top of the multilayer substrate 202 having a width × length × height of about 8 mm × 6 mm × 0.5 mm. A magnetic resin layer 203 having a shape of 8 mm × 6 mm × 0.1 mm is laminated to form a so-called chip-type electronic component.
 多層基板202は、共振器層220と、接続層222と、配線層221とが積層されて焼成されることにより一体的に誘電体セラミック層として形成されている。また、各層220~222は、上記第1実施形態で説明したセラミックグリーンシートと同様のセラミックグリーンシートにより形成されており、この実施形態では、多層基板202の誘電率εrが60となるように構成されている。 The multilayer substrate 202 is integrally formed as a dielectric ceramic layer by laminating and firing the resonator layer 220, the connection layer 222, and the wiring layer 221. Each layer 220 to 222 is formed of a ceramic green sheet similar to the ceramic green sheet described in the first embodiment. In this embodiment, the multilayer substrate 202 has a dielectric constant εr of 60. Has been.
 図15(c)に示すように、共振器層220には、共振器パターン220aと、入出力結合用電極220b,220cとが設けられている。また、配線層221には、入力電極P21、出力電極P22、接地電極Gとが設けられている。そして、接続層222は、層間接続導体222a、222bが設けられており、入出力結合用電極220bおよび入力電極P21が層間接続導体222aを介して接続され、入出力結合用電極220cおよび入力電極P22が層間接続導体222bを介して接続されることにより、図16に示す、コンデンサC21,C22,共振器RFを有する共振器回路204が形成されている。 As shown in FIG. 15C, the resonator layer 220 is provided with a resonator pattern 220a and input / output coupling electrodes 220b and 220c. The wiring layer 221 is provided with an input electrode P21, an output electrode P22, and a ground electrode G. The connection layer 222 is provided with interlayer connection conductors 222a and 222b, the input / output coupling electrode 220b and the input electrode P21 are connected via the interlayer connection conductor 222a, and the input / output coupling electrode 220c and the input electrode P22. Are connected via the interlayer connection conductor 222b, a resonator circuit 204 having capacitors C21 and C22 and a resonator RF shown in FIG. 16 is formed.
 なお、コンデンサC21は、入出力結合用電極220bと共振器パターン220aとの間隔で決まる容量であり、コンデンサC22は、入出力結合用電極220cと共振器パターン220aとの間隔で決まる容量である。 The capacitor C21 is a capacitance determined by the interval between the input / output coupling electrode 220b and the resonator pattern 220a, and the capacitor C22 is a capacitance determined by the interval between the input / output coupling electrode 220c and the resonator pattern 220a.
 図15(b)に示すように、磁性体樹脂層203は、上記第1実施形態で説明した磁性体樹脂と同様の磁性体樹脂により形成されている。 As shown in FIG. 15B, the magnetic resin layer 203 is formed of a magnetic resin similar to the magnetic resin described in the first embodiment.
 なお、多層チップ型平板共振器素子200は、上記第1実施形態で説明した製造方法と同様の方法で製造される。 The multilayer chip type plate resonator element 200 is manufactured by a method similar to the manufacturing method described in the first embodiment.
 (磁性体樹脂層203の有無による周波数特性)
 図17は多層チップ型平板共振器素子200の周波数特性と、磁性体樹脂層203が設けられていない状態の多層基板202による共振器回路204の周波数特性を示す図である。同図中の上側の曲線は反射特性を示し、同図中の下側の曲線は通過特性を示す。また、図17において、点線の曲線が、磁性体樹脂層3が設けられていない状態の多層基板202による共振器回路204の周波数特性を示し、実線の曲線が、多層チップ型平板共振器素子200の周波数特性を示す。図17に示す例では、磁性体樹脂層203の透磁率μrが8となるように構成されている。
(Frequency characteristics with and without magnetic resin layer 203)
FIG. 17 is a diagram showing the frequency characteristics of the multilayer chip type plate resonator element 200 and the frequency characteristics of the resonator circuit 204 by the multilayer substrate 202 in a state where the magnetic resin layer 203 is not provided. The upper curve in the figure shows the reflection characteristics, and the lower curve in the figure shows the pass characteristics. In FIG. 17, the dotted curve indicates the frequency characteristics of the resonator circuit 204 by the multilayer substrate 202 in the state where the magnetic resin layer 3 is not provided, and the solid curve indicates the multilayer chip type plate resonator element 200. The frequency characteristics of are shown. In the example shown in FIG. 17, the magnetic material resin layer 203 is configured so that the magnetic permeability μr is 8.
 図17に示すように、磁性体樹脂層203が設けられた多層チップ型平板共振器素子200の共振周波数fは低周波側に移動する。 As shown in FIG. 17, the resonance frequency f of the multilayer chip type plate resonator element 200 provided with the magnetic resin layer 203 moves to the low frequency side.
 (磁性体樹脂層203の透磁率μrの変化による周波数特性)
 図18は磁性体樹脂層203の透磁率μrを変化させたときの多層チップ型平板共振器素子200の周波数特性を示すものであって、(a)は反射特性を示し、(b)は通過特性を示す。また、図18(a),(b)中の一番右側の曲線が磁性体樹脂層203の透磁率μrが8となるように構成されたときの例を示し、以下、低周波側に向かう順に、磁性体樹脂層203の透磁率μrが16、32となるように構成されたときの例を示す。なお、磁性体樹脂層203の透磁率μrは、磁性体樹脂層203中に含まれる磁性粉のコンテント、いわゆる樹脂分と磁性粉末との割合を変えることで変化させることができる。そのため、磁性体樹脂層203の厚みを同じにしていても、透磁率μrを変化させることで共振器の周波数を微調整することができる。
(Frequency characteristics due to change of magnetic permeability μr of magnetic resin layer 203)
FIG. 18 shows the frequency characteristics of the multilayer chip type plate resonator element 200 when the magnetic permeability μr of the magnetic resin layer 203 is changed. (A) shows the reflection characteristics, and (b) shows the passage characteristics. Show properties. Also, the rightmost curve in FIGS. 18 (a) and 18 (b) shows an example when the magnetic permeability μr of the magnetic resin layer 203 is configured to be 8, and will be directed to the low frequency side hereinafter. In this example, the magnetic resin layer 203 is configured so that the magnetic permeability μr is 16 and 32 in order. The magnetic permeability μr of the magnetic resin layer 203 can be changed by changing the content of the magnetic powder contained in the magnetic resin layer 203, that is, the ratio between the so-called resin component and the magnetic powder. Therefore, even if the thickness of the magnetic resin layer 203 is the same, the frequency of the resonator can be finely adjusted by changing the magnetic permeability μr.
 図18に示すように、磁性体樹脂層203の透磁率μrが大きくなるのに伴い、多層チップ型平板共振器素子200の共振周波数fは低周波側に移動する。 As shown in FIG. 18, as the magnetic permeability μr of the magnetic resin layer 203 increases, the resonance frequency f of the multilayer chip type plate resonator element 200 moves to the lower frequency side.
 (共振器パターンの変形例)
 図19は共振器パターンの変形例であって、(a)はλ/2共振器パターン220dを示し、(b)は片端が接地されたλ/4共振器パターン220eを示す。また、図20は共振器パターンの変形例であって、(a)はリング形状の共振器パターン220fを示し、(b)は円形状の共振器パターン220gを示し、(c)は矩形状の共振器パターン220hを示す。また、図21は共振器パターンの変形例であって、2つの共振モードを発生することによりバンドパスフィルタを構成するデュアルモード共振器パターン220iを示す。
(Modification of resonator pattern)
FIG. 19 shows a modification of the resonator pattern. FIG. 19A shows a λ / 2 resonator pattern 220d, and FIG. 19B shows a λ / 4 resonator pattern 220e with one end grounded. FIG. 20 shows a modification of the resonator pattern, in which (a) shows a ring-shaped resonator pattern 220f, (b) shows a circular resonator pattern 220g, and (c) shows a rectangular shape. A resonator pattern 220h is shown. FIG. 21 is a modification of the resonator pattern, and shows a dual mode resonator pattern 220i that forms a band-pass filter by generating two resonance modes.
 上記した例では、共振器層220に共振器パターン220a~220cを形成したが、これに換えて、図19~21に変形例として示す種々の共振器パターンを形成してもよい。 In the above example, the resonator patterns 220a to 220c are formed in the resonator layer 220, but various resonator patterns shown as modified examples in FIGS. 19 to 21 may be formed instead.
 以上のように、この実施形態においても、上記第1実施形態と同様の効果を奏することができる。 As described above, also in this embodiment, the same effects as in the first embodiment can be obtained.
 <第4実施形態>
 次に、本発明の電子部品の第4実施形態たる多層チップ型共振器素子1aについて、図22を参照して説明する。図22は本発明の電子部品の第4実施形態たる多層チップ型共振器素子1aを示す図であって、(a)は断面図、(b)は平面図である。
<Fourth embodiment>
Next, a multilayer chip resonator element 1a according to a fourth embodiment of the electronic component of the present invention will be described with reference to FIG. 22A and 22B are views showing a multilayer chip resonator element 1a according to a fourth embodiment of the electronic component of the present invention, in which FIG. 22A is a cross-sectional view and FIG. 22B is a plan view.
 この第4実施形態が、上記第1実施形態と異なる点は、図22に示すように、磁性体樹脂層3の上面に金属膜層6をさらに備えている点である。その他の構成は上記第1実施形態と同様であるため、その構成の説明は同一符号を付すことにより省略する。 The fourth embodiment is different from the first embodiment in that a metal film layer 6 is further provided on the upper surface of the magnetic resin layer 3 as shown in FIG. Since the other configuration is the same as that of the first embodiment, description of the configuration is omitted by attaching the same reference numerals.
 図22(a),(b)に示すように、金属膜層6は、上面視においてコイルパターン20aの少なくとも一部と重なるように設けられている。そして、金属膜層6と接地電極Gとがビア構造の層間接続導体6aにより接続されている。 22A and 22B, the metal film layer 6 is provided so as to overlap with at least a part of the coil pattern 20a in a top view. The metal film layer 6 and the ground electrode G are connected by an interlayer connection conductor 6a having a via structure.
 ところで、電子部品内部に形成された共振器パターンやフィルタ回路のコイルパターンからは磁界が発生するが、発生した磁界が電子部品の外部に放射されることで、電子部品に近接配置された他の電子部品に干渉し、当該部品の特性を変動させるおそれがある。また、電子部品に外部から磁界が侵入することで、電子部品に設けられたコイルや共振器の特性が変動するおそれもある。 By the way, although a magnetic field is generated from the resonator pattern formed inside the electronic component and the coil pattern of the filter circuit, the generated magnetic field is radiated to the outside of the electronic component, so that other electronic components arranged close to the electronic component There is a risk of interfering with an electronic component and changing the characteristics of the component. In addition, when a magnetic field enters the electronic component from the outside, the characteristics of the coil or resonator provided in the electronic component may change.
 そこで、この実施形態によれば、磁性体樹脂層3の上面に、上面視においてコイルパターン20aの少なくとも一部と重なるように金属膜層6が設けられているため、金属膜層6を接地することで、コイルから生じる輻射や放射を抑制することができる。また、外部から磁界が侵入することによる回路パターンの特性変化を抑制することができる。 Therefore, according to this embodiment, since the metal film layer 6 is provided on the upper surface of the magnetic resin layer 3 so as to overlap at least a part of the coil pattern 20a in a top view, the metal film layer 6 is grounded. Thus, radiation and radiation generated from the coil can be suppressed. In addition, it is possible to suppress a change in circuit pattern characteristics caused by a magnetic field entering from the outside.
 <第5実施形態>
 次に、本発明の電子部品の第5実施形態について、図23を参照して説明する。図23は本発明の電子部品の第5実施形態を示す図である。
<Fifth Embodiment>
Next, a fifth embodiment of the electronic component of the present invention will be described with reference to FIG. FIG. 23 is a view showing a fifth embodiment of the electronic component of the present invention.
 この第5実施形態が、上記第1ないし第4実施形態と異なる点は、図23に示すように、磁性体樹脂層303が透磁率μrの異なる2つの層により形成されている点である。その他の構成は上記第1ないし第4実施形態と同様であるため、その構成の説明は相当符号を付すことにより省略する。 The fifth embodiment is different from the first to fourth embodiments in that the magnetic resin layer 303 is formed of two layers having different magnetic permeability μr as shown in FIG. Since other configurations are the same as those of the first to fourth embodiments, description of the configurations will be omitted by attaching corresponding reference numerals.
 図23に示すように、この実施形態の電子部品300は、多層基板302と、磁性体樹脂層303とを備えている。そして、磁性体樹脂層303は、透磁率μrの異なる2つの層303b,303aにより構成されている。 As shown in FIG. 23, the electronic component 300 of this embodiment includes a multilayer substrate 302 and a magnetic resin layer 303. The magnetic resin layer 303 is composed of two layers 303b and 303a having different magnetic permeability μr.
 このように構成すれば、上記第1実施形態と同様の効果を奏することができ、さらに、磁性体樹脂層303を、透磁率μrの異なる複数の層303a,303bにより形成することで、より効率よく磁性体樹脂層303の透磁率μrを調整することができる。例えば、層303bの透磁率μrを大きくしたり、磁性損失が大きくなるように構成することで、コイルからの輻射や放射を抑制することができる。 If configured in this manner, the same effects as those of the first embodiment can be obtained, and the magnetic resin layer 303 is formed by a plurality of layers 303a and 303b having different magnetic permeability μr, thereby further improving the efficiency. The magnetic permeability μr of the magnetic resin layer 303 can be adjusted well. For example, it is possible to suppress radiation and radiation from the coil by increasing the magnetic permeability μr of the layer 303b or increasing the magnetic loss.
 なお、この実施形態では、磁性体樹脂層303が、2つの層303a,303bにより形成されるように構成したが、さらに透磁率μrの異なる層を増やして磁性体樹脂層303を構成してもよい。 In this embodiment, the magnetic resin layer 303 is formed by the two layers 303a and 303b. However, the magnetic resin layer 303 may be configured by increasing the number of layers having different magnetic permeability μr. Good.
 <第6実施形態>
 次に、本発明の電子部品の第6実施形態について、図24~図26を参照して説明する。図24は本発明の電子部品の第6施形態の要部拡大図である。図25はヘリカル型コイルの巻数とインダクタンスとの関係の一例を示す図である。図26はヘリカル型コイルの巻数とQ値との関係の一例を示す図である。
<Sixth Embodiment>
Next, a sixth embodiment of the electronic component of the present invention will be described with reference to FIGS. FIG. 24 is an enlarged view of an essential part of the sixth embodiment of the electronic component of the present invention. FIG. 25 is a diagram showing an example of the relationship between the number of turns of the helical coil and the inductance. FIG. 26 is a diagram illustrating an example of the relationship between the number of turns of the helical coil and the Q value.
 この第6実施形態が、上記第1実施形態と異なる点は、図24に示すように、コイルL41を形成するコイルパターン420a~422aが、電子部品400を形成する多層基板402の積層方向にヘリカル状に形成されている点である。その他の構成は上記第1実施形態と同様であるため、その構成の説明は相当符号を付すことにより省略する。 As shown in FIG. 24, the sixth embodiment differs from the first embodiment in that coil patterns 420a to 422a forming a coil L41 are helical in the stacking direction of the multilayer substrate 402 forming the electronic component 400. It is the point formed in the shape. Since the other configuration is the same as that of the first embodiment, description of the configuration is omitted by assigning a corresponding symbol.
 (構成)
 図24に示すように、電子部品400は、積層したセラミックグリーンシートを焼成して形成された多層基板402を備えており、内部にはAgやCuなどの導体パターンにより形成された各種フィルタ回路(図示省略)が設けられている。
(Constitution)
As shown in FIG. 24, an electronic component 400 includes a multilayer substrate 402 formed by firing laminated ceramic green sheets, and various filter circuits (inside with a conductive pattern such as Ag or Cu) ( (Not shown) is provided.
 多層基板402は、第1~第3コイル層420~422を備えており、第1~第3コイル層420~422と、図示省略する接続層や絶縁体(誘電体)層、コンデンサ層、配線層などとが積層されて焼成されることにより一体的に形成されている。また、多層基板402を形成する各層は、上記第1実施形態で説明したセラミックグリーンシートと同様のセラミックグリーンシートにより形成されている。 The multilayer substrate 402 includes first to third coil layers 420 to 422, a first to third coil layers 420 to 422, a connection layer (not shown), an insulator (dielectric) layer, a capacitor layer, and a wiring. The layers are integrally formed by laminating and firing. Each layer forming the multilayer substrate 402 is formed of a ceramic green sheet similar to the ceramic green sheet described in the first embodiment.
 図24に示すように、第1~第3コイル層420~422それぞれにはコイルL41を形成する略コ字状のコイルパターン420a~422aが設けられている。そして、第1~第3コイル層420~422は、それぞれに設けられた略コ字状のコイルパターン420a~422aの開口の向きが交互に逆方向を向くように積層される。 As shown in FIG. 24, the first to third coil layers 420 to 422 are provided with substantially U-shaped coil patterns 420a to 422a that form the coil L41. The first to third coil layers 420 to 422 are laminated so that the directions of the openings of the substantially U-shaped coil patterns 420a to 422a provided in the first to third coil layers 420 to 422 are alternately opposite to each other.
 そして、第1コイル層に設けられたコイルパターン420aの一端420bと、第2コイル層に設けられたコイルパターン421aの一端421bとがビア構造の層間接続導体420cにより接続され、コイルパターン421aの他端421cと、第3コイル層422に設けられたコイルパターン422aの他端422bとがビア構造の層間接続導体421dにより接続されることで、ヘリカル型のコイルL41が形成される。 Then, one end 420b of the coil pattern 420a provided in the first coil layer and one end 421b of the coil pattern 421a provided in the second coil layer are connected by an interlayer connection conductor 420c having a via structure, and other than the coil pattern 421a. The end 421c and the other end 422b of the coil pattern 422a provided on the third coil layer 422 are connected by an interlayer connection conductor 421d having a via structure, thereby forming a helical coil L41.
 なお、電子部品400は、上記第1実施形態で説明した製造方法と同様の方法で製造される。また、略コ字状のコイルパターンが形成された複数のコイル層を上記したように適宜積層することで、任意の巻数を有するコイルL41を容易に形成することができる。 The electronic component 400 is manufactured by a method similar to the manufacturing method described in the first embodiment. Moreover, the coil L41 which has arbitrary turns can be easily formed by laminating | stacking the some coil layer in which the substantially U-shaped coil pattern was formed suitably as mentioned above.
 (コイルL41の巻数とインダクタンスとの関係)
 次に、コイルL41の巻数とインダクタンスとの関係について説明する。図25はコイルL41の巻数とインダクタンスとの関係の一例を示す図であって、◆は磁性体樹脂層が多層基板に設けられていないときのコイルL41の巻数とインダクタンスとの関係を示し、▲は透磁率μr=2の磁性体樹脂層が多層基板に設けられているときのコイルL41の巻数とインダクタンスとの関係を示し、■は透磁率μr=4の磁性体樹脂層が多層基板に設けられているときのコイルL41の巻数とインダクタンスとの関係を示す。
(Relationship between number of turns of coil L41 and inductance)
Next, the relationship between the number of turns of the coil L41 and the inductance will be described. FIG. 25 is a diagram showing an example of the relationship between the number of turns of the coil L41 and the inductance, and ♦ shows the relationship between the number of turns of the coil L41 and the inductance when the magnetic resin layer is not provided on the multilayer substrate. Indicates the relationship between the number of turns of the coil L41 and the inductance when a magnetic resin layer with magnetic permeability μr = 2 is provided on the multilayer substrate, and ■ indicates a magnetic resin layer with magnetic permeability μr = 4 provided on the multilayer substrate. The relationship between the number of turns of the coil L41 and the inductance when it is applied is shown.
 図25に示すように、コイルL41の巻数の二乗に比例してコイルL41のインダクタンスが増大する。また、多層基板に設けられる磁性体樹脂層の透磁率μrを大きくすればコイルL41のインダクタンスは増大する。 As shown in FIG. 25, the inductance of the coil L41 increases in proportion to the square of the number of turns of the coil L41. Further, if the magnetic permeability μr of the magnetic resin layer provided on the multilayer substrate is increased, the inductance of the coil L41 increases.
 (コイルL41の巻数とQ値との関係)
 次に、コイルL41の巻数とQ値との関係について説明する。図26はコイルL41の巻数とQ値との関係の一例を示す図であって、◆は磁性体樹脂層が多層基板に設けられていないときのコイルL41の巻数とQ値との関係を示し、▲は透磁率μr=2の磁性体樹脂層が多層基板に設けられているときのコイルL41の巻数をQ値との関係を示し、■は透磁率μr=4の磁性体樹脂層が多層基板に設けられているときのコイルL41の巻数とQ値との関係を示す。
(Relationship between number of turns of coil L41 and Q value)
Next, the relationship between the number of turns of the coil L41 and the Q value will be described. FIG. 26 is a diagram showing an example of the relationship between the number of turns of the coil L41 and the Q value, and ◆ shows the relationship between the number of turns of the coil L41 and the Q value when the magnetic resin layer is not provided on the multilayer substrate. , ▲ indicate the relationship between the number of turns of the coil L41 and the Q value when the magnetic resin layer having a magnetic permeability μr = 2 is provided on the multilayer substrate, and ■ indicates the multilayer of the magnetic resin layer having the magnetic permeability μr = 4. The relationship between the number of turns of the coil L41 and the Q value when provided on the substrate is shown.
 図26に示すように、コイルL41の巻数が増大するのに伴いコイルL41のQ値も増大する。また、多層基板に設けられる磁性体樹脂層の透磁率μrを大きくすればコイルL41のQ値は増大する。 As shown in FIG. 26, as the number of turns of the coil L41 increases, the Q value of the coil L41 also increases. Further, if the magnetic permeability μr of the magnetic resin layer provided on the multilayer substrate is increased, the Q value of the coil L41 increases.
 以上のように、この実施形態においても、上記第1実施形態と同様の効果を奏することができる。また、コイルパターン420a~422aは多層基板402の積層方向にヘリカル状に形成されているため、コイルL41のインダクタンスは積層方向へのコイルL41の巻き数の二乗に比例して大きくなるが、コイルパターン420a~422aに通電されることで発生する磁束はコイルL41の中心軸に沿った方向に集中する。したがって、多層基板402の少なくとも一方の主面に磁性体樹脂層を設けることで、コイルL41の中心軸に沿った方向に集中して発生する磁束の磁束密度を効率よく大きくすることができるので、コイルL41のインダクタンスをより効率よく調整して大きくすることができる。また、磁性体樹脂層を磁性損失の小さな材質で形成することにより、効率よくコイルL41のQ値を大きくすることができる。 As described above, also in this embodiment, the same effects as in the first embodiment can be obtained. Further, since the coil patterns 420a to 422a are formed in a helical shape in the stacking direction of the multilayer substrate 402, the inductance of the coil L41 increases in proportion to the square of the number of turns of the coil L41 in the stacking direction. Magnetic flux generated by energizing 420a to 422a is concentrated in the direction along the central axis of the coil L41. Therefore, by providing the magnetic resin layer on at least one main surface of the multilayer substrate 402, the magnetic flux density of the magnetic flux generated in a concentrated manner in the direction along the central axis of the coil L41 can be efficiently increased. The inductance of the coil L41 can be adjusted and increased more efficiently. Further, the Q value of the coil L41 can be efficiently increased by forming the magnetic resin layer with a material having a small magnetic loss.
 また、多層基板402の一方の主面に磁性体樹脂層を設けることにより、コイルL41を形成するコイルパターン420a~422aに生じる浮遊容量は、磁性体樹脂層の誘電率εrの影響を受けるが、コイルパターン420a~422aは多層基板402に積層方向に設けられているため、磁性体樹脂層の影響を最も大きく受けるのは、最上面側のコイルパターン420aもしくは最下面側のコイルパターン422aとなる。 Further, by providing the magnetic resin layer on one main surface of the multilayer substrate 402, the stray capacitance generated in the coil patterns 420a to 422a forming the coil L41 is affected by the dielectric constant εr of the magnetic resin layer. Since the coil patterns 420a to 422a are provided in the stacking direction on the multilayer substrate 402, the coil pattern 420a on the uppermost surface side or the coil pattern 422a on the lowermost surface side is most affected by the magnetic resin layer.
 したがって、コイルL41が所定の特性を有するように形成された多層基板402の一方の主面に磁性体樹脂層が設けられても、コイルL41を形成するコイルパターン420a~422aの一部に生じる浮遊容量のみが磁性体樹脂層の誘電率εrの影響を受けるだけであるため、コイルL41の特性は磁性体樹脂層の誘電率εrに大きくは影響されないので、磁性体樹脂層の設計範囲が広がり、磁性体樹脂層を形成するための磁性粉末や樹脂などの材料の選択の幅を広げることができる。 Therefore, even if the magnetic resin layer is provided on one main surface of the multilayer substrate 402 formed so that the coil L41 has a predetermined characteristic, the floating generated in a part of the coil patterns 420a to 422a forming the coil L41. Since only the capacitance is affected only by the dielectric constant εr of the magnetic resin layer, the characteristics of the coil L41 are not greatly influenced by the dielectric constant εr of the magnetic resin layer, so the design range of the magnetic resin layer is expanded, The range of selection of materials such as magnetic powder and resin for forming the magnetic resin layer can be expanded.
 なお、この実施形態では、コイルL41の構成のみについて説明したが、ヘリカル型のコイルL41を用いて、共振器回路やフィルタ回路、バラン回路、方向性結合器、アンテナ回路などの各種電子回路を電子部品400内に形成するとよい。 Although only the configuration of the coil L41 has been described in this embodiment, various electronic circuits such as a resonator circuit, a filter circuit, a balun circuit, a directional coupler, and an antenna circuit are electronically converted using the helical coil L41. It may be formed in the part 400.
 <第7実施形態>
 次に、本発明の電子部品の第7実施形態たる多層チップ型バンドパスフィルタ素子500について、図27~図31を参照して説明する。
<Seventh embodiment>
Next, a multilayer chip type bandpass filter element 500 according to a seventh embodiment of the electronic component of the present invention will be described with reference to FIGS.
 図27は第7実施形態の多層チップ型バンドパスフィルタ素子500を示す図であって、(a)は断面図、(b)~(j)は多層チップ型バンドパスフィルタ素子500を構成する各層503,520~527の平面図である。図28は図27に示す多層チップ型バンドパスフィルタ素子500に設けられたバンドパスフィルタ回路504の等価回路を示す図である。 FIG. 27 is a view showing a multilayer chip type bandpass filter element 500 according to the seventh embodiment, wherein (a) is a cross-sectional view, and (b) to (j) are each layer constituting the multilayer chip type bandpass filter element 500. 5 is a plan view of 503 and 520 to 527. FIG. FIG. 28 is a diagram showing an equivalent circuit of the band-pass filter circuit 504 provided in the multilayer chip type band-pass filter element 500 shown in FIG.
 この第7実施形態が、上記第1実施形態と異なる点は、図27,28に示すように、多層チップ型バンドパスフィルタ(BPF)素子500の内部に設けられた回路構成が異なる点である。 The seventh embodiment is different from the first embodiment in that the circuit configuration provided in the multilayer chip type bandpass filter (BPF) element 500 is different as shown in FIGS. .
 すなわち、本発明の共振器パターンとして、第1コイルL51を有する第1共振器回路504aを形成する第1の共振器パターンと、第2コイルL52を有する第2共振器回路504bを形成する第2の共振器パターンとが、多層基板502に上面視において並べて設けられている。そして、磁性体樹脂層503は、少なくとも第1コイルL51を形成する第1のコイルパターン520aと第2コイルL52を形成する第2のコイルパターン520bとの間に設けられている。その他の構成は上記第1実施形態と同様であるため、その構成の説明は相当符号を付すことにより省略する。 That is, as the resonator pattern of the present invention, the first resonator pattern forming the first resonator circuit 504a having the first coil L51 and the second resonator circuit 504b having the second coil L52 are formed. Are arranged side by side on the multilayer substrate 502 in a top view. The magnetic resin layer 503 is provided at least between the first coil pattern 520a that forms the first coil L51 and the second coil pattern 520b that forms the second coil L52. Since the other configuration is the same as that of the first embodiment, description of the configuration is omitted by assigning a corresponding symbol.
 (構成)
 図27(a)に示すように、多層チップ型BPF素子500は、積層したセラミックグリーンシートを焼成して形成された多層基板502と、多層基板502の一方の主面に設けられた磁性体樹脂層503とを備え、図28に示すように、内部にはAgやCuなどの導体パターンにより形成されたバンドパスフィルタ回路504が設けられている。
(Constitution)
As shown in FIG. 27A, a multilayer chip type BPF element 500 includes a multilayer substrate 502 formed by firing laminated ceramic green sheets, and a magnetic resin provided on one main surface of the multilayer substrate 502. As shown in FIG. 28, a band-pass filter circuit 504 formed of a conductor pattern such as Ag or Cu is provided therein.
 この実施形態のバンドパスフィルタ回路504は、第1共振器回路504aおよび第2共振器回路504bがそれぞれ有する第1コイルL51の第1のコイルパターン520aおよび第2コイルL52の第2のコイルパターン520bが電磁結合されて形成されている。 The band-pass filter circuit 504 of this embodiment includes a first coil pattern 520a of the first coil L51 and a second coil pattern 520b of the second coil L52 that the first resonator circuit 504a and the second resonator circuit 504b have, respectively. Are formed by electromagnetic coupling.
 多層基板502は、第1コイル層520と、第1接続層521と、第1コンデンサ層522と、第2コンデンサ層523と、第2接続層524と、第3コンデンサ層525と、配線層526と、絶縁体(誘電体)層527とが積層されて焼成されることにより一体的に形成されている。また、各層520~527は、上記第1実施形態で説明したセラミックグリーンシートと同様のセラミックグリーンシートにより形成されている。 The multilayer substrate 502 includes a first coil layer 520, a first connection layer 521, a first capacitor layer 522, a second capacitor layer 523, a second connection layer 524, a third capacitor layer 525, and a wiring layer 526. And an insulating (dielectric) layer 527 are laminated and fired to form a single body. Each of the layers 520 to 527 is formed of a ceramic green sheet similar to the ceramic green sheet described in the first embodiment.
 図27(c)に示すように、第1コイル層520には、コイルL51を形成する略L字状の第1のコイルパターン520aと、コイルL52を形成する第2のコイルパターン520bとが設けられている。そして、コイルパターン520aの一端には、第2コンデンサ層523の電極パターン523aおよび第3コンデンサ層525の電極パターン525aと、第1接続層521、第1コンデンサ層522および第2接続層524を介して接続するためのビア構造の層間接続導体520cが設けられている。 As shown in FIG. 27C, the first coil layer 520 is provided with a substantially L-shaped first coil pattern 520a that forms the coil L51 and a second coil pattern 520b that forms the coil L52. It has been. Then, one end of the coil pattern 520a is provided with the electrode pattern 523a of the second capacitor layer 523 and the electrode pattern 525a of the third capacitor layer 525, and the first connection layer 521, the first capacitor layer 522, and the second connection layer 524. An interlayer connection conductor 520c having a via structure is provided.
 また、コイルパターン520bの一端には、第2コンデンサ層523の電極パターン523bおよび第3コンデンサ層525の電極パターン525bと、第1接続層521、第1コンデンサ層522および第2接続層524を介して接続するためのビア構造の層間接続導体520dが設けられている。また、コイルパターン520aおよびコイルパターン520bそれぞれの他端は、外部電極である接地電極に接続される。 In addition, the coil pattern 520b has one end through the electrode pattern 523b of the second capacitor layer 523 and the electrode pattern 525b of the third capacitor layer 525, and the first connection layer 521, the first capacitor layer 522, and the second connection layer 524. An interlayer connection conductor 520d having a via structure is provided. The other end of each of the coil pattern 520a and the coil pattern 520b is connected to a ground electrode that is an external electrode.
 図27(d)に示すように、第1接続層521には、第1コイル層520の第1のコイルパターン520aの一端と、第2コンデンサ層523の電極パターン523aおよび第3コンデンサ層525の電極パターン525aとを接続するためのビア構造の層間接続導体521aが設けられている。また、第1接続層521には、第1コイル層520の第2のコイルパターン520bの一端と、第2コンデンサ層523の電極パターン523bおよび第3コンデンサ層525の電極パターン525bとを接続するためのビア構造の層間接続導体521bが設けられている。 As shown in FIG. 27D, the first connection layer 521 includes one end of the first coil pattern 520a of the first coil layer 520, the electrode pattern 523a of the second capacitor layer 523, and the third capacitor layer 525. An interlayer connection conductor 521a having a via structure for connecting to the electrode pattern 525a is provided. In addition, one end of the second coil pattern 520b of the first coil layer 520, the electrode pattern 523b of the second capacitor layer 523, and the electrode pattern 525b of the third capacitor layer 525 are connected to the first connection layer 521. An interlayer connection conductor 521b having a via structure is provided.
 また、図27(e)に示すように、第1コンデンサ層522には、コンデンサC52の他方の電極を形成する電極パターン522aが設けられており、電極パターン522aと、第2コンデンサ層523に設けられた電極パターン523aとによりコンデンサC52が形成される。また、第1コンデンサ層522には、コンデンサC54の他方の電極を形成する電極パターン522bが設けられており、電極パターン522bと、第2コンデンサ層523に設けられた電極パターン523bとによりコンデンサC54が形成される。また、電極パターン522aおよび電極パターン522bはそれぞれ外部電極である接地電極に接続される。 As shown in FIG. 27E, the first capacitor layer 522 is provided with an electrode pattern 522a that forms the other electrode of the capacitor C52. The electrode pattern 522a and the second capacitor layer 523 are provided. A capacitor C52 is formed by the electrode pattern 523a. The first capacitor layer 522 is provided with an electrode pattern 522b that forms the other electrode of the capacitor C54. The capacitor C54 is formed by the electrode pattern 522b and the electrode pattern 523b provided on the second capacitor layer 523. It is formed. Electrode pattern 522a and electrode pattern 522b are each connected to a ground electrode which is an external electrode.
 また、第1コンデンサ層522には、第1コイル層520の第1のコイルパターン520aの一端と、第2コンデンサ層523の電極パターン523aおよび第3コンデンサ層525の電極パターン525aとを接続するためのビア構造の層間接続導体522cが設けられている。また、第1コンデンサ層522には、第1コイル層520の第2のコイルパターン520bの一端と、第2コンデンサ層523の電極パターン523bおよび第3コンデンサ層525の電極パターン525bとを接続するためのビア構造の層間接続導体522dが設けられている。 The first capacitor layer 522 is connected to one end of the first coil pattern 520a of the first coil layer 520, the electrode pattern 523a of the second capacitor layer 523, and the electrode pattern 525a of the third capacitor layer 525. An interlayer connection conductor 522c having a via structure is provided. The first capacitor layer 522 is connected to one end of the second coil pattern 520b of the first coil layer 520, the electrode pattern 523b of the second capacitor layer 523, and the electrode pattern 525b of the third capacitor layer 525. An interlayer connection conductor 522d having a via structure is provided.
 また、図27(f)に示すように、第2コンデンサ層523には、コンデンサC52の一方の電極を形成する電極パターン523aと、コンデンサC54の一方の電極を形成する電極パターン523bとが設けられている。 As shown in FIG. 27F, the second capacitor layer 523 is provided with an electrode pattern 523a for forming one electrode of the capacitor C52 and an electrode pattern 523b for forming one electrode of the capacitor C54. ing.
 図27(g)に示すように、第2接続層524には、第1コイル層520の第1のコイルパターン520aの一端と、第2コンデンサ層523の電極パターン523aおよび第3コンデンサ層525の電極パターン525aとを接続するためのビア構造の層間接続導体524aが設けられている。また、第2接続層524には、第1コイル層520の第2のコイルパターン520bの一端と、第2コンデンサ層523の電極パターン523bおよび第3コンデンサ層525の電極パターン525bとを接続するためのビア構造の層間接続導体524bが設けられている。 As shown in FIG. 27G, the second connection layer 524 includes one end of the first coil pattern 520a of the first coil layer 520, the electrode pattern 523a of the second capacitor layer 523, and the third capacitor layer 525. An interlayer connection conductor 524a having a via structure for connecting to the electrode pattern 525a is provided. The second connection layer 524 is connected to one end of the second coil pattern 520b of the first coil layer 520, the electrode pattern 523b of the second capacitor layer 523, and the electrode pattern 525b of the third capacitor layer 525. An interlayer connection conductor 524b having a via structure is provided.
 また、図27(h)に示すように、第3コンデンサ層525には、コンデンサC51の一方の電極を形成する電極パターン525aが設けられており、電極パターン525aと、配線層526に設けられた電極パターン526aとによりコンデンサC51が形成される。また、第3コンデンサ層525には、コンデンサC53の一方の電極を形成する電極パターン525bが設けられており、電極パターン525bと、配線層526に設けられた電極パターン526bとによりコンデンサC53が形成される。 As shown in FIG. 27 (h), the third capacitor layer 525 is provided with an electrode pattern 525a that forms one electrode of the capacitor C51, and is provided in the electrode pattern 525a and the wiring layer 526. A capacitor C51 is formed by the electrode pattern 526a. The third capacitor layer 525 is provided with an electrode pattern 525b that forms one electrode of the capacitor C53, and the capacitor C53 is formed by the electrode pattern 525b and the electrode pattern 526b provided on the wiring layer 526. The
 図27(i)に示すように、配線層526には、コンデンサC51の他方の電極を形成する電極パターン526aと、コンデンサC53の他方の電極を形成する電極パターン526bとが設けられている。また、電極パターン526aは外部電極である入力電極P51に接続され、電極パターン526bは外部電極である出力電極P52に接続されて、バンドパスフィルタ回路504が形成されている。また、図12(j)に示すように、絶縁体層527は、各電極パターンの間隔を調整するために設けられている。 As shown in FIG. 27 (i), the wiring layer 526 is provided with an electrode pattern 526a that forms the other electrode of the capacitor C51 and an electrode pattern 526b that forms the other electrode of the capacitor C53. The electrode pattern 526a is connected to the input electrode P51 which is an external electrode, and the electrode pattern 526b is connected to the output electrode P52 which is an external electrode, thereby forming a band-pass filter circuit 504. Further, as shown in FIG. 12 (j), the insulator layer 527 is provided for adjusting the interval between the electrode patterns.
 図27(b)に示すように、磁性体樹脂層503は、上記第1実施形態で説明した磁性体樹脂と同様の磁性体樹脂により形成されており、第1コイル層520の第1のコイルパターン520aと第2のコイルパターン520bとの間に配置される。 As shown in FIG. 27B, the magnetic resin layer 503 is formed of the same magnetic resin as the magnetic resin described in the first embodiment, and the first coil of the first coil layer 520 is formed. It arrange | positions between the pattern 520a and the 2nd coil pattern 520b.
 なお、多層チップ型BPF素子500は、上記第1実施形態で説明した製造方法と同様の方法で製造される。 The multilayer chip type BPF element 500 is manufactured by a method similar to the manufacturing method described in the first embodiment.
 (バンドパスフィルタの周波数特性)
 次に、多層チップ型BPF素子500の周波数特性について説明する。図29は図27に示す多層チップ型BPF素子500の周波数特性の一例を示す図であって、(a)はコイルL51とコイルL52との間の電磁結合における結合係数K=0.4のときの周波数特性を示し、(b)はコイルL51とコイルL52との間の電磁結合における結合係数K=0.5のときの周波数特性を示し、(c)はコイルL51とコイルL52との間の電磁結合における結合係数K=0.6のときの周波数特性を示す。また、図29(a)~(c)それぞれの、上側の曲線は反射特性を示し、下側の曲線は通過特性を示す。
(Frequency characteristics of bandpass filter)
Next, frequency characteristics of the multilayer chip type BPF element 500 will be described. FIG. 29 is a diagram showing an example of frequency characteristics of the multilayer chip type BPF element 500 shown in FIG. 27. FIG. 29A shows a case where the coupling coefficient K = 0.4 in the electromagnetic coupling between the coil L51 and the coil L52. (B) shows the frequency characteristic when the coupling coefficient K = 0.5 in the electromagnetic coupling between the coil L51 and the coil L52, and (c) shows the frequency characteristic between the coil L51 and the coil L52. The frequency characteristic when the coupling coefficient K in electromagnetic coupling is 0.6 is shown. In each of FIGS. 29A to 29C, the upper curve indicates the reflection characteristic, and the lower curve indicates the transmission characteristic.
 図29に示すように、多層チップ型BPF素子500を形成するコイルL51,L52の電磁結合における結合係数Kが変化することにより、多層チップ型BPF素子500の周波数特性は変化する。 As shown in FIG. 29, when the coupling coefficient K in the electromagnetic coupling of the coils L51 and L52 forming the multilayer chip type BPF element 500 is changed, the frequency characteristics of the multilayer chip type BPF element 500 are changed.
 (コイルパターンの変形例)
 次に、コイルパターンの変形例の一例について説明する。図30はコイルパターンの変形例の一例を示す図であって、(a)はこの実施形態におけるコイルパターン520a,520bを示し、(b)は多層基板502の積層方向に形成されたビア構造によるコイルパターン520e,520fを示す。
(Coil pattern modification)
Next, an example of a modification of the coil pattern will be described. FIG. 30 is a view showing an example of a modification of the coil pattern. FIG. 30A shows the coil patterns 520a and 520b in this embodiment, and FIG. 30B shows a via structure formed in the stacking direction of the multilayer substrate 502. Coil patterns 520e and 520f are shown.
 この実施形態では、図30(a)に示すように、上面視において略L字状のコイルパターン520a,520bが並べて設けられており、コイルパターン520aとコイルパターン520bとの間に磁性体樹脂層503が設けられている。 In this embodiment, as shown in FIG. 30A, substantially L-shaped coil patterns 520a and 520b are provided side by side in a top view, and a magnetic resin layer is provided between the coil pattern 520a and the coil pattern 520b. 503 is provided.
 一方、図30(b)に示すように、多層基板502の積層方向に設けられたビア構造によるコイルパターン520e,520fを、上面視において並べて形成してもよい。そして、コイルパターン520eとコイルパターン520fとの間に磁性体樹脂層503を設けるとよい。 On the other hand, as shown in FIG. 30B, coil patterns 520e and 520f having a via structure provided in the stacking direction of the multilayer substrate 502 may be formed side by side in a top view. And it is good to provide the magnetic body resin layer 503 between the coil pattern 520e and the coil pattern 520f.
 (磁性体樹脂層による結合係数の調整)
 次に、磁性体樹脂層503を設けることにより、コイルL51およびコイルL52の電磁結合における結合係数が調整されることについて図31を参照して説明する。図31は多層基板に磁性体樹脂層503を設けることによる効果を説明するための図であって、(a)はコイルにより発生する磁束MFの様子を示す図、(b)は磁性体樹脂層503が設けられた状態を示す図、(c)は多層基板に磁性体樹脂層503が設けられることによる磁束MFの変化を示す図である。
(Adjustment of coupling coefficient by magnetic resin layer)
Next, it will be described with reference to FIG. 31 that the coupling coefficient in the electromagnetic coupling between the coil L51 and the coil L52 is adjusted by providing the magnetic resin layer 503. 31A and 31B are diagrams for explaining the effect of providing the magnetic resin layer 503 on the multilayer substrate, wherein FIG. 31A is a diagram showing a state of the magnetic flux MF generated by the coil, and FIG. 31B is a magnetic resin layer. FIG. 5C is a diagram illustrating a state in which a magnetic resin layer 503 is provided on a multilayer substrate, and FIG. 5C is a diagram illustrating a change in magnetic flux MF.
 図31(a)に示すように、ビア構造によりコイルパターン520e,520fが形成されると、各コイルパターン520e,520fを中心とする同心円状に磁束MFが発生し、この磁束MFによりコイルパターン520e,520f間に電磁結合が生じる。このとき、図31(b)に示すように、コイルパターン520e,520f間に磁性体樹脂層503が設けられると、両コイルパターン520e,520fにより発生する磁束MFが透磁率の大きい磁性体樹脂層503に集中する。 As shown in FIG. 31A, when the coil patterns 520e and 520f are formed by the via structure, the magnetic flux MF is generated concentrically around the coil patterns 520e and 520f, and the coil pattern 520e is generated by the magnetic flux MF. , 520f is electromagnetically coupled. At this time, as shown in FIG. 31 (b), when the magnetic resin layer 503 is provided between the coil patterns 520e and 520f, the magnetic resin layer having a high magnetic permeability for the magnetic flux MF generated by both the coil patterns 520e and 520f. Concentrate on 503.
 すなわち、図31(c)に示すように、両コイルパターン520e,520f間に生じた磁束MFが、それぞれ同図中矢印で示すように、コイルパターン520e,520fの方向に移動する。したがって、コイルパターン520e,520f間の電磁結合が弱められる。これにより、磁性体樹脂層503への磁束MFの集中度は磁性体樹脂層503の透磁率μrに依存するため、透磁率μrの異なる磁性体樹脂層503を多層基板502に設けることにより、コイルパターン520e,520f間の電磁結合における結合係数を調整することができる。 That is, as shown in FIG. 31 (c), the magnetic flux MF generated between the two coil patterns 520e and 520f moves in the direction of the coil patterns 520e and 520f, respectively, as indicated by arrows in the figure. Therefore, the electromagnetic coupling between the coil patterns 520e and 520f is weakened. As a result, the concentration of the magnetic flux MF on the magnetic resin layer 503 depends on the magnetic permeability μr of the magnetic resin layer 503. Therefore, by providing the multilayer resin 502 with the magnetic resin layer 503 having different magnetic permeability μr, the coil The coupling coefficient in the electromagnetic coupling between the patterns 520e and 520f can be adjusted.
 以上のように、この実施形態においても、上記第1実施形態と同様の効果を奏することができると共に以下の効果を奏することができる。すなわち、共振器パターンとして、第1コイルL51を有する第1共振器回路504aを形成する第1の共振器パターンと、第2コイルL52を有する第2共振器回路504bを形成する第2の共振器パターンとが、多層基板502に上面視において並べて設けられることにより、第1コイルL51を形成する第1のコイルパターン520aと第2コイルL52を形成する第2のコイルパターン520bとが電磁結合されて各種フィルタ回路(BPF回路504)を形成することができる。 As described above, also in this embodiment, the same effects as in the first embodiment can be obtained and the following effects can be obtained. That is, as the resonator pattern, the first resonator pattern forming the first resonator circuit 504a having the first coil L51 and the second resonator forming the second resonator circuit 504b having the second coil L52. By arranging the patterns on the multilayer substrate 502 in a top view, the first coil pattern 520a that forms the first coil L51 and the second coil pattern 520b that forms the second coil L52 are electromagnetically coupled. Various filter circuits (BPF circuit 504) can be formed.
 このとき、第1コイルL51を形成する第1のコイルパターン520aと第2コイルL52を形成する第2のコイルパターン520bとの間に磁性体樹脂層503を設けることにより、第1コイルL51および第2コイルL52に発生する磁束MFが透磁率μrの大きい磁性体樹脂層503に集中するため、互いのコイルL51,L52で発生する磁束MFによる電磁結合が阻害されて、第1コイルL51と第2コイルL52との間の電磁結合が弱められて結合係数Kが小さくなる。磁性体樹脂層503への磁束MFの集中度は磁性体樹脂層503の透磁率μrに依存するため、第1コイルL51および第2コイルL52間の電磁結合における結合係数Kを、透磁率μrの異なる磁性体樹脂層503を多層基板502に設けるだけで簡単に調整することができる。 At this time, by providing the magnetic resin layer 503 between the first coil pattern 520a forming the first coil L51 and the second coil pattern 520b forming the second coil L52, the first coil L51 and the first coil L51 Since the magnetic flux MF generated in the two coils L52 concentrates on the magnetic resin layer 503 having a high permeability μr, electromagnetic coupling by the magnetic flux MF generated in the coils L51 and L52 is inhibited, and the first coil L51 and the second coil L52 The electromagnetic coupling with the coil L52 is weakened and the coupling coefficient K is reduced. Since the degree of concentration of the magnetic flux MF on the magnetic resin layer 503 depends on the magnetic permeability μr of the magnetic resin layer 503, the coupling coefficient K in the electromagnetic coupling between the first coil L51 and the second coil L52 is determined by the magnetic permeability μr. Adjustment can be made simply by providing different magnetic resin layers 503 on the multilayer substrate 502.
 また、第1コイルL51と第2コイルL52との間の電磁結合を弱めたい場合に、第1コイルL51と第2コイルL52との距離を物理的に離さなくとも、多層基板502に磁性体樹脂層503を設けるだけで電磁結合を弱めることができるため、多層チップ型BPF素子500の小型化を図ることができる。 Further, when it is desired to weaken the electromagnetic coupling between the first coil L51 and the second coil L52, the magnetic resin is applied to the multilayer substrate 502 without physically separating the first coil L51 and the second coil L52. Since the electromagnetic coupling can be weakened only by providing the layer 503, the multilayer chip BPF element 500 can be downsized.
 また、磁性体損が小さい磁性体樹脂層を設けることにより、漏れ電流損を小さくしてコイルのQ値の増大を図ることもできる(例えば、磁性体樹脂層のtanδ<0.1)。 Also, by providing a magnetic resin layer with a small magnetic loss, the leakage current loss can be reduced and the Q value of the coil can be increased (for example, tan δ <0.1 of the magnetic resin layer).
 <第8実施形態>
 次に、本発明の電子部品の第8実施形態たる多層チップ型バンドパスフィルタ素子について、図32を参照して説明する。
<Eighth Embodiment>
Next, a multilayer chip type bandpass filter device according to an eighth embodiment of the electronic component of the present invention will be described with reference to FIG.
 (構成)
 図32は本発明の電子部品の第8実施形態たる多層チップ型バンドパスフィルタ素子に設けられたバンドパスフィルタ回路604の等価回路を示す図である。この第8実施形態が、上記第7実施形態と異なる点は、図32に示すように、多層チップ型バンドパスフィルタ(BPF)素子内部に設けられた回路構成が異なる点である。
(Constitution)
FIG. 32 is a diagram showing an equivalent circuit of a band-pass filter circuit 604 provided in the multilayer chip type band-pass filter element according to the eighth embodiment of the electronic component of the present invention. The eighth embodiment differs from the seventh embodiment in that the circuit configuration provided in the multilayer chip type bandpass filter (BPF) element is different as shown in FIG.
 すなわち、第1共振器回路604aを形成する第1コイルL61と、第2共振器回路604bを形成する第2コイルL62とがコンデンサC65により結合されている。その他の構成は上記第7実施形態と同様であるため、その構成の説明は相当符号を付すことにより省略する。 That is, the first coil L61 forming the first resonator circuit 604a and the second coil L62 forming the second resonator circuit 604b are coupled by the capacitor C65. Since the other configuration is the same as that of the seventh embodiment, description of the configuration is omitted by assigning a corresponding symbol.
 (バンドパスフィルタの周波数特性)
 次に、多層チップ型BPF素子の周波数特性について説明する。図33は図32に示す多層チップ型バンドパスフィルタ素子の周波数特性の一例を示す図であって、(a)はコイルL61とコイルL62との間の電磁結合における結合係数K=0.4のときの周波数特性を示し、(b)はコイルL61とコイルL62との間の電磁結合における結合係数K=0.5のときの周波数特性を示し、(c)はコイルL61とコイルL62との間の電磁結合における結合係数K=0.6のときの周波数特性を示す。また、図33(a)~(c)それぞれの、上側の曲線は反射特性を示し、下側の曲線は通過特性を示す。
(Frequency characteristics of bandpass filter)
Next, frequency characteristics of the multilayer chip type BPF element will be described. FIG. 33 is a diagram showing an example of frequency characteristics of the multilayer chip type bandpass filter element shown in FIG. 32. FIG. 33A shows a coupling coefficient K = 0.4 in electromagnetic coupling between the coil L61 and the coil L62. (B) shows the frequency characteristic when the coupling coefficient K = 0.5 in the electromagnetic coupling between the coil L61 and the coil L62, and (c) shows the frequency characteristic between the coil L61 and the coil L62. The frequency characteristic when the coupling coefficient K = 0.6 in the electromagnetic coupling is shown. Further, in each of FIGS. 33A to 33C, the upper curve indicates the reflection characteristic, and the lower curve indicates the transmission characteristic.
 図33に示すように、多層チップ型BPF素子500を形成するコイルL61,L62の電磁結合における結合係数Kが変化することにより、多層チップ型BPF素子500の周波数特性は変化する。 33, the frequency characteristic of the multilayer chip type BPF element 500 changes as the coupling coefficient K in the electromagnetic coupling of the coils L61 and L62 forming the multilayer chip type BPF element 500 changes.
 以上のように、この実施形態においても、上記第7実施形態と同様の効果を奏することができる。 As described above, this embodiment can achieve the same effects as those of the seventh embodiment.
 <第9実施形態>
 次に、本発明の電子部品の第9実施形態たる多層チップ型バンドパスフィルタ素子600について、図34を参照して説明する。図34は本発明の電子部品の第9実施形態たる多層チップ型バンドパスフィルタ素子600を示す図であって(a)は平面図、(b)は断面図、(c)は周波数特性の一例を示す図である。
<Ninth Embodiment>
Next, a multilayer chip type bandpass filter device 600 according to a ninth embodiment of the electronic component of the present invention will be described with reference to FIG. 34A and 34B are diagrams showing a multilayer chip type bandpass filter element 600 according to the ninth embodiment of the electronic component of the present invention, wherein FIG. 34A is a plan view, FIG. 34B is a cross-sectional view, and FIG. FIG.
 (構成)
 この第9実施形態が、上記第7実施形態と大きく異なる点は、図34(a),(b)に示すように、多層基板602の一方の主面に上面視において並べて設けられた第1のコイルパターン620aと第2のコイルパターン620bとの間にキャビティ610が設けられており、キャビティ610に磁性体樹脂層603が充填されている点である。その他の構成は上記第7実施形態と同様であるため、その構成の説明は相当符号を付すことにより省略する。
(Constitution)
The ninth embodiment differs greatly from the seventh embodiment in that the first embodiment provided side by side on one main surface of the multilayer substrate 602 as shown in FIGS. 34 (a) and 34 (b). A cavity 610 is provided between the coil pattern 620 a and the second coil pattern 620 b, and the magnetic resin layer 603 is filled in the cavity 610. Since the other configuration is the same as that of the seventh embodiment, description of the configuration is omitted by assigning a corresponding symbol.
 (バンドパスフィルタの周波数特性)
 次に、多層チップ型BPF素子600の周波数特性について説明する。図34(c)は磁性体樹脂層603の有無による周波数特性を示し、上側の曲線は反射特性を示し、下側の曲線は通過特性を示す。
(Frequency characteristics of bandpass filter)
Next, frequency characteristics of the multilayer chip type BPF element 600 will be described. FIG. 34C shows the frequency characteristics depending on the presence or absence of the magnetic resin layer 603, the upper curve shows the reflection characteristics, and the lower curve shows the pass characteristics.
 図34(c)に示すように、多層チップ型BPF素子500を形成するコイルパターン620a,620b間に磁性体樹脂層603を設けることにより、通過周波数における挿入損失が大きくなり、第1のコイルパターン620aと第2のコイルパターン620bとの間の電磁結合が弱くなることが分かる。 As shown in FIG. 34 (c), by providing the magnetic resin layer 603 between the coil patterns 620a and 620b forming the multilayer chip type BPF element 500, the insertion loss at the passing frequency increases, and the first coil pattern It can be seen that the electromagnetic coupling between 620a and the second coil pattern 620b is weak.
 以上のように、この実施形態においても、上記第7実施形態と同様の効果を奏することができると共に、以下の効果を奏することができる。すなわち、第1コイルを形成する第1のコイルパターン620aと第2コイルを形成する第2のコイルパターン620bとの間に配置されるキャビティ610が多層基板602に設けられており、キャビティ610に磁性体樹脂層603が充填されているため、第1コイルおよび第2コイルで発生する磁束がキャビティ610に充填された磁性体樹脂層603に集中することにより、当該磁性体樹脂層603が電磁シールドとして機能するため、第1コイルと第2コイルとの間の電磁結合における結合係数をさらに小さくすることができる。このとき、磁性体樹脂層603の透磁率μrを大きくすることで、第1コイルと第2コイルとの間の電磁結合をほぼ解消することも可能となる。 As described above, also in this embodiment, the same effects as in the seventh embodiment can be obtained, and the following effects can be obtained. That is, a cavity 610 disposed between the first coil pattern 620a that forms the first coil and the second coil pattern 620b that forms the second coil is provided in the multilayer substrate 602, and the cavity 610 has a magnetic property. Since the body resin layer 603 is filled, the magnetic flux generated in the first coil and the second coil concentrates on the magnetic body resin layer 603 filled in the cavity 610, so that the magnetic body resin layer 603 serves as an electromagnetic shield. Since it functions, the coupling coefficient in the electromagnetic coupling between the first coil and the second coil can be further reduced. At this time, by increasing the magnetic permeability μr of the magnetic resin layer 603, the electromagnetic coupling between the first coil and the second coil can be substantially eliminated.
 <その他>
 次に、多層基板の一方の主面に磁性体樹脂層を設ける構成の変形例について、図35~図39を参照して説明する。図35~図39は多層基板に設けられる磁性体樹脂層の変形例を示す図であって、各図の(a)はそれぞれ平面図を示し、各図の(b)はそれぞれ断面図を示す。なお、以下の説明においては、上記実施形態と同様の構成については同一符号を付すことによりその構成の説明は省略する。
<Others>
Next, a modified example of the configuration in which the magnetic resin layer is provided on one main surface of the multilayer substrate will be described with reference to FIGS. FIG. 35 to FIG. 39 are views showing modifications of the magnetic resin layer provided on the multilayer substrate, in which (a) of each figure shows a plan view and (b) of each figure shows a sectional view. . In the following description, the same components as those in the above embodiment are denoted by the same reference numerals, and the description of the components is omitted.
 図35に示すように、多層チップ型BPF素子600の多層基板602の一方の主面に設けられたキャビティ610に、磁性体樹脂をキャビティ610から溢れないように充填することにより磁性体樹脂層603aを形成してもよい。 As shown in FIG. 35, the magnetic resin layer 603a is filled by filling the cavity 610 provided on one main surface of the multilayer substrate 602 of the multilayer chip type BPF element 600 so as not to overflow the cavity 610. May be formed.
 図36に示すように、電子部品700の多層基板702の一方の主面にマスク層705を設け、マスク層705により形成される凹部に、第1のコイルパターン720aおよび第2のコイルパターン720bの全体が覆われるように磁性体樹脂を充填することにより磁性体樹脂層703を形成してもよい。 As shown in FIG. 36, a mask layer 705 is provided on one main surface of the multilayer substrate 702 of the electronic component 700, and the first coil pattern 720a and the second coil pattern 720b are formed in the recess formed by the mask layer 705. The magnetic resin layer 703 may be formed by filling a magnetic resin so that the whole is covered.
 図37に示すように、電子部品800の多層基板802の一方の主面にマスク層805と、第1のコイルパターン820aおよび第2のコイルパターン820b間に配置されるキャビティ810とを設け、マスク層805およびキャビティ810により形成される凹部に磁性体樹脂を充填することにより磁性体樹脂層803を形成してもよい。 As shown in FIG. 37, a mask layer 805 and a cavity 810 disposed between the first coil pattern 820a and the second coil pattern 820b are provided on one main surface of the multilayer substrate 802 of the electronic component 800, and the mask The magnetic resin layer 803 may be formed by filling a concave portion formed by the layer 805 and the cavity 810 with a magnetic resin.
 図38に示すように、電子部品900の多層基板902の積層方向に形成されたビア構造による第1のコイルパターン920aおよび第2のコイルパターン920bが設けられているときに、多層基板902の一方の主面にマスク層905を設け、マスク層905により形成される凹部に磁性体樹脂を充填することにより磁性体樹脂層903を形成してもよい。 As shown in FIG. 38, when the first coil pattern 920a and the second coil pattern 920b having a via structure formed in the stacking direction of the multilayer substrate 902 of the electronic component 900 are provided, one of the multilayer substrates 902 The magnetic layer 903 may be formed by providing a mask layer 905 on the main surface and filling a concave portion formed by the mask layer 905 with a magnetic resin.
 図39に示すように、電子部品1000の多層基板1002の積層方向に形成されたビア構造による第1のコイルパターン1020aおよび第2のコイルパターン1020bが設けられているときに、多層基板1002の一方の主面の第1のコイルパターン1020aと第2のコイルパターン1020bとの間にキャビティ1010を設け、キャビティ1010に磁性体樹脂を充填することにより磁性体樹脂層1003を形成してもよい。 As shown in FIG. 39, when the first coil pattern 1020a and the second coil pattern 1020b having a via structure formed in the stacking direction of the multilayer substrate 1002 of the electronic component 1000 are provided, one of the multilayer substrates 1002 Alternatively, the magnetic resin layer 1003 may be formed by providing a cavity 1010 between the first coil pattern 1020a and the second coil pattern 1020b on the main surface and filling the cavity 1010 with a magnetic resin.
 なお、本発明は上記した実施形態に限定されるものではなく、その趣旨を逸脱しない限りにおいて、上記したもの以外に種々の変更を行なうことが可能であり、例えば、大きなインダクタンスが必要な磁性体樹脂層の効果を得たいコイルパターンのみを、磁性体樹脂層の内部または磁性体樹脂層および誘電体セラミック層の境界の近傍に配置し、その他のコイルパターンは多層基板(誘電体セラミック層)の内部に配置するようにしてもよい。 The present invention is not limited to the above-described embodiment, and various modifications other than those described above can be made without departing from the spirit thereof, for example, a magnetic material that requires a large inductance. Only the coil pattern for which the effect of the resin layer is desired is placed inside the magnetic resin layer or near the boundary between the magnetic resin layer and the dielectric ceramic layer, and the other coil patterns are arranged on the multilayer substrate (dielectric ceramic layer). You may make it arrange | position inside.
 また、透磁率μrが1よりも大きくなるように磁性体樹脂層を構成するのが望ましい。また、磁性体樹脂層を構成する磁性体材料の粒子径はどのような大きさであってもよいが、より高周波帯域での電子部品の使用を鑑みれば、磁性体材料の粒子径は2μm以下であることが望ましい。また、磁性損失が小さい磁性体樹脂層を形成することで、電子部品をさらに高周波に適した構成とすることができる。 Also, it is desirable to configure the magnetic resin layer so that the magnetic permeability μr is greater than 1. Moreover, the particle diameter of the magnetic material constituting the magnetic resin layer may be any size, but in view of the use of electronic components in a higher frequency band, the particle diameter of the magnetic material is 2 μm or less. It is desirable that Further, by forming a magnetic resin layer with a small magnetic loss, the electronic component can be configured to be more suitable for high frequencies.
 また、誘電体セラミック層としての多層基板の少なくとも一方の主面にのみ磁性体樹脂層を設けることで、上記した種々の効果を奏することができるため、電子部品の、磁性体樹脂層が設けられていない面に外部電極などを容易に形成することができる。したがって、表面実装用のチップ部品に本発明を容易に適用することができる。また、多層基板の両主面に磁性体樹脂層を設けてもよい。 Moreover, since the above-described various effects can be achieved by providing the magnetic resin layer only on at least one main surface of the multilayer substrate as the dielectric ceramic layer, the magnetic resin layer of the electronic component is provided. An external electrode or the like can be easily formed on the unexposed surface. Therefore, the present invention can be easily applied to surface mount chip components. A magnetic resin layer may be provided on both main surfaces of the multilayer substrate.
 さら、図1、図12などに示すように、コンデンサやコイルを、所定の電極パターンが形成された誘電体層のみで形成する場合は、積層された誘電体層の焼成後、誘電体層の少なくとも一方の主面に磁性体樹脂層を形成するだけでよいので、容易に電子部品の製造を行える。また、従来のように、コイルを誘電体層のみで形成した場合には、コイルの漏れ電流などによるQ値の低下を極力少なくするため、コイルの上下に電極パターンが形成されていない誘電体層がダミー層として形成されていたが、本発明の図1、図12などに示す構成では、コイル上部に設けられた磁性体樹脂層の透磁率μrが1以上となるため、磁性体樹脂層を設けることで、電子部品の高さを低くすることができる。 Furthermore, as shown in FIGS. 1 and 12, when a capacitor or a coil is formed only by a dielectric layer on which a predetermined electrode pattern is formed, after the laminated dielectric layer is fired, Since it is only necessary to form a magnetic resin layer on at least one main surface, electronic parts can be easily manufactured. In addition, when the coil is formed of only a dielectric layer as in the prior art, a dielectric layer in which electrode patterns are not formed above and below the coil in order to minimize the decrease in the Q value due to the leakage current of the coil. 1 is formed as a dummy layer. However, in the configuration shown in FIGS. 1 and 12 of the present invention, the magnetic resin layer provided on the coil has a magnetic permeability μr of 1 or more. By providing, the height of the electronic component can be reduced.
 また、本発明はモジュールなどの集合基板にも適用することができるが、図1、図12などに示すように、チップ型の受動部品に本発明を適用することで、前記製造方法の利点の1つである電子部品を容易に形成できることに加え、電子部品を誘電体層のみで形成したときの電気的特性よりも特性を向上することができる。 The present invention can also be applied to a collective substrate such as a module. However, as shown in FIGS. 1 and 12, the application of the present invention to a chip-type passive component improves the advantages of the manufacturing method. In addition to being able to easily form one electronic component, the characteristics can be improved over the electrical characteristics when the electronic component is formed only of a dielectric layer.
 また、上記実施形態では、多層基板に直方体状の凹状のキャビティを形成したが、キャビティの形状としては上記した形状に限られず、多層基板を貫通してキャビティを形成してもよく、円柱状にキャビティを形成してもよい。 In the above embodiment, a rectangular parallelepiped concave cavity is formed in the multilayer substrate. However, the shape of the cavity is not limited to the above-described shape, and the cavity may be formed through the multilayer substrate. A cavity may be formed.
 本発明は、多層基板の内部にコンデンサやコイルが設けられた電子部品に広く適用することができる。 The present invention can be widely applied to electronic components in which capacitors and coils are provided inside a multilayer substrate.
 1,1a 多層チップ型共振器素子(電子部品)
 2、102,202,302,402,502,602,702,802,902,1002 多層基板
 20a,20d,20e,20f,120a,122a,420a,421a,422a,520a,520b,520e,520f,620a,620b,720a,720b,820a,820b,920a,920b,1020a,1020b コイルパターン
 3,103,203,303,503,603,603a,703,803,903,1003 磁性体樹脂層
 4,204,504a,504b,604a,604b 共振器回路(共振器パターン)
 5,5a,705,805,905 マスク層
 100,500,600 多層チップ型バンドパスフィルタ素子(電子部品)
 200 多層チップ型平板共振器素子(電子部品)
 220a~220i 共振器パターン
 300,400,700,800,900,1000 電子部品
 610,810,1010 キャビティ
1,1a Multilayer chip resonator element (electronic component)
2, 102, 202, 302, 402, 502, 602, 702, 802, 902, 1002 Multilayer substrate 20a, 20d, 20e, 20f, 120a, 122a, 420a, 421a, 422a, 520a, 520b, 520e, 520f, 620a , 620b, 720a, 720b, 820a, 820b, 920a, 920b, 1020a, 1020b Coil pattern 3,103,203,303,503,603,603a, 703,803,903,1003 Magnetic resin layer 4,204,504a , 504b, 604a, 604b Resonator circuit (resonator pattern)
5,5a, 705,805,905 Mask layer 100,500,600 Multilayer chip type bandpass filter element (electronic component)
200 Multi-layer chip type plate resonator element (electronic component)
220a to 220i Resonator pattern 300, 400, 700, 800, 900, 1000 Electronic component 610, 810, 1010 Cavity

Claims (11)

  1.  積層したセラミックグリーンシートを焼成して形成された多層基板と、
     前記多層基板の少なくとも一方の主面に設けられた磁性体樹脂層とを備えることを特徴とする電子部品。
    A multilayer substrate formed by firing laminated ceramic green sheets;
    An electronic component comprising: a magnetic resin layer provided on at least one main surface of the multilayer substrate.
  2.  コイルを形成するコイルパターンをさらに備える請求項1に記載の電子部品。 The electronic component according to claim 1, further comprising a coil pattern forming a coil.
  3.  前記コイルパターンは前記多層基板の積層方向にヘリカル状に形成されている請求項2に記載の電子部品。 The electronic component according to claim 2, wherein the coil pattern is formed in a helical shape in the stacking direction of the multilayer substrate.
  4.  前記コイルパターンは前記磁性体樹脂層と接するように設けられている請求項2または3に記載の電子部品。 4. The electronic component according to claim 2, wherein the coil pattern is provided in contact with the magnetic resin layer.
  5.  前記コイルパターンの少なくとも一部は前記磁性体樹脂層の内部に設けられている請求項2または3に記載の電子部品。 4. The electronic component according to claim 2, wherein at least a part of the coil pattern is provided inside the magnetic resin layer.
  6.  前記多層基板と反対側の前記磁性体樹脂層の主面に設けられた金属膜層をさらに備え、
     前記金属膜層は、上面視において前記コイルパターンの少なくとも一部と重なるように設けられている請求項2ないし5のいずれかに記載の電子部品。
    A metal film layer provided on the main surface of the magnetic resin layer opposite to the multilayer substrate;
    The electronic component according to claim 2, wherein the metal film layer is provided so as to overlap at least a part of the coil pattern in a top view.
  7.  共振器を形成する共振器パターンをさらに備える請求項1ないし6のいずれかに記載の電子部品。 The electronic component according to claim 1, further comprising a resonator pattern that forms a resonator.
  8.  前記共振器パターンとして、第1コイルを有する第1共振器を形成する第1の共振器パターンと、第2コイルを有する第2共振器を形成する第2の共振器パターンとが、上面視において並べて設けられており、前記磁性体樹脂層は、少なくとも前記第1コイルを形成する第1のコイルパターンと前記第2コイルを形成する第2のコイルパターンとの間に設けられている請求項7に記載の電子部品。 As the resonator pattern, a first resonator pattern forming a first resonator having a first coil and a second resonator pattern forming a second resonator having a second coil are viewed from above. The magnetic resin layer is provided side by side, and is provided between at least a first coil pattern that forms the first coil and a second coil pattern that forms the second coil. Electronic components described in
  9.  前記第1のコイルパターンと前記第2のコイルパターンとの間に配置されるキャビティが前記多層基板に設けられており、前記キャビティに磁性体樹脂が充填されている請求項8に記載の電子部品。 The electronic component according to claim 8, wherein a cavity disposed between the first coil pattern and the second coil pattern is provided in the multilayer substrate, and the cavity is filled with a magnetic resin. .
  10.  前記磁性体樹脂層が設けられた前記多層基板の主面に設けられたマスク層をさらに備え、
     前記マスク層は、前記磁性体樹脂層を囲繞するように設けられている請求項1ないし9のいずれかに記載の電子部品。
    A mask layer provided on the main surface of the multilayer substrate provided with the magnetic resin layer;
    The electronic component according to claim 1, wherein the mask layer is provided so as to surround the magnetic resin layer.
  11.  前記磁性体樹脂層は、透磁率の異なる複数の層により形成されている請求項1ないし10のいずれかに記載の電子部品。 The electronic component according to claim 1, wherein the magnetic resin layer is formed of a plurality of layers having different magnetic permeability.
PCT/JP2011/000559 2010-02-18 2011-02-02 Electronic component WO2011102088A1 (en)

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JPH0344905A (en) * 1989-07-13 1991-02-26 Matsushita Electric Ind Co Ltd Inductance element
JPH0327013U (en) * 1989-07-27 1991-03-19
JPH06325939A (en) * 1993-05-13 1994-11-25 Murata Mfg Co Ltd Inductor
JPH09260145A (en) * 1996-03-22 1997-10-03 Murata Mfg Co Ltd Layer-built balun transformer
JPH10241942A (en) * 1997-02-28 1998-09-11 Taiyo Yuden Co Ltd Laminated electronic parts and it characteristic adjusting method
JP2003209331A (en) * 2002-01-17 2003-07-25 Toppan Printing Co Ltd Printed wiring board and its manufacturing method
JP2007221472A (en) * 2006-02-16 2007-08-30 Tdk Corp Noise filter, and noise filter mounting structure

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0344905A (en) * 1989-07-13 1991-02-26 Matsushita Electric Ind Co Ltd Inductance element
JPH0327013U (en) * 1989-07-27 1991-03-19
JPH06325939A (en) * 1993-05-13 1994-11-25 Murata Mfg Co Ltd Inductor
JPH09260145A (en) * 1996-03-22 1997-10-03 Murata Mfg Co Ltd Layer-built balun transformer
JPH10241942A (en) * 1997-02-28 1998-09-11 Taiyo Yuden Co Ltd Laminated electronic parts and it characteristic adjusting method
JP2003209331A (en) * 2002-01-17 2003-07-25 Toppan Printing Co Ltd Printed wiring board and its manufacturing method
JP2007221472A (en) * 2006-02-16 2007-08-30 Tdk Corp Noise filter, and noise filter mounting structure

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