WO2011100803A1 - Générateur de signal de commande pour un circuit gradateur - Google Patents

Générateur de signal de commande pour un circuit gradateur Download PDF

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Publication number
WO2011100803A1
WO2011100803A1 PCT/AU2011/000177 AU2011000177W WO2011100803A1 WO 2011100803 A1 WO2011100803 A1 WO 2011100803A1 AU 2011000177 W AU2011000177 W AU 2011000177W WO 2011100803 A1 WO2011100803 A1 WO 2011100803A1
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WO
WIPO (PCT)
Prior art keywords
control signal
period
control
signal
user
Prior art date
Application number
PCT/AU2011/000177
Other languages
English (en)
Inventor
James Robert Vanderzon
Alex Stelmach
Original Assignee
Clipsal Australia Pty Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from AU2010900685A external-priority patent/AU2010900685A0/en
Application filed by Clipsal Australia Pty Ltd filed Critical Clipsal Australia Pty Ltd
Priority to NZ601621A priority Critical patent/NZ601621A/en
Priority to AU2011217744A priority patent/AU2011217744B2/en
Priority to CN2011800100644A priority patent/CN102783252A/zh
Priority to KR1020127024380A priority patent/KR20130018694A/ko
Priority to SG2012057840A priority patent/SG182843A1/en
Publication of WO2011100803A1 publication Critical patent/WO2011100803A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B39/00—Circuit arrangements or apparatus for operating incandescent light sources
    • H05B39/04—Controlling
    • H05B39/041—Controlling the light-intensity of the source
    • H05B39/044—Controlling the light-intensity of the source continuously
    • H05B39/048—Controlling the light-intensity of the source continuously with reverse phase control
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
    • H05B47/10—Controlling the light source
    • H05B47/165—Controlling the light source following a pre-assigned programmed sequence; Logic control [LC]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps

Definitions

  • the present invention relates to dimmer circuits for controlling loads such as Compact Flourescent Lamps (CFLs).
  • loads such as Compact Flourescent Lamps (CFLs).
  • Phase control dimmer circuits are used to control the power provided to a load such as a light or electric motor from a power source such as mains power. Such circuits often use a technique referred to as phase control dimming. This allows power provided to the load to be controlled by varying the amount of time that a switch connecting the load to the power source is conducting during a given cycle. For example, if voltage provided by the power source can be represented by a sine wave, then maximum power is provided to the load if the switch connecting the load to the power source is on at all times. In this way the, the total energy of the power source is transferred to the load.
  • the switch is turned off for a portion of each cycle (both positive and negative), then a proportional amount of the sine wave is effectively isolated from the load, thus reducing the average energy provided to the load. For example, if the switch is turned on and off half way through each cycle, then only half of the power will be transferred to the load.
  • the overall effect will be, for example in the case of a light, a smooth dimming action resulting in the control of the luminosity of the light.
  • Modem phase control dimming circuits generally operate in one of two ways - leading edge or trailing edge.
  • leading edge technology the dimmer circuit "chops out” or blocks conduction of electricity by the load in the front part of each half cycle (hence the term “leading edge”).
  • trailing edge technology the dimmer circuit "chops out "or blocks conduction of electricity by the load in the back part of each half cycle.
  • Figure 1 A shows a representation of the function of a leading edge dimmer, illustrating the current I L through the load while Figure IB shows the function of a trailing edge dimmer.
  • FIG 2A shows a typical prior art phase control dimmer circuit (or dimmer circuit) 1 comprising a switch 4 (e.g. a solid state switch such as a triac), which switches current to the load 10 in accordance with timing signals provided by a timing control circuit 3 as will be understood by the person skilled in the art.
  • the timing control circuit 3 determines the angle at which the switch 4 fires into conduction (the firing angle), to allow current to flow into the load 10.
  • the output 5' (provided as a drive signal) of the timing control circuit 3 is controlled by the input 5 of the timing control circuit 3 which is a control voltage.
  • the value of this control voltage 5 may be varied by a user operating a user-settable interface 2 such as a potentiometer or digital switch.
  • FIG. 2B shows a typical user control signal/control signal control voltage/drive signal vs conduction angle transfer function.
  • CFL Compact Fluorescent Lamp
  • CFLs Compact Flourescent Lamps
  • phase control lighting dimmers are being increasingly used as a more energy-efficient lighting source over traditional incandescent lamps.
  • One disadvantage of CFLs is that they are much more difficult to control by phase control lighting dimmers as they can be very unstable at low conduction angles.
  • starting of these load types can be unreliable or in some cases, not possible, with standard dimmers when the dimmer control setting is set to a low level (or low conduction angle).
  • the user In order to achieve reliable starting of the CFL load, currently, the user must typically ensure that the dimmer control setting is set to a level beyond approximately 50% of the maximum conduction period, before it is possible to dim to a lower brightness level after the CFL has warmed up.
  • Figure 1 A - shows a representation of the function of a leading edge phase control dimmer
  • Figure I B - shows a representation of the function of a trailing edge phase control dimmer
  • FIG. 2A - shows a typical prior art phase control dimmer arrangement
  • Figure 2B - shows a typical control voltage vs conduction angle transfer function
  • Figure 3 - shows one example of an arrangement of a phase control dimmer circuit according to one aspect of the present invention
  • Figure 4A - shows the arrangement of Figure 3 with a low user setting
  • Figure 4B - shows the load current I L for the selected user setting of Figure 4A
  • Figure 4C - shows the load current I L during the "kick-start” or start up period
  • Figure 5 A - shows the arrangement of Figure 3 with a high user setting
  • Figure 5B - shows the load current I L for the selected user setting of Figure 5A
  • FIG. 5C - shows the load current I L output from the control signal generator
  • Figure 6A - shows a graph of Drive Signal vs time during and after the "kick start” or start up period
  • Figure 6B - shows a modified version of the graph of Figure 6 A with a ramp up and ramp down period
  • Figure 6C - shows a ramp up period longer than the ramp down period
  • Figure 6D - shows the ramp up period shorter than the ramp down period
  • Figure 6E shows no ramp up period and a ramp down period
  • Figure 6F shows a ramp up period and no ramp down period
  • Figure 6G - shows a ramp up period and a ramp down period using a soft ramp
  • Figure 7 - shows the load current I L as it changes in accordance with the drive signal of Figure 6B;
  • Figure 8 - shows a different arrangement of the phase control dimmer circuit of Figure 3;
  • Figure 9 - shows yet another arrangement of the phase control dimmer circuit of Figure 3.
  • Figure 1 OA - shows a general block diagram of one embodiment of a control signal generator
  • Figure 10B - shows a block diagram of another embodiment of a control signal generator
  • Figure 1 1 - shows a circuit arrangement of one embodiment of the control signal generator
  • Figure 12 - shows a digital implementation of the phase control dimmer circuit of Figure 3;
  • Figure 13 - shows a flow chart of the steps performed by the microcontroller as shown in Figure 12;
  • Figure 14 - shows a flowchart of a broad method of generating a control signal according to one embodiment
  • Figure 15 - shows a block diagram of a broad embodiment of a phase control dimmer circuit according to an embodiment described herein.
  • a control signal generator for use in a phase control dimmer circuit.
  • the control signal generator generates as an output, either a user input if the user input is greater than r or equal to a conduction threshold, or a boost signal if the user input is less than the conduction threshold.
  • the output is used to control the firing angle of the dimmer circuit and may be used to control a load such as a compact flourescent light (CFL).
  • CFL compact flourescent light
  • control signal generator for use in a phase control dimmer circuit, the control signal generator comprising:
  • a boost signal generator for generating a boost signal at or above a conduction threshold for a start up period if the user control signal is less than the conduction threshold
  • the output outputs the input signal if no boost signal is generated.
  • the input signal is the user control signal.
  • the input signal is a drive signal generated by a timing control circuit of the phase control dimmer circuit.
  • the start up period is between about 0.5 seconds and about 5 seconds.
  • the start up period is about 2 seconds.
  • the start up period is about 4 seconds.
  • the start up period begins with a ramp up period.
  • the start up period finishes with a ramp down period.
  • the conduction threshold is determined by a voltage divider of two resistors. In one embodiment, the start up period is determined by an RC network.
  • control signal generator is provided by a microcontroller. In one embodiment, the output is provided as a control signal for input to a timing control circuit of the phase control dimmer circuit.
  • the output is provided as a control drive signal for input to a switch of the phase control dimmer circuit.
  • the conduction threshold is between about 50% and about 100% of line voltage half cycle period.
  • the conduction threshold is about 80% of line voltage half cycle period.
  • a method of generating a control signal for use in a phase control dimmer circuit comprising:
  • the method further comprises outputting the input signal if no boost signal is generated.
  • the start up period is about 2 seconds.
  • start up period is about 4 seconds. In another embodiment, the start up period is preceded by a ramp up period.
  • the start up period is followed by a ramp down period.
  • phase control dimmer circuit for controlling power delivered to a load, comprising:
  • a control signal generator for providing a control signal as the user control signal if the user control signal is greater than or equal to a conduction threshold, or a boost signal that is greater than or equal to the conduction threshold if the user control signal is less than the conduction threshold;
  • timing control circuit for generating a drive signal in response to the control signal; and a switch for switching current to the load in response to the drive signal.
  • FIG. 3 shows a block diagram of a phase control dimmer circuit (or dimmer circuit) 100 comprising a switch 1 10 (e.g. a solid state switch such as a triac), which switches current to the load 10 from a source 9 in accordance with timing signals provided as a switch drive signal 8 by a timing control circuit 120 as will be understood by the person skilled in the art.
  • the timing control circuit 120 determines the angle at which the switch 1 10 fires into conduction (the firing or conduction angle), to allow current to flow into the load 10.
  • the output of the timing control circuit 120 as switch drive signal 8 is controlled by the input of the timing control circuit 120 provided as a control signal 7.
  • the value of this control signal 7 may be varied by a user operating a user control 130 such as a potentiometer or digital switch, producing a user control signal 6.
  • the load 10 is a compact fluorescent lamp (CFL)
  • CFL compact fluorescent lamp
  • a "kick- start" circuit provided in one embodiment, as a control signal generator 140 that will generate or provide an appropriate boost signal as a control signal 7 that is sufficiently large to avoid this instability.
  • the control signal generator 140 will generate a boost signal or control signal or voltage 7 sufficient to provide a conduction angle equal to or greater than the load operating threshold.
  • a conduction threshold is set at or above the load operating threshold.
  • the conduction threshold is set at about 50% of the line voltage half cycle period. It will be appreciated that the load operating threshold (i.e. the threshold at and above which the CFL will operate in a stable mode), may be different for each load, and this may be determined by experimentation. In one example a conservative approach is to set the conduction threshold well above the load operating threshold, such as for example, at 80% of the line voltage half cycle period.
  • the conduction threshold is between about 50% and about 80% of the maximum conduction period.
  • the conduction threshold may be any suitable value including between about 50% and about 100%, about 50% and 60%, about 55%, between about 50% and about 70%, about 60%, between about 50% and about 90%, about 70%, about 80%, about 90%, between about 80% and about 100%, about 85%, and about 95%.
  • the maximum conduction period of the dimmer circuit 100 is less than the line voltage half-cycle period. For example, for a 50Hz system with 10ms half-cycle period a maximum dimmer conduction period of 80% (8ms) is typical. In a 3-wire dimmer application a maximum dimmer conduction period of 100% is possible.
  • the actual achievable maximum conduction period of the dimmer circuit 100 is limited by the CFL load characteristics, due to the requirement of the dimmer circuit 100 to receive some line voltage to sustain operation in each half-cycle.
  • a poor-case CFL would result in an allowable maximum conduction period of the dimmer circuit 100 to be approximately 6ms.
  • the dimmer half-cycle conduction period during the kick-start event or start up period would be close to 100% of allowable maximum conduction period of the dimmer circuit (i.e. 6ms).
  • the dimmer half-cycle conduction period during the kick-start event or start up period can be within the range of about 65% to about 100% of the dimmer maximum half-cycle conduction period or alternatively it may be stated that the dimmer half-cycle conduction period during the kick- start event or start up period may be about 60% (6ms) of line voltage half-cycle period, for a poor-case CFL load type.
  • FIG 4A shows the dimmer circuit 100 of Figure 3 with a user control 130 (also represented as a potentiometer dial 131 ) set at a low setting (for example about 20% of maximum setting).
  • a user control 130 also represented as a potentiometer dial 131
  • dimmer circuit 100 would normally apply this user setting to the load 10.
  • the load 10 is a CFL
  • the CFL would become unstable since the user setting is well below the load operating threshold of for example 50% of the maximum conduction period or line voltage half cycle conduction period.
  • Figure 4B shows what the load current I L would normally be with the 20% user setting, in a trailing edge mode.
  • Figure 4B shows where the load operating threshold for this load is at about 50%, as well as the conduction threshold selected in this case to be about 80%.
  • Figure 4C shows the equivalent load current I L upon application of this aspect of the invention in this example, in which control signal generator 140 generates a boost signal control signal (for example control voltage) 7 at a level so as to cause the timing control circuit 120 to generate a switch drive signal 8 to control the switch 1 10 for a start up period at the selected conduction threshold of about
  • a boost signal control signal for example control voltage
  • Figure 4C shows the load current now being passed at a level of about 80%, well above the 50% load operating threshold.
  • control signal generator 140 since a boost signal is generated, the output of control signal generator 140 is the boost signal.
  • FIG. 5 A shows the arrangement of Figure 4A but with the user control 130 (such as potentiometer dial 131 ) set at about 90% of the maximum setting. Since this setting is above the selected conduction threshold of 80% in this example, meaning that the user selected level at turn on is high enough to control the load (CFL) 10 in a stable manner, control signal generator 140 outputs as control signal 7, a signal that is the same as the input user control signal 6. This output may be the actual input signal or a new signal that is generated by control signal generator 1 0 that is the same level as the input user control signal 6.
  • Figure 5B shows what the load current I L would be with the 90% user setting, in a trailing edge mode.
  • Figure 5B shows where the load operating threshold for this load is at about 50%, as well as the conduction threshold selected in this case to be about 80%.
  • the load current I L generated at the user setting is at 90%, well above the selected conduction threshold of 80%.
  • Figure 5C shows the load current I L resulting from the output of control signal generator 140.
  • the level is above the minimum level to operate the load in a stable manner (i.e. above the selected 80% conduction threshold)
  • no change is required by the control signal generator 140 and so this waveform is the same as the waveform in Figure 5B.
  • Figure 6A shows one example of how the higher conduction threshold may be applied by increasing the switch drive signal 8 as the boost signal (in one example, by increasing the control signal 7 generated by the control signal generator 140).
  • the switch drive signal or boost signal is caused to be high (for example 80% of maximum) so as to provide a load current as shown in Figure 4C.
  • This higher drive signal and consequent load current is applied for only a short time (the start up period) after the load is switched on or powered up.
  • This time is selected to be sufficiently long to allow the CFL to warm up sufficiently so as to operate in a stable fashion at low settings or conduction angles. In one example, this is about 5 seconds as shown in Figure 6A.
  • this period may less or greater, including about 0.5 seconds, about 1 second, about 1.5 seconds, about 2 seconds, about 2.5 seconds, about 3 seconds, about 3.5 seconds, about 4 seconds, about 4.5 seconds, about 5 seconds, about 5.5 seconds, about 6 seconds, about 6.5 seconds, about 7 seconds, between about 5 seconds and about 10 seconds, or more.
  • the control signal 7 and subsequent switch drive signal 8 is set to the user control signal 6 to cause the dimmer circuit 100 to control the CFL or load 10 at the user selected level (for example, in this case, about 20%).
  • the load current will then appear as shown in Figure 4B, until it is subsequently adjusted again by the user to adopt a desired lighting level as per the normal operation of the dimmer circuit 100.
  • the user may decide to reduce the user setting to provide a user control signal 6 to about 10% maximum setting, thus reducing the brightness of the CFL load 10. Since the CFL has warmed up, it is able to be reduced to any desired setting in a stable manner.
  • the user may decide to increase the user setting to about 50% to increase the brightness of the CFL.
  • a refinement to the above example involves providing a ramping effect to achieve the boost signal as a switch drive signal 8, as shown in Figure 6B.
  • the boost signal as the drive signal 8 is ramped up from about 0% to about 80% over a ramp up period of for example about 0.5 seconds. It will be appreciated that this ramp up period may be any reasonable period, including anywhere between about 0 seconds and about 1 second, including about 0.1 seconds, about 0.2 seconds, about 0.3 seconds, about 0.4 seconds, about 0.5 seconds, about 0.6 seconds, about 0.7 seconds, about 0.8 seconds, about 0.9 seconds and about 1 second.
  • the boost signal or conduction threshold level may be applied for the selected period as described above in relation to Figure 6A (shown in Figure 6B to be about 4 seconds), and then allowed to ramp down again during a ramp down period to the user selected level as determined by the user control signal 6.
  • the ramp down period is about the same as the ramp up period of about 0.5 seconds, but this need not be the case.
  • the ramp up period is longer than the ramp down period (for example Figure 6C), and in other embodiments, the ramp down period is longer than the ramp up period (for example Figure 6D), or indeed in some other embodiments, there is no ramp up period, only a ramp down period (for example Figure 6E), and in yet other embodiments, there is a ramp up period but no ramp down period (for example Figure 6F).
  • the ramping up and/or ramping down may be provided as a "soft ramp", having a curved start and a curved end to provide a smoother transition.
  • Figure 6F shows the ramp up as a soft ramp and
  • Figure 6G shows both the ramp up and the ramp down as soft ramps.
  • FIG 7 shows the equivalent schematic of I L as Figures 4B and 4C but with the ramped application of the boost signal or higher drive signal of Figure 6B.
  • the load current I L begins to ramp up, starting at about 20% of maximum conduction, then to about 30% in subsequent cycles, then to about 40% until it reaches the selected conduction threshold of (in this example) about 80%. This value is maintained for a period (e.g.
  • the user control signal 6 is input directly into the timing control circuit 120 as in traditional arrangements, and the control signal generator 140 receives the drive signal 8 from timing control circuit 120 as the user control signal 6. In this arrangement, control signal generator 140 still receives as its input, user control signal 6, but in the form of drive signal 8. It will be understood that in this configuration, drive signal 8 is equivalent to, proportional to or representative of user control signal 6 and is representative of the user setting set by the user at user control 130. If control signal generator 140 determines that the switch drive signal 8 generated by timing control circuit 120 is too low (i.e.
  • the control signal generator 140 will generate the boost signal to adjust the input drive signal 8 to generate drive signal 8' to cause the switch 1 10 to switch at the selected conduction threshold (for example about 80% of maximum conduction) for an initial start up period (for example about 5 seconds) as described above with reference to Figures 6A to 6G.
  • Figure 9 shows yet another possible configuration in which control signal generator 140 is operationally connected to user control 130 (by wire, wirelessly or a combination of both) and operationally connected to switch 1 10 (by wire, wirelessly or a combination of both) to provide the required increase in drive signal as the boost signal to drive switch 110 at or above the selected conduction threshold for the initial period, should the user selected level be less than the selected conduction threshold. If the user selected level is equal to or greater than the selected conduction threshold in the initial CFL warm up or start up period, the control signal generator 140 takes no amending action.
  • control signal generator 140 comprises an input 141 for receiving an input signal representative of a user control signal, a boost signal generator 1 2 for generating a boost signal at or above a conduction threshold for a start up period if the user control signal is less than the conduction threshold, and an output 142 for outputting the boost signal if the boost signal is generated.
  • FIG. 10A shows a block diagram of one embodiment of the control signal generator 140. Shown is a control signal generator 140 for use in a phase control dimmer circuit having a conduction period.
  • the control signal generator 140 comprises an input 141 for receiving an input signal representative of a user control signal (6).
  • the control signal generator 140 also comprises a boost signal generator 142 for generating a boost signal 145 which is at or above the conduction threshold for the start up period if the user control signal 6 is less than the conduction threshold.
  • the control signal generator 140 also comprises an output 142 for outputting either the input signal 6 if no boost signal is generated or the boost signal 145 if the boost signal is generated.
  • control signal generator 140 comprises a comparator 143 for comparing the input user control signal with the selected conduction threshold. If the user control signal is less than the selected conduction threshold, then the boost signal generator 142 will generate the boost signal 145. If the boost signal 145 is generated, then this boost signal 145 will be output from control signal generator 140 at output 142 as the control signal 7. If the boost signal 145 is not generated (e.g. because the user control signal is greater than or equal to the selected conduction threshold), then the control signal generator 140 will output the user control signal 6 at output 142 as the control signal 7. This determination is made at block 144.
  • the start up period is between about 0.5 seconds and about 5 seconds. In another embodiment, the start up period is about 2 seconds. In another embodiment, the start up period is about 4 seconds.
  • the start up period begins with a ramp up period. In another embodiment, the start up period ends with a ramp down period.
  • Figure 1 1 shows one example of one embodiment of a circuit embodiment for signal control generator 140.
  • an RC timing network R5/C1
  • Ql transistor
  • a resistive voltage divider R2 & R3 determines the conduction threshold setting, as a percentage of the supply voltage Vcc-
  • Dl diode
  • potentiometer wiper series resistor prevents loading effects on kick-start voltage level.
  • components and component values to achieve approximately a 2 second "kick- start" or conduction threshold period are selected as:
  • VCC 12V It is well within the skill of the person skilled in the art to select different values to achieve” different periods, such as the 4 or 5 second period described above.
  • the circuit acts as follows. Immediately following the power-up event (switched active dimmer) capacitor CI has zero charge voltage hence base bias current to activate transistor Ql flows via R5. Voltage divider resistors R2 & R3 determine the resultant voltage applied to the anode of diode Dl , hence the actual voltage (or signal) generated by the control signal generator 140 is reduced by an amount equal to Dl forward voltage drop.
  • the selected conduction threshold is equivalent to about 80% of the maximum conduction period of the line voltage half cycle conduction period of about 10ms.
  • this generated output signal or boost signal acting in this case as control signal 7, in this embodiment, is be applied to the input of the timing control circuit 120 as shown in Figure 3, or, in other embodiments, the output of control signal generator 140 is applied directly as a modified drive signal 8' as shown in the configurations of Figures 8 and 9.
  • Potentiometer series buffer resistor Rl has sufficiently high value so as to not permit potentiometer resistance from adversely loading the R2/R3 voltage divider.
  • the input impedance of the timing control circuit 120 is significantly greater than the value of Rl so as to not adversely load the potentiometer output voltage during normal operation.
  • the function of the circuit is as follows.
  • the potentiometer output voltage is applied via Rl directly to the timing control circuit since it has a magnitude exceeding that of voltage divider R2/R3, and diode Dl is consequently reverse-biased to create a blocking condition, therefore no "kick-start" event occurs, and the value of the user control signal is generated as the output of the signal control generator 140, either as the control signal 7 or drive signal 8, depending upon the configuration of the dimmer circuit.
  • This point in the circuit provides the comparator 143 and block 144 functions of Figure 10B.
  • the CFL Since the user selected user control signal results in a conduction angle greater than the load operating threshold (and in fact greater than the selected conduction threshold), the CFL will be able to turn on in a stable mode. If the user subsequently adjusts the dimming levels after the CFL has warmed up, the dimmer will be able to operate as normal and dim the CFL in a stable manner.
  • FIG 12 shows yet a further possible arrangement or embodiment of phase control dimmer circuit 100.
  • a microcontroller 150 provides the functionality of control signal generator 140 as well as that of timing control circuit 120.
  • the input of microcontroller 150 is the user control signal 6 acting as the input signal representative of the user control and the output is the boost signal provided as drive signal 8, applied to switch 110.
  • microcontroller 150 provides other functions of the dimmer circuit 100, or in other embodiments, simply provides some, such as just that of the control signal generator, as will be appreciated by the person skilled in the art.
  • Figure 13 illustrates the functionality provided by microcontroller 150 to provide the function of control signal generator 140.
  • the output of the user control 130 being the user control signal 6, acting as the input signal representative of the user control signal, is read at turn on.
  • step 202 a determination of the level of the input is made. If the level is greater than the selected conduction threshold, this level is generated as the output of microcontroller 150, for example, as a control signal to be applied to the timing control circuit 120 (whether a separate component or provided by the microcontroller itself), or as a drive signal applied directly to switch 1 10.
  • the level is increased as the boost signal to or above the selected conduction threshold at step 203, maintained at that level for a selected period (the start up period) (for example 0.5 seconds, 1 second, 2 seconds, 3 seconds, 4 seconds or 5 seconds) at step 204, and then returned to the user selected level after the start up period at step 205.
  • the selected conduction threshold is about 70% of maximum, but of course, as described previously, may take on any suitable value at or above the load operating threshold.
  • Suitable pseudocode for microcontroller 150 to effect the method outlined above with respect to Figure 13 is as follows: #define NEAR_MAX_CONDUCTION_TIME 7000 // 80% conduction
  • the threshold conduction is selected to be about 80%. It will be appreciated that these steps need only be performed at turn on, and not after the load has warmed up. Subsequent user setting changes may be applied directly. There are numerous ways of determining whether the load is being turned on, as will be appreciated by the person skilled in the art.
  • a broad method of generating a control signal for use in a phase control dimmer circuit comprises receiving an input representative of a user control signal, generating a boost signal at or above a conduction threshold for a start up period if the user control signal is less than the conduction threshold and outputting the boost signal if the boost signal is generated.
  • the method also comprises outputting the input signal if no boost signal is generated.
  • a broad method of generating a control signal for use in a phase control dimmer circuit is provided.
  • step 301 an input representative of a user control signal is received.
  • step 302 a boost signal at or above a conduction threshold is generated for a start up period if the user control signal is less than the conduction threshold; and at step 303, the control signal is output as either the input signal if no boost signal is generated or the boost signal if the boost signal is generated.
  • the start up period is between about 0.5 seconds and about 5 seconds. In another embodiment, the start up period is about 2 seconds. In another embodiment, the start up period is about 4 seconds. In one embodiment, the start up period begins with a ramp up period. In another embodiment, the start up period ends with a ramp down period.
  • dimmer circuit 100 for controlling power delivered to a load.
  • dimmer circuit 100 comprises an input 101 for receiving a user control signal 6 from a user control (not shown in this view); a control . signal generator 140 for providing a control signal 7 as either the user control signal 6 if the user control signal 6 is greater than or equal to a conduction threshold, or a boost signal that is greater than or equal to the conduction threshold if the user control signal 6 is less than the conduction threshold.
  • dimmer circuit 100 also comprises a timing control circuit 120 for generating a drive'signal 8 in response to the control signal 7; and a switch 1 10 for switching current to the load (not shown in this view) in response to the drive signal 8.
  • phase control dimming circuits including leading edge, trailing edge and universal dimmers, and including those described in detail in PCT/AU03/00365 entitled “Improved Dimmer Circuit Arrangement”; PCT/AU03/00366 entitled “Dimmer Circuit with Improved Inductive Load”; PCT/AU03/00364 entitled “Dimmer Circuit with Improved Ripple Control”; PCT/AU2006/001883 entitled “Current Zero Crossing Detector in A Dimmer Circuit”; PCT/AU2006/001882 entitled “Load Detector For A Dimmer”; PCT/AU2006/001881 entitled “A Universal Dimmer”; PCT/AU2008/001398 entitled “Improved Start-Up Detection in a Dimmer Circuit”; PCT/AU2008/001399 entitled “Dimmer Circuit With Overcurrent Detection”; and PCT/AU2008/001400 entitled “Overcurrent Protection in a Dimmer Circuit

Landscapes

  • Circuit Arrangement For Electric Light Sources In General (AREA)
  • Discharge-Lamp Control Circuits And Pulse- Feed Circuits (AREA)

Abstract

La présente invention concerne un générateur de signal de commande (140) destiné à être utilisé dans un circuit gradateur à commande de phase (100). Le générateur de signal de commande (140) génère en tant que sortie (7), un signal d'entrée utilisateur (6) si le signal d'entrée utilisateur (6) est supérieur ou égal à un seuil de conduction, ou un signal de suralimentation (145) si le signal d'entrée utilisateur (6) est inférieur au seuil de conduction. La sortie (7) est utilisée pour commander l'angle d'allumage du circuit gradateur à commande de phase (100) et peut être utilisée pour commander une charge (10) telle qu'une lumière fluorescente compacte (« compact fluorescent light » ou CFL). La présente invention concerne également un procédé pour générer un signal de commande et un circuit gradateur à commande de phase.
PCT/AU2011/000177 2010-02-18 2011-02-18 Générateur de signal de commande pour un circuit gradateur WO2011100803A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
NZ601621A NZ601621A (en) 2010-02-18 2011-02-18 Control signal generator for a dimmer circuit
AU2011217744A AU2011217744B2 (en) 2010-02-18 2011-02-18 Control signal generator for a dimmer circuit
CN2011800100644A CN102783252A (zh) 2010-02-18 2011-02-18 用于调光器电路的控制信号发生器
KR1020127024380A KR20130018694A (ko) 2010-02-18 2011-02-18 디머 회로용 제어 신호 발생기
SG2012057840A SG182843A1 (en) 2010-02-18 2011-02-18 Control signal generator for a dimmer circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
AU2010900685A AU2010900685A0 (en) 2010-02-18 Control signal generator for a dimmer circuit
AU2010900685 2010-02-18

Publications (1)

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WO2011100803A1 true WO2011100803A1 (fr) 2011-08-25

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PCT/AU2011/000177 WO2011100803A1 (fr) 2010-02-18 2011-02-18 Générateur de signal de commande pour un circuit gradateur

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KR (1) KR20130018694A (fr)
CN (1) CN102783252A (fr)
AU (1) AU2011217744B2 (fr)
NZ (1) NZ601621A (fr)
SG (1) SG182843A1 (fr)
WO (1) WO2011100803A1 (fr)

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WO2013054297A1 (fr) * 2011-10-14 2013-04-18 Koninklijke Philips Electronics N.V. Système et procédé de contrôle de la gradation d'intensité d'un dispositif d'éclairage à semi-conducteurs
US10182481B2 (en) 2016-04-26 2019-01-15 RAB Lighting Inc. Bi-level low voltage dimming controller for lighting drivers
EP3914048A1 (fr) * 2020-05-18 2021-11-24 Smart Home SA Gradateur numérique et procédé pour faire varier l'intensité lumineuse d'une source de lumière électronique

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CN111564979A (zh) * 2020-04-16 2020-08-21 厦门天力源光电科技有限公司 一种基于切相电子调光/调速器的负载启动方法

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US5629607A (en) * 1984-08-15 1997-05-13 Callahan; Michael Initializing controlled transition light dimmers
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US6020689A (en) * 1997-04-10 2000-02-01 Philips Electronics North America Corporation Anti-flicker scheme for a fluorescent lamp ballast driver
US7420333B1 (en) * 2004-01-29 2008-09-02 Marvell International Ltd. Mixed mode control for dimmable fluorescent lamp
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US20070217237A1 (en) * 2006-03-17 2007-09-20 Lutron Electronics Co., Inc. Dimmer for preventing asymmetric current flow through an unloaded magnetic low-voltage transformer
EP2059097A1 (fr) * 2006-08-31 2009-05-13 Panasonic Electric Works Co., Ltd Dispositif de commande de lampe à décharge et dispositif d'éclairage
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Publication number Priority date Publication date Assignee Title
WO2013054297A1 (fr) * 2011-10-14 2013-04-18 Koninklijke Philips Electronics N.V. Système et procédé de contrôle de la gradation d'intensité d'un dispositif d'éclairage à semi-conducteurs
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US9674904B2 (en) 2011-10-14 2017-06-06 Philips Lighting Holding B.V. System and method for controlling dimming of solid state lighting device
US10182481B2 (en) 2016-04-26 2019-01-15 RAB Lighting Inc. Bi-level low voltage dimming controller for lighting drivers
EP3914048A1 (fr) * 2020-05-18 2021-11-24 Smart Home SA Gradateur numérique et procédé pour faire varier l'intensité lumineuse d'une source de lumière électronique
US11638337B2 (en) 2020-05-18 2023-04-25 Smart Home Sa Digital dimmer and method for varying the luminous intensity of an electronic light source

Also Published As

Publication number Publication date
SG182843A1 (en) 2012-09-27
AU2011217744A1 (en) 2012-08-23
KR20130018694A (ko) 2013-02-25
CN102783252A (zh) 2012-11-14
NZ601621A (en) 2014-07-25
AU2011217744B2 (en) 2015-07-02

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