WO2011095962A2 - Puce - Google Patents

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Publication number
WO2011095962A2
WO2011095962A2 PCT/IB2011/051124 IB2011051124W WO2011095962A2 WO 2011095962 A2 WO2011095962 A2 WO 2011095962A2 IB 2011051124 W IB2011051124 W IB 2011051124W WO 2011095962 A2 WO2011095962 A2 WO 2011095962A2
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WO
WIPO (PCT)
Prior art keywords
die
transaction
identity information
source identity
response
Prior art date
Application number
PCT/IB2011/051124
Other languages
English (en)
Other versions
WO2011095962A3 (fr
Inventor
Ignazio Antonino Urzi
Olivier Sauvage
Philippe D'Audigier
Andrew Michael Jones
Stuart Ryan
Original Assignee
Stmicroelectronics (Grenoble2) Sas
Stmicroelectronics (Research & Development) Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from EP10305123A external-priority patent/EP2333672B1/fr
Application filed by Stmicroelectronics (Grenoble2) Sas, Stmicroelectronics (Research & Development) Limited filed Critical Stmicroelectronics (Grenoble2) Sas
Publication of WO2011095962A2 publication Critical patent/WO2011095962A2/fr
Publication of WO2011095962A3 publication Critical patent/WO2011095962A3/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

Definitions

  • the present invention relates to a die, a package comprising a die and a further die, and a method.
  • CMOS complementary metal-oxide-semiconductor
  • a die for use in a package comprising said die and at least one further die, said die comprising an interface configured to receive a transaction from said further die via an interconnect and to transmit a response to said transaction to said further die via said interconnect; and mapping circuitry configured to receive at least first source identity information of said received transaction, said first source identity information associated with a source of said transaction, and to modify said transaction to comprise local source identity information as source identity information for said transaction.
  • a method comprising receiving at an interface of a die, a transaction from a further die, said die and further die being provided in a package; receiving at least first source identity information of said received transaction, said first source identity information associated with a source of said transaction; modifying said transaction to comprise local source identity information as source identity information for said transaction; and transmitting via said interface, a response to said transaction to said further die.
  • Figure lb shows a schematic side view of the package incorporating two dies of Figure la;
  • Figure 2 schematically shows the interface between the two die of Figure 1 ;
  • Figure 3 shows schematically different types of the packets transmitted from one die to the other
  • Figure 4 shows two dies, including respective circuitry, die embodying the present invention
  • Figure 5 shows a flow diagram for a method embodying the present invention
  • FIGS. 6a to 6h show the format of messages in an embodiment of the invention. Detailed description of embodiments of the invention
  • a plurality of integrated circuit dies is incorporated within a single package.
  • a single package having two dies is described. However, it should be appreciated that this is by way of example only and more than two dies may be provided in some embodiments of the invention.
  • a communication channel is provided between the systems on the different silicon dies.
  • the communications channel or on-chip interconnect may provide high bandwidth and low latency.
  • various signals are integrated onto the communication channel in order to reduce pin count and power consumption.
  • Some embodiments of the present invention may provide a universal communication channel which allows the interface to retain their compatibility with the channel that allows for different implementations of the interfaces.
  • the analogue circuitry can be provided on one die and the digital circuitry can be provided on a different die.
  • the analogue die may have its required voltage and/or transistor gate oxide thickness whilst the digital part of the die can use a different voltage and/or transistor gate oxide thickness.
  • the digital die may predominantly contain digital circuitry and a relatively small amount of analogue circuitry and/or the analogue die may predominantly contain analogue circuitry and a relative small amount of digital circuitry.
  • each die may be designed to provide a particular function which may require various different mixes of analogue and digital circuitry in the implementation of that particular function. In some embodiments, this may mean that the same die or same design for a die may be used in different packages. By introducing this modularity, design time may be reduced.
  • a single package comprising two or more dies will be referred to as a system in package.
  • one system in package may comprise: a 32 nanometre die containing high speed CPUs (central processing units), one or more DDR3 controllers and other elements; and a 55 nanometre die containing analogue PHYs (physical layer devices).
  • the analogue circuitry is contained on a different die to that containing the digital circuitry, the 32 nanometre die is able to maximise the benefits from the reduction in size.
  • a system in package embodiment is described for a set top box.
  • a set top box application die and a media processing engine 4.
  • one package could comprise an RF (radio frequency) die and a TV tuner die.
  • a wireless networking PHY layer die may be incorporated in the same package as an RF die.
  • Embodiments of the invention may be used where there are two or more dies in a package and the dies are manufactured in different technologies. Embodiments of the invention may alternatively or additionally be used where it is advantageous for at least one of the dies to be certified, validated or tested independently for conformance to some standard. Embodiments of the invention may alternatively or additionally be used where one of the dies contains special- purpose logic to drive specific wireless, optical or electrical interfaces so that the other die(s) can be manufactured independently and not incur any cost associated with the special purpose logic. Embodiments of the invention may alternatively or additionally be used where one of the dies contains information (for example encryption information) which is to be withheld from the designers/manufacturers of the other dies. Embodiments of the invention may alternatively or additionally be used where one of the die contains high-density RAM or ROM and it is preferable to separate this from standard high speed logic for reasons of fabrication yield and/or product flexibility.
  • the system in-package 12 comprises a set top box application die 2 and a media processing engine die 4.
  • the two dies, 2 and 4 are connected to each other via an interface 6.
  • the interface 6 comprises a bidirectional point-to-point-interface 8, a HD (high definition) video output 10 and a SD (secure digital) video output 11 from the media processing engine 4 to the set top application die 2.
  • the dies 2 and 4 are connected to circuitry outside the system in package.
  • the set top box application die 2 is connected to a Wi-Fi chipset 14 and to a FLASH memory 18.
  • the set top box application die 2 also comprises inputs/outputs 16. It should be appreciated that the number of inputs/outputs shown is by way of example only and more or less than six inputs/outputs may be provided. Each of these inputs/outputs may be both an input and an output, just an input or just an output.
  • the set top box application die 2 is also connected to three demodulators 20a, 20b and 20c. Each of the demodulators is connected to a respective tuner 22a, 22b and 22c.
  • the media processing engine die 4 is connected to a DDR3-DRAM 24.
  • FIG. lb shows the system in package of Figure la, but from the side. Again, this is a schematic representation of the system in package 12.
  • the system in package 12 comprises PCB (printed circuit board) layers 200 with vias 202 extending there though.
  • a substrate structure 206 is supported by balls 204 of solder, the solder balls 204 being between the PCB 200 and the substrate structure 206.
  • the substrate structure 206 is provided with vias 208 there through.
  • the substrate structure 206 may be of fibre glass.
  • the substrate structure 206 has layer 0 referenced 207d which contacts the solder balls 204.
  • layer 1 referenced 207c which is the power layer.
  • layer 2 referenced 207b
  • the ground layer Next there is the fourth layer, layer 3, referenced 207a, which is the signal layer which is in contact with solder balls 210.
  • the solder balls 210 on the side of the substrate structure opposite to that facing the PCB layers 200 support the dies 2 and 4.
  • electrical paths are provided by the solder balls and the vias.
  • the interface 8 is defined by paths from one die to the other die comprising: solder balls connected to the one die; the solder balls connected to the one die being connected to the signal layer of the substrate structure 206, the signal layer of the substrate structure being connected to respective solder balls associated with the other die.
  • the connection path may include vias in the substrate structure. It should be appreciated that this is only one example of a possible implementation for the interface and the connections of the interface 8 may be implemented in a number of alternative ways.
  • the elements which are supported by the PCB layers 200 are then encapsulated in a plastic moulding 212 to provide a system in package.
  • Some Embodiments of the invention use a common interface which avoids the need for a relatively large number of wires dedicated to particular control signals. Some embodiments are such that modification of the die to take into account new or different control signals is simplified. Some embodiments of the invention are such that testing, validation and packaging of the die is simplified and the inter-die communication can be simplified.
  • the memory mapped transactions will typically be issued from an initiator port or the like.
  • the transactions issued from the initiator port will include an address which is used by a router to route the transactions.
  • the transaction On the receive side, the transaction is received by a target port or the like and then routed by a router to a destination depending on the address information.
  • the memory transactions can be considered to be routed point-to-point transactions.
  • a control signal is point-to-point, without requiring any routing. In other words a line or wire on one die is mapped to a corresponding line or wire on the other die.
  • a signal change on a wire in one die is communicated via the interface and associated circuitiy such that there is corresponding signal change on a corresponding wire in the other die in such a manner as to be functionality transparent to the entities which communicate using this wire.
  • control signals include, but are not limited to, interrupts, handshakes (e.g. request, acknowledge pairs), resets, power state change requests, enable/disable signals, alarm signals, synchronisation signals, clock signals, status signals, functional mode setting signals, sense signals, presence detect signals, power status signals, endian signals, security mode signals, LED (light emitting diode) control, external chip control (e.g. chip select, write protect, chip enables etc) and signals taken off-chip (i.e. outside the package) to control associated electronic items.
  • Figures 2 and 3 are used to illustrate the communication between the dies 2 and 4 of Figure 1.
  • the majority of the communication between the two dies 2 and 4 connected by the inter-die interface 8 will be read and write transactions to the memory address space associated with the respective dies.
  • This traffic will generally be two- way traffic.
  • DMA direct memory access
  • These signals can additionally or alternatively include any one or more of the controls signals mentioned above. These latter signals are the control signals discussed previously and are sometimes referred to out of band signals (OOB).
  • the memory transactions (for example read and write) are carried by a sequence of packets over the inter-die interface 8.
  • Figure 2 shows the inter-die interface.
  • a packet multiplexer 26 is provided on each of the dies. This is connected to the inter-die interface 8, at the other end of which is a respective packet de-multiplexer 28.
  • Each die thus comprises a packet multiplexer for the traffic going to the other die and a packet de-multiplexer for the traffic received from the other die.
  • the packet multiplexer receives an input from a respective bundle 30 0 -30N.
  • each bundle has the same number of wires.
  • each bundle may have different numbers of wires.
  • Each wire is connected to a respective register 3 lo -n which holds the current signal value associated with that wire.
  • Each wire is allocated a predefined position within one bundle.
  • One or more respective signals are associated with a particular wire.
  • a particular signal will be allocated a particular wire in a particular bundle of wires.
  • the power down request will be allocated wire number b+1 in bundle 1.
  • Each bundle is arranged to be transmitted as a single packet together with a bundle identifier which is referred to as a virtual channel identifier.
  • the packet may be atomic.
  • the packet multiplexer 26 receives an input in the form of packets from one or more of the bundles.
  • the packet multiplexer also receives memory transactions which have been split into packets.
  • the packet multiplexer multiplexes the packets output by the bundles and the memory transaction packets and transmits them across the point-to-point interface 6 to the packet demultiplexer 28.
  • the packet de-multiplexer 28 uses the bundle identifier of the bundle packets to direct each received bundle packet to a respective incoming bundle circuitry 32 0 to 32 n .
  • the respective incoming bundle circuitry 32 associate each bit in the received packet with the associated output wire and output the associated value to the associated incoming bundle registers 33.
  • the bundle registers 33 are shown as a single block for simplicity. In practice a register is associated with each wire.
  • wire 1 on bundle 0 has a particular signal value on the transmit side
  • the output 1 of the register for bundle 0 will have that signal value.
  • the wires of one bundle may correspond to respective outputs of different registers.
  • two or more wires may map to a fewer number of wires.
  • one or more wires may map to a greater number of wires.
  • the state of each wire in the bundle is not continuously transmitted.
  • the state of the wire is sampled at regular intervals and these samples are transmitted across the interface 8 in a respective wire packet along with data traffic.
  • the sample may be used to specify the state of the respective register 31 which holds the state of each out of band signal on the transmit side of the interface.
  • the number of registers may be the same as the number of wires or less than the number of wires.
  • each register is connected to a single wire. Alternatively or additionally, one register may be connected to two or more wires. Where a register connected to more than one wire a plurality of bits may be used to represent information such as a state or the like.
  • the transmission in the interface 8 is performed bi-directionally so that the wires can be virtually connected from either side.
  • each die has a packet multiplexer and a packet de-multiplexer.
  • the packet multiplexer and de-multiplexer may share the same physical interface so that a die will receive and transmit via a common interface, that is on the same physical connection.
  • a packet multiplexer and de-multiplexer on one die have separate interfaces. In other words, a die will receive and transmit on different interfaces.
  • the interface can be regarded as a set of wires or connectors extending between the two dies.
  • the wires may be subdivided into one or more lanes. Where the wires are subdivided into lanes, the or each lane may be arranged to carry packets.
  • the interface 8 may be considered in some sense universal and is capable of carrying different classes of communication such as signals (control signals) and busses (memory transactions).
  • the interface 8 can be implemented in serial or parallel form.
  • the data in a packet may be transmitted serially or in parallel. It is preferred that the interface 8 be a high speed link.
  • the sampling rate, the number of bundles transmitted and/or the priority of transmission of these bundles can be configured as required.
  • the states of signals comprising each wire bundle can be periodically sampled at a rate which is separately configurable for each bundle, In other words, each bundle can have a different sampling rate associated therewith.
  • Each bundle sample is formatted into a packet as illustrated in Figure 3.
  • the bundle sample may be formatted in the respective bundle 30 where the additional information to packetize the bundles samples are added.
  • the multiplexer may incorporate circuitiy which is configured to perform or complete the packetization.
  • the bundle sample packet is referenced 34.
  • the first field 36a of the bundle sample packet 34 comprises information to identify the packet to the receiving logic as a wire bundle packet.
  • this field of the packet comprises two bits. However, it should be appreciated that in alternative embodiments of the invention, more or less than two bits may be used for this field.
  • This field is followed by a bundle identity field 36b.
  • the bundle identity field allows the packet to be routed to the appropriate bundle circuitry 32 on the receiving die. This therefore identifies the bundle from which the packet originates.
  • the field comprises 8 bits. However, it should be appreciated that more or less than 8 bits may be used.
  • the packet payload 36c comprises b bits, one for each input wire to the bundle on the transmitting side.
  • b may be, for example 80 bits. In one implementation, there may be four bundles.
  • the appropriate payload is routed to the appropriate bundle circuitry 32 on the receive side, shown in Figure 2 using the bundle identification.
  • the bundle circuitry 32 will map the bundle payload to the appropriate incoming bundle register 33.
  • each bundle is sampled at a rate of (CLK)/2 N where CLK is the clock rate and N is one of: (2, 3, 4....31).
  • CLK is the clock rate
  • N is one of: (2, 3, 4....31).
  • CLK the clock rate
  • N is one of: (2, 3, 4....31).
  • the packet multiplexer 26 illustrated in Figure 2 will comprise logic to arbitrate, if necessary, and decide on the transmission order of the packets. This will typically produce a time division multiplex of bundle packets and memoiy packets on the physical transmission on the interface between the first and second die.
  • the interface 8 is also used for the memory transactions such as memory reads and/or writes.
  • An example of the memory transaction packet 38 which is sent across the same interface 8 is also shown in Figure 3 and is referenced 38.
  • the first field indicates that the packet is a NoC (network-on-chip) packet.
  • the second field 40b indicates the FIFO-ID (first- in first-out identifier).
  • the die comprises queues implemented by FIFOs.
  • FIFOs In the embodiment shown in Figure 2, there are two FIFOs which provide a high priority queue 35 and a low priority queue 37.
  • the interconnect delivers the memory transaction to the appropriate FIFO depending on which queue the transaction belongs to. There can be more than two queue classifications in alternative embodiments.
  • the third field 40c indicates if the packet is a head packet, a tail packet or an intermediate packet.
  • One memory instruction may be sent in a plurality of different packets.
  • the final field is the payload field 40d which includes the address and/or data to be written or read and/or the associated instruction and/or the transaction attributes of belonging to the protocol used on chip to perform memory transactions.
  • the NoC field is allocated 2 bits
  • the FIFO-ID field is allocated 6 bits
  • information as to whether the packet is a head, a tail or intermediate packet is allocated 2 bits
  • the payload is allocated B bits. It should be appreciated that the actual sizes of the respective field is by way of example only and alternative embodiments may have different sizes for the fields.
  • the wire packet 34 and the NoC 38 packet have the same format as represented by the general packet format 42.
  • the first 2 bits 44a represent the type of the packet.
  • the second 6 bits represents the VC-ID 44b (virtual channel-identity). This is followed by the segment identifier 44c and the payload 44d.
  • the type is allocated 2 bits, the VC-ID 44b is allocated 6 bits, the packet ID segment ID 44c is allocated 2 bits and the payload 44d is allocated B bits.
  • a time slot structure may be used where packets are allocated to a particular time slot. This may be controlled by the packet multiplexer or control circuitry associated therewith. Time slots could be assigned to particular wire bundle packets or to memory transaction packets belonging to a particular priority queue.
  • the packets may be sent serially or in parallel.
  • One embodiment of the present invention involves transmitting the packets in a narrow parallel form with, for example, seven or fifteen wires.
  • the packets, when received are latched into the bundle circuitry 32 on the receiving side. Once latched, the incoming bundle circuitry 32 causes the values to be stored to the appropriate register 33.
  • the signals can then be asserted to where the incoming signals need to be mapped on the incoming die. For example, interrupts will typically be mapped directly to the interrupt controller of the main CPU.
  • the packet/bundle mapping is performed in a simple one to one manner without permutation, in one embodiment of the invention. This means that wire W of bundle B on the outgoing bundle is mapped to wire W of bundle B on the incoming bundle circuitry 32 for all implemented values ofW and B.
  • the initiator source identifier (SRC) in the interconnect bus may be implemented using a field of "n" bits that is carried along the bus together with the other information the build a bus transaction such as address, data, size, opcode, etc.
  • the overall system on chip source map is, in embodiments of the present invention, set up such that there is no ambiguity for the response traffic routing.
  • the initiator is on one die and the target is on another die.
  • Embodiments of the present invention are such that the different dies may be independently developed, but nevertheless be such that incorporating two or more such dies into a common package is simplified. The package thus functions as a single entity but the dies can be independently designed and easily integrated.
  • Embodiments of the present invention therefore may allow the designing of the interconnects on the respective dies with two independent source identifier maps but at the same time allowing full interoperability between the dies.
  • FIG. 4 schematically shows two dies embodying the present invention.
  • the first die 2 is the initiator of a transaction whilst the second die 4 is the recipient of the transaction and generates the response which is sent back to the initiator.
  • each die will both be an initiator and a responder so that the circuitry shown schematically in relation to die 4 will also be present in die 2 and the circuitry shown schematically in die 2 will also be present in die 4.
  • separate interfaces may be provided in dependence on whether the die is acting as an initiator or a responder.
  • common interface circuitry may be used regardless of whether or not the die is acting as an initiator or a responder.
  • the interconnect between the dies may be shared by the initiation and response traffic provided to and from a die.
  • the initiator traffic from one die may use one interconnect and a separate interconnect may be provided for the response traffic to that one die.
  • Figure 4 comprises an initiator 100 which may be a processor or the like.
  • the initiator 100 may initiate a transaction which requires a response.
  • This transaction can be any suitable transaction and may be, for example a memory transaction.
  • the transaction is a read request. However, this is by way of example only. Other examples of request are a write request.
  • the message which is provided by the initiator 100 can be seen from Figure 6a. It should be appreciated that the transactions discussed is by way of example only and the transaction may be any transaction where an initiator requires a response from a target on a second die.
  • the response may be a simple acknowledgement or grant, or may additionally or alternatively require some data.
  • the message may be in the form of a packet or may take any other suitable format.
  • the message comprises a first field 120.
  • This field 120 comprises the memory address which is to be read.
  • This address field will identify a unique location on the second die. The address information will thus be sufficient to ensure that the packet is routed to the second die and that the appropriate memory location on the second die will read.
  • the second field 122 defines the size of the packet.
  • the third field 124 has the source identifier 124 of the initiator 100.
  • the initiator 100 may have for example n source identifiers associated therewith. One of the n source identifiers is used. Typically the source identifiers will be from the set of: 0,1....n-1. n can have an integer value of 1 or more.
  • the initiator 100 is connected to the interconnect bus 102 of the first die 2. It should be appreciated that in embodiments of the present invention, the interconnect bus 102 may be connected to a number of other elements on that die which have been omitted for clarity.
  • the interconnect bus 102 is connected to an interface 104. Alternative forms of connection between the interface 104 and initiator 100 may be used in alternative embodiments of the invention.
  • the interconnect 102 is arranged to modify the packet of Figure 6a and this is shown in Figure 6b.
  • the first field is the address field 120, as in Figure 6a.
  • the second field 122 is the size field, again as in Figure 6a.
  • the third field 126 includes a modified version of the source address 124. Typically a die will have more than one initiator.
  • a first initiator may use a range of source identifiers of 0 to n-1 and a second initiator may use a range of source identifiers of 0 to m-1.
  • the interconnect 102 adds no offset to the source identifiers from the first initiator and an offset of n to the source identifiers of the second initiator. In this way the source of each transaction is uniquely identified.
  • the modified version of the address means that the initiator is identified as well as the particular source address of that initiator.
  • the offset added to the source address is dependent on which initiator is providing the transaction. In this way the identity provided in field 126 will uniquely identify the initiator and the source address within the initiator.
  • the packet shown in Figure 6b is put by the interface 104 onto the interconnect 106.
  • the interconnect 106 provides a connection between the first and second dies 2 and 4 respectively.
  • the packet shown in Figure 6b is therefore received by an interface 108 of the second die 4.
  • the interface 108 is arranged to send the received packet to a mapper 110.
  • the mapper 110 is arranged to modify the packet. In one alternative embodiment, this function may be incorporated in the interconnect 108.
  • This modified packet is shown in Figure 6c.
  • the first field is the address field 120 as discussed for example in relation to Figure 6a.
  • the second field shown is the size field 122 which is similar to the size field shown in Figures 6a and 6b. However it should be appreciated that the value in this field may be altered if the size of the packet has been altered.
  • the third field 128 represents a new source identifier which is assigned by the mapper 110 and which has a unique and fixed value, regardless of the source of the transaction.
  • This same value is used for received transactions from the first die when they reach the second die.
  • This new source identifier value is used on the second die to ensure that the response is routed back to the mapper 110, as will be discussed later. Alternatively or additionally the new source identifier will identify different circuitry to which the response is to be routed before being routed back to the first die.
  • the source identifier from the first die is included in a new user defined field of the interconnect transaction.
  • This field comprises the first die source identity and includes the information which was included in the third field 126 shown in Figure 6b. This is to allow the response to be routed back to the first die.
  • the packet shown in Figure 6c is put onto the bus 116 of the second die 4.
  • the interconnect bus 116 will modify the packet.
  • the modified packet is shown in Figure 6d.
  • the first field, the second field and the fourth field are as shown in Figure 6c.
  • the third field is modified to include a modified version of the local source identifier.
  • an offset is added so that the modified local source identifier for the second die is provided. This offset will allow the mapper to be uniquely identified from other sources on the second die.
  • the mapper could be regarded as being or at least analogous to an initiator in this regard.
  • the bus 116 Using the address information included in the packet, the bus 116 will ensure that the memory transaction is routed to the memory circuitry 114.
  • the memory circuitry 114 will ensure that the requested information is, for example read out.
  • the packet provided by memory circuitry 114 is put onto the bus 116 is shown in Figure 6e.
  • the packet will comprise a first field 134 which comprises the requested data.
  • the second field 132 comprises the modified local source identifier, as shown in the third field of Figure 6d.
  • the third field contains the same information as the fourth field of the packet as shown in Figure 6d.
  • the response can be directed to the mapper.
  • the interconnect bus 116 is arranged to modify the packet put by the memory circuitry 114 onto the bus to the format shown in Figure 6f.
  • the first and third fields are the same as shown in Figure 6e.
  • the second field is modified to insert instead the local source identifier for the second die, as discussed in relation of third field of Figure 6c, in other words to remove the offset.
  • the local source identifier is used to route to response to a particular address of the mapper.
  • the mapper 110 receives the packet shown in Figure 6f and provides the packet as shown in Figure 6g.
  • This response packet consists of a first field with the requested data 134 and a second field which includes the original first die source identity, that identity being the identity as discussed in relation to the third field of the packet of Figure 6b. That packet is transmitted across interconnect 106.
  • the packet is received by the interface 104 of the first die which causes the packet to be modified to the format shown in Figure 6h.
  • the first field comprises the requested data 134 and the second field comprises the local source identifier 124 as discussed in relation to the third field of Figure 6a.
  • the offset is thus removed.
  • This response is then routed to the particular address of the initiator 100 which sent the original request.
  • the source identifier used in the first die is not treated as a source identifier in the second die and vice versa.
  • the first die identifier is carried in the packet in the second die inside a user defined field of the interconnect transaction, this being the field containing information 130. This information is used to allow the response to be routed back to the first die.
  • a new source identifier is assigned to the inter-die request i.e. the request from the first die.
  • a unique and fixed source identifier value (that is a common value) is assigned by the mapper module in the second die, for any transactions from the first die when the transaction is received by the second die. This mapping is reversed for those response transactions leaving the second die and going back to the first die.
  • the source identifier assigned by the mapper 110 is used to ensure the response is routed back to the mapper. .
  • the mapper 110 is also arranged to re-assign the original source identifier carried inside the packet to the response transaction before the response transaction leaves the second die.
  • the original source identifier value of the first die is then used for local routing in the first die of the response transactions which are returned from the second die.
  • Figure 5 shows schematically a method embodying the present invention.
  • the steps shown to the left of Figure 5 represent steps which are taken in the first die whilst the steps shown to the right of Figure 5 represent steps taken in the second die.
  • the initiator 100 will initiate the memory request.
  • the initiator address included in the original request is modified (offset added) to take into account which initiator is providing the request.
  • Step S3 the modified request is transmitted to the second die.
  • Step S4 the memory request is received at the second die.
  • Step S5 a local source address is assigned to the received request and the original source address is included in a further field.
  • the local source address is modified to add an offset to provide a unique modified local source address.
  • Step S7 the request is sent to the memory circuitry.
  • Step S8 the memory circuitry provides the requested information in response to the memory request.
  • Step S9 the local address is modified to the originally assigned local address, by removing the offset.
  • Step S10 the request is modified to re-assign the first die source identifier.
  • Step S 11 the response is transmitted to the first die.
  • Step SI 2 the response is received by the first die.
  • Step S13 the initiator address included in the response is modified to the original initiator identity, by removing the offset.
  • Step S14 the response is routed to the initiator.
  • Embodiments of the present invention may allow for the independency of the two interconnect source identifier maps on the two dies.
  • Embodiments of the present invention may allow the transmit and response sides to the data flows to be treated independently. For example, the first transmit die source identifier is not stored locally in the first die before sending the transactions to the other die. This leads to a simple interconnect architecture which may not require for example outstanding information memory buffers.
  • Embodiments of the present invention may provide further wires on each interconnect link which represents the size of the source identifier field.
  • a typical value for the number of wires is 10. It should be appreciated that this is by way of example and the size of the source identifier field may be larger or smaller than 10 bits. However, serial transmission of packets may avoid the need for this additional wiring.
  • the orientation of the respective dies with respect to the substrates can be changed as compared to the flip chip orientation shown in Figure lb.
  • the dies may be arranged in a stacked arrangement, one above the other.
  • the interface between the two dies is described in preferred embodiments of the invention as being a wired interface, that is provided by a series of wired or wire patterned connections.
  • the interface may be provided by any suitable means for example an optical interface or a wireless interface.
  • both dies may have the "transmitting" part of the circuitry and the "receiving" part of the circuitry so that the interface is bi-directional. It should be appreciated that in some embodiments at least some of the wires or other interface mechanism are bidirectional. In alternative embodiments the interface may comprise two separate paths, on path for received packets and the other path for transmitted packets.

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Abstract

L'invention concerne une puce destinée à être utilisée dans un boîtier. Le boîtier comprend la puce et au moins une autre puce. La puce présente une interface conçue pour recevoir une transaction à partir de l'autre puce via une interconnexion et pour transmettre une réponse à ladite transaction à ladite autre puce via l'interconnexion. La puce présente également un circuit de mappage qui est conçu pour recevoir au moins des premières informations d'identité de source de la transaction reçue, lesdites premières informations d'identité de source étant associées à une source de la transaction. Le circuit de mappage est conçu pour modifier la transaction afin qu'elle comprenne des informations d'identité de source locale en tant qu'informations d'identité de source pour la transaction. Le circuit de mappage est conçu pour modifier ladite transaction reçue afin de fournir lesdites premières informations d'identité de source dans un autre champ.
PCT/IB2011/051124 2010-02-05 2011-03-17 Puce WO2011095962A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP10305123A EP2333672B1 (fr) 2009-12-07 2010-02-05 Interface d'interconnexion de microplaquettes
EP10305123.1 2010-02-05

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WO2011095962A2 true WO2011095962A2 (fr) 2011-08-11
WO2011095962A3 WO2011095962A3 (fr) 2011-10-06

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KR100560761B1 (ko) * 2003-07-08 2006-03-13 삼성전자주식회사 인터페이스 변환 시스템 및 그 방법
DE602005027804D1 (de) * 2005-02-03 2011-06-16 Texas Instruments Inc Chipverbindungsschnittstelle und Protokoll für gestapelten Halbleiterchip
US20060190655A1 (en) * 2005-02-24 2006-08-24 International Business Machines Corporation Apparatus and method for transaction tag mapping between bus domains

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