WO2011081232A1 - Système et procédé informatique pour la mise en œuvre sélective de persistance du processus utilisant une mémoire vive non volatile et une mémoire vive volatile - Google Patents

Système et procédé informatique pour la mise en œuvre sélective de persistance du processus utilisant une mémoire vive non volatile et une mémoire vive volatile Download PDF

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Publication number
WO2011081232A1
WO2011081232A1 PCT/KR2009/007920 KR2009007920W WO2011081232A1 WO 2011081232 A1 WO2011081232 A1 WO 2011081232A1 KR 2009007920 W KR2009007920 W KR 2009007920W WO 2011081232 A1 WO2011081232 A1 WO 2011081232A1
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Prior art keywords
processes
scm
computing
computing system
memory
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PCT/KR2009/007920
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English (en)
Korean (ko)
Inventor
김효진
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주식회사 프롬나이
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Priority to PCT/KR2009/007920 priority Critical patent/WO2011081232A1/fr
Publication of WO2011081232A1 publication Critical patent/WO2011081232A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1438—Restarting or rejuvenating

Definitions

  • It relates to a computing system and a computing method, and more particularly to a computing system and a method that selectively implements process persistence for a plurality of processes.
  • Non-volatile random access memory (hereinafter referred to as NVRAM) is a RAM that does not lose data even when the power supply is cut off.
  • NVRAM includes a battery backed RAM that is maintained in a non-volatile state by a battery, and a storage class memory that maintains stored data without a power supply due to device characteristics without a power supply.
  • SCM Storage Class Memory
  • NVRAM Non-Volatile Random Access Memory
  • PCRAM Phase change RAM
  • MRAM Magnetic RAM
  • FeRAM Feroelectric RAM
  • this SCM has been researched to be utilized as a storage device, a disk cache, etc. in the system hierarchy.
  • a computing system and computing method are provided that implement the persistence of some individual processes being selected without changing the source code of the individual processes.
  • a computing system and computing method are provided in which the persistence of some selected processes and some information for operating the system is maintained even if an unexpected interruption of power supply occurs during execution of the process.
  • a processor that performs computing operations for a plurality of processes, NVRAM operating as at least part of main memory, volatile memory operating as another part of the main memory together with the NVRAM, and the NVRAM and the A computing system is provided that includes a memory controller for controlling at least one of volatile memories.
  • the NVRAM may be a storage class memory (SCM).
  • SCM storage class memory
  • the case of SCM will be described as an example, but embodiments of other forms of NVRAM, such as a battery backed RAM, are not excluded by this exemplary description.
  • the SCM serves as a main memory in a computing operation associated with at least some of the processes selected as persistent processes, and the volatile memory is another portion of the plurality of processes not selected as a persistent process. It may serve as a main memory in computing operations associated with the process of.
  • the first process when a new first process is executed in addition to the plurality of processes, if there is a process associated with the first process among the plurality of processes, the first process inherits persistence from the associated process. I can receive it.
  • the computing system may further include a temporary power supply unit supplying power to the process and the SCM for a threshold time when the power supply of the computing system is cut off.
  • At least some of the registers, cache data, and device state information of the processor may be stored at a first predetermined address in the SCM.
  • the SCM is at least one of a phase change RAM (PCRAM), a magnetroresistive RAM (MRAM), and a ferroelectric RAM (FeRAM).
  • PCRAM phase change RAM
  • MRAM magnetroresistive RAM
  • FeRAM ferroelectric RAM
  • the memory controller stores a slab cache and a file page generated in a computing operation of the plurality of processes in the SCM.
  • the memory controller may allocate a paging space for the DRAM during the booting of the computing system and manage the DRAM through an array of zone descriptors and page descriptors.
  • the memory controller when the computing system is turned on or turned off, the memory controller generates a slab cache (Slab) generated in a computing operation process for a portion of the recovery processes not selected as the permanent process. Cache) and file pages can be deleted from the SCM.
  • slab cache Slab
  • Cache Cache
  • a storage class memory SCM
  • performing a computing operation associated with at least some of the processes selected as a persistent process among a plurality of processes, and using volatile memory as the main memory SCM
  • performing a computing operation associated with some other process not selected as a persistent process of the plurality of processes is provided.
  • the system does not need to be frozen to maintain process continuity, allowing execution to continue while ensuring system stability or consistency.
  • FIG. 1 illustrates a computing system in accordance with one embodiment of the present invention.
  • FIG. 2 is a conceptual diagram illustrating a processing method of a persistent process in a computing system according to an exemplary embodiment of the present invention.
  • FIG. 3 is a conceptual diagram illustrating a processing method of a non-persistent process in a computing system according to an exemplary embodiment of the present invention.
  • FIG. 4 illustrates a physical memory map that recognizes SCMs and DRAMs within a computing system in accordance with one embodiment of the present invention.
  • FIG. 5 illustrates a computing method in accordance with one embodiment of the present invention.
  • FIG. 6 illustrates a process of determining whether a new process is a permanent process when a new process is executed in the computing method according to an embodiment of the present invention.
  • FIG. 7 illustrates a processing method when the power of the computing system is cut off in the computing method according to an exemplary embodiment of the present invention.
  • FIG. 8 illustrates a processing method when power is resumed to a computing system, in accordance with an embodiment of the present invention.
  • FIG. 1 illustrates a computing system 100 in accordance with one embodiment of the present invention.
  • the computing system 100 includes a processor 110, a main memory 120, a memory controller 130, and a storage 140 that process a plurality of processes.
  • the main memory 120 is a storage class memory (SCM) 121 that operates as a main memory in a computing operation for at least some of the plurality of processes, and another part of the plurality of processes.
  • SCM storage class memory
  • DRAM Dynamic Random Access Memory
  • the DRAM 122 is an example of volatile memory capable of operating as a main memory, and may be replaced with another type.
  • the SCM is only one form of NVRAM, and examples of NVRAM other than the SCM are not excluded from the present invention. Same as below.
  • the main memory 120 reads and temporarily stores a required file from the storage 140 for computing operations for a plurality of processes processed by the processor 110, and may be used to cause the computing operation of the process to be terminated.
  • the data during the computing operation for the process and the result data are stored until the data is transferred to the storage 140.
  • Check pointing is a technique for periodically storing an execution image of a process in main memory in storage.
  • check pointing technique has low efficiency due to large space overhead and execution time overhead.
  • check pointing schemes do not back up data continuously, so there is an interval between data backup points, and thus data changed between data backup points may be lost.
  • non-volatile memory such as non-volatile RAM (NVRAM).
  • a plurality of processes performed in the computing system are divided into a persistent process and a non-persistent process.
  • a persistent process is herein where all data and state generated during the execution of the computing operation for the process are preserved even when the computing system is powered off, so that the execution of the computing operation when the system is powered on again. This is a lasting process.
  • a non-persistent process is a process in which data and state generated during the execution of a computing operation for a process are not preserved by powering off the computing system.
  • the main memory 120 of the computing system 100 is the main memory in the computing operation for the non-persistent process and the SCM 121 operating as the main memory in the computing operation for the persistent process.
  • DRAM 122 that operates.
  • the SCM 121 includes, for example, a phase change RAM (PCRAM), a magnetroresistive RAM (MRAM), a ferroelectric RAM (FeRAM), and the like.
  • PCRAM phase change RAM
  • MRAM magnetroresistive RAM
  • FeRAM ferroelectric RAM
  • the SCM 121 and the DRAM 122 may be controlled by the memory controller 130.
  • At least some of the processes set by the user and / or selected by the system operating system are selected as persistent processes.
  • This setting of persistence may be subject to other criteria, depending on the user of the computing system.
  • an image editing process may be set as a permanent process
  • a word processor may be set as a permanent process.
  • Such setting criteria of persistence and / or specific persistence setting values for individual processes may be changed dynamically at any point in time. For example, some processes may be temporarily or persistently set by the user or by the system during operation of the computing system.
  • the persistence of the new process may be set by a user or a system.
  • the setting of the persistence by the system is that the persistence of the new process is set by the setting criteria of the persistence established in the computing system in advance.
  • either of the process's persistence setting by the user and the process's persistence setting by the system may be designated as having a high priority.
  • the computing system 100 may receive an answer from the user as to whether to set the new process as a permanent process. And, the answer received in this way can take precedence over the result of setting the persistence by other criteria established by the system itself.
  • a setup program may be included in the computing system 100 to allow a user to set persistence for an individual process.
  • the newly executed process is an associated application of another process or a dependent process
  • the process is a persistent process
  • the newly executed process is determined as a persistent process.
  • the kernel process and the shell of the operating system are set to be a persistent process unconditionally, so that such persistence is not inherited by other related processes. It is also possible to set exceptions.
  • a plurality of processes are selectively selected as a persistent process or a non-persistent process, and in each case, the SCM 121 or the DRAM 122 operate as the main memory.
  • FIG. 2 is a conceptual diagram 200 illustrating a method of processing a persistent process in the computing system 100 according to an embodiment of the present invention.
  • the computing system 100 may simultaneously recognize the SCM 121 and the DRAM 122 as main memory.
  • caching or paging may be performed in the SCM 121 for the persistent process and for the DRAM 122 for the non-persistent process, respectively, in the same manner as in the conventional main memory.
  • the SCM 121 and the DRAM 122 are recognized and operated by the computing system 100 and the memory controller 130, the SCM 121 and the DRAM 122 are in parallel, and / Or complementarily. Thus, there is no difference in layer or priority on the system between the SCM 121 and the DRAM 122.
  • either the SCM 121 or the DRAM 122 is selected to function as a high priority primary memory and the other is a separate auxiliary. It may be chosen to function as a memory.
  • the present invention should not be limitedly interpreted by this form.
  • an embodiment in which both the SCM 121 and the DRAM 122 are recognized and operated by the computing system 100 and the memory controller 130 should not be excluded.
  • the SCM 121 may be recognized by the kernel 210 as a basic memory of the computing system 100.
  • the SCM 121 is accessed through the memory controller 130 and the interface accessed by the kernel 210.
  • the slab cache 230 of the kernel 210, the persistent processes 220, and the non-persistent processes may be independent of the process persistence. Are all stored in the basic memory SCM 121.
  • the kernel 210, the persistent processes 220, and all of the non-persistent processes may be stored in the SCM 121, which is a basic memory.
  • the SCM manager manages the above contents, and the contents of the data stored in the SCM cell 270 are the same as those of the normal main memory.
  • FIG. 3 is a conceptual diagram 310 for explaining a method of processing a non-persistent process in the computing system 100 according to an embodiment of the present invention.
  • the SCM 121 and the DRAM 122 are each a permanent process and a non-persistent process. It acts as a separate main memory for the process.
  • the structure of the memory control unit 130 that recognizes the basic memory is changed to recognize the DRAM 122, thereby changing the DRAM 122.
  • the computing system 100 may be provided with a separate manager and an interface for recognizing or driving the DRAM 122.
  • the slab cache 230 and the file mapped pages 250 of the non-persistent processes 310 are stored in the SCM 121, as described in the conceptual diagram of FIG. 2.
  • dirty pages whose contents have been changed after being loaded into memory for the file page may be stored in the SCM, and clean pages having no contents may be stored in the DRAM.
  • DRAM 122 is an embodiment of the secondary memory of the SCM 121 which is the primary memory
  • the process of the DRAM manager 330 performing the paging to the DRAM cell 340 may be different from that of the conventional main memory. Can be.
  • the memory controller 130 manages the SCM 121 and the DRAM 122 through a kernel in which some code is modified based on the Linux kernel 2.6.21.
  • the present invention should not be construed as being limited to being implemented by some operating system kernel environments, such as the Linux kernel, and the Linux kernel 2.6.21-based implementation is merely an embodiment.
  • the kernel 210 recognizes the DRAM 121 with ioremap () during the booting process and performs paging for a space starting with a virtual address received as the return value.
  • the additionally and auxiliaryly recognized DRAM 122 is managed by an array of zone descriptors called vrzoone and page descriptors called vrzone_mem_map_t. Since the vrzone or vrzone_mem_map_t data structure itself is initialized during the boot process, it may exist on the SCM 121.
  • the SCM 121 stores a slab cache, a file page, and the like of a non-persistent process, and these are stored when the computing system 100 is powered off and on. Can be removed. That is, residuals such as metadata of a non-persistent process may be erased.
  • the residue erasing process of this non-persistent process may be set to a point in time when the computing system is powered off, or a point in time when the power is turned back on, or any other specific point in time.
  • FIG. 4 illustrates an example physical memory map 400 that recognizes the SCM 121 and the DRAM 122 within a computing system in accordance with one embodiment of the present invention.
  • an address translation method for the DRAM 122 is provided so that the kernel 210 can access the DRAM 122.
  • various values such as a physical address, a virtual address, a page table entry (PTE), a page descriptor address, and a physical page frame number (PFN) may be converted to and used for memory access.
  • PTE page table entry
  • PDN physical page frame number
  • page_addess () used when converting a physical address into a virtual number of weeks is set to correspond to vr_page_address ().
  • the conversion between the PTE and the PFN does not require a separate additional conversion method for the DRAM 122.
  • a DRAM manager (330 of FIG. 3) for managing DRAM may utilize Linux's Buddy system code.
  • DRAM 122 is used only for anonymous page 320 of non-persistent processes 310.
  • a slab cache for non-persistent processes 310 may be used.
  • the DRAM 122 may also be used for the 230 and the file pages 250.
  • vr_alloc_pages corresponds to vr_alloc_pages ().
  • DRAM pages are used in anonymous pages of non-persistent processes, and vr_do_wp_page (), vr_do_no_page (), and vr_do_anonymous_page () functions are added to the page fault routine to allocate when a request for an anonymous page 320 occurs.
  • FIG. 5 illustrates a computing method in accordance with one embodiment of the present invention.
  • step S510 If any process is handled by the processor, it is identified in step S510 whether the process is a persistent process.
  • the persistence may be determined by receiving a user input through a user interface so as to be designated by the user.
  • policies on inheritance of persistence can be established in various ways, for example, a child process (or dependent process) of a non-persistent process can be determined as a non-persistent process.
  • some of the persistent processes do not inherit persistence to child processes.
  • a shell created during the boot of a computing system becomes the parent process of all processes, so inheriting persistence from a child process makes all processes processed in the computing system persistent. It is specified not to inherit persistence.
  • the persistence of such a process may be stored and managed in a persistence field in a data structure.
  • a non-persistent process for example, can have its identity set to zero, a process that is persistent and inherits persistence to child processes 1, which is persistent but 2 that does not inherit persistence to child processes.
  • Each identification value can be set.
  • the pages allocated to the DRAM 122 are transferred to the SCM 121, and when the process is successfully completed, the value of the persistence field is changed from 0 to 1.
  • the pages allocated to the DRAM 122 are found through the list of the vm_area_struct data structure, which is a region describer of the process, and the contents of the pages of the DRAM 122 are assigned to the pages newly allocated in the SCM 121. Copy and modify the PTE for it. In this process, if the persistence specification process fails due to lack of memory or the like, the pages are restored to the DRAM 122, and a report on the failure of the persistent assignment is returned.
  • step S510 the computing method is thus identified in step S510 whether it is a persistent process for any process, and if it is a persistent process, then in step S520 the SCM 121 is stored in main memory.
  • step S540 the process is performed by selecting the DRAM 122 as the main memory in operation S530.
  • FIG. 6 illustrates a process of determining whether a new process is a permanent process when a new process is executed in the computing method according to an embodiment of the present invention.
  • step S620 it is determined in step S620 whether the persistence for the new process has already been specified, that is, whether the persistence specification already exists. If the persistence is already specified, step S510 of FIG. 5 or less is performed.
  • step S630 it is determined in step S630 whether there is a process associated with the newly executed process. If there is an associated process, in step S640 the persistence of the associated processor is inherited and step S510 of FIG. 5 or less is performed again.
  • step S630 determines whether there is no associated processor. If it is determined in step S630 that there is no associated processor, after receiving the persistent designation input through the user interface (S650), the following steps (S510) of FIG. 5 are performed.
  • FIG. 7 illustrates a processing method when the power of the computing system is cut off in the computing method according to an exemplary embodiment of the present invention.
  • step S720 necessary information for system restart, such as a register of the processor, cache data, and device information of the computing system, is backed up to the SCM 121 within the threshold time.
  • the temporary power supply unit is not limited to a specific physical device, but may be in any form such as a battery, an uninterruptible power supply system (UPS), a dual power supply line, and the like, which can be simply inserted into the system.
  • UPS uninterruptible power supply system
  • dual power supply line and the like, which can be simply inserted into the system.
  • the threshold time may be differently designated by a setting, but may be typically specified at several milliseconds to several tens of milliseconds.
  • This backup ensures that all data about the persistent process and the data needed to restart the system are not lost, even in the event of a sudden power off at any point in time.
  • an application may be forcibly reset by a user when an error occurs in the computing system, and then the system may be restored to the state before the error.
  • step 720 it is also possible to back up to any address in the SCM 121, according to an embodiment of the present invention, a space for such a backup in advance, such as power off, When an event is detected, it is also possible to always back up the specified location.
  • FIG. 8 illustrates a processing method when power supply to the computing system is resumed after the power supply shutdown event of FIG. 7 according to an embodiment of the present invention.
  • step S810 data such as processor registers, cache data, and device information, which have been backed up in step S720 of FIG. 7, may be restored.
  • step S720 data may be recovered by directly accessing an address of the dedicated space in this recovery process.
  • step S510 or less continues.

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Abstract

La présente invention concerne un système informatique. Le système informatique peut comporter un processeur effectuant une opération informatique pour une pluralité de processus, une mémoire de classe mémoire (SCM) fonctionnant au moins comme une partie d'une mémoire principale, et une mémoire volatile fonctionnant comme une autre partie de la mémoire principale conjointement avec la mémoire SCM.
PCT/KR2009/007920 2009-12-29 2009-12-29 Système et procédé informatique pour la mise en œuvre sélective de persistance du processus utilisant une mémoire vive non volatile et une mémoire vive volatile WO2011081232A1 (fr)

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PCT/KR2009/007920 WO2011081232A1 (fr) 2009-12-29 2009-12-29 Système et procédé informatique pour la mise en œuvre sélective de persistance du processus utilisant une mémoire vive non volatile et une mémoire vive volatile

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PCT/KR2009/007920 WO2011081232A1 (fr) 2009-12-29 2009-12-29 Système et procédé informatique pour la mise en œuvre sélective de persistance du processus utilisant une mémoire vive non volatile et une mémoire vive volatile

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Cited By (2)

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Publication number Priority date Publication date Assignee Title
WO2016107429A1 (fr) * 2014-12-31 2016-07-07 华为技术有限公司 Procédé d'accès à une mémoire, mémoire de classes de stockage et système informatique
WO2017155551A1 (fr) * 2016-03-11 2017-09-14 Hewlett Packard Enterprise Development Lp Stockage de registre

Citations (3)

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US20070150654A1 (en) * 2005-12-27 2007-06-28 Samsung Electronics Co., Ltd. Storage apparatus using non-volatile memory as cache and method of managing the same
US7321959B2 (en) * 2002-10-02 2008-01-22 Matsushita Electric Industrial Co., Ltd. Control method of a non-volatile memory apparatus

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US7321959B2 (en) * 2002-10-02 2008-01-22 Matsushita Electric Industrial Co., Ltd. Control method of a non-volatile memory apparatus
US20040083405A1 (en) * 2002-10-28 2004-04-29 Sandisk Corporation Power management block for use in a non-volatile memory system
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WO2016107429A1 (fr) * 2014-12-31 2016-07-07 华为技术有限公司 Procédé d'accès à une mémoire, mémoire de classes de stockage et système informatique
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