WO2011079883A1

WO2011079883A1 - Transmission channel, in particular for ultrasound applications

Info

Publication number: WO2011079883A1
Application number: PCT/EP2010/005932
Authority: WO
Inventors: Sandro Rossi; Giulio Ricotti
Original assignee: Stmicroelectronics S.R.L.
Priority date: 2009-12-30
Filing date: 2010-09-29
Publication date: 2011-07-07
Also published as: CN102656802A; CN102656802B

Abstract

A transmission channel (1) is described of the type comprising at least one high voltage buffer block (4) comprising buffer transistors (MB1, MB2, MB3, MB4) and respective buffer diodes (DB1, DB2, DB3, DB4), being inserted between respective voltage references (HVPO, HVP1, HVMO, HVM1), these buffer transistors (MB1, MB2, MB3, MB4) being also connected to a clamping block (5), in turn comprising clamping transistors (MC1, MC2) connected to at least one output terminal (HVout) of this transmission channel through diodes (DC1, DC2) connected to prevent the body diodes of the clamping transistors (MC1, MC2) from conducting. Advantageously according to the invention, the transmission channel (1) comprises at least one reset circuit (20) comprising diodes (DME1, DME2, DME3, DME4) and being inserted between circuit nodes (XME1, XME2, XME3, XME4, XC1, XC2) of the high voltage buffer block (4) and of the clamping block (5), these circuit nodes (XME1, XME2, XME3, XME4, XC1, XC2) being in correspondence with conduction terminals of the transistors (MB l, MB2, MB3, MB4; MC1, MC2) comprised into the high voltage buffer block (4) and into the clamping block (5).

Description

Title: Transmission channel, in particular for ultrasound applications

DESCRIPTION

Technical Field

The present invention relates to a transmission channel.

More specifically the invention relates to a transmission channel of the type comprising at least one high voltage buffer block connected to a clamping block, in turn connected to at least one output terminal of said transmission channel.

The invention particularly, but not exclusively, relates to a transmission channel, in particular for ultrasound applications and the following description is made with reference to this field of application by way of illustration only.

Background Art

As it is well known, the sonography or ultrasonography is a system of medical diagnostic testing that uses ultrasonic waves or ultrasounds and is based on the principle of the transmission of the ultrasounds and of the emission of echo and is widely used in the internist, surgical and radiological field.

The ultrasounds being normally used are comprised between 2 and 20 MHz. The frequency is chosen by taking into consideration that higher frequencies have a greater image resolving power, but penetrate less in depth in the subject under examination.

These ultrasounds are normally generated by a piezoceramic crystal inserted in a probe being maintained in direct contact with the skin of the subject with the interposition of a suitable gel (being suitable for eliminating the air between probe and subject's skin, allowing the ultrasounds to penetrate in the anatomic segment under examination). The same probe is able to collect a return signal or echo, which is suitably processed by a computer and displayed on a monitor.

In particular, the ultrasounds that reach a variation point of the acoustic impedance, and thus for example an internal organ, are partially reflected and the eflected percentage conveys information about the impedance difference between the crossed tissues. It is to be noted that, the big impedance difference between a bone and a tissue being considered, with the sonography it is not possible to see behind a bone, which causes a total reflection of the ultrasounds, while air or gas zones give "shade", causing a partial reflection of the ultrasounds.

The time employed by an ultrasonic wave for carrying out the path of going, reflection and return is provided to the computer, which calculates the depth wherefrom the echo has come, thus identifying the division surface between the crossed tissues (corresponding to the variation point of the acoustic impedance and thus to the depth wherefrom the echo comes).

Substantially, an ultrasonographer, in particular a diagnostic apparatus based on the ultrasound sonography, essentially comprises three parts: - - a probe comprising at least one transducer, in particular of the ultrasonic type, which transmits and receives an ultrasound signal;

an electronic system that drives the transducer for the generation of the ultrasound signal or pulse to be transmitted and receives an echo signal of return at the probe of this pulse, processing in consequence the received echo signal; and

a displaying system of a corresponding sonography image processed starting from the echo signal received by the probe.

In particular, the word transducer generally indicates an electric or electronic device that converts a type of energy relative to mechanical and physical quantities into electric signals. In a broad sense, a transducer is sometimes defined as any device that converts energy from one form to another, so that this latter can be re-processed either by men or by other machines. Many transducers are both sensors and actuators. An ultrasonic transducer usually comprises a piezoelectric crystal that is suitably biased for causing its deformation and the generation of the ultrasound signal or pulse.

A typical transmission channel or TX channel being used in these applications is schematically shown in Figure 1 , globally indicated with 1.

In particular, the transmission channel 1 comprises an input logic 2 that drives, in correspondence with an input bus BUS™, a level shifter 3, in turn connected to a high voltage buffer block 4. The high voltage buffer block 4 is inserted between pairs of high voltage references, respectively higher HVPO and HVP1 and lower HVMO and HVM 1, and has a pair of input terminals, INB1 and INB2, connected to the level shifter 3, as well as a pair of output terminals, OUTB1 and OUTB2, connected to a corresponding pair of input terminals, INC 1 and INC2 of a clamping block 5.

Furthermore, the clamping block 5 is connected to a clamp voltage reference PGND and has an output terminal corresponding to a first output terminal HVout of the transmission channel 1, in turn connected, through an antinoise block 6, to a connection terminal Xdcr for the transducer to be driven through the transmission channel 1.

Finally, a high voltage switch 7 is inserted between the connection terminal Xdcr and a second output terminal LVout of the transmission channel 1.

More in detail, the high voltage buffer block 4 comprises a first branch comprising a first buffer transistor MB 1 and a first buffer diode DB 1, inserted, in series to each other, between a first higher voltage reference HVPO and a buffer central node XBc, as well as a second buffer diode DB2 and a second buffer transistor MB2, being inserted, in series to each other, between the buffer central node XBc and a first lower voltage reference HVMO. The first and the second - - buffer transistor, MB 1 and MB2, have respective control or gate terminals in correspondence with a first XB 1 and a second inner circuit node XB2 of the high voltage buffer block 4 and connected to, and driven by, a first DRB 1 and a second buffer input driver DRB2, in turn connected to the level shifter 3 in correspondence with the first and the second input terminals, INB l and INB2, of the high voltage buffer block 4.

The high voltage buffer block 4 also comprises, in parallel to the first branch, a second branch in turn comprising a third buffer transistor MB3 and a third buffer diode DB3, inserted, in series to each other, between a second higher voltage reference HVP1 and the buffer central node XBc, as well as a fourth buffer diode DB4 and a fourth buffer transistor MB4, inserted, in series to each other, between the buffer central node XBc and a second lower voltage reference HVM 1. The third and fourth buffer transistor, MB3 and MB4, have respective control or gate terminals in correspondence with a third XB3 and a fourth inner circuit node XB4 of the high voltage buffer block 4 and connected to, and driven by, a third DRB3 and a fourth buffer input driver DRB4, in turn connected to the first XB1 and to the second inner circuit node XB2 and then to the first DRB 1 and to the second buffer input driver DRB2, respectively, as well as to a first OUTB 1 and to a second output terminal OUTB2.

In particular, in the example of the figure, the first and third buffer transistors, MB1 and MB3, are high voltage P-channel MOS transistors (HV Pmos) while the second and fourth buffer transistors, MB2 and MB4, are high voltage N-channel MOS transistors (HV Nmos). Moreover, the buffer diodes, DB1, DB2, DB3 and DB4, are high voltage diodes (HV diode).

The clamping block 5 has in turn a first INCl and a second input terminal

INC2, respectively connected to the first OUTB 1 and second output terminal OUTB2 of the high voltage buffer block 4.

In particular, the clamping block 5 comprises a first clamp driver DRC1 connected between the first input terminal INCl and a control or gate terminal of a first clamp transistor MC I, in turn inserted, in series with a first clamp diode DC1, between the clamp voltage reference PGND, in particular a ground, and a clamp central node XCc. The first clamp transistor MC I and the first clamp diode DC 1 are interconnected in correspondence with a first clamp circuit node XC 1.

The clamping block 5 also comprises a second clamp driver DRC2 connected between the second input terminal INC2 and a control or gate terminal of a second clamp transistor MC2, in turn inserted, in series with a second clamp diode DC2, between the clamp central node XCc and the clamp voltage reference PGND. The second clamp transistor MC2 and the second clamp diode DC2 are interconnected in correspondence with a second clamp circuit node XC2. - -

The clamp central node XCc is also connected to the first output terminal HVout of the transmission channel 1, in turn connected to the connection terminal Xdcr through an antinoise block 6 comprising respective first and second antinoise diodes, DN1 and DN2, connected in antiparallel, i.e. by having the anode terminal of the first diode connected to the cathode terminal of the second one and vice versa, between the first output terminal Hvout and the connection terminal Xdcr.

In particular, in the example of the figure, the first clamp transistor MC I is a high voltage P-channel MOS transistor (HV Pmos) while the second clamp transistor MC2 is a high voltage N-channel MOS transistor (HV Nmos). Moreover, the clamp diodes, DC1 and DC2, are high voltage diodes (HV diode) while the antinoise diodes, DN1 and DN2, are low voltage diodes (LV diode).

When the clamping block 5 is on, the first output terminal HVout is at a voltage value substantially corresponding to the ground voltage value GND.

After a pulse cycle, the anode terminals of the first DB1 and third buffer diode DB3 and the cathode terminals of the second DB2 and fourth buffer diode DB4 stabilise themselves at a voltage depending on different factors such as the supply voltage value, inner capacities, which one and how many transistors are used for the switch, the switching frequency etc..

This means that any successive pulse train finds a different, non defined initial condition.

By changing the initial status also the output wave form is modified with the consequence that the input control being identical it is possible to obtain difference outputs. In other words, the wave form of the output signal is function of the input signals and of the initial condition resulting from the previously occurred switches thus creating a sort of "memory effect".

The technical problem of the present invention is that of providing a configuration for a transmission channel able to ensure correct and predictable initial switch conditions, thus suitable for being used for ultrasound applications and having such structural and functional features as to allow to overcome the limits and the drawbacks still affecting the channels realised according to the prior art.

Disclosure of Invention

The solution idea underlying the present invention is that of using suitable high voltage diodes connected to the inner nodes of the high voltage buffer block of the transmission channel for correctly biasing its condition between a pulse cycle and another one.

On the basis of this solution idea the technical problem is solved by a transmission channel of the type comprising at least one high voltage buffer block - - comprising buffer transistors and respective buffer diodes, being inserted between respective voltage references, said buffer transistors being also connected to a clamping block, in turn comprising clamping transistors connected to at least one output terminal of said transmission channel through diodes connected to prevent the body diodes of said clamping transistors from conducting, characterised in that it comprises at least one reset circuit comprising diodes and being inserted between circuit nodes of said high voltage buffer block and of said clamping block, said circuit nodes being in correspondence with conduction terminals of said transistors comprised into said high voltage buffer block and into said clamping block.

More in particular, the invention comprises the following supplementary and optional characteristics, taken alone or in combination, if needed.

According to an aspect of the invention, said clamping block can comprise at least one first clamp transistor inserted, in series with a first clamp diode, between a clamp voltage reference and a clamp central node and interconnected in correspondence with a first clamp circuit node, as well as a second clamp transistor inserted, in series with a second clamp diode, between said clamp voltage reference and said clamp central node and interconnected in correspondence with a second clamp circuit node and wherein said high voltage buffer block comprises at least one first branch in turn including a first buffer transistor and a first buffer diode, inserted, in series to each other, between a first higher voltage reference and a buffer central node and interconnected in correspondence with a first memory node, as well as a second buffer diode and a second buffer transistor, inserted, in series to each other, between said buffer central node and a first lower voltage reference and interconnected in correspondence with a second memory node, characterised in that said reset circuit can comprise:

a first memory diode, inserted between said first memory node and said first clamp circuit node; and

- a second memory diode, inserted between said second memory diode and said second clamp circuit node.

According to this aspect of the invention, said first memory diode can have a cathode terminal connected to said first memory node and an anode terminal connected to said first clamp circuit node and said second memory diode can have an anode terminal connected to said second memory node and a cathode terminal connected to said second clamp circuit node.

Also according to this aspect of the invention, said first memory node can be connected to an anode terminal of said first buffer diode and said first clamp circuit node can be connected to an anode terminal of said first clamp diode and - - said second memory node can be connected to a cathode terminal of said second buffer diode and said second clamp circuit node can be connected to a cathode terminal of said second clamp diode.

Furthermore, according to this aspect of the invention, said first memory node can be in correspondence with a drain terminal of said first buffer transistor and said second memory node can be in correspondence with a drain terminal of said second buffer transistor.

According to another aspect of the invention, said high voltage buffer block can also comprise, in parallel to said first branch, a second branch in turn including a third buffer transistor and a third buffer diode, inserted, in series to each other, between a second higher voltage reference and said buffer central node interconnected in correspondence with a third memory node, as well as a fourth buffer diode and a fourth buffer transistor, inserted, in series to each other, between said buffer central node and a second lower voltage reference and interconnected in correspondence with a fourth memory node, characterised in that said reset circuit can further comprise:

a third memory diode, inserted between said third memory node and said first clamp circuit node; and

a fourth memory diode, inserted between said fourth memory node and said second clamp circuit node.

According to this aspect of the invention, said third memory diode can have a cathode terminal connected to said third memory node and an anode terminal connected to said first clamp circuit node and said fourth memory diode can have an anode terminal connected to said fourth memory node and a cathode terminal connected to said second clamp circuit node.

Also according to this aspect of the invention, said third memory node can be connected to an anode terminal of said third buffer diode and said first clamp circuit node can be connected to an anode terminal of said first clamp diode and said fourth memory node can be connected to a cathode terminal of said fourth buffer diode and said second clamp circuit node can be connected to a cathode terminal of said second clamp diode.

Furthermore, according to this aspect of the invention, said third memory node can be in correspondence with a drain terminal of said third buffer transistor and said fourth memory node can be in correspondence with a drain terminal of said fourth buffer transistor.

Moreover, according to another aspect of the invention, said clamping block can comprise respective first and second clamp drivers connected to control terminals of said first and second clamp transistors.

Furthermore, according to another aspect of the invention, said high voltage - - buffer block can comprise respective buffer drivers connected to control terminals of said buffer transistors.

According to a preferred aspect of the invention, said transmission channel can further comprise an antinoise block between said at least one output terminal and one connection terminal for a load to be driven.

According to this aspect of the invention, said load can be a piezoelectric transducer.

Finally, according to another aspect of the invention, said transmission channel can further comprise a high voltage switch inserted between said connection terminal and a further output terminal of such a transmission channel.

The characteristics and the advantages of the transmission channel according to the invention will be apparent from the following description of an embodiment thereof given by way of indicative and non limiting example with reference to the annexed drawings.

Brief Description of Drawings

In these drawings:

Figure 1 schematically shows a transmission channel for ultrasound applications realised according to the prior art;

- Figure 2 schematically shows a transmission channel, in particular for ultrasound applications, realised according to the invention.

Modes for Carrying Out the Invention

With reference to these figures, and in particular to Figure 2, a transmission channel is described for ultrasound applications, always globally indicated with 1.

Elements being structurally and functionally correspondent to the transmission channel described in relation to the prior art and shown in Figure 1 will be given the same alphanumeric references for sake of simplicity.

In its more general form, the transmission channel 1 is of the type comprising at least one high voltage buffer block 4 in turn comprising buffer transistors and respective buffer diodes, being inserted between respective voltage. The buffer transistors are also connected to a clamping block 5, in turn comprising clamping transistors connected to at least one output terminal HVout of the transmission channel 1 through diodes connected to prevent the body diodes of the clamping transistors from conducting. Moreover, the transmission channel 1 comprises at least one reset circuit 20 comprising diodes and being inserted between circuit nodes of the high voltage buffer block 4 and of the clamping block 5, said circuit nodes being in correspondence with conduction terminals of the transistors comprised into the high voltage buffer block 4 and - - into the clamping block 5.

According to an embodiment of the invention, the reset circuit 20 is suitably connected to the inner nodes of the high voltage buffer block 4 and of the clamping block 5 that are to be correctly "re-positioned".

More in detail, according to an embodiment of the invention, the reset circuit

20 is connected to the interconnection circuit nodes between the transistors and the buffer diodes of the high voltage buffer block 4 and the clamp circuit nodes of the clamping block 5. In particular, the reset circuit 20 is connected:

to a first memory diode XME1, between the first buffer transistor MB 1 and the first buffer diode DB 1 ;

to a second memory node XME2, between the second buffer transistor MB2 and the second buffer diode DB2;

to a third memory node XME3, between the third buffer transistor MB3 and the third buffer diode DB3;

- to a fourth memory node XME4, between the fourth buffer transistor

MB4 and the fourth buffer diode DB4;

to the first clamp circuit node XC1 , between the first clamp transistor MCI and the first clamp diode DC1; and

to the second clamp circuit node XC2, between the second clamp transistor MC2 and the second clamp diode DC2.

In fact, as previously seen, the clamping block 5 comprises the first clamp transistor MCI inserted, in series with the first clamp diode DC 1, between the clamp voltage reference PGND and the clamp central node XCc and interconnected in correspondence with the first clamp circuit node XC1, as well as the second clamp transistor MC2 inserted, in series with the second clamp diode DC2, between the clamp voltage reference PGND and the clamp central node XCc and interconnected in correspondence with the second clamp circuit node XC2.

Moreover, the high voltage buffer block 4 comprises at least one first branch in turn including the first buffer transistor MB 1 and the first buffer diode DB 1, being inserted, in series to each other, between a first higher voltage reference HVP0 and a buffer central node XBc and interconnected in correspondence with the first memory node XME1 , as well as the second buffer diode DB2 and the second buffer transistor MB2, being inserted, in series to each other, between the buffer central node XBc and a first lower voltage reference HVM0 and interconnected in correspondence with the second memory node XME2.

According to an embodiment of the invention, the reset circuit 20 comprises respective memory diodes inserted between these circuit nodes and in particular at least: - - a first memory diode DME1, being inserted between the first memory node XME1 and the first clamp circuit node XC1 ; and

a second memory diode DME2, being inserted between the second memory node XME2 and the second clamp circuit node XC2.

In particular, the first memory diode DME1 has a cathode terminal connected to the first memory node XME1 and an anode terminal connected to the first clamp circuit node XC1. In a dual way, the second memory diode DME2 has an anode terminal connected to the second memory node XME2 and a cathode terminal connected to the second clamp circuit node XC2.

Moreover, as previously seen, the high voltage buffer block 4 comprises, in parallel to the first branch, a second branch in turn including the third buffer transistor MB3 and the third buffer diode DB3, being inserted, in series to each other, between a second higher voltage reference HVP1 and the buffer central node XBc and interconnected in correspondence with the third memory node XME3, as well as the fourth buffer diode DB4 and the fourth buffer transistor MB4, being inserted, in series to each other, between the buffer central node XBc and a second lower voltage reference HVM1 and interconnected in correspondence with the fourth memory node XME4.

Further, the reset circuit 20 then comprises:

- a third memory diode DME3, being inserted between the third memory node XME3 and the first clamp circuit node XC 1 ; and

a fourth memory diode DME4, being inserted between the fourth memory node XME4 and the second clamp circuit node XC2.

In particular, the third memory diode DME3 has a cathode terminal connected to the third memory node XME3 and an anode terminal connected to the first clamp circuit node XC 1. In a dual way, the fourth memory diode DME4 has an anode terminal connected to the fourth memory node XME4 and a cathode terminal connected to the second clamp circuit node XC2.

According to an embodiment of the invention, the memory diodes DME1 , DME2, DME3 and DME4 are high voltage diodes (HV diode).

In substance, the reset circuit 20 forces all the circuit nodes whereto it is connected in a neighbourhood of a ground reference value and allows the transmission channel 1 to restart under a same condition at any pulse cycle.

It is to be noted that the memory circuit nodes correspond to the drain terminals of the corresponding buffer transistors of the high voltage buffer block 4. Moreover, the memory diodes are connected so as to have terminals being not homologue with the buffer diodes.

In particular, the first memory diode DME1 has the cathode terminal connected to the anode terminal of the first buffer diode DB 1 , the second memory - - diode DME2 has the anode terminal connected to the cathode terminal of the second buffer diode DB2, the third memory diode DME3 has the cathode terminal connected to the anode terminal of the third buffer diode DB3, and the fourth memory diode DME4 has the anode terminal connected to the cathode terminal of the fourth buffer diode DB4.

A previously seen, the clamping block 5 and the high voltage buffer block 4 comprise respective clamp and buffer drivers connected to control terminals of the clamp and buffer transistor, respectively.

Furthermore, the transmission channel 1 comprises an antinoise block 6 inserted between the output terminal HVout and a connection terminal Xdcr for a load to be driven, in particular a piezoelectric transducer.

Finally, the transmission channel 1 comprises a high voltage switch 7 inserted between the connection terminal Xdcr and a further output terminal LVout thereof.

According to an embodiment of the invention, the transmission channel 1 is particularly used for the driving of a piezoelectric transducer for ultrasound applications.

In substance, the reset circuit 20, after each clamping step realised by the clamping block 5, forces the drain terminal voltage value of the buffer transistors, which are high power MOS transistors, comprised into the high voltage buffer block 4 to voltage values next to a ground reference value, so that successive pulse cycles applied to the transmission channel 1 restart all from a same initial condition. In particular, in the case of ultrasound applications, this limits the differences between ultrasound pulse and ultrasound pulse.

Obviously a technician of the field, with the aim of meeting incidental and specific needs, will be allowed to introduce several modifications and variations to the transmission channel above described, all comprised within the scope of protection of the invention as defined by the following claims.

Claims

1. Transmission channel (1) of the type comprising at least one high voltage buffer block (4) comprising buffer transistors (MB l, MB2, MB3, MB4) and respective buffer diodes (DB 1, DB2, DB3, DB4), being inserted between respective voltage references (HVPO, HVP1, HVMO, HVM 1), said buffer transistors (MBl , MB2, MB3, MB4) being also connected to a clamping block (5), in turn comprising clamping transistors (MC I , MC2) connected to at least one output terminal (HVout) of said transmission channel (1) through diodes (DCl, DC2) connected to prevent the body diodes of said clamping transistors (MC 1 , MC2) from conducting characterised in that it comprises at least one reset circuit (20) comprising diodes (DME1, DME2, DME3, DME4) and being inserted between circuit nodes (XME1, XME2, XME3, XME4, XC 1, XC2) of said high voltage buffer block (4) and of said clamping block (5), said circuit nodes (XME1, XME2, XME3, XME4, XC 1 , XC2) being in correspondence with conduction terminals of said transistors (MB l, MB2, MB3, MB4; MC I, MC2) comprised into said high voltage buffer block (4) and into said clamping block (5).

2. Transmission channel (1) according to claim 1 , wherein said clamping block (5) comprises at least one first clamp transistor (MCI) inserted, in series with a first clamp diode (DC l), between a clamp voltage reference (PGND) and a clamp central node (XCc) and interconnected in correspondence with a first clamp circuit node (XC1), as well as a second clamp transistor (MC2) inserted, in series with a second clamp diode (DC2), between said clamp voltage reference (PGND) and said clamp central node (XCc) and interconnected in correspondence with a second clamp circuit node (XC2) and wherein said high voltage buffer block (4) comprises at least one first branch in turn including a first buffer transistor (MB l) and a first buffer diode (DB 1), being inserted, in series to each other, between a first higher voltage reference (HVPO) and a buffer central node (XBc) and interconnected in correspondence with a first memory node (XME1), as well as a second buffer diode (DB2) and a second buffer transistor (MB2), being inserted, in series to each other, between said buffer central node (XBc) and a first lower voltage reference (HVMO) and interconnected in correspondence with a second memory node (XME2), characterised in that said reset circuit (20) comprises:

a first memory diode (DME1), being inserted between said first memory node (XME1) and said first clamp circuit node (XC1); and

a second memory diode (DME2), being inserted between said second memory node (XME2) and said second clamp circuit node (XC2).

3. Transmission channel (1) according to claim 2, characterised in that said first memory diode (DME1) has a cathode terminal connected to said first memory node (XME l) and an anode terminal connected to said first clamp circuit node (XC 1) and in that said second memory diode (DME2) has an anode terminal connected to said second memory node (XME2) and a cathode terminal connected to said second clamp circuit node (XC2).

4. Transmission channel (1) according to claim 3, characterised in that said first memory node (XMEl) is connected to an anode terminal of said first buffer diode (DB1) and said first clamp circuit node (XC 1) is connected to an anode terminal of said first clamp diode (DC1) and in that said second memory node (XME2) is connected a cathode terminal of said second buffer diode (DB2) and said second clamp circuit node (XC2) is connected to a cathode terminal of said second clamp diode (DC2).

5. Transmission channel (1) according to claim 3, characterised in that said first memory node (XMEl) is in correspondence with a drain terminal of said first buffer transistor (MB1) and in that said second memory node (XME2) is in correspondence with a drain terminal of said second buffer transistor (MB2).

6. Transmission channel (1) according to claim 2, wherein said high voltage buffer block (4) also comprises, in parallel to said first branch, a second branch in turn including a third buffer transistor (MB3) and a third buffer diode (DB3), being inserted, in series to each other, between a second higher voltage reference (HVP1) and said buffer central node (XBc) and interconnected in correspondence with a third memory node (XME3), as well as a fourth buffer diode (DB4) and a fourth buffer transistor (MB4), being inserted, in series to each other, between said buffer central node (XBc) and a second lower voltage reference (HVM 1) and interconnected in correspondence with a fourth memory node (XME4), characterised in that said reset circuit (20) further comprises:

a third memory diode (DME3), being inserted between said third memory node (XME3) and said first clamp circuit node (XC1); and

a fourth memory diode (DME4), being inserted between said fourth memory node (XME4) and said second clamp circuit node (XC2).

7. Transmission channel (1) according to claim 6, characterised in that said third memory diode (DME3) has a cathode terminal connected to said third memory node (XME3) and an anode terminal connected to said first clamp circuit node (XC 1) and in that said fourth memory diode (DME4) has an anode terminal connected to said fourth memory node (XME4) and a cathode terminal connected to said second clamp circuit node (XC2).

8. Transmission channel (1) according to claim 6, characterised in that said third memory node (XME3) is connected to an anode terminal of said third buffer diode (DB3) and said first clamp circuit node (XC 1) is connected to an anode terminal of said first clamp diode (DC 1) and in that said fourth memory node (XME4) is connected to a cathode terminal of said fourth buffer diode (DB4) and said second clamp circuit node (XC2) is connected to a cathode terminal of said second clamp diode (DC2).

9. Transmission channel (1) according to claim 6, characterised in that said third memory node (XME3) is in correspondence with a drain terminal of said third buffer transistor (MB3) and in that said fourth memory node (XME4) is in correspondence with a drain terminal of said fourth buffer transistor (MB4).

10. Transmission channel (1) according to claim 2, characterised in that said clamping block (5) comprises respective first and second clamp drivers (DRC1, DRC2) connected to control terminals of said first and second clamp transistors (MC I , MC2).

1 1. Transmission channel (1) according to claim 2, characterised in that said high voltage buffer block (4) comprises respective buffer drivers (DRB 1 , DRB2, DRB3, DRB4) connected to control terminals of said buffer transistors (MB1 , MB2, MB3, MB4).

12. Transmission channel (1) according to any of the preceding claims, characterised in that it further comprises an antinoise block (6) inserted between said at least one output terminal (Hvout) and one connection terminal (Xdcr) for a load to be driven.

13. Transmission channel (1) according to claim 12, characterised in that said load is a piezoelectric transducer.

14. Transmission channel (1) according to any of the preceding claims, characterised in that it further comprises a high voltage switch (7) inserted between said connection terminal (Xdcr) and a further output terminal (LVout) of such a transmission channel (1).

15. Use of a transmission channel (1) according to any of the preceding claims for the driving of a piezoelectric transducer.