WO2011079882A1

WO2011079882A1 - Switching circuit, suitable to be used in a transmission channel for ultrasound applications

Info

Publication number: WO2011079882A1
Application number: PCT/EP2010/005931
Authority: WO
Inventors: Sandro Rossi; Antonio Ricciardo; Davide Ugo Ghisu
Original assignee: Stmicroelectronics S.R.L.
Priority date: 2009-12-30
Filing date: 2010-09-29
Publication date: 2011-07-07

Abstract

A switching circuit (30) is described being inserted between a connection terminal (Xdcr) and an output terminal (LVout) of a transmission channel (1) and of the type comprising at least one first and one second switching transistor (MSW1, MSW2) which are high voltage MOS transistors of complementary type inserted, in series to each other and by having respective equivalent or body diodes (DSW1, DSW2) in anti-series, between the connection terminal (Xdcr) and the output terminal (LVout). Advantageously according to the invention, the switching circuit comprises at least one bootstrap circuit (31) connected to respective first and second control terminals (XG1, XG2) of these at least one first and one second switching transistor (MSW1, MSW2), as well as to respective first and second voltage references (VDD_P, VDD_M) and having values of parasite capacities between these first and second control terminals (XG1, XG2) and at least one first and one second bootstrap node (XB1, XB2) of at least one order of magnitude lower with respect to the gate-source capacities (Csw1, Csw2) of these at least one first and one second switching transistor (MSW1, MSW2).

Description

Title: Switching circuit, suitable to be used in a transmission channel for ultrasound applications

DESCRIPTION

Technical Field

The present invention relates to a switching circuit.

More specifically the invention relates to a switching circuit inserted between a connection terminal and an output terminal of a transmission channel of the type comprising at least one first and one second switching transistor inserted, in series to each other, between the connection terminal and the output terminal.

The invention also relates to a transmission channel of the type comprising at least such a switching circuit.

The invention particularly, but not exclusively, relates to a switching circuit between a receiving mode and a transmission mode suitable for being used by a transmission channel for ultrasound applications and the following description is made with reference to this field of application by way of illustration only.

Background Art

As it is well known, the sonography or ultrasonography is a system of medical diagnostic testing that uses ultrasonic waves or ultrasounds and is based on the principle of the transmission of the ultrasounds and of the emission of echo and is widely used in the internist, surgical and radiological field.

The ultrasounds being normally used are comprised between 2 and 20 MHz. The frequency is chosen by taking into consideration that higher frequencies have a greater image resolving power, but penetrate less in depth in the subject under examination.

These ultrasounds are normally generated by a piezoceramic crystal inserted in a probe being maintained in direct contact with the skin of the subject with the interposition of a suitable gel (being suitable for eliminating the air between probe and subject's skin, allowing the ultrasounds to penetrate in the anatomic segment under examination).

The same probe is able to collect a return signal or echo, which is suitably processed by a computer and displayed on a monitor. In particular, the ultrasounds that reach a variation point of the acoustic impedance, and thus for example an internal organ, are partially reflected and the reflected percentage conveys information about the impedance difference between the crossed tissues. It is to be noted that, the big impedance difference between a bone and a tissue being considered, with the sonography it is not possible to see behind a bone, which causes a total reflection of the ultrasounds, while air or gas zones give "shade", causing a partial reflection of the ultrasounds.

The time employed by an ultrasonic wave for carrying out the path of going, reflection and return is provided to the computer, which calculates the depth wherefrom the echo has come, thus identifying the division surface between the tissues crossed (corresponding to the variation point of the acoustic impedance and thus to the depth wherefrom the echo comes).

Substantially, an ultrasonographer, in particular a diagnostic apparatus based on the ultrasound sonography, essentially comprises three parts:

a probe comprising at least one transducer, in particular of the ultrasonic type, which transmits and receives an ultrasound signal;

- an electronic system that drives the transducer for the generation of the ultrasound signal or pulse to be transmitted and receives an echo signal of return at the probe of this pulse, processing in consequence the received echo signal; and

- a displaying system of a corresponding sonography image processed starting from the echo signal received by the probe.

In particular, the word transducer generally indicates an electric or electronic device that converts a type of energy relative to mechanical and physical quantities into electric signals. In a broad sense, a transducer is sometimes defined as any device that converts energy from one form to another, so that this latter can be re-processed either by men or by other machines. Many transducers are both sensors and actuators. An ultrasonic transducer usually comprises a piezoelectric crystal that is suitably biased for causing its deformation and the generation of the ultrasound signal or pulse. A typical transmission channel or TX channel being used in these applications is schematically shown in Figure 1 , globally indicated with 1.

In particular, the transmission channel 1 comprises an input logic 2 that drives, in correspondence with an input bus BUSIN, a level shifter 3, in turn connected to a high voltage buffer block 4. The high voltage buffer block 4 is inserted between pairs of high voltage references, respectively higher HVPO and HVP1 and lower HVMO and HVM1, and has a pair of input terminals, INB 1 and INB2, connected to the level shifter 3, as well as a pair of output terminals, OUTB 1 and OUTB2, connected to a corresponding pair of input terminals, INC1 and INC2 of a clamping block 5.

Furthermore, the clamping block 5 is connected to a clamp voltage reference PGND and has an output terminal corresponding to a first output terminal HVout of the transmission channel 1, in turn connected, through an antinoise block 6, to a connection terminal Xdcr for the transducer to be driven through the transmission channel 1.

Finally, a high voltage switch 7 is inserted between the connection terminal Xdcr and a second output terminal LVout of the transmission channel 1. This high voltage switch 7 is able to transmit an output signal being at the output of the antinoise block 6 to the output terminal LVout during the receiving step of the transmission channel 1.

More in detail, the high voltage buffer block 4 comprises a first branch comprising a first buffer transistor MB 1 and a first buffer diode DB1, being inserted, in series to each other, between a first higher voltage reference HVPO and a buffer central node XBc, as well as a second buffer diode DB2 and a second buffer transistor MB2, being inserted, in series to each other, between the buffer central node XBc and a first lower voltage reference HVMO. The first and the second buffer transistor, MB 1 and MB2, have respective control or gate terminals in correspondence with a first XB 1 and a second inner circuit node XB2 of the high voltage buffer block 4 and connected to, and driven by, a first DRB 1 and a second buffer input driver DRB2, in turn connected to the level shifter 3 in correspondence with the first and the second input terminals, INB 1 and INB2, of the high voltage buffer block 4.

The high voltage buffer block 4 also comprises, in parallel to the first branch, a second branch in turn comprising a third buffer transistor MB3 and a third buffer diode DB3, inserted, in series to each other, between a second higher voltage reference HVP1 and the buffer central node XBc, as well as a fourth buffer diode DB4 and a fourth buffer transistor MB4, inserted, in series to each other, between the buffer central node XBc and a second lower voltage reference HVM1. The third and fourth buffer transistor, MB3 and MB4, have respective control or gate terminals in correspondence with a third XB3 and a fourth inner circuit node XB4 of the high voltage buffer block 4 and connected to, and driven by, a third DRB3 and a fourth buffer input driver DRB4, in turn connected to the first XB1 and to the second inner circuit node XB2 and then to the first DRBl and to the second buffer input driver DRB2, respectively, as well as to a first OUTB1 and to a second output terminal OUTB2.

In particular, in the example of the figure, the first and third buffer transistor, MB1 and MB3, are high voltage P-channel MOS transistors (HV Pmos) while the second and fourth buffer transistor, MB2 and MB4, are high voltage N-channel MOS transistors (HV Nmos). Moreover, the buffer diodes, DB 1, DB2, DB3 and DB4, are high voltage diodes (HV diode).

The clamping block 5 has in turn a first INC1 and a second input terminal INC2, respectively connected to the first OUTB 1 and second OUTB2 output terminals of the high voltage buffer block 4.

In particular, the clamping block 5 comprises a first clamp driver DRC1 connected between the first input terminal INC 1 and a control or gate terminal of a first clamp transistor MCI , in turn inserted, in series with a first clamp diode DC 1, between the clamp voltage reference PGND, in particular a ground, and a clamp central node XCc. The first clamp transistor MC 1 and the first clamp diode DC 1 are interconnected in correspondence with a first clamp circuit node XC1.

The clamping block 5 also comprises a second clamp driver DRC2 connected between the second input terminal INC2 and a control or gate terminal of a second clamp transistor MC2, in turn inserted, in series with a second clamp diode DC2, between the clamp central node XCc and the clamp voltage reference PGND. The second clamp transistor MC2 and the second clamp diode DC2 are interconnected in correspondence with a second clamp circuit node XC2.

The clamp central node XCc is also connected to the first output terminal HVout of the transmission channel 1 , in turn connected to the connection terminal Xdcr through an antinoise block 6 comprising respective first and second antinoise diode, DN1 and DN2, connected in antiparallel, i.e. by having the anode terminal of the first diode connected to the cathode terminal of the second one and vice versa, between the first output terminal HVout and connection terminal Xdcr.

In particular, in the example of the figure, the first clamp transistor MC I is a high voltage P-channel MOS transistor (HV Pmos) while the second clamp transistor MC2 is a high voltage N-channel MOS transistor (HV Nmos). Moreover, the clamp diodes, DC1 and DC2, are high voltage diodes (HV diode) while the antinoise diodes, DN1 and DN2, are low voltage diodes (LV diode).

The high voltage switch 7 is shown in greater detail in Figure 2A, while its equivalent circuit according to working conditions (ON) is shown in Figure 2B.

In particular, the high voltage switch 7 comprises a first MS 1 and a second switch transistor MS2, being inserted, in series to each other, between the connection terminal Xdcr and the second output terminal LVout of the transmission channel 1 and having respective control or gate terminals being connected, at the turn-on of the switch 7 itself, to a first and to a second supply voltage reference, VDD_M and VDD_P respectively. Figure 2A also shows the equivalent diodes, DS1 and DS2, of the switching transistors, MS I and MS2, as well as their gate-source capacities, Cgl and Cg2 respectively.

In particular, the first capacity Cgl of the first switching transistor MS I is connected between the corresponding gate terminal, in turn connected to the first supply voltage reference VDD_M and a first switching node XS1, corresponding to a source terminal of the first switching transistor MS I . Similarly, the second capacity Cg2 of the second switching transistor MS2 is connected between the corresponding gate terminal, in turn connected to the second supply voltage reference VDD_P and a second switching node XS2, corresponding to a source terminal of the second switching transistor MS2.

As shown in the equivalent circuit of Figure 2B, when the high voltage switch 7 is on and thus the gate terminals of the switching transistors MSI and MS2 are connected to the first VDD_M and to the second supply voltage reference VDD_P as indicated in the Figure 2A (that in Figure 2B, for sake of simplicity, have been shown as a single reference voltage, in particular the ground, being these first and second supply voltage references fix supplies), these switching transistors behave as respective resistances Rl and R2, which are inserted between the connection terminal Xdcr and the second output terminal LVout of the transmission channel 1 (the second output terminal Lvout coinciding with the second switching node XS2) and interconnected in correspondence with the first switching node XS 1.

According to these conditions, the first capacity Cgl is connected between the first connection node XS1 and the first supply voltage reference VDD_M, while the second capacity Cg2 is connected between the second connection node XS2 and the second supply voltage reference VDD_P, being these first and second supply voltage references fix supplies, shown for sake of simplicity in Figure 2B as a single reference voltage, in particular the ground GND. This capacity parallel introduces unwillingly a strong mitigation of the signal at the input of the high voltage switch 7, i.e. of the signal at the output from the transmission channel 1 after the antinoise block 6.

It is to be noted that the switch 7 is a high voltage one since, during the transmission step of the transmission channel 1 , a signal being on the connection terminal Xdcr, always indicated with Xdcr, is a high voltage signal even if the switch 7 is off. When this switch 7 is instead on, i.e. during the reception step of the transmission channel 1, the signal Xdcr is generally at a voltage value next to zero since the piezoelectric transducer being connected to the transmission channel 1 is detecting small return echoes of ultrasound pulse signals, as shown in Figure 2C.

Typically, in fact, an ultrasonic transducer transmits a high voltage pulse of the duration of a few us, and receives the echo of this pulse, generated by the reflection on the organs of a subject under examination, for the duration of about 250us, for going back to the transmission of a new high voltage pulse.

For example, a first pulse IM 1 and a second pulse IM2 are transmitted with a peak to peak excursion equal, in the example shown, to 190Vpp with reception by the transducer of corresponding echoes shown in Figure 2C and indicated with El and E2.

In general thus the switch 7 should be a high voltage one so as not to break itself during the transmission step but it is in practice on always with low voltages during the receiving step.

The technical problem of the present invention is that of providing a switching circuit able to avoid undesired mitigations of a signal at its input during the receiving step, ensuring a correct working of a transmission channel that comprises it as a switching circuit between a receiving mode and a transmission mode, in particular for ultrasound applications, and having such structural and functional features as to allow to overcome the limits and the drawbacks still affecting the circuits realised according to the prior art.

Disclosure of Invention

The solution idea underlying the present invention is that of realising a switching circuit of the type comprising switching transistors as well as suitable bootstrap circuitry able to correctly drive the control terminals of such switching transistors with a correct "following" of a signal at the input of the same switching circuit towards its output.

On the basis of this solution idea the technical problem is solved by a switching circuit inserted between a connection terminal and an output terminal of a transmission channel and of the type comprising at least one first and one second switching transistor which are high voltage MOS transistors of complementary type being inserted, in series to each other and by having respective equivalent or body diodes in anti-series, between said connection terminal and said output terminal, characterised in that it comprises at least one bootstrap circuit connected to respective first and second control terminals of said at least one first and one second switching transistor, as well as to respective first and second voltage references and having parasite capacity values between said first and second control terminals and at least one first and one second bootstrap node of at least one order of magnitude lower with respect to the gate-source capacities of said at least one first and one second switching transistor.

More in particular, the invention comprises the following supplementary and optional characteristics, taken alone or in combination, if needed.

According to an aspect of the present invention, the bootstrap circuit can comprise at least one first biasing generator inserted between said first control terminal (XG1) and said first bootstrap node, as well as a second biasing generator inserted between said second bootstrap node and said second control terminal as first and second parasite capacities of said bootstrap circuit.

According to this aspect of the invention, said at least one first and second biasing generators can supply respective first and second biasing currents.

According to another aspect of the invention, said bootstrap circuit can further comprise a first bootstrap transistor being inserted, in series to a first bootstrap resistive element, between said first control terminal of said first switching transistor and said second bootstrap node, as well as a second bootstrap transistor being inserted, in series to a second bootstrap resistive element, between said second control terminal of said second switching transistor and said first bootstrap node.

According to this aspect of the invention, said first bootstrap transistor can have a control terminal connected to a first inner circuit node of said switching circuit, corresponding to a source terminal of said first switching transistor and said second bootstrap transistor can have a control terminal connected to a second inner circuit node of said switching circuit, corresponding to a source terminal of said second switching transistor.

Also according to this aspect of the invention, said first bootstrap transistor can be a low voltage N-channel MOS transistor and said second bootstrap transistor can be a low voltage P-channel MOS transistor.

Furthermore, according to another aspect of the invention, said values of parasite capacities of said bootstrap circuit can be of at least some orders of magnitude, preferably three, lower with respect to the gate-source capacities of said at least one first and one second switching transistor.

Moreover, also according to another aspect of the invention, said first and second bootstrap nodes can be connected to said first and second voltage references, respectively.

The technical problem is also solved by a transmission channel of the type comprising at least one switching circuit as above described and by the use of this switching circuit as switching circuit between a receiving mode and a transmission mode of a transmission channel for transferring, when on, a signal being at the output of an antinoise block of said transmission channel towards said output terminal.

The characteristics and the advantages of the switching circuit according to the invention will be apparent from the following description of an embodiment thereof given by way of indicative and non limiting example with reference to the annexed drawings.

Brief Description of Drawings

In these drawings:

Figure 1 schematically shows a transmission channel for ultrasound applications realised according to the prior art;

Figure 2A shows in greater detail a high voltage switch during a turn-on step and being comprised in the transmission channel of Figure 1 ;

Figure 2B shows an equivalent circuit of the switch of Figure 2 A according to the on conditions;

Figure 2C schematically shows a first and a second ultrasound pulse used in an ultrasonic transducer;

Figure 3A shows in greater detail a switching circuit according to the invention, suitable for being used in a transmission channel for ultrasound applications; and

Figure 3B shows an equivalent circuit of the switching circuit of Figure 3A according to the on conditions.

Modes for Carrying Out the Invention

With reference to these figures, and in particular to Figure 3A, a switching circuit is described, in particular that can be used in a transmission channel for ultrasound applications, globally indicated with 30.

Elements that structurally and functionally correspond to the high voltage switch of the transmission channel described in relation to the prior art and shown in Figures 1 and 2A will be given the same alphanumeric references for simplicity of illustration.

The switching circuit 30 comprises at least one first switching transistor MSW1 and one second switching transistor MSW2 being inserted, in series to each other, between a connection terminal Xdcr and an output terminal LVout of a transmission channel, of the type shown in Figure 1 and described with reference to the prior art. In particular, the switching circuit 30 is suitable for being used as switching circuit between a receiving mode and a transmission mode of this transmission channel 1 and transfers, when on, a low voltage signal being at the output of an antinoise block of the transmission channel (as seen in relation to the prior art) towards the output terminal LVout.

In particular, in the example of the figure, the first switching transistor MSW1 is a high voltage P-channel MOS transistor (HV Pmos) while the second switching transistor MSW2 is a high voltage N-channel MOS transistor (HV Nmos). Figure 3A also indicates parasite or body diodes of these transistors, respectively DSW1 and DSW2, being connected in antiseries in correspondence with a first inner circuit node XI .

According to an embodiment of the invention, the switching circuit

30 comprises at least one bootstrap circuit 31 connected to a first XG1 and to a second control or gate terminal XG2 of the first MSWl and of the second switching transistor MSW2, respectively.

The bootstrap circuit 31 is also connected, in correspondence with a first XB 1 and with a second bootstrap node XB2, to a first VDD_M and to a second voltage reference VDD_P, in particular supply references.

According to an embodiment of the invention, the bootstrap circuit

31 comprises at least one first biasing generator Gl inserted between the first control terminal XG1 and the first bootstrap node XB 1, as well as a second biasing generator G2 being inserted between the second bootstrap node XB2 and the second control terminal XG2. These first and second biasing generators, Gl and G2, supply respective first and second biasing currents, Ibl and Ib2 and have respective first and second parasite capacities, Cgenl and Cgen2, that are the parasite capacities of said bootstrap circuit 31, respectively inserted between the first control terminal XG1 and the first bootstrap node XB 1 and between the second control terminal XG2 and the second bootstrap node XB2.

Further preferably, these first and second parasite capacities, Cgenl and Cgen2, have a much lower capacitive value than respective first and second gate-source capacities, Cswl and Csw2, of the first and second switching transistors, MSWl and MSW2. In particular, these first and second parasite capacities, Cgenl and Cgen2, have a capacitive value of at least one order of magnitude, preferably some orders of magnitude, in particular three orders of magnitude, lower than the first and second gate-source capacities, Cswl and Csw2.

In particular, the first parasite capacity Cgenl has capacitive value of at least one order of magnitude lower than the first gate-source capacity Cswl of the first switching transistor MSWl and the second parasite capacity Cgen2 has capacitive value of at least one order of magnitude lower than the second gate- source capacity Csw2 of the second switching transistor MSW2.

The bootstrap circuit 31 also comprises a first bootstrap transistor MB l being inserted, in series to a first bootstrap resistive element RB I , between the first control terminal XG1 of the first switching transistor MSW1 and the second bootstrap node XB2. The first bootstrap transistor MB l also has a control terminal, or gate, connected to the first inner circuit node XI of the switching circuit 30, corresponding to a source terminal of the first switching transistor MSW1.

Similarly, the bootstrap circuit 31 comprises a second bootstrap transistor MB2 being inserted, in series to a second bootstrap resistive element RB2, between the second control terminal XG2 of the second switching transistor MSW2 and the first bootstrap node XB 1. The second bootstrap transistor MB2 also has a control terminal, or gate, connected to a second inner circuit node X2 of the switching circuit 30, corresponding to a source terminal of the second switching transistor MSW2.

In particular, in the example of the figure, the first bootstrap transistor MBl is a low voltage N-channel MOS transistor (LV Nmos) while the second bootstrap transistor MB2 is a low voltage P-channel MOS transistor (LV Pmos).

The first biasing generator Gl is a current generator suitable for supplying such a current Ibl that the voltage developed by this current Ibl flowing through the first bootstrap transistor MB l and the first bootstrap resistive element RB I is able to turn on the first switching transistor MSW1. The same way, the second biasing generator G2 is a current generator suitable for supplying such a current Ib2 that the voltage developed by this current Ib2 passing through the second bootstrap transistor MB2 and the second bootstrap resistive element RB2 is able to turn on the second switching transistor MSW2.

It is thus clear that, according to working or on conditions of the switching circuit 30, the same behaves like its equivalent circuit shown in Figure 3B.

In particular, the gate terminals of the switching transistors MSW1 and MSW2 are both connected to a fix node in voltage, schematised in the Figure as connected to the ground GND and these transistors behave as respective resistances RSW1 and RSW2, that result inserted between the connection terminal Xdcr and the output terminal LVout of the transmission channel 1 (the output terminal LVout coinciding with the second inner circuit node X2) and interconnected in correspondence with the first inner circuit node XI .

According to these conditions, thanks to the presence of the bootstrap circuit 31 and of its biasing generators Gl and G2, the first gate-source capacity Cswl of the first switching transistor MSW1 is inserted, in series to the first parasite capacity Cgenl of the first biasing generator Gl between the first inner circuit node XI and the ground GND, while the second gate- source capacity Csw2 of the second switching transistor MSW2 is inserted, in series to the second parasite capacity Cgen2 of the second biasing generator G2 between the second inner circuit node X2 and the ground GND.

In this way, the total parasite capacity (enclosed by a dotted circle in Figure 3B) is reduced with respect to the known circuits, decreasing in consequence the undesired mitigation of the signal at the input of the same switching circuit 30, in particular applied to its connection terminal Xdcr and transmitted to its output terminal LVout.

In conclusion, the switching circuit according to the invention ensures a correct transmission of a signal applied thereto at the input, in particular on the connection terminal Xdcr, showing a reduced total parasite capacity according to the on conditions.

Obviously, a technician of the field, with the aim of meeting incidental and specific needs, will be allowed to introduce several modifications and variations to the above described circuit, all within the scope of protection of the invention as defined by the following claims.

Claims

1. Switching circuit (30) being inserted between a connection terminal (Xdcr) and an output terminal (LVout) of a transmission channel (1) and of the type comprising at least one first and one second switching transistor (MSW1, MSW2) which are high voltage MOS transistors of complementary type being inserted, in series to each other and by having respective equivalent or body diodes (DSW1, DSW2) in anti-series, between said connection terminal (Xdcr) and said output terminal (LVout), characterised in that it comprises at least one bootstrap circuit (31) connected to respective first and second control terminals (XG 1 , XG2) of said at least one first and one second switching transistor (MSW1, MSW2), as well as to respective first and second voltage references (VDD_P, VDD_M) and having values of parasite capacities between said first and second control terminals (XG1, XG2) and at least one first and one second bootstrap node (XB 1 , XB2) of at least one order of magnitude lower than the gate-source capacities (Cswl, Csw2) of said at least one first and one second switching transistor (MSW1, MSW2).

2. Switching circuit (30) according to claim 1, characterised in that said bootstrap circuit (31) comprises at least one first biasing generator (Gl) being inserted between said first control terminal (XG1) and said first bootstrap node (XB 1), as well as a second biasing generator (G2) being inserted between said second bootstrap node (XB2) and said second control terminal (XG2) as first and second parasite capacities (Cgenl , Cgen2) of said bootstrap circuit (31).

3. Switching circuit (30) according to claim 2, characterised in that said at least one first and one second biasing generator (Gl , G2) supply respective first and second biasing currents (Ibl , Ib2).

4. Switching circuit (30) according to claim 1 , characterised in that said bootstrap circuit (31) further comprises a first bootstrap transistor (MB1) being inserted, in series to a first bootstrap resistive element (RBI), between said first control terminal (XG1) of said first switching transistor (MSW1) and said second bootstrap node (XB2), as well as a second bootstrap transistor (MB2) being inserted, in series to a second bootstrap resistive element (RB2), between said second control terminal (XG2) of said second switching transistor (MSW2) and said first bootstrap node (XB 1).

5. Switching circuit (30) according to claim 4, characterised in that said first bootstrap transistor (MB1) has a control terminal connected to a first inner circuit node (XI) of said switching circuit (30), corresponding to a source terminal of said first switching transistor (MSW1) and said second bootstrap transistor (MB2) has a control terminal connected to a second inner circuit node (X2) of said switching circuit (30), corresponding to a source terminal of said second switching transistor (MSW2).

6. Switching circuit (30) according to claim 4, characterised in that said first bootstrap transistor (MB1) is a low voltage N-channel MOS transistor and said second bootstrap transistor (MB2) is a low voltage P-channel MOS transistor.

7. Switching circuit (30) according to claim 1, characterised in that said first and second bootstrap nodes (XB1, XB2) are connected to said first and second voltage references (VDD_M, VDD_P), respectively.

8. Switching circuit (30) according to claim 1, characterised in that said values of parasite capacities of said bootstrap circuit (31) are of at least some orders of magnitude, preferably three, lower with respect to the gate-source capacities (Cswl, Csw2) of said at least one first and one second switching transistor (MSW1, MSW2).

9. Transmission channel (1) of the type comprising at least one switching circuit (30) according to any of the preceding claims.

10. Use of a switching circuit (30) according to any claim 1 to 8 as switching circuit between a receiving mode and a transmission mode of a transmission channel for transferring, when on, a signal being at the output of an antinoise block of said transmission channel towards said output terminal (LVout).