WO2011079881A1 - Circuit de calage à une tension de référence, en particulier à une tension de masse, approprié pour être utilisé dans un canal de transmission pour des applications ultrasonores - Google Patents

Circuit de calage à une tension de référence, en particulier à une tension de masse, approprié pour être utilisé dans un canal de transmission pour des applications ultrasonores Download PDF

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Publication number
WO2011079881A1
WO2011079881A1 PCT/EP2010/005930 EP2010005930W WO2011079881A1 WO 2011079881 A1 WO2011079881 A1 WO 2011079881A1 EP 2010005930 W EP2010005930 W EP 2010005930W WO 2011079881 A1 WO2011079881 A1 WO 2011079881A1
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WO
WIPO (PCT)
Prior art keywords
transistor
clamp
transistors
switching
clamping circuit
Prior art date
Application number
PCT/EP2010/005930
Other languages
English (en)
Inventor
Sandro Rossi
Davide Ugo Ghisu
Antonio Ricciardo
Original Assignee
Stmicroelectronics S.R.L.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stmicroelectronics S.R.L. filed Critical Stmicroelectronics S.R.L.
Publication of WO2011079881A1 publication Critical patent/WO2011079881A1/fr
Priority to US13/538,802 priority Critical patent/US8638132B2/en
Priority to US13/538,598 priority patent/US9323268B2/en
Priority to US13/538,821 priority patent/US8648629B2/en
Priority to US13/538,840 priority patent/US8749099B2/en
Priority to US14/071,315 priority patent/US8710874B2/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
    • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
    • B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
    • B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
    • B06B1/0207—Driving circuits
    • B06B1/0215—Driving circuits for generating pulses, e.g. bursts of oscillations, envelopes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/74—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of diodes

Definitions

  • the present invention relates to a clamping circuit to a voltage reference, in particular to ground.
  • the invention relates to a clamping circuit to a voltage reference of the type comprising at least one clamping core connected to an output terminal and having a central node connected to the voltage reference and in turn including at least one first and one second clamp transistor, connected to the central node and having respective control terminals, the clamping core being also connected at the input to an input driver block.
  • the invention also relates to a transmission channel of the type comprising at least such a clamping circuit.
  • the invention particularly, but not exclusively, relates to a clamping circuit suitable for being used by a transmission channel for ultrasound applications and the following description is made with reference to this field of application by way of illustration only.
  • the sonography or ultrasonography is a system of medical diagnostic testing that uses ultrasonic waves or ultrasounds and is based on the principle of the transmission of the ultrasounds and of the emission of echo and is widely used in the internist, surgical and radiological field.
  • the ultrasounds being normally used are comprised between 2 and 20 MHz.
  • the frequency is chosen by taking into consideration that higher frequencies have a greater image resolving power, but penetrate less in depth in the subject under examination.
  • These ultrasounds are normally generated by a piezoceramic crystal inserted in a probe being maintained in direct contact with the skin of the subject with the interposition of a suitable gel (being suitable for eliminating the air between probe and subject's skin, allowing the ultrasounds to penetrate in the anatomic segment under examination).
  • a suitable gel being suitable for eliminating the air between probe and subject's skin, allowing the ultrasounds to penetrate in the anatomic segment under examination.
  • the same probe is able to collect a return signal or echo, which is suitably processed by a computer and displayed on a monitor.
  • the ultrasounds that reach a variation point of the acoustic impedance, and thus for example an internal organ, are partially reflected and the reflected percentage conveys information about the impedance difference between the crossed tissues.
  • the time employed by an ultrasonic wave for carrying out the path of going, reflection and return is provided to the computer, which calculates the depth wherefrom the echo has come, thus identifying the division surface between the crossed tissues (corresponding to the variation point of the acoustic impedance and thus to the depth wherefrom the echo comes).
  • an ultrasonographer in particular a diagnostic apparatus based on the ultrasound sonography, essentially comprises three parts:
  • a probe comprising at least one transducer, in particular of the ultrasonic type, which transmits and receives an ultrasound signal;
  • the word transducer generally indicates an electric or electronic device that converts a type of energy relative to mechanical and physical quantities into electric signals.
  • a transducer is sometimes defined as any device that converts energy from one form to another, so that this latter can be re-processed either by men or by other machines.
  • Many transducers are both sensors and actuators.
  • An ultrasonic transducer usually comprises a piezoelectric crystal that is suitably biased for causing its deformation and the generation of the ultrasound signal or pulse.
  • a typical transmission channel or TX channel being used in these applications is schematically shown in Figure 1 , globally indicated with 1.
  • the transmission channel 1 comprises an input logic 2 that drives, in correspondence with an input bus BUSIN, a level shifter 3, in turn connected to a high voltage buffer block 4.
  • the high voltage buffer block 4 is inserted between pairs of high voltage references, respectively higher HVPO and HVP1 and lower HVM0 and HVM1, and has a pair of input terminals, INB 1 and INB2, connected to the level shifter 3, as well as a pair of output terminals, OUTB 1 and OUTB2, connected to a corresponding pair of input terminals, INC 1 and INC2 of a clamping block 5.
  • clamping block 5 is connected to a clamp voltage reference
  • PGND and has an output terminal corresponding to a first output terminal HVout of the transmission channel 1 , in turn connected, through an antinoise block 6, to a connection terminal Xdcr for the transducer to be driven through the transmission channel 1.
  • a high voltage switch 7 is inserted between the connection terminal Xdcr and a second output terminal LVout of the transmission channel 1. This high voltage switch 7 is able to transmit an output signal being at the output of the antinoise block 6 to the output terminal LVout during the receiving step of the transmission channel 1.
  • the switch 7 is a high voltage one since, during the transmission step of the transmission channel 1 , a signal being on the connection terminal Xdcr, always indicated with Xdcr, is a high voltage signal although the switch 7 is off.
  • this switch 7 is instead on, i.e. during the reception step of the transmission channel 1, the signal Xdcr is generally at a voltage value next to zero since the piezoelectric transducer connected to the transmission channel 1 is sensing small return echoes of ultrasound pulse signals, as shown in Figure 2.
  • an ultrasonic transducer transmits a high voltage pulse of the duration of a few us, and receives the echo of this pulse, generated by the reflection on the organs of a subject under examination, for the duration of about 250us, to go back to the transmission of a new high voltage pulse.
  • a first pulse IM1 and a second pulse IM2 are transmitted with a peak to peak excursion equal, in the example shown, to 190Vpp with reception by the transducer of corresponding echoes shown in Figure 2 and indicated with El and E2.
  • the switch 7 must be a high voltage one so as not to break itself during the transmission step but it is in practice on always with low voltages during the reception step.
  • the high voltage buffer block 4 comprises a first branch comprising a first buffer transistor MB1 and a first buffer diode DB1, being inserted, in series to each other, between a first higher voltage reference HVPO and a buffer central node XBc, as well as a second buffer diode DB2 and a second buffer transistor MB2, being inserted, in series to each other, between the buffer central node XBc and a first lower voltage reference HVM0.
  • the first and second buffer transistors, MB 1 and MB2 have respective control or gate terminals in correspondence with a first XB 1 and a second inner circuit node XB2 of the high voltage buffer block 4 and connected to, and driven by, a first DRB1 and a second buffer input driver DRB2, in turn connected to the level shifter 3 in correspondence with the first and second input terminals, INB 1 and INB2, of the high voltage buffer block 4.
  • the high voltage buffer block 4 also comprises, in parallel to the first branch, a second branch in turn comprising a third buffer transistor MB3 and a third buffer diode DB3, inserted, in series to each other, between a second higher - - voltage reference HVP1 and the buffer central node XBc, as well as a fourth buffer diode DB4 and a fourth buffer transistor MB4, inserted, in series to each other, between the buffer central node XBc and a second lower voltage reference HVM 1.
  • the third and fourth buffer transistors, MB3 and MB4 have respective control or gate terminals in correspondence with a third XB3 and a fourth inner circuit node XB4 of the high voltage buffer block 4 and connected to, and driven by, a third DRB3 and a fourth buffer input driver DRB4, in turn connected to the first XB l and to the second inner circuit node XB2 and then to the first DRB l and to the second buffer input driver DRB2, respectively, as well as to a first OUTB 1 and to a second output terminal OUTB2.
  • the first and third buffer transistors, MB1 and MB3 are high voltage P-channel MOS transistors (HV Pmos) while the second and fourth buffer transistors, MB2 and MB4, are high voltage N-channel MOS transistors (HV Nmos).
  • the buffer diodes, DB 1, DB2, DB3 and DB4 are high voltage diodes (HV diode).
  • the clamping block 5 has in turn a first INCl and a second input terminal INC2, respectively connected to the first OUTB 1 and second OUTB2 output terminals of the high voltage buffer block 4.
  • the clamping block 5 comprises a first clamp driver DRC 1 connected between the first input terminal INCl and a control or gate terminal of a first clamp transistor MC I, in turn inserted, in series with a first clamp diode DC 1 , between the clamp voltage reference PGND, in particular a ground, and a clamp central node XC.
  • the first clamp transistor MCI and the first clamp diode DC 1 are interconnected in correspondence with a first clamp circuit node XC 1.
  • the clamping block 5 also comprises a second clamp driver DRC2 connected between the second input terminal INC2 and a control or gate terminal of a second clamp transistor MC2, in turn inserted, in series with a second clamp diode DC2, between the clamp central node XC and the clamp voltage reference PGND.
  • the second clamp transistor MC2 and the second clamp diode DC2 are interconnected in correspondence with a second clamp circuit node XC2.
  • the clamp circuit node XC is also connected to the first output terminal HVout of the transmission channel 1, in turn connected to the connection terminal Xdcr through an antinoise block 6 comprising respective first and second antinoise diodes, DN1 and DN2, connected in antiparallel, i.e. by having the anode terminal of the first diode connected to the cathode terminal of the second one and vice versa, between these first output terminal HVout and connection terminal Xdcr.
  • the first clamp transistor MC I is a high voltage P-channel MOS transistor (HV Pmos) while the second clamp - - transistor MC2 is a high voltage N-channel MOS transistor (HV Nmos).
  • the clamp diodes, DC1 and DC2 are high voltage diodes (HV diode) while the antinoise diodes, DN 1 and DN2, are low voltage diodes (LV diode).
  • the clamping block 5 is also shown in Figure 3, in the case of a clamping operation to a ground voltage reference GND, i.e. in the receiving step of the transmission channel 1. Moreover, the clamping to the ground voltage reference GND must be ensured also when the load is mainly capacitive. In this case, the output terminal of the transmission channel must be brought back to this ground value after the transmission. Furthermore, the correct clamping to the ground is important in applications in which the high voltage wave form to be transmitted, besides oscillating between a high voltage positive value and a high voltage negative value, stays for determined periods of time at the ground value. Also the antinoise block 6 is indicated, connected between the first output terminal HVout and the connection terminal Xdcr of the transmission channel 1.
  • DMC2 of the clamp transistors, MC I and MC2, respectively, the first and second clamp input drivers, DRC1 and DRC2, being connected between a first and a second clamp supply voltage reference, higher VDD_P and lower VDD_M, respectively, and the ground GND, whereto also the clamp central node XC is connected.
  • the first output terminal HVout is at a voltage value, corresponding to the ground voltage value GND plus or minus a diode voltage and the connection terminal Xdcr at a ground voltage value GND plus or minus two diode voltages.
  • the optimal working condition would have this first output terminal HVout at a value equal to the ground GND, condition in which the distortions of the transmitted signal from the transmission channel 1 are minimal.
  • the real operation conditions of the above illustrated clamping block 5 show worsening in the performances of second harmonic, especially under low supply voltage conditions.
  • connection terminal Xdcr is at zero. Any leakage current of the first output terminal HVout, caused by the noise introduced by the charges being in the clamp diodes DC 1 and DC2, causes a raising of the voltage value also on this connection terminal and then a receiving disturbance.
  • the - - first output terminal HVout does not immediately respond since most of the current supplied by this high voltage buffer block 4 is used for the discharge of the junction capacities of the clamp diodes DC 1 and DC2, precharged during the clamping step. This malfunction is particularly felt in the case of short pulses.
  • a leakage current could charge the first output terminal HVout at a voltage higher than the threshold voltage of the antinoise diodes, DN 1 and DN2, of the antinoise block 6 and, in consequence, disturb a reception on the connection terminal Xdcr indeed.
  • the technical problem of the present invention is that of providing a clamping circuit able to ensure a correct clamping to a voltage reference, in particular ground, in correspondence with an output terminal thereof, suitable for being used by a transmission channel for ultrasound applications and having such structural and functional features as to allow to overcome the limits and the drawbacks still affecting the circuits realised according to the prior art.
  • the solution idea underlying the present invention is that of associating with the clamp transistors corresponding high voltage MOS transistors able to close themselves when the clamping circuit is active and likewise able to sustain high positive and negative voltages when instead the clamping circuit is not active and the transistors are in open configuration.
  • the high voltage MOS transistors are driven by suitable switching off circuitry able to ensure a correct switching off of an output terminal of the clamping circuit and thus a correct clamp to a voltage reference, in particular a ground.
  • a clamping circuit to a voltage reference of the type comprising at least one clamp core connected to an output terminal and having a central node connected to said voltage reference and in turn including at least one first and one second clamp transistor, connected to said central node and having respective control terminals, said clamp core being also connected at the input to a low voltage input driver block, said clamping circuit being characterised in that said clamp core further comprises at least one first switching off transistor connected to said output terminal and to said first clamp transistor, as well as a second switching off transistor connected to said output terminal and to said second clamp transistor, said first and second clamp transistors being high voltage MOS transistors of complementary type and said first and second switching off transistor being high voltage MOS transistors of complementary type and - - connected to said first and second clamp transistors by having the respective equivalent or body diodes in an ti- series so as to close themselves when said clamping circuit is active and to sustain high positive and negative voltages when said clamping circuit is not active.
  • the invention comprises the following supplementary and optional characteristics, taken alone or in combination, if needed.
  • said first switching off transistor can be a high voltage P-channel MOS transistor and said second switching off transistor can be a high voltage N-channel MOS transistor.
  • said clamping circuit can further comprise a driving circuit connected to respective control terminals of said first and second clamp transistors and of said first and second switching off transistors and suitable for closing said first and second switching off transistors when said clamping circuit is active.
  • said clamping circuit can comprise a first and a second driving transistor, inserted, in a crossed way, between said control terminals of said first and second clamp transistor, and respective control terminals of said first and second switching off transistors.
  • said first driving transistor can be inserted between said control terminal of said first clamp transistor and a control terminal of said second switching off transistor and said second driving transistor can be inserted between a control terminal of said first switching off transistor and said control terminal of said second clamp transistor.
  • said first and second driving transistor can have respective control terminals connected to said central node.
  • said input driver block can comprise a first and a second driver inserted between a first and a second supply voltage reference and having respective output terminals connected to said control terminals of said first and second clamp transistors.
  • said first clamp transistor can be a high voltage N-channel MOS transistor and said second clamp transistor can be a high voltage P-channel MOS transistor.
  • said first and second driving transistors can be high voltage MOS transistors of the type similar with respect to said first and second switching off transistors.
  • said first driving transistor can be a high voltage N-channel MOS transistor and said second driving transistor can be a high voltage P-channel MOS transistor.
  • a transmission channel of the type comprising at least one clamping circuit as above described, inserted between an input driver block and an antinoise circuit, said antinoise circuit being connected between said output terminal of said clamping circuit and a connection terminal of said transmission channel and said input driver block being connected to a high voltage buffer block of said transmission channel.
  • Figure 1 schematically shows a transmission channel for ultrasound applications realised according to the prior art
  • FIG. 2 schematically shows a first and a second ultrasound pulse being used in an ultrasonic transducer
  • Figure 3 shows in greater detail a block comprised within the transmission channel of Figure 1 ;
  • Figure 4 schematically shows a clamping circuit, that can in particular be used in a transmission channel for ultrasound applications, being realised according to the invention.
  • a clamping circuit is described, that in particular can be used in a transmission channel for ultrasound applications, globally indicated with 10.
  • the clamping circuit 10 comprises a clamping core 1 1 connected to an output terminal HVout and having a central node XC connected to a voltage reference, in particular a ground GND.
  • the clamping core 1 1 comprises a first and a second clamp transistor, MC I and MC2, connected to this central node XC and having respective control or gate terminals, XG1 and XG2.
  • first and second clamp transistors MCI and MC2 have respective first and second equivalent diodes, DMC 1 and DMC2, as indicated in the figure.
  • the first clamp transistor MC I is a high voltage N-channel MOS transistor (HV Nmos) while the second clamp - - transistor MC2 is a high voltage P-channel MOS transistor (HV Pmos).
  • the clamping core 1 1 also comprises a first and a second switching off transistor, MS I and MS2.
  • the first switching off transistor MS 1 is inserted in series to the first clamp transistor MCI and connected to the output terminal HVout.
  • the second switching off transistor MS2 is inserted in series to the second clamp transistor MC2 and also connected to the output terminal HVout.
  • first and second switching off transistors, MS I and MS2 have respective first and second equivalent diodes, DMSl and DMS2, as indicated in the figure.
  • the first and second switching off transistors, MS I and MS2 are high voltage MOS transistors of opposed type with respect to the clamp transistors MCI and MC2.
  • the first switching off transistor MSI is a high voltage P-channel MOS transistor (HV Pmos) while the second switching off transistor MS2 is a high voltage N-channel MOS transistor (HV Nmos).
  • first equivalent or body diodes, DMSl and DMC l , of the first switching off transistor MS I and of the first clamping transistor MC I , respectively, are connected in anti-series in correspondence with a first clamp circuit node XC 1.
  • second equivalent or body diodes, DMS2 and DMC2, of the second switching off transistor MS2 and of the second clamping transistor MC2, respectively, are connected in anti-series in correspondence with a second clamp circuit node XC2.
  • these first and second switching off transistors, MS I and MS2 are MOS transistors able to close themselves when the clamping circuit 10 is active and to sustain positive and negative high voltages when the clamping circuit is not active and the transistors are in open configuration, in particular also thanks to the use of a suitable driving circuit, as it will be clarified hereafter.
  • the clamping core 1 1 is connected, in correspondence with the output terminal HVout to an antinoise circuit 12 comprising respective first and second antinoise diodes, DN 1 and DN2, connected in antiparallel, i.e. by having the anode terminal of the first diode connected to the cathode terminal of the second one and vice versa, between this first output terminal HVout and a connection terminal Xdcr.
  • clamping core 1 1 is also connected at the input to an input driver block 13 through a driving circuit 14 of the switching off transistors M l and M2, suitable for closing the first and second switching off transistors, MSI and MS2 when the clamping circuit 10 is active, as it will be clarified hereafter in the description.
  • the input driver block 13 is of the low voltage type and - - comprises a first driver DRC 1 inserted between a first and a second clamp supply voltage reference, higher VDD_P and lower VDD_M, respectively, and having an output terminal connected to the first control terminal XG1 of the first clamp transistor MCI as well as a second driver DRC2, in turn inserted between the first and second clamp supply voltage references, higher VDD_P and lower VDD_M, and having an output terminal connected to the second control terminal XG2 of the second clamp transistor MC2.
  • a first driver DRC 1 inserted between a first and a second clamp supply voltage reference, higher VDD_P and lower VDD_M, respectively, and having an output terminal connected to the first control terminal XG1 of the first clamp transistor MCI as well as a second driver DRC2, in turn inserted between the first and second clamp supply voltage references, higher VDD_P and lower VDD_M, and having an output terminal connected to the second control terminal XG2 of the second clamp transistor MC2.
  • the driving circuit 14 comprises a first and a second driving transistor, M l and M2, inserted, in a crossed way, between the control terminals of the first and second clamp transistors, MC I and MC2, and of the first and second switching off transistors, MS I and MS2.
  • the first driving transistor M l is inserted between the control terminal XG 1 of the first clamp transistor MC 1 and a control or gate terminal XS2 of the second driving transistor MS2, while the second driving transistor M2 is inserted between a control or gate terminal XS1 of the first driving transistor MS I and the control terminal XG2 of the second clamp transistor MC2.
  • first and second driving transistors, M l and M2 have respective control or gate terminals, XI and X2, connected to the clamp central node XC.
  • the first and second driving transistors, Ml and M2 are high voltage MOS transistors of the type similar to the switching off transistors MS I and MS2.
  • the first driving transistor M2 is a high voltage P-channel MOS transistor (HV Pmos) while the second driving transistor M2 is a high voltage N-channel MOS transistor (HV Nmos).
  • HV Pmos high voltage P-channel MOS transistor
  • HV Nmos high voltage N-channel MOS transistor
  • the driving circuit 14 ensures the switching off of the switching off transistors MS I and MS2.
  • the driving circuit 14 correctly drives in high voltage the first and second switching off transistors, MS I and MS2, forcing their closure during the clamping step, while the first and second clamp transistors, MC I and MC2, are driven at low voltage (with voltage that varies between 0 and 3 V) directly by the input driver block 13.
  • the output terminal HVout is thus brought to ground and kept to ground thanks to the switching off transistors MSI and MS2 being driven by the driving circuit 14, in particular at the turning on and switching off of the first and of the second switching off transistors MSI and MS2 by means of the first and second driving transistors Ml and M2.
  • the current flows through the channel of the transistors of the clamping circuit 1 1 without charging the intrinsic diodes DMS 1 and DMS2 of the switching off transistors MSI and MS2, overcoming in this way the problems seen in relation to the prior art.
  • the load current does not flow through the junction of the equivalent diodes DMS 1 and DMS2 of the switching off transistors MSI and MS2, but through their channel, avoiding to charge possible junction capacities that would be present with the diodes of the known circuit shown in Figure 3.
  • the clamping circuit ensures the correct clamping to a voltage reference, in particular to a ground GND, also under clamp conditions of a load of high value and during the receiving in the case of application to a transmission channel, eliminating malfunctions connected to the charge of the junction capacities of the diodes of the known circuit being shown in Figure 3.
  • the voltage value being on the connection terminal Xdcr reaches a value equal to the ground value GND plus or minus a diode voltage, improving the performances of second harmonic especially at low supply voltages.
  • a leakage current during a receiving step of the transmission channel which comprises the clamping circuit according to the invention is conveyed towards the ground reference terminal GND preventing the output terminal HVout from charging itself and overcoming in this way the drawbacks of the circuits described in relation to the prior art.

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Electronic Switches (AREA)

Abstract

L'invention concerne un circuit de calage (10) à une référence de tension (GND), du type comprenant au moins un noyau de calage (11) connecté à une borne de sortie (HVout) et présentant un noeud central (XC) connecté à la référence de tension (GND) et comprenant à son tour au moins un premier et un second transistor de calage (MC1; MC2), connectés au noeud central (XC) et présentant des bornes de commande (XG1, XG2) respectives, le noyau de calage (11) étant également connecté à l'entrée à un bloc de commande d'entrée basse tension (13). Avantageusement selon l'invention, le noyau de calage (11) comprend également au moins un premier transistor de commutation (MS1) connecté à la borne de sortie (HVout) et au premier transistor de calage (MC1), ainsi qu'un second transistor de commutation (MS2), lesdits premier et second transistors de calage (MC1, MC2) étant des transistors MOS haute tension de type complémentaire et lesdits premier et second transistors de commutation (MS1, MS2) étant des transistors MOS haute tension de type complémentaire et connectés aux premier et second transistors de calage (MC1, MC2) au moyen des diodes de substrat ou équivalentes respectives connectées en anti-série de manière à les fermer lorsque le circuit de calage (10) est actif et à supporter de hautes tensions positives et négatives lorsque le circuit de calage (10) n'est pas actif.
PCT/EP2010/005930 2009-12-30 2010-09-29 Circuit de calage à une tension de référence, en particulier à une tension de masse, approprié pour être utilisé dans un canal de transmission pour des applications ultrasonores WO2011079881A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US13/538,802 US8638132B2 (en) 2009-12-30 2012-06-29 Transmission channel for ultrasound applications
US13/538,598 US9323268B2 (en) 2009-12-30 2012-06-29 Low voltage isolation switch, in particular for a transmission channel for ultrasound applications
US13/538,821 US8648629B2 (en) 2009-12-30 2012-06-29 Transmission channel for ultrasound applications
US13/538,840 US8749099B2 (en) 2009-12-30 2012-06-29 Clamping circuit to a reference voltage for ultrasound applications
US14/071,315 US8710874B2 (en) 2009-12-30 2013-11-04 Transmission channel for ultrasound applications

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
ITMI2009A002338 2009-12-30
ITMI20092338 2009-12-30

Related Child Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2010/005927 Continuation-In-Part WO2011088853A1 (fr) 2009-12-30 2010-09-29 Canal de transmission, en particulier pour des applications ultrasonores

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WO2011079881A1 true WO2011079881A1 (fr) 2011-07-07

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PCT/EP2010/005930 WO2011079881A1 (fr) 2009-12-30 2010-09-29 Circuit de calage à une tension de référence, en particulier à une tension de masse, approprié pour être utilisé dans un canal de transmission pour des applications ultrasonores

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103635866A (zh) * 2011-07-04 2014-03-12 艾酷里克有限公司 电流调节器
IT201700021353A1 (it) * 2017-02-24 2018-08-24 St Microelectronics Srl Dispositivo di pilotaggio, apparecchiatura e procedimento corrispondenti
US10734954B2 (en) 2017-02-24 2020-08-04 Stmicroelectronics S.R.L. Operational amplifier, corresponding circuit, apparatus and method
US10730073B2 (en) 2017-02-24 2020-08-04 Stmicroelectronics S.R.L. Electronic circuit, corresponding ultrasound apparatus and method
US10873328B2 (en) 2017-02-24 2020-12-22 Stmicroelectronics S.R.L. Driver circuit, corresponding ultrasound apparatus and method

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CN103635866B (zh) * 2011-07-04 2017-09-26 艾酷里克有限公司 电流调节器
IT201700021353A1 (it) * 2017-02-24 2018-08-24 St Microelectronics Srl Dispositivo di pilotaggio, apparecchiatura e procedimento corrispondenti
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