WO2011070694A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

Info

Publication number
WO2011070694A1
WO2011070694A1 PCT/JP2010/005211 JP2010005211W WO2011070694A1 WO 2011070694 A1 WO2011070694 A1 WO 2011070694A1 JP 2010005211 W JP2010005211 W JP 2010005211W WO 2011070694 A1 WO2011070694 A1 WO 2011070694A1
Authority
WO
WIPO (PCT)
Prior art keywords
insulating film
wiring
semiconductor device
manufacturing
region
Prior art date
Application number
PCT/JP2010/005211
Other languages
French (fr)
Japanese (ja)
Inventor
小堀悦理
Original Assignee
パナソニック株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Publication of WO2011070694A1 publication Critical patent/WO2011070694A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/1042—Formation and after-treatment of dielectrics the dielectric comprising air gaps
    • H01L2221/1047—Formation and after-treatment of dielectrics the dielectric comprising air gaps the air gaps being formed by pores in the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a method of improving a withstand voltage between wires and reducing a capacitance between wires in a semiconductor device including a low dielectric constant film including holes.
  • Cu which is a low resistance material
  • damascene wiring in which Cu is embedded is adopted as a wiring structure.
  • the wiring width is reduced and the inter-wiring capacitance that affects the wiring delay is increased. Since this hinders the speeding up of the semiconductor device, it is essential to lower the dielectric constant of the insulating film in order to reduce the inter-wiring capacitance.
  • a hole forming material (porogen) is used together with a raw material gas to form an insulating film including holes. The technique of Patent Document 1 described in this regard will be described below.
  • Patent Document 1 shows a structure in which an interlayer insulating film 3 including a large number of holes 4 is formed on a lower wiring layer 1 via an etching stopper film 2 (FIG. 6A).
  • etching stopper film 2 FIG. 6A
  • a film forming process using the raw material gas and the vacancy forming material and a UV cure process for sublimating the porogen are repeated. It is shown that.
  • a protective film made of an insulating film having a high dielectric constant is formed on the insulating film 3 before the damascene wiring 5 is formed. 4 is not exposed (FIG. 6C).
  • the cap layer has a high dielectric constant for preventing exposure of holes. For this reason, the effect of reducing the capacitance between wirings using an insulating film having a low dielectric constant including holes is hindered. Therefore, this solution becomes a problem.
  • the method for manufacturing a semiconductor device includes a step (a) of forming an insulating film made of a single layer and including a hole forming material on a substrate, and a first step from the surface to a predetermined depth of the insulating film.
  • a step (b) of forming a hole in the second region below the first region by removing the hole forming material As a region, a step (b) of forming a hole in the second region below the first region by removing the hole forming material, a step (c) of forming at least one wiring groove in the insulating film, A step (d) of forming a conductive film so as to fill the wiring trench; and a step (e) of forming a wiring by removing the excess portion of the conductive film protruding from the wiring trench.
  • step (a) it is preferable to form an insulating film by a single film formation step.
  • step (a) it is preferable to form a portion of the insulating film including the hole forming material to be the second region and then forming a portion of the insulating film not including the hole forming material to be the first region.
  • step (e) it is preferable to remove at least a part of the first region of the insulating film.
  • the first region that does not include holes has a higher dielectric constant than the second region that includes holes. Therefore, by removing at least a part of the first region, it is possible to reduce the inter-wiring capacitance.
  • step (b) it is preferable to control so that the holes in the second region become smaller from the substrate side toward the first region side.
  • step (b) it is preferable to perform at least one of ultraviolet irradiation and heating.
  • the pore forming material can be removed to form the pores. Furthermore, by setting the conditions for ultraviolet irradiation and heating, the size of the holes, the thickness of the first region not including the holes, and the like can be controlled.
  • the insulating film is formed using the raw material gas and the hole forming material, and the supply amount of the hole forming material with respect to the amount of the raw material gas is reduced in accordance with the progress of the formation of the insulating film. It is preferable.
  • the vacancies in the insulating film (in the second region) can be reduced from the substrate side toward the first region side.
  • the pore forming material in an amount of 0.8 times or more and 1.28 times or less with respect to the amount of the raw material gas.
  • the diameter of the holes formed in the second region is preferably 0.85 nm or more and 0.95 nm or less and the maximum is 1.05 nm or less.
  • the film thickness of the first region is preferably 20 nm or less, and the diameter of the pores immediately below the first region is preferably 0.8 nm or less.
  • the first region with a high dielectric constant should be thin.
  • the hole has a diameter of 0.8 nm or less, even if it is exposed on the upper surface of the insulating film, it is difficult to cause breakdown of the breakdown voltage.
  • a second insulating film including the second wiring is formed on the first insulating film after the step (e). It is preferable that the method further includes the step (f), and the second insulating film does not include voids.
  • a second insulating film including the second wiring is formed on the first insulating film after the step (e). Step (f) is further provided, and the porosity of the second insulating film is preferably lower than the porosity of the first insulating film.
  • the configuration described above may be applied only to a part of the insulating films (here, the first insulating film). Further, any of the insulating films may include a hole, and the porosity may be different (here, the first insulating film has a lower porosity).
  • first wiring may be formed more densely than the second wiring.
  • first wirings and a plurality of second wirings are formed in the main surface direction of the substrate, respectively, and the distance between the wirings of the first wiring is shorter than the distance between the wirings of the second wiring. May be.
  • the structure of holes in the insulating film may be set according to the density of wirings, the distance between wirings, and the like.
  • the wiring width of the first wiring is less than 70 nm, and the distance between the wirings of the first wiring is 140 nm or less.
  • the technique of the present disclosure is particularly useful when forming wiring with such dimensions.
  • a semiconductor device of the present disclosure includes an insulating film that is formed on a substrate and includes a plurality of holes, and at least one wiring that is formed so as to be embedded in the upper part of the insulating film. Changes so as to decrease from the bottom to the top of the insulating film.
  • the insulating film is preferably a single layer.
  • the second insulating film formed so as to cover the first insulating film and the first wiring, and the second insulating film It is preferable that at least one second wiring formed above is provided, and the second insulating film does not include a hole.
  • the configuration described above may be applied only to a part of the insulating films (here, the first insulating film). Further, any of the insulating films may include a hole, and the porosity may be different (here, the first insulating film has a lower porosity).
  • first wiring may be formed more densely than the second wiring.
  • first wirings and a plurality of second wirings are formed in the main surface direction of the substrate, respectively, and the distance between the wirings of the first wiring is shorter than the distance between the wirings of the second wiring. It may be.
  • the structure of holes in the insulating film may be set according to the density of wirings, the distance between wirings, and the like.
  • a semiconductor device having a low dielectric constant insulating film including fine wiring for example, a wiring width of 70 nm or less and a wiring pitch of 140 nm or less
  • a hole has a high dielectric constant.
  • a cap layer it is possible to prevent vacancies from being exposed on the upper surface of the insulating film. For this reason, while reducing the capacity
  • FIGS. 1A, 1 ⁇ / b> B, and 1 ⁇ / b> C are diagrams showing a schematic cross section, an inter-wiring capacitance, and a TDDB life in order for an exemplary semiconductor device according to an embodiment of the present disclosure.
  • 2A to 2D are diagrams illustrating a method for manufacturing an exemplary semiconductor device according to an embodiment of the present disclosure.
  • FIGS. 3A to 3D are views for explaining a method for manufacturing an exemplary semiconductor device according to an embodiment following FIG. 2D.
  • FIGS. 4A and 4B are diagrams sequentially showing the hole diameter distribution and the TDDB lifetime for the exemplary semiconductor device of the embodiment.
  • FIG. 5 is a diagram illustrating a state in which a multilayer wiring structure is provided in an exemplary semiconductor device according to an embodiment of the present disclosure.
  • 6A to 6C are diagrams for explaining the background art.
  • FIG. 1 is a diagram schematically showing a cross section of an exemplary semiconductor device 100 of the present embodiment.
  • a low dielectric constant insulating film 103 including a large number of holes 104 is formed on a substrate 101.
  • a wiring groove is formed in the low dielectric constant insulating film 103, and a damascene wiring 107 in which a conductive film 106 such as Cu is embedded through a barrier metal film 105 is formed.
  • the holes 104 are distributed in size in the low dielectric constant insulating film 103, and are larger toward the lower side and smaller toward the upper side.
  • the lower side means the substrate 101 side
  • the upper side means the damascene wiring 107 side which is the opposite side.
  • the diameter of the hole 104a exposed on the upper surface of the low dielectric constant insulating film 103 can be reduced to, for example, 0.8 nm or less, and the adsorption of moisture, conduction components, and the like is suppressed to suppress the deterioration of the breakdown voltage. be able to.
  • the diameter of the hole 104 in the vicinity of the substrate 101 is, for example, 1.05 nm.
  • the semiconductor device 100 it is avoided that large holes are exposed on the upper surface of the low dielectric constant insulating film to increase the surface area. As a result, it is not necessary to provide a cap layer with a high dielectric constant for the purpose of suppressing the breakdown voltage deterioration, and the inter-wiring capacitance is reduced.
  • FIG. 1B is a diagram showing the relationship between the wiring thickness and the inter-wiring capacitance, and includes a case of the semiconductor device 100 (example, plotted by white circles ⁇ ) and holes of uniform size. The case where a low dielectric constant insulating film is formed (background art, plotted by black circles ⁇ ) is shown. As shown in FIG. 1B, the inter-wiring capacitance is reduced as compared with the background art. This is because, in the case of the background art, the low dielectric constant film above the wiring absorbs moisture and increases the capacitance between the wirings, whereas this can be avoided in the configuration of the present embodiment.
  • FIG. 1C is a diagram showing the withstand voltage between wirings, both of which have a capless structure. Compared to the background art (black circle), the TDDB (Time Dependent Dielectric Breakdown) of the embodiment (open circle) is shown. ) Indicates that the life has improved.
  • TDDB Time Dependent Dielectric Breakdown
  • the semiconductor device 200 includes a damascene wiring 207 in which a low dielectric constant insulating film 203 including a hole 204 is formed on a lower wiring layer 201 and a Cu plating film 215 that is a conductive film is embedded through a barrier metal film 213. It has a formed structure.
  • a liner film 208 is formed to cover the low dielectric constant insulating film 203 and the damascene wiring 207. Also in this case, the holes 204 are distributed so that they are larger toward the lower side (lower wiring layer 201 side) and smaller toward the upper side.
  • the lower wiring layer 201 shown in FIG. That is, after the insulating film 253 is formed on the liner film 251, a wiring groove is formed in the insulating film 253, and the conductive film 256 is buried through the barrier metal film 255 to form the lower layer wiring 257. Thereafter, a liner film 258 is formed so as to cover the insulating film 253 and the lower layer wiring 257. Since both can be performed by a known method, detailed description is omitted.
  • a low dielectric constant insulating film 203 containing a hole forming material 202 (porogen) is formed on the lower wiring layer 201.
  • a CVD (Chemical Vapor Deposition) method using a raw material gas by a precursor such as DEMS (Diethoxymethylsilan) and a pore forming material such as ⁇ -terpinene.
  • DEMS Diethoxymethylsilan
  • a pore forming material such as ⁇ -terpinene.
  • 0.25 g / min ⁇ -terpinene may be used for 0.3 g / min DEMS.
  • the applied high frequency power is about 300 W to 500 W
  • the oxygen flow rate is about 10 cm 3 / min to 15 cm 3 / min.
  • the process of FIG. in order to remove the hole forming material 202 contained in the low dielectric constant insulating film 203, heater heating and UV light irradiation are performed.
  • the hole forming material 202 is sublimated and removed, and a hole 204 is formed in the low dielectric constant insulating film 203.
  • the heater temperature is 400 ° C.
  • the UV irradiation intensity is 150 to 200 mW / cm 2
  • the irradiation time is 80 to 160 seconds.
  • the first region which is the surface portion of the low dielectric constant insulating film 203 becomes the non-porous region 210.
  • the film thickness of the non-porous region 210 is, for example, about 20 nm.
  • the holes 204 have a hole diameter distribution in the film thickness direction.
  • FIG. 4A shows a specific example of the pore diameter distribution.
  • the hole diameter is larger under the low dielectric constant insulating film 203 (on the lower wiring layer 201 side) and gradually increases upward.
  • On the surface portion of the low dielectric constant insulating film 203 there is a non-vacant region 210 in which the vacancy 204 is not formed.
  • the average pore diameter is preferably 0.85 nm or more and 0.95 nm or less, and the maximum pore diameter is preferably 1.05 nm or less. Further, it is desirable that the hole diameter is 0.8 nm or less immediately below the non-hole area 210.
  • the UV curing processing time is long, the non-porous region 210 becomes thick, and sublimation of the hole forming material 202 is hindered. Therefore, it is preferable to adjust the UV curing time so that the film thickness of the non-porous region 210 is 20 nm or less.
  • the UV curing time is 60 seconds to 240 seconds.
  • FIG. 4 (a) also shows an example in the case where the conditions of UV curing are not controlled.
  • the void-free region 210 is thick, and the hole diameter in a relatively shallow region is generally large.
  • the amount of the hole forming material 202 is increased and gradually decreased as the film formation proceeds, so that a hole is formed in the surface portion that becomes the non-hole region 210.
  • Film formation is performed without using the material 202. Such a method is particularly desirable in order to reduce the hole 204 immediately below the non-hole area 210.
  • the low dielectric constant insulating film 203 is formed by a single film forming step and a single UV cure. Therefore, the manufacturing process can be shortened and the cost can be reduced as compared with the case where one low dielectric constant insulating film is formed by repeating these processes a plurality of times.
  • the UV cure which performs both heater heating and UV light irradiation was demonstrated, it can replace with this and the method of performing only heating or only UV light irradiation can also be taken.
  • a wiring groove 211 is formed in the low dielectric constant insulating film 203 including the non-vacant region 210 and a connection hole 212 that communicates with the wiring groove 211 and reaches the conductive film 256 of the lower wiring layer 201 is formed.
  • lithography and etching may be used.
  • connection hole 212 is formed, part of the liner film 258 of the lower wiring layer 201 is also removed by etching.
  • the barrier metal film 213 and the Cu seed film 214 are formed on the entire surface of the low dielectric constant insulating film 203 by the PVD method. As a result, the barrier metal film 213 and the Cu seed film 214 are also laminated in the wiring trench 211 and the connection hole 212 (side wall and bottom).
  • a Cu plating film 215 is formed by electroplating. Thereby, the inside of the wiring groove 211 and the connection hole 212 is also filled with the Cu plating film 215.
  • the Cu seed film 214 is not shown in FIG. 3B because it is integrated with the Cu plating film 215.
  • the excess Cu plating film 215 and the barrier metal film 213 protruding from the wiring trench 211 are removed by polishing using a CMP (Chemical Mechanical Polishing) method. Thereby, the damascene wiring 207 in which the Cu plating film 215 is embedded via the barrier metal film 213 is formed.
  • CMP Chemical Mechanical Polishing
  • the non-porous region 210 which is the surface portion of the low dielectric constant insulating film 203 is also removed by the CMP method. Further, a small amount of the upper part of the low dielectric constant insulating film 203 including the hole 204 is also etched. This amount of cutting is desirably 20 nm to 30 nm. Further, it is desirable that the diameter of the hole 204a exposed on the upper surface of the low dielectric constant insulating film 203 between the damascene wirings 207 as a result of cutting is 0.8 nm or less.
  • the amount of etching of the low dielectric constant insulating film 203 and the diameter of the holes 204 exposed on the upper surface affect the inter-wiring breakdown voltage (TDDB). As shown in FIG. 4B, when the cutting is performed until the pore diameter exceeds 0.8 nm (overpolishing), the TDDB deteriorates.
  • a liner film 208 covering the damascene wiring 207 is formed as shown in FIG. This is a diffusion preventing film that prevents the Cu plating film 215 from diffusing Cu.
  • a wiring layer having a structure in which wiring is embedded in a low dielectric constant insulating film including holes is formed without using a cap film.
  • wiring layers 301, 302, and 303 having a structure in which wiring is embedded in a low dielectric constant insulating film including holes are stacked, and further, a vacant layer is formed thereon.
  • a semiconductor device in which wiring layers 401 and 402 having a structure not including a hole are stacked is illustrated.
  • the structure of the wiring layer of this embodiment is effective when applied to a fine wiring layer having a narrow wiring width and a narrow wiring pitch. Further, it is effective to apply to a wiring layer having a high wiring density.
  • the present invention is applied to a wiring layer whose wiring width is less than 70 nm and whose wiring pitch (the sum of the wiring width and the distance between adjacent wirings) is 140 nm or less.
  • the distance between the wirings in the upper layer of these layers may be made larger than that in the lower layer, and the porosity on the upper layer side may be reduced.
  • the porosity in the wiring layer 303 may be smaller than the porosity in the wiring layer 302.
  • wiring layer for example, relatively thick wiring such as the uppermost wiring, power wiring, etc.
  • the wiring layer having the structure of this embodiment including the holes but the necessity Is relatively low.
  • a low dielectric constant insulating film having a lower porosity than the low dielectric constant insulating film of the fine wiring layer may be used.
  • the degree of requirement for inter-wiring capacitance and inter-wiring withstand voltage is lower than that of a fine wiring layer, so that the above structure is less likely to be a problem.

Abstract

A method for manufacturing a semiconductor device (200) is provided with the following steps (a-e): a step (a) wherein an insulating film (203) is formed on a substrate, said insulating film being composed of a single layer and containing a hole-forming material (202); a step (b) wherein holes (204) are formed in a second region below a first region (210) in the insulating film (203) by removing the hole-forming material (202), without forming holes in the first region (210), which is the surface portion of the insulating film (203); a step (c) wherein at least one wiring trench (211) is formed in the insulating film (203); a step (d) wherein a conductive film (215) is formed such that the wiring trench (211) is embedded in the conductive film; and a step (e) wherein wiring (207) is formed by removing the surplus portion of the conductive film (215), said surplus portion protruding from the wiring trench (211).

Description

半導体装置及びその製造方法Semiconductor device and manufacturing method thereof
　本開示は、半導体装置とその製造方法に関し、特に、空孔を含む低誘電率膜を備える半導体装置において配線間耐圧を向上し且つ配線間容量を低減する方法に関する。 The present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a method of improving a withstand voltage between wires and reducing a capacitance between wires in a semiconductor device including a low dielectric constant film including holes.
　近年、半導体集積回路の高集積化に伴い、配線遅延を低減することが要求されている。配線遅延を低減する方法の１つとして、配線材料に低抵抗材料であるＣｕを採用し、配線構造としてはＣｕを埋め込むダマシン配線が採用されている。 In recent years, with the high integration of semiconductor integrated circuits, it is required to reduce wiring delay. As one of the methods for reducing the wiring delay, Cu, which is a low resistance material, is adopted as a wiring material, and damascene wiring in which Cu is embedded is adopted as a wiring structure.
　また、半導体集積回路の高集積化に伴い、配線幅が縮小されると共に、配線遅延に影響を及ぼす配線間容量が増大している。これは、半導体デバイスの高速化を阻害する原因となるので、配線間容量の低減のために、絶縁膜の低誘電率化が必須となっている。その方法の１つとして、絶縁膜形成時に、原材料ガスと共に空孔形成材（ポロジェン）を用い、空孔を含む絶縁膜を形成することが行なわれている。これに関して記載されている特許文献１の技術について、以下に説明する。 Further, with the high integration of semiconductor integrated circuits, the wiring width is reduced and the inter-wiring capacitance that affects the wiring delay is increased. Since this hinders the speeding up of the semiconductor device, it is essential to lower the dielectric constant of the insulating film in order to reduce the inter-wiring capacitance. As one of the methods, when forming an insulating film, a hole forming material (porogen) is used together with a raw material gas to form an insulating film including holes. The technique of Patent Document 1 described in this regard will be described below.
　特許文献１は、下層配線層１上に、エッチングストッパ膜２を介して、多数の空孔４を含む層間絶縁膜３が形成された構造（図６（ａ））を示している。また、絶縁膜３中に一様な空孔４を形成するために、原材料ガス及び空孔形成材を用いて成膜を行なう工程と、ポロジェンを昇華させるためのＵＶキュアプロセスとを繰り返して行なうことを示している。 Patent Document 1 shows a structure in which an interlayer insulating film 3 including a large number of holes 4 is formed on a lower wiring layer 1 via an etching stopper film 2 (FIG. 6A). In addition, in order to form uniform vacancies 4 in the insulating film 3, a film forming process using the raw material gas and the vacancy forming material and a UV cure process for sublimating the porogen are repeated. It is shown that.
　しかしながら、このような構造に対してダマシン配線５を形成した場合、配線間の絶縁膜３において、表面に露出した空孔４ａが発生する（図６（ｂ））。この結果、絶縁膜の表面積が増加して水分、導通成分等が吸着しやすくなり、耐圧劣化が生じる。 However, when the damascene wiring 5 is formed for such a structure, a hole 4a exposed on the surface is generated in the insulating film 3 between the wirings (FIG. 6B). As a result, the surface area of the insulating film increases and moisture, conductive components, etc. are easily adsorbed, resulting in deterioration of pressure resistance.
　このような耐圧劣化を抑制するためには、ダマシン配線５を形成する前に、絶縁膜３上に誘電率の高い絶縁膜からなる保護膜（キャップ層６）を形成し、配線間において空孔４を露出させないようにする（図６（ｃ））。 In order to suppress such breakdown voltage degradation, a protective film (cap layer 6) made of an insulating film having a high dielectric constant is formed on the insulating film 3 before the damascene wiring 5 is formed. 4 is not exposed (FIG. 6C).
特開２００５－２２３１９５号公報JP 2005-223195 A
　しかしながら、前記に説明した特許文献１の場合、空孔の露出を防ぐためのキャップ層の誘電率が高い。このため、空孔を含む低誘電率の絶縁膜を用いて配線間容量を低減する効果が阻害されてしまう。よって、この解決が課題となる。 However, in the case of Patent Document 1 described above, the cap layer has a high dielectric constant for preventing exposure of holes. For this reason, the effect of reducing the capacitance between wirings using an insulating film having a low dielectric constant including holes is hindered. Therefore, this solution becomes a problem.
　以上に鑑み、空孔を含む絶縁膜を用いる半導体装置及びその製造方法において、配線間耐圧を向上すると共に配線間容量を低減する技術について、以下に説明する。 In view of the above, a technique for improving the withstand voltage between wires and reducing the capacitance between wires in a semiconductor device using an insulating film including voids and a manufacturing method thereof will be described below.
　本開示に係る半導体装置の製造方法は、基板上に、単一層からなり且つ空孔形成材料を含む絶縁膜を形成する工程（ａ）と、絶縁膜のうち表面から所定の深さまでを第１領域として、第１領域よりも下方の第２領域に、空孔形成材料の除去により空孔を形成する工程（ｂ）と、絶縁膜に少なくとも１つの配線溝を形成する工程（ｃ）と、配線溝を埋め込むように導電膜を形成する工程（ｄ）と、配線溝からはみ出た余剰部分の導電膜を除去することにより配線を形成する工程（ｅ）とを備える。 The method for manufacturing a semiconductor device according to the present disclosure includes a step (a) of forming an insulating film made of a single layer and including a hole forming material on a substrate, and a first step from the surface to a predetermined depth of the insulating film. As a region, a step (b) of forming a hole in the second region below the first region by removing the hole forming material, a step (c) of forming at least one wiring groove in the insulating film, A step (d) of forming a conductive film so as to fill the wiring trench; and a step (e) of forming a wiring by removing the excess portion of the conductive film protruding from the wiring trench.
　ここで、第１領域には空孔を形成しないことが好ましい。 Here, it is preferable not to form holes in the first region.
　このような半導体装置の製造方法によると、誘電率の高いキャップ層を用いること無しに、絶縁膜上面に空孔が露出するのを防ぐことができる。このため、配線間容量を低減すると共に、絶縁膜に対する水分、導通成分等の吸着を抑制して耐圧劣化を抑制することができる。 According to such a method for manufacturing a semiconductor device, it is possible to prevent vacancies from being exposed on the upper surface of the insulating film without using a cap layer having a high dielectric constant. For this reason, while reducing the capacity | capacitance between wirings, adsorption | suction of the water | moisture content, a conduction | electrical_connection component, etc. with respect to an insulating film can be suppressed, and pressure | voltage resistant deterioration can be suppressed.
　尚、工程（ａ）において、１回の成膜工程により絶縁膜を形成することが好ましい。 In step (a), it is preferable to form an insulating film by a single film formation step.
　このように、連続した１回の成膜工程により成膜を行なうと、工程数が少なくなることから、半導体装置の製造コストを低減することができる。 As described above, when film formation is performed by one continuous film formation process, the number of processes is reduced, so that the manufacturing cost of the semiconductor device can be reduced.
　また、工程（ａ）において、第２領域となる空孔形成材料を含む部分の絶縁膜を形成した後、第１領域となる空孔形成材料を含まない部分の絶縁膜を形成することが好ましい。 Further, in the step (a), it is preferable to form a portion of the insulating film including the hole forming material to be the second region and then forming a portion of the insulating film not including the hole forming material to be the first region. .
　このようにすると、空孔を含まない第１領域を確実に形成することができる。 This makes it possible to reliably form the first region that does not include holes.
　また、工程（ｅ）において、絶縁膜の第１領域の少なくとも一部を除去することが好ましい。 In the step (e), it is preferable to remove at least a part of the first region of the insulating film.
　空孔を含まない第１領域は、空孔を含む第２領域に比べて誘電率が高い。よって、第１領域の少なくとも一部を除去することにより、配線間容量を低減することができる。 The first region that does not include holes has a higher dielectric constant than the second region that includes holes. Therefore, by removing at least a part of the first region, it is possible to reduce the inter-wiring capacitance.
　また、工程（ｂ）において、第２領域の空孔が、基板の側から第１領域の側に向かって小さくなるように制御することが好ましい。 In the step (b), it is preferable to control so that the holes in the second region become smaller from the substrate side toward the first region side.
　このようにすると、絶縁膜の上面に大きな空孔が露出するのを避けることができ、特に、空孔を含まない第１領域を全て除去した場合にも大きな空孔の露出を避けることができる。その結果、配線間の耐圧劣化を抑制することができる。 In this way, it is possible to avoid exposure of large vacancies on the upper surface of the insulating film, and in particular, even when all of the first region not including vacancies is removed, exposure of large vacancies can be avoided. . As a result, it is possible to suppress breakdown voltage degradation between the wirings.
　また、工程（ｂ）において、紫外線照射及び加熱の少なくとも一方を行なうことが好ましい。 In the step (b), it is preferable to perform at least one of ultraviolet irradiation and heating.
　これにより、空孔形成材料を除去して空孔を形成することができる。更に、紫外線照射及び加熱の条件を設定することにより、空孔の大きさ、空孔を含まない第１領域の厚さ等を制御することができる。 Thereby, the pore forming material can be removed to form the pores. Furthermore, by setting the conditions for ultraviolet irradiation and heating, the size of the holes, the thickness of the first region not including the holes, and the like can be controlled.
　また、工程（ａ）において、絶縁膜は、原材料ガス及び空孔形成材料を用いて形成され、原材料ガスの量に対する空孔形成材料の供給量を、絶縁膜の形成の進行に合わせて少なくすることが好ましい。 In the step (a), the insulating film is formed using the raw material gas and the hole forming material, and the supply amount of the hole forming material with respect to the amount of the raw material gas is reduced in accordance with the progress of the formation of the insulating film. It is preferable.
　このようにすると、絶縁膜中（第２領域中）の空孔について、基板の側から第１領域の側に向かって小さくなるようにすることができる。 In this way, the vacancies in the insulating film (in the second region) can be reduced from the substrate side toward the first region side.
　また、原材料ガスの量に対し、０．８倍以上１．２８倍以下の量の空孔形成材料を用いることが好ましい。 Further, it is preferable to use the pore forming material in an amount of 0.8 times or more and 1.28 times or less with respect to the amount of the raw material gas.
　また、第２領域に形成される空孔の径は、平均が０．８５ｎｍ以上で且つ０．９５ｎｍ以下であり、最大が１．０５ｎｍ以下であることが好ましい。 Further, the diameter of the holes formed in the second region is preferably 0.85 nm or more and 0.95 nm or less and the maximum is 1.05 nm or less.
　また、第１領域の膜厚は２０ｎｍ以下であり、第１領域の直下における空孔の径は０．８ｎｍ以下であることが好ましい。 In addition, the film thickness of the first region is preferably 20 nm or less, and the diameter of the pores immediately below the first region is preferably 0.8 nm or less.
　誘電率の高い第１領域は薄い方が良い。また、径が０．８ｎｍ以下の空孔であれば、絶縁膜の上面に露出したとしても耐圧劣化の原因にはなりにくい。 The first region with a high dielectric constant should be thin. In addition, if the hole has a diameter of 0.8 nm or less, even if it is exposed on the upper surface of the insulating film, it is difficult to cause breakdown of the breakdown voltage.
　また、絶縁膜を第１の絶縁膜、配線を第１の配線とするとき、工程（ｅ）の後に、第１の絶縁膜上に、第２の配線を含む第２の絶縁膜を形成する工程（ｆ）を更に備え、第２の絶縁膜は、空孔を含まないことが好ましい。 When the insulating film is the first insulating film and the wiring is the first wiring, a second insulating film including the second wiring is formed on the first insulating film after the step (e). It is preferable that the method further includes the step (f), and the second insulating film does not include voids.
　また、絶縁膜を第１の絶縁膜、配線を第１の配線とするとき、工程（ｅ）の後に、第１の絶縁膜上に、第２の配線を含む第２の絶縁膜を形成する工程（ｆ）を更に備え、第２の絶縁膜における空孔率は、第１の絶縁膜における空孔率よりも低いことが好ましい。 When the insulating film is the first insulating film and the wiring is the first wiring, a second insulating film including the second wiring is formed on the first insulating film after the step (e). Step (f) is further provided, and the porosity of the second insulating film is preferably lower than the porosity of the first insulating film.
　このように、配線を含む絶縁膜が複数積層されている場合に、一部の絶縁膜（ここでは第１の絶縁膜）だけに、以上に説明した構成が適用されていても良い。また、いずれの絶縁膜も空孔を含み、それぞれ空孔率が異なる（ここでは、第１の絶縁膜の方が空孔率が低い）構成としても良い。 As described above, when a plurality of insulating films including wirings are stacked, the configuration described above may be applied only to a part of the insulating films (here, the first insulating film). Further, any of the insulating films may include a hole, and the porosity may be different (here, the first insulating film has a lower porosity).
　また、第１の配線は、第２の配線よりも密集して形成されても良い。 Further, the first wiring may be formed more densely than the second wiring.
　また、第１の配線及び第２の配線は、それぞれ、基板の主面方向に複数ずつ形成され、第１の配線の配線間距離は、第２の配線の配線間距離よりも短いようになっていても良い。 In addition, a plurality of first wirings and a plurality of second wirings are formed in the main surface direction of the substrate, respectively, and the distance between the wirings of the first wiring is shorter than the distance between the wirings of the second wiring. May be.
　このように、配線を含む絶縁膜が複数積層されている場合、配線の密集度、配線間の距離等に応じて、絶縁膜中の空孔の構成を設定してもよい。 As described above, when a plurality of insulating films including wirings are stacked, the structure of holes in the insulating film may be set according to the density of wirings, the distance between wirings, and the like.
　また、第１の配線の配線幅は７０ｎｍ未満であり、第１の配線の配線間距離は１４０ｎｍ以下であることが好ましい。 Further, it is preferable that the wiring width of the first wiring is less than 70 nm, and the distance between the wirings of the first wiring is 140 nm or less.
　このような寸法の配線を形成する場合に、本開示の技術は特に有用である。 The technique of the present disclosure is particularly useful when forming wiring with such dimensions.
　次に、本開示の半導体装置は、基板上に形成され、複数の空孔を含む絶縁膜と、絶縁膜上部に埋め込むように形成された少なくとも１つの配線とを備え、複数の空孔の径は、絶縁膜の下方から上方に向かって小さくなるように変化している。 Next, a semiconductor device of the present disclosure includes an insulating film that is formed on a substrate and includes a plurality of holes, and at least one wiring that is formed so as to be embedded in the upper part of the insulating film. Changes so as to decrease from the bottom to the top of the insulating film.
　尚、絶縁膜は、単一層であることが好ましい。 Note that the insulating film is preferably a single layer.
　このような半導体装置によると、誘電率の高いキャップ層を用いること無しに、絶縁膜上面に空孔が露出するのを防ぐことができる。このため、配線間容量を低減すると共に、絶縁膜に対する水分、導通成分等の吸着を抑制して耐圧劣化を抑制することができる。 According to such a semiconductor device, it is possible to prevent vacancies from being exposed on the upper surface of the insulating film without using a cap layer having a high dielectric constant. For this reason, while reducing the capacity | capacitance between wirings, adsorption | suction of the water | moisture content, a conduction | electrical_connection component, etc. with respect to an insulating film can be suppressed, and pressure | voltage resistant deterioration can be suppressed.
　また、絶縁膜を第１の絶縁膜、配線を第１の配線とするとき、第１の絶縁膜及び第１の配線を覆うように形成された第２の絶縁膜と、第２の絶縁膜上に形成された少なくとも１つの第２の配線とを備え、第２の絶縁膜は、空孔を含まないことが好ましい。 When the insulating film is the first insulating film and the wiring is the first wiring, the second insulating film formed so as to cover the first insulating film and the first wiring, and the second insulating film It is preferable that at least one second wiring formed above is provided, and the second insulating film does not include a hole.
　また、第１の絶縁膜及び第１の配線を覆うように形成され、複数の空孔を含む第２の絶縁膜と、第２の絶縁膜上に形成された少なくとも１つの第２の配線とを備え、第２の絶縁膜における空孔率は、第１の絶縁膜における空孔率よりも低いことが好ましい。 A second insulating film formed to cover the first insulating film and the first wiring and including a plurality of holes; and at least one second wiring formed on the second insulating film; It is preferable that the porosity of the second insulating film is lower than the porosity of the first insulating film.
　このように、配線を含む絶縁膜が複数積層されている場合に、一部の絶縁膜（ここでは第１の絶縁膜）だけに、以上に説明した構成が適用されていても良い。また、いずれの絶縁膜も空孔を含み、それぞれ空孔率が異なる（ここでは、第１の絶縁膜の方が空孔率が低い）構成としても良い。 As described above, when a plurality of insulating films including wirings are stacked, the configuration described above may be applied only to a part of the insulating films (here, the first insulating film). Further, any of the insulating films may include a hole, and the porosity may be different (here, the first insulating film has a lower porosity).
　また、第１の配線は、第２の配線よりも密集して形成されていてもよい。 Further, the first wiring may be formed more densely than the second wiring.
　また、第１の配線及び第２の配線は、それぞれ、基板の主面方向に複数ずつ形成されており、第１の配線の配線間距離は、第２の配線の配線間距離よりも短いようにしてもよい。 Further, a plurality of first wirings and a plurality of second wirings are formed in the main surface direction of the substrate, respectively, and the distance between the wirings of the first wiring is shorter than the distance between the wirings of the second wiring. It may be.
　このように、配線を含む絶縁膜が複数積層されている場合、配線の密集度、配線間の距離等に応じて、絶縁膜中の空孔の構成を設定してもよい。 As described above, when a plurality of insulating films including wirings are stacked, the structure of holes in the insulating film may be set according to the density of wirings, the distance between wirings, and the like.
　本開示の半導体装置及びその製造方法によると、微細化した配線（例えば、配線幅７０ｎｍ以下、配線ピッチ１４０ｎｍ以下）及び空孔を含む低誘電率絶縁膜を備えた半導体装置において、誘電率の高いキャップ層を用いること無しに、絶縁膜上面に空孔が露出するのを防ぐことができる。このため、配線間容量を低減すると共に、絶縁膜に対する水分、導通成分等の吸着を抑制して耐圧劣化を抑制することができる。 According to the semiconductor device and the manufacturing method thereof of the present disclosure, a semiconductor device having a low dielectric constant insulating film including fine wiring (for example, a wiring width of 70 nm or less and a wiring pitch of 140 nm or less) and a hole has a high dielectric constant. Without using a cap layer, it is possible to prevent vacancies from being exposed on the upper surface of the insulating film. For this reason, while reducing the capacity | capacitance between wirings, adsorption | suction of the water | moisture content, a conduction | electrical_connection component, etc. with respect to an insulating film can be suppressed, and pressure | voltage resistant deterioration can be suppressed.
図１（ａ）、（ｂ）及び（ｃ）は、本開示の一実施形態における例示的半導体装置について、順に、模式的な断面、配線間容量及びＴＤＤＢ寿命を示す図である。FIGS. 1A, 1 </ b> B, and 1 </ b> C are diagrams showing a schematic cross section, an inter-wiring capacitance, and a TDDB life in order for an exemplary semiconductor device according to an embodiment of the present disclosure. 図２（ａ）～（ｄ）は、本開示の一実施形態における例示的半導体装置の製造方法を説明する図である。2A to 2D are diagrams illustrating a method for manufacturing an exemplary semiconductor device according to an embodiment of the present disclosure. 図３（ａ）～（ｄ）は、図２（ｄ）に続いて、一実施形態の例示的半導体装置の製造方法を説明する図である。FIGS. 3A to 3D are views for explaining a method for manufacturing an exemplary semiconductor device according to an embodiment following FIG. 2D. 図４（ａ）及び（ｂ）は、順に、一実施形態の例示的半導体装置について、空孔の径分布及びＴＤＤＢ寿命を示す図である。FIGS. 4A and 4B are diagrams sequentially showing the hole diameter distribution and the TDDB lifetime for the exemplary semiconductor device of the embodiment. 図５は、本開示の一実施形態における例示的半導体装置において多層配線構造を設けた様子を示す図である。FIG. 5 is a diagram illustrating a state in which a multilayer wiring structure is provided in an exemplary semiconductor device according to an embodiment of the present disclosure. 図６（ａ）～（ｃ）は、背景技術を説明する図である。6A to 6C are diagrams for explaining the background art.
　以下、本開示の一実施形態の半導体装置及びその製造方法について、図面を参照しながら説明する。 Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present disclosure will be described with reference to the drawings.
　図１は、本実施形態の例示的半導体装置１００の断面を模式的に示す図である。半導体装置１００において、基板１０１上に、多数の空孔１０４を含む低誘電率絶縁膜１０３が形成されている。低誘電率絶縁膜１０３には配線溝が形成され、バリアメタル膜１０５を介してＣｕ等の導電膜１０６が埋め込まれたダマシン配線１０７が形成されている。 FIG. 1 is a diagram schematically showing a cross section of an exemplary semiconductor device 100 of the present embodiment. In the semiconductor device 100, a low dielectric constant insulating film 103 including a large number of holes 104 is formed on a substrate 101. A wiring groove is formed in the low dielectric constant insulating film 103, and a damascene wiring 107 in which a conductive film 106 such as Cu is embedded through a barrier metal film 105 is formed.
　空孔１０４は、低誘電率絶縁膜１０３中において大きさに分布があり、下方ほど大きく、上方に向かって小さくなっている。尚、下方とは基板１０１の側、上方とはその反対側であるダマシン配線１０７の側を意味するものとする。 The holes 104 are distributed in size in the low dielectric constant insulating film 103, and are larger toward the lower side and smaller toward the upper side. Here, the lower side means the substrate 101 side, and the upper side means the damascene wiring 107 side which is the opposite side.
　このことから、低誘電率絶縁膜１０３の上面に露出する空孔１０４ａの径を、例えば０．８ｎｍ以下と小さくすることができ、水分、導通成分等の吸着を抑制して耐圧劣化を抑制することができる。尚、基板１０１付近における空孔１０４の径は、例えば１．０５ｎｍである。 Therefore, the diameter of the hole 104a exposed on the upper surface of the low dielectric constant insulating film 103 can be reduced to, for example, 0.8 nm or less, and the adsorption of moisture, conduction components, and the like is suppressed to suppress the deterioration of the breakdown voltage. be able to. The diameter of the hole 104 in the vicinity of the substrate 101 is, for example, 1.05 nm.
　このように、半導体装置１００において、大きな空孔が低誘電率絶縁膜の上面に露出して表面積を増加させることは避けられている。この結果、耐圧劣化を抑制する目的で誘電率の高いキャップ層を設けることは不要となり、配線間容量が低減されている。 Thus, in the semiconductor device 100, it is avoided that large holes are exposed on the upper surface of the low dielectric constant insulating film to increase the surface area. As a result, it is not necessary to provide a cap layer with a high dielectric constant for the purpose of suppressing the breakdown voltage deterioration, and the inter-wiring capacitance is reduced.
　図１（ｂ）は、配線厚さと配線間容量との関係について示す図であり、半導体装置１００の場合（実施例、白抜きの丸○によりプロット）と、均一な大きさの空孔を含む低誘電率絶縁膜が形成されている場合（背景技術、黒丸●によりプロット）とを示している。図１（ｂ）に示される通り、背景技術に比べて配線間容量が低減されている。この理由は、背景技術の場合、配線上部の低誘電率膜が水分を吸収し、配線間容量を増加させるのに対し、本実施形態の構成ではこれを避けることができることである。 FIG. 1B is a diagram showing the relationship between the wiring thickness and the inter-wiring capacitance, and includes a case of the semiconductor device 100 (example, plotted by white circles ○) and holes of uniform size. The case where a low dielectric constant insulating film is formed (background art, plotted by black circles ●) is shown. As shown in FIG. 1B, the inter-wiring capacitance is reduced as compared with the background art. This is because, in the case of the background art, the low dielectric constant film above the wiring absorbs moisture and increases the capacitance between the wirings, whereas this can be avoided in the configuration of the present embodiment.
　また、図１（ｃ）は、配線間耐圧について示す図であり、どちらもキャップレス構造であるが、背景技術（黒丸）に比べて実施例（白抜きの丸）のＴＤＤＢ（Time Dependent Dielectric Breakdown ）寿命が改善していることを示している。 FIG. 1C is a diagram showing the withstand voltage between wirings, both of which have a capless structure. Compared to the background art (black circle), the TDDB (Time Dependent Dielectric Breakdown) of the embodiment (open circle) is shown. ) Indicates that the life has improved.
　次に、図２（ａ）～（ｄ）及び図３（ａ）～（ｄ）を参照し、図３（ｄ）に示す第２の例示的半導体装置２００の製造方法について説明する。半導体装置２００は、下層配線層２０１上に、空孔２０４を含む低誘電率絶縁膜２０３が形成され、バリアメタル膜２１３を介して導電膜であるＣｕめっき膜２１５が埋め込まれたダマシン配線２０７が形成された構造を有する。また、低誘電率絶縁膜２０３上及びダマシン配線２０７上を覆うライナー膜２０８が形成されている。ここでも、空孔２０４は、下方（下層配線層２０１の側）ほど大きく、上方に向かって小さくなるように分布している。 Next, with reference to FIGS. 2A to 2D and FIGS. 3A to 3D, a method for manufacturing the second exemplary semiconductor device 200 shown in FIG. 3D will be described. The semiconductor device 200 includes a damascene wiring 207 in which a low dielectric constant insulating film 203 including a hole 204 is formed on a lower wiring layer 201 and a Cu plating film 215 that is a conductive film is embedded through a barrier metal film 213. It has a formed structure. A liner film 208 is formed to cover the low dielectric constant insulating film 203 and the damascene wiring 207. Also in this case, the holes 204 are distributed so that they are larger toward the lower side (lower wiring layer 201 side) and smaller toward the upper side.
　半導体装置２００を製造するには、初めに、図２（ａ）に示す下層配線層２０１を形成する。つまり、ライナー膜２５１上に絶縁膜２５３を形成した後、該絶縁膜２５３に配線溝を形成し、バリアメタル膜２５５を介して導電膜２５６を埋め込んで下層配線２５７とする。その後、絶縁膜２５３及び下層配線２５７上を覆うように、ライナー膜２５８を形成する。いずれも、公知の方法により行なうことができるため、詳しい説明は省略する。 To manufacture the semiconductor device 200, first, the lower wiring layer 201 shown in FIG. That is, after the insulating film 253 is formed on the liner film 251, a wiring groove is formed in the insulating film 253, and the conductive film 256 is buried through the barrier metal film 255 to form the lower layer wiring 257. Thereafter, a liner film 258 is formed so as to cover the insulating film 253 and the lower layer wiring 257. Since both can be performed by a known method, detailed description is omitted.
　次に、図２（ｂ）に示す通り、下層配線層２０１上に、空孔形成材料２０２（ポロジェン）を含む低誘電率絶縁膜２０３を形成する。例えば、ＤＥＭＳ（Diethoxymethylsilan、ジエトキシメチルシラン）等のプリカーサー（precursor）による原材料ガスと、αテルピネン等の空孔形成材料とを用い、ＣＶＤ（Chemical Vapor Deposition ）法によって形成する。この際、原材料ガス１に対し、空孔形成材料を０．８～１．２８を用いることが望ましい。一例として、０．３ｇ／ｍｉｎのＤＥＭＳに対し、０．２５ｇ／ｍｉｎのαテルピネンを用いても良い。また、印加する高周波電力は３００Ｗ～５００Ｗ程度、酸素流量は１０ｃｍ3 ／ｍｉｎ～１５ｃｍ3 ／ｍｉｎ程度とするのが望ましい。 Next, as shown in FIG. 2B, a low dielectric constant insulating film 203 containing a hole forming material 202 (porogen) is formed on the lower wiring layer 201. For example, it is formed by a CVD (Chemical Vapor Deposition) method using a raw material gas by a precursor such as DEMS (Diethoxymethylsilan) and a pore forming material such as α-terpinene. At this time, it is desirable to use 0.8 to 1.28 pore forming material for the raw material gas 1. As an example, 0.25 g / min α-terpinene may be used for 0.3 g / min DEMS. Further, it is desirable that the applied high frequency power is about 300 W to 500 W, and the oxygen flow rate is about 10 cm 3 / min to 15 cm 3 / min.
　次に、図２（ｃ）の工程を行なう。ここでは、低誘電率絶縁膜２０３に含有される空孔形成材料２０２を除去するために、ヒーター加熱及びＵＶ光の照射を行なう。このようなＵＶキュアにより、空孔形成材料２０２は昇華して除去され、低誘電率絶縁膜２０３中に空孔２０４が形成される。ＵＶキュアの条件としては、例えば、ヒーター温度を４００℃、ＵＶ照射強度を１５０～２００ｍＷ／ｃｍ2 、照射時間を８０～１６０秒とする。 Next, the process of FIG. Here, in order to remove the hole forming material 202 contained in the low dielectric constant insulating film 203, heater heating and UV light irradiation are performed. By such UV curing, the hole forming material 202 is sublimated and removed, and a hole 204 is formed in the low dielectric constant insulating film 203. As the UV curing conditions, for example, the heater temperature is 400 ° C., the UV irradiation intensity is 150 to 200 mW / cm 2 , and the irradiation time is 80 to 160 seconds.
　このようなＵＶキュアにより、低誘電率絶縁膜２０３の表面部である第１領域は、無空孔領域２１０となる。該無空孔領域２１０の膜厚は、例えば２０ｎｍ程度となる。また、無空孔領域２１０よりも下の第２領域の低誘電率絶縁膜２０３において、空孔２０４は膜厚方向に空孔径分布を持つ。 By such UV curing, the first region which is the surface portion of the low dielectric constant insulating film 203 becomes the non-porous region 210. The film thickness of the non-porous region 210 is, for example, about 20 nm. Further, in the low dielectric constant insulating film 203 in the second region below the non-hole region 210, the holes 204 have a hole diameter distribution in the film thickness direction.
　図４（ａ）に、空孔径分布について具体例を示している。空孔径は、低誘電率絶縁膜２０３の下方（下層配線層２０１側）ほど大きく、上方に向かって徐々に大きくなる。低誘電率絶縁膜２０３の表面部には、空孔２０４が形成されていない無空孔領域２１０が存在する。空孔径の平均は０．８５ｎｍ以上で且つ０．９５ｎｍ以下であることが望ましく、また、空孔径の最大は１．０５ｎｍ以下であることが好ましい。更に、無空孔領域２１０の直下において、空孔径は０．８ｎｍ以下であることが望ましい。 FIG. 4A shows a specific example of the pore diameter distribution. The hole diameter is larger under the low dielectric constant insulating film 203 (on the lower wiring layer 201 side) and gradually increases upward. On the surface portion of the low dielectric constant insulating film 203, there is a non-vacant region 210 in which the vacancy 204 is not formed. The average pore diameter is preferably 0.85 nm or more and 0.95 nm or less, and the maximum pore diameter is preferably 1.05 nm or less. Further, it is desirable that the hole diameter is 0.8 nm or less immediately below the non-hole area 210.
　また、ＵＶキュアの処理時間が長いと無空孔領域２１０が厚くなり、空孔形成材料２０２の昇華を妨げる。よって、ＵＶキュア時間を調整し、無空孔領域２１０の膜厚が２０ｎｍ以下となるようにするのがよい。例えば、ＵＶキュア時間を６０秒～２４０秒とする。 In addition, when the UV curing processing time is long, the non-porous region 210 becomes thick, and sublimation of the hole forming material 202 is hindered. Therefore, it is preferable to adjust the UV curing time so that the film thickness of the non-porous region 210 is 20 nm or less. For example, the UV curing time is 60 seconds to 240 seconds.
　図４（ａ）には、ＵＶキュアについて条件の制御を行なわない場合の例も示している。この例では、無空孔領域２１０については厚くなり、且つ、比較的浅い領域における空孔径は概ね大きくなっている。 FIG. 4 (a) also shows an example in the case where the conditions of UV curing are not controlled. In this example, the void-free region 210 is thick, and the hole diameter in a relatively shallow region is generally large.
　ここで、空孔形成材料２０２の径の分布を実現するために、図２（ｂ）に示すＣＶＤ法による成膜の際、原材料ガスに対する空孔形成材料２０２の量を変化させることが望ましい。 Here, in order to realize the distribution of the diameter of the hole forming material 202, it is desirable to change the amount of the hole forming material 202 with respect to the raw material gas during film formation by the CVD method shown in FIG.
　つまり、低誘電率絶縁膜２０３を形成する初期には空孔形成材料２０２の量を多くしておき、成膜の進行に従って次第に減少させて、無空孔領域２１０となる表面部では空孔形成材料２０２を用いずに成膜する。このような方法は、無空孔領域２１０直下における空孔２０４を小さくするためには特に望ましい。 That is, at the initial stage of forming the low dielectric constant insulating film 203, the amount of the hole forming material 202 is increased and gradually decreased as the film formation proceeds, so that a hole is formed in the surface portion that becomes the non-hole region 210. Film formation is performed without using the material 202. Such a method is particularly desirable in order to reduce the hole 204 immediately below the non-hole area 210.
　本実施形態の場合、低誘電率絶縁膜２０３は一度の成膜工程と一度のＵＶキュアによって形成される。よって、これらの工程をそれぞれ複数回繰り返して１つの低誘電率絶縁膜を形成する場合に比べ、製造工程を短く且つ低コストにすることができる。尚、ヒーター加熱とＵＶ光の照射を共に行なうＵＶキュアの場合を説明したが、これに代えて、加熱のみ又はＵＶ光の照射のみを行なう方法を取ることも可能である。 In the case of this embodiment, the low dielectric constant insulating film 203 is formed by a single film forming step and a single UV cure. Therefore, the manufacturing process can be shortened and the cost can be reduced as compared with the case where one low dielectric constant insulating film is formed by repeating these processes a plurality of times. In addition, although the case of the UV cure which performs both heater heating and UV light irradiation was demonstrated, it can replace with this and the method of performing only heating or only UV light irradiation can also be taken.
　次に、図２（ｄ）の工程を行なう。ここでは、無空孔領域２１０を含む低誘電率絶縁膜２０３に対し、配線溝２１１を形成すると共に、配線溝２１１と連通して下層配線層２０１の導電膜２５６に達する接続孔２１２を形成する。これには、リソグラフィ及びエッチングを用いればよい。尚、接続孔２１２を形成する際には、下層配線層２０１のライナー膜２５８についても一部エッチング除去される。 Next, the process of FIG. 2D is performed. Here, a wiring groove 211 is formed in the low dielectric constant insulating film 203 including the non-vacant region 210 and a connection hole 212 that communicates with the wiring groove 211 and reaches the conductive film 256 of the lower wiring layer 201 is formed. . For this, lithography and etching may be used. When the connection hole 212 is formed, part of the liner film 258 of the lower wiring layer 201 is also removed by etching.
　次に、図３（ａ）の工程を行なう。つまり、低誘電率絶縁膜２０３上の全面に、ＰＶＤ法により、バリアメタル膜２１３及びＣｕシード膜２１４を成膜する。これにより、配線溝２１１及び接続孔２１２の内部（側壁及び底部）についても、バリアメタル膜２１３及びＣｕシード膜２１４が積層形成される。 Next, the process of FIG. That is, the barrier metal film 213 and the Cu seed film 214 are formed on the entire surface of the low dielectric constant insulating film 203 by the PVD method. As a result, the barrier metal film 213 and the Cu seed film 214 are also laminated in the wiring trench 211 and the connection hole 212 (side wall and bottom).
　次に、図３（ｂ）に示すように、電界めっきによりＣｕめっき膜２１５を形成する。これにより、配線溝２１１及び接続孔２１２の内部についても、Ｃｕめっき膜２１５によって充填される。尚、Ｃｕシード膜２１４は、Ｃｕめっき膜２１５と一体化するため、図３（ｂ）には図示していない。 Next, as shown in FIG. 3B, a Cu plating film 215 is formed by electroplating. Thereby, the inside of the wiring groove 211 and the connection hole 212 is also filled with the Cu plating film 215. The Cu seed film 214 is not shown in FIG. 3B because it is integrated with the Cu plating film 215.
　次に、図３（ｃ）に示すように、ＣＭＰ（Chemical Mechanical Polishing ）法を用いた研磨により、配線溝２１１からはみ出た余剰部分のＣｕめっき膜２１５及びバリアメタル膜２１３を除去する。これにより、バリアメタル膜２１３を介してＣｕめっき膜２１５が埋め込まれたダマシン配線２０７が構成される。 Next, as shown in FIG. 3C, the excess Cu plating film 215 and the barrier metal film 213 protruding from the wiring trench 211 are removed by polishing using a CMP (Chemical Mechanical Polishing) method. Thereby, the damascene wiring 207 in which the Cu plating film 215 is embedded via the barrier metal film 213 is formed.
　このとき、低誘電率絶縁膜２０３のうち表面部である無空孔領域２１０も、ＣＭＰ法により除去する。更に、空孔２０４を含む部分の低誘電率絶縁膜２０３についても、上部の若干量を削り込む。この削り込み量は、２０ｎｍ～３０ｎｍとすることが望ましい。また、削り込んだ結果、ダマシン配線２０７間の低誘電率絶縁膜２０３上面に露出する空孔２０４ａについて、その径が０．８ｎｍ以下であることが望ましい。 At this time, the non-porous region 210 which is the surface portion of the low dielectric constant insulating film 203 is also removed by the CMP method. Further, a small amount of the upper part of the low dielectric constant insulating film 203 including the hole 204 is also etched. This amount of cutting is desirably 20 nm to 30 nm. Further, it is desirable that the diameter of the hole 204a exposed on the upper surface of the low dielectric constant insulating film 203 between the damascene wirings 207 as a result of cutting is 0.8 nm or less.
　低誘電率絶縁膜２０３の削り込み量及び上面に露出する空孔２０４の径は、配線間耐圧（ＴＤＤＢ）に影響する。図４（ｂ）に示すように、前記空孔径が０．８ｎｍを越えるまで削り込みを行なった場合（過研磨）、ＴＤＤＢに劣化が生じる。 The amount of etching of the low dielectric constant insulating film 203 and the diameter of the holes 204 exposed on the upper surface affect the inter-wiring breakdown voltage (TDDB). As shown in FIG. 4B, when the cutting is performed until the pore diameter exceeds 0.8 nm (overpolishing), the TDDB deteriorates.
　ＣＭＰ法による研磨の後、図３（ｄ）に示すように、ダマシン配線２０７上を覆うライナー膜２０８を形成する。これは、Ｃｕめっき膜２１５のＣｕの拡散を防止する拡散防止膜である。 After polishing by the CMP method, a liner film 208 covering the damascene wiring 207 is formed as shown in FIG. This is a diffusion preventing film that prevents the Cu plating film 215 from diffusing Cu.
　以上のようにして、キャップ膜を用いること無く、空孔を含む低誘電率絶縁膜に配線が埋め込まれた構造の配線層が一層形成される。 As described above, a wiring layer having a structure in which wiring is embedded in a low dielectric constant insulating film including holes is formed without using a cap film.
　図５には、以上に説明した工程を繰り返すことにより、空孔を含む低誘電率絶縁膜に配線が埋め込まれた構造の配線層３０１、３０２及び３０３が積層形成され、更にその上に、空孔を含まない構造の配線層４０１及び４０２が積層された半導体装置を示している。 In FIG. 5, by repeating the steps described above, wiring layers 301, 302, and 303 having a structure in which wiring is embedded in a low dielectric constant insulating film including holes are stacked, and further, a vacant layer is formed thereon. A semiconductor device in which wiring layers 401 and 402 having a structure not including a hole are stacked is illustrated.
　本実施形態の配線層の構造は、配線幅が狭く且つ配線ピッチが狭い微細配線層に適用することが効果的である。また、配線密集度の高い配線層に適用することが効果的である。例えば、配線幅が７０ｎｍ未満、配線ピッチ（配線幅と、隣り合う配線同士の間の距離との和）が１４０ｎｍ以下の配線層に適用する。 The structure of the wiring layer of this embodiment is effective when applied to a fine wiring layer having a narrow wiring width and a narrow wiring pitch. Further, it is effective to apply to a wiring layer having a high wiring density. For example, the present invention is applied to a wiring layer whose wiring width is less than 70 nm and whose wiring pitch (the sum of the wiring width and the distance between adjacent wirings) is 140 nm or less.
　また、空孔を含む低誘電率膜を用いる配線層３０１～３０３について、これらのうちの上層において下層よりも配線間距離を大きくすると共に、上層側の空孔率を小さくしても良い。例えば、配線層３０３における配線間距離が配線層３０２における配線間距離よりも大きいのであれば、配線層３０３における空孔率を配線層３０２における空孔率よりも小さくしても良い。 Further, in the wiring layers 301 to 303 using the low dielectric constant film including the voids, the distance between the wirings in the upper layer of these layers may be made larger than that in the lower layer, and the porosity on the upper layer side may be reduced. For example, if the inter-wiring distance in the wiring layer 303 is larger than the inter-wiring distance in the wiring layer 302, the porosity in the wiring layer 303 may be smaller than the porosity in the wiring layer 302.
　それ以外の配線層、例えば最上層配線等の比較的太い配線、電源配線等の層については、空孔を含む本実施形態の構造の配線層を使用することも当然可能であるが、必要性は比較的低い。使用する場合、微細配線層の低誘電率絶縁膜に比べて、空孔率が低い低誘電率絶縁膜を用いても良い。 As for other wiring layers, for example, relatively thick wiring such as the uppermost wiring, power wiring, etc., it is naturally possible to use the wiring layer having the structure of this embodiment including the holes, but the necessity Is relatively low. When used, a low dielectric constant insulating film having a lower porosity than the low dielectric constant insulating film of the fine wiring layer may be used.
　比較的太い配線の層では、配線間容量及び配線間耐圧についての要求の程度が微細配線層に比べると低いので、以上のような構造でも問題になりにくい。 In the case of a relatively thick wiring layer, the degree of requirement for inter-wiring capacitance and inter-wiring withstand voltage is lower than that of a fine wiring layer, so that the above structure is less likely to be a problem.
１００　　　　　　　　　半導体装置
１０１　　　　　　　　　基板
１０３　　　　　　　　　低誘電率絶縁膜
１０４　　　　　　　　　空孔
１０４ａ　　　　　　　　露出する空孔
１０５　　　　　　　　　バリアメタル膜
１０６　　　　　　　　　導電膜
１０７　　　　　　　　　ダマシン配線
２００　　　　　　　　　半導体装置
２０１　　　　　　　　　下層配線層
２０２　　　　　　　　　空孔形成材料
２０３　　　　　　　　　低誘電率絶縁膜
２０４　　　　　　　　　空孔
２０７　　　　　　　　　ダマシン配線
２０８　　　　　　　　　ライナー膜
２１０　　　　　　　　　無空孔領域
２１１　　　　　　　　　配線溝
２１２　　　　　　　　　接続孔
２１３　　　　　　　　　バリアメタル膜
２１４　　　　　　　　　Ｃｕシード膜
２１５　　　　　　　　　Ｃｕめっき膜
２５１　　　　　　　　　ライナー膜
２５３　　　　　　　　　絶縁膜
２５５　　　　　　　　　バリアメタル膜
２５６　　　　　　　　　導電膜
２５７　　　　　　　　　下層配線
２５８　　　　　　　　　ライナー膜
３０１、３０２、３０３　配線層
４０１、４０２　　　　　配線層 100 Semiconductor device 101 Substrate 103 Low dielectric constant insulating film 104 Hole 104a Exposed hole 105 Barrier metal film 106 Conductive film 107 Damascene wiring 200 Semiconductor device 201 Lower wiring layer 202 Hole forming material 203 Low dielectric constant insulating film 204 Hole 207 Damascene wiring 208 Liner film 210 Non-vacuum region 211 Wiring groove 212 Connection hole 213 Barrier metal film 214 Cu seed film 215 Cu plating film 251 Liner film 253 Insulating film 255 Barrier metal film 256 Conductive film 257 Lower layer wiring 258 Liner film 301, 302, 303 Wiring layer 401, 402 Wiring layer

Claims (22)

  1. 　基板上に、単一層からなり且つ空孔形成材料を含む絶縁膜を形成する工程（ａ）と、
    　前記絶縁膜のうち表面から所定の深さまでを第１領域として、前記第１領域よりも下方の第２領域に、前記空孔形成材料の除去により空孔を形成する工程（ｂ）と、
    　前記絶縁膜に少なくとも１つの配線溝を形成する工程（ｃ）と、
    　前記配線溝を埋め込むように導電膜を形成する工程（ｄ）と、
    　前記配線溝からはみ出た余剰部分の前記導電膜を除去することにより配線を形成する工程（ｅ）とを備えることを特徴とする半導体装置の製造方法。     A step (a) of forming an insulating film comprising a single layer and including a pore forming material on a substrate;
    (B) forming a hole by removing the hole forming material in a second region below the first region from the surface to a predetermined depth of the insulating film as a first region;
    Forming at least one wiring groove in the insulating film (c);
    A step (d) of forming a conductive film so as to fill the wiring trench;
    And a step (e) of forming a wiring by removing the conductive film in an excess portion protruding from the wiring trench.
  2. 　請求項１の半導体装置の製造方法において、
    　前記第１領域には空孔を形成しないことを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device of Claim 1,
    A method of manufacturing a semiconductor device, wherein no void is formed in the first region.
  3. 　請求項１の半導体装置の製造方法において、
    　前記工程（ａ）において、１回の成膜工程により前記絶縁膜を形成すること特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device of Claim 1,
    In the step (a), the insulating film is formed by a single film formation step.
  4. 　請求項１の半導体装置の製造方法において、
    　前記工程（ａ）において、前記第２領域となる前記空孔形成材料を含む部分の前記絶縁膜を形成した後、前記第１領域となる前記空孔形成材料を含まない部分の前記絶縁膜を形成することを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device of Claim 1,
    In the step (a), after forming the insulating film in a portion including the hole forming material to be the second region, the insulating film in a portion not including the hole forming material to be the first region is formed. A method for manufacturing a semiconductor device, comprising: forming a semiconductor device.
  5. 　請求項１の半導体装置の製造方法において、
    　前記工程（ｅ）において、前記絶縁膜の前記第１領域の少なくとも一部を除去することを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device of Claim 1,
    In the step (e), at least a part of the first region of the insulating film is removed.
  6. 　請求項１の半導体装置の製造方法において、
    　前記工程（ｂ）において、前記第２領域の前記空孔が、前記基板の側から前記第１領域の側に向かって小さくなるように制御することを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device of Claim 1,
    In the step (b), the semiconductor device manufacturing method is characterized in that the vacancy in the second region is controlled to become smaller from the substrate side toward the first region side.
  7. 　請求項１の半導体装置の製造方法において、
    　前記工程（ｂ）において、紫外線照射及び加熱の少なくとも一方を行なうことを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device of Claim 1,
    In the step (b), at least one of ultraviolet irradiation and heating is performed.
  8. 　請求項１の半導体装置の製造方法において、
    　前記工程（ａ）において、
    　前記絶縁膜は、原材料ガス及び前記空孔形成材料を用いて形成され、
    　前記原材料ガスの量に対する前記空孔形成材料の供給量を、前記絶縁膜の形成の進行に合わせて少なくすることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device of Claim 1,
    In the step (a),
    The insulating film is formed using a raw material gas and the hole forming material,
    A method of manufacturing a semiconductor device, wherein the supply amount of the hole forming material relative to the amount of the raw material gas is reduced in accordance with the progress of the formation of the insulating film.
  9. 　請求項８の半導体装置の製造方法において、
    　前記原材料ガスの量に対し、０．８倍以上１．２８倍以下の量の前記空孔形成材料を用いることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device of Claim 8,
    A method for manufacturing a semiconductor device, wherein the hole forming material is used in an amount of 0.8 to 1.28 times the amount of the raw material gas.
  10. 　請求項１の半導体装置の製造方法において、
    　前記第２領域に形成される前記空孔の径は、平均が０．８５ｎｍ以上で且つ０．９５ｎｍ以下であり、最大が１．０５ｎｍ以下であることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device of Claim 1,
    The method of manufacturing a semiconductor device, wherein the average diameter of the holes formed in the second region is 0.85 nm or more and 0.95 nm or less, and the maximum is 1.05 nm or less.
  11. 　請求項１の半導体装置の製造方法において、
    　前記第１領域の膜厚は２０ｎｍ以下であり、前記第１領域の直下における前記空孔の径は０．８ｎｍ以下であることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device of Claim 1,
    The method of manufacturing a semiconductor device, wherein the film thickness of the first region is 20 nm or less, and the diameter of the vacancy immediately below the first region is 0.8 nm or less.
  12. 　請求項１の半導体装置の製造方法において、
    　前記絶縁膜を第１の絶縁膜、前記配線を第１の配線とするとき、
    　前記工程（ｅ）の後に、前記第１の絶縁膜上に、第２の配線を含む第２の絶縁膜を形成する工程（ｆ）を更に備え、
    　前記第２の絶縁膜は、空孔を含まないことを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device of Claim 1,
    When the insulating film is a first insulating film and the wiring is a first wiring,
    After the step (e), the method further includes a step (f) of forming a second insulating film including a second wiring on the first insulating film,
    The method for manufacturing a semiconductor device, wherein the second insulating film does not include a hole.
  13. 　請求項１の半導体装置の製造方法において、
    　前記絶縁膜を第１の絶縁膜、前記配線を第１の配線とするとき、
    　前記工程（ｅ）の後に、前記第１の絶縁膜上に、第２の配線を含む第２の絶縁膜を形成する工程（ｆ）を更に備え、
    　前記第２の絶縁膜における空孔率は、前記第１の絶縁膜における空孔率よりも低いことを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device of Claim 1,
    When the insulating film is a first insulating film and the wiring is a first wiring,
    After the step (e), the method further includes a step (f) of forming a second insulating film including a second wiring on the first insulating film,
    A method for manufacturing a semiconductor device, wherein a porosity of the second insulating film is lower than a porosity of the first insulating film.
  14. 　請求項１２の半導体装置の製造方法において、
    　前記第１の配線は、前記第２の配線よりも密集して形成されることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device of Claim 12,
    The method of manufacturing a semiconductor device, wherein the first wiring is formed denser than the second wiring.
  15. 　請求項１２の半導体装置の製造方法において、
    　前記第１の配線及び前記第２の配線は、それぞれ、前記基板の主面方向に複数ずつ形成され、
    　前記第１の配線の配線間距離は、前記第２の配線の配線間距離よりも短いことを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device of Claim 12,
    A plurality of the first wirings and the second wirings are formed in the main surface direction of the substrate, respectively.
    A method of manufacturing a semiconductor device, wherein a distance between wirings of the first wiring is shorter than a distance between wirings of the second wiring.
  16. 　請求項１５の半導体装置の製造方法において、
    　前記第１の配線の配線幅は７０ｎｍ未満であり、
    　前記第１の配線の配線間距離は１４０ｎｍ以下であることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device of Claim 15,
    The wiring width of the first wiring is less than 70 nm,
    A method for manufacturing a semiconductor device, wherein a distance between wirings of the first wiring is 140 nm or less.
  17. 　基板上に形成され、複数の空孔を含む絶縁膜と、
    　前記絶縁膜上部に埋め込むように形成された少なくとも１つの配線とを備え、
    　前記複数の空孔の径は、前記絶縁膜の下方から上方に向かって小さくなるように変化していることを特徴とする半導体装置。     An insulating film formed on the substrate and including a plurality of holes;
    And at least one wiring formed so as to be embedded in the upper part of the insulating film,
    The diameter of the plurality of holes is changed so as to decrease from the lower side to the upper side of the insulating film.
  18. 　請求項１７の半導体装置において、
    　前記絶縁膜は、単一層であることを特徴とする半導体装置。     The semiconductor device according to claim 17.
    The semiconductor device is characterized in that the insulating film is a single layer.
  19. 　請求項１７の半導体装置において、
    　前記絶縁膜を第１の絶縁膜、前記配線を第１の配線とするとき、
    　前記第１の絶縁膜及び前記第１の配線を覆うように形成された第２の絶縁膜と、
    　前記第２の絶縁膜上に形成された少なくとも１つの第２の配線とを備え、
    　前記第２の絶縁膜は、空孔を含まないことを特徴とする半導体装置。     The semiconductor device according to claim 17.
    When the insulating film is a first insulating film and the wiring is a first wiring,
    A second insulating film formed to cover the first insulating film and the first wiring;
    And at least one second wiring formed on the second insulating film,
    The semiconductor device, wherein the second insulating film does not include a hole.
  20. 　請求項１７の半導体装置において、
    　前記絶縁膜を第１の絶縁膜、前記配線を第１の配線とするとき、
    　前記第１の絶縁膜及び前記第１の配線を覆うように形成され、複数の空孔を含む第２の絶縁膜と、
    　前記第２の絶縁膜上に形成された少なくとも１つの第２の配線とを備え、
    　前記第２の絶縁膜における空孔率は、前記第１の絶縁膜における空孔率よりも低いことを特徴とする半導体装置。     The semiconductor device according to claim 17.
    When the insulating film is a first insulating film and the wiring is a first wiring,
    A second insulating film formed to cover the first insulating film and the first wiring and including a plurality of holes;
    And at least one second wiring formed on the second insulating film,
    The semiconductor device according to claim 1, wherein a porosity of the second insulating film is lower than a porosity of the first insulating film.
  21. 　請求項１９の半導体装置において、
    　前記第１の配線は、前記第２の配線よりも密集して形成されていることを特徴とする半導体装置。     The semiconductor device according to claim 19.
    The semiconductor device, wherein the first wiring is formed more densely than the second wiring.
  22. 　請求項１９の半導体装置において、
    　前記第１の配線及び前記第２の配線は、それぞれ、前記基板の主面方向に複数ずつ形成されており、
    　前記第１の配線の配線間距離は、前記第２の配線の配線間距離よりも短いことを特徴とする半導体装置。     The semiconductor device according to claim 19.
    Each of the first wiring and the second wiring is formed in a plurality in the main surface direction of the substrate,
    The distance between the wirings of the first wiring is shorter than the distance between the wirings of the second wiring.
PCT/JP2010/005211 2009-12-10 2010-08-24 Semiconductor device and method for manufacturing same WO2011070694A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009280026A JP2011124351A (en) 2009-12-10 2009-12-10 Semiconductor device and method for manufacturing same
JP2009-280026 2009-12-10

Publications (1)

Publication Number Publication Date
WO2011070694A1 true WO2011070694A1 (en) 2011-06-16

Family

ID=44145263

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2010/005211 WO2011070694A1 (en) 2009-12-10 2010-08-24 Semiconductor device and method for manufacturing same

Country Status (2)

Country Link
JP (1) JP2011124351A (en)
WO (1) WO2011070694A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101998788B1 (en) 2013-04-22 2019-07-11 삼성전자주식회사 Semiconductor Devices and Methods of Fabricating the Same
CN104979272B (en) * 2014-04-04 2018-03-30 中芯国际集成电路制造(上海)有限公司 Interconnection structure and forming method thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003273216A (en) * 2002-03-18 2003-09-26 Sony Corp Semiconductor device and its manufacturing method
JP2004146798A (en) * 2002-09-30 2004-05-20 Sanyo Electric Co Ltd Semiconductor device and manufacturing method therefor
JP2005504433A (en) * 2001-07-18 2005-02-10 トリコン ホールディングス リミティド Low dielectric constant layer
JP2005079116A (en) * 2003-08-29 2005-03-24 Semiconductor Leading Edge Technologies Inc Method for manufacturing semiconductor device
JP2005136301A (en) * 2003-10-31 2005-05-26 Fujitsu Ltd Semiconductor device and manufacturing method thereof
JP2007073914A (en) * 2005-09-09 2007-03-22 Rohm Co Ltd Porous thin film, manufacturing method therefor, and semiconductor device using it

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005504433A (en) * 2001-07-18 2005-02-10 トリコン ホールディングス リミティド Low dielectric constant layer
JP2003273216A (en) * 2002-03-18 2003-09-26 Sony Corp Semiconductor device and its manufacturing method
JP2004146798A (en) * 2002-09-30 2004-05-20 Sanyo Electric Co Ltd Semiconductor device and manufacturing method therefor
JP2005079116A (en) * 2003-08-29 2005-03-24 Semiconductor Leading Edge Technologies Inc Method for manufacturing semiconductor device
JP2005136301A (en) * 2003-10-31 2005-05-26 Fujitsu Ltd Semiconductor device and manufacturing method thereof
JP2007073914A (en) * 2005-09-09 2007-03-22 Rohm Co Ltd Porous thin film, manufacturing method therefor, and semiconductor device using it

Also Published As

Publication number Publication date
JP2011124351A (en) 2011-06-23

Similar Documents

Publication Publication Date Title
JP5355892B2 (en) Wiring structure, semiconductor device and manufacturing method thereof
JP5180426B2 (en) Manufacturing method of semiconductor device
JP5554951B2 (en) Manufacturing method of semiconductor device
US8129254B2 (en) Semiconductor device and manufacturing method thereof
US7655576B2 (en) Insulator film, manufacturing method of multilayer wiring device and multilayer wiring device
US8564136B2 (en) Semiconductor device and method for fabricating the same
JP2010258215A5 (en) Semiconductor device
US20090152732A1 (en) Semiconductor device and method of manufacturing the same
US7781301B2 (en) Method of fabricating semiconductor device
JP2007227507A (en) Semiconductor device, and method of manufacturing semiconductor device
JP5213010B2 (en) Semiconductor device, manufacturing method thereof, and manufacturing device thereof
JP2007165428A (en) Process for fabricating semiconductor device
WO2011070694A1 (en) Semiconductor device and method for manufacturing same
RU2486632C2 (en) Method for manufacturing of improved multilevel copper metallisation using dielectrics with ultra low dielectric constant (ultra low-k)
US7129164B2 (en) Method for forming a multi-layer low-K dual damascene
US8878364B2 (en) Method for fabricating semiconductor device and semiconductor device
KR100426147B1 (en) Method for forming an interlayer insulating film, and semiconductor devices
JP2008193038A (en) Method and structure for manufacturing porous low-permittivity layer, interconnection processing method, and interconnection structure
US7482275B2 (en) Plasma treatment method and method of manufacturing semiconductor device
JP4257252B2 (en) Manufacturing method of semiconductor device
KR100877095B1 (en) Method of fabricating interconnection in semicondutor device
JP5200436B2 (en) Manufacturing method of semiconductor device
WO2011039898A1 (en) Semiconductor device manufacturing method and semiconductor device
JP2006319116A (en) Semiconductor device and its manufacturing method
KR101107568B1 (en) Method for forming metal line of semiconductor device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10835625

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10835625

Country of ref document: EP

Kind code of ref document: A1