WO2011066786A1 - Ultra-shallow junction and method for forming the same - Google Patents

Ultra-shallow junction and method for forming the same Download PDF

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Publication number
WO2011066786A1
WO2011066786A1 PCT/CN2010/079240 CN2010079240W WO2011066786A1 WO 2011066786 A1 WO2011066786 A1 WO 2011066786A1 CN 2010079240 W CN2010079240 W CN 2010079240W WO 2011066786 A1 WO2011066786 A1 WO 2011066786A1
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ions
implanting
kev
region
ultra
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Jian Du
Jianling Cai
Jiajia Li
Dejin Wang
Keyun Zhang
Hao Fang
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/225—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of a molecular ion, e.g. decaborane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/28—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by an annealing step, e.g. for activation of dopants

Definitions

  • the present disclosure relates to the field of semiconductor technology and, more particularly, to an ultra-shallow junction and a method for forming the same and a PMOS transistor.
  • Ion implantation is an impurity doping technique widely used in forming a variety of semiconductor devices and integrated circuits.
  • the amount of ions implanted by an ion beam into a semiconductor substrate and their distribution can be accurately adjusted by controlling the current and voltage of the ion beam.
  • Feature size of semiconductor devices becomes smaller as the technology advances.
  • Vertical size of a device i.e., depth of the device
  • horizontal size i.e., linewidth represented by the feature size
  • ion implementation is used to form shallow junctions or ultra-shallow junctions, e.g., a lightly-doped source region or a lightly-doped drain region of a Metal-Oxide-Semiconductor (MOS) transistor.
  • MOS Metal-Oxide-Semiconductor
  • Threshold voltage of a MOS transistor is a parameter that reflects performance of the MOS transistor.
  • the threshold voltage of the MOS transistor may be improved by enhancing substrate bias effect, also known as body effect.
  • the substrate bias effect can be provided for a PMOS transistor, if its substrate and its source are reverse biased (i.e., a negative voltage is applied to the P substrate) such that a depletion region in the substrate becomes thicker, causing an increase in fixed electric charges in the depletion layer.
  • the increase of the electric charges in the depletion layer leads to a reduction of mobile electric charges in the channel, for a balance requirement of charges on both sides of a gate capacitance. Therefore, the reduction of mobile electric charges in the channel results in degraded electric conductivity. Improvement of gate voltage may increase the electric charges on the gate, thus maintaining electric conductivity level.
  • the threshold voltage of the PMOS transistor is increased by substrate bias.
  • the body effect may be characterized using a body effect parameter ⁇ .
  • a higher body effect ⁇ parameter represents a greater body effect and a higher threshold voltage.
  • the body effect parameter ⁇ may be determined by the following equation: [0007] wherein 0 is vacuum permittivity, ⁇ is a quantity of elementary charges, is an ion doping concentration in the channel region, and Cox [ s a capacitance per unit of area of the gate dielectric layer.
  • the body effect parameter ⁇ may be improved by increasing the ion doping concentration in the channel region.
  • [0009] may be increased by increasing the distance between the source and the drain.
  • impurity diffusion in the source and the drain can be better controlled, such that the amount of electric charges in the depletion layer is reduced, thereby increasing ⁇ a and improving the body effect.
  • the body effect can also be improved by thickening sidewall spacers. However, this may reduce the saturation drain current, affecting other electric parameters of the MOS device.
  • a method for forming an ultra-shallow junction includes:
  • a method for forming a PMOS transistor includes:
  • a gate structure on a semiconductor substrate, wherein a source region and a drain region are defined in the substrate on opposite sides of the gate structure;
  • the ultra-shallow junction includes:
  • junction structure in the substrate, the junction structure including a first ion implantation region including an amorphized structure
  • a method for manufacturing a PMOS transistor includes:
  • FIG. 1 illustrates a flow chart of a method for forming an ultra-shallow junction structure according to an embodiment
  • Fig. 2 to Fig. 6 illustrate cross-sectional views of a method for forming an ultra-shallow junction structure according to an embodiment
  • Fig. 7 illustrates a flow chart of a method for forming a PMOS transistor according to an embodiment
  • Fig. 8 and Fig. 9 illustrate cross-sectional views of a method for forming a PMOS transistor according to an embodiment.
  • a method disclosed herein of forming an ultra-shallow junction may include implantation of boron fluoride ions before amorphization of a substrate.
  • the method takes advantage of easier diffusion of fluoride ions in, for example, a crystalline silicon than in amorphous silicon.
  • Silicon-oxygen bonds in a gate dielectric layer on a surface of the substrate may be more easily broken by the fluoride ions. Oxygen ions separated from the broken silicon-oxygen bonds may oxidize the substrate silicon near the gate dielectric layer, which increases thickness of the gate dielectric layer.
  • boron fluoride ions are heavier than boron ions, they may block subsequent boron ions from diffusing, so as to control horizontal diffusion of boron. Such limiting of horizontal diffusion may further improve the body effect, and thus the threshold voltage.
  • Fig. 1 illustrates a flow chart of a method for forming an ultra-shallow junction structure according to an embodiment of the present disclosure. The method includes:
  • Step S 101 providing a semiconductor substrate
  • Step SI 02 implanting first ions into the semiconductor substrate, to form a first implantation region
  • Step SI 03 implanting second ions into the first implantation region, to amorphize the first implantation region
  • Step SI 04 implanting third ions into the amorphized first implantation region, to form an ultra-shallow junction structure.
  • Fig. 2 to Fig. 6 are schematic cross-sectional views of a device in various stages of the method for forming an ultra-shallow junction structure according to an embodiment of the disclosure.
  • the present embodiment is described with an example by which a Lightly Doped Drain (LDD) of a PMOS transistor is formed as an ultra-shallow junction structure.
  • LDD Lightly Doped Drain
  • a semiconductor substrate 101 is provided.
  • the semiconductor substrate 101 may be monocrystalline silicon or silicon-germanium, or Silicon On Insulator (SOI).
  • SOI Silicon On Insulator
  • the semiconductor substrate 101 may include other materials such as III- V compound semiconductors, e.g., gallium arsenide.
  • An N-type well and a channel region are formed in the semiconductor substrate 101.
  • An isolation structure may also be formed in the semiconductor substrate 101.
  • Such an isolation structure may be, for example, a LOCOS region formed by local oxidation, or a shallow trench isolation structure.
  • a gate dielectric layer 102 is formed on a surface of the semiconductor substrate 101.
  • the gate dielectric layer 102 may be silicon oxide, silicon nitride or a High-k dielectric material.
  • the gate dielectric layer 102 may have a thickness ranging from tens of Angstroms to hundreds of Angstroms.
  • the gate dielectric layer 102 may be formed by, for example, thermal oxidation, Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or Plasma Enhanced Chemical Vapor Deposition (PECVD).
  • a gate electrode layer 103 is formed over the gate dielectric layer 102.
  • the gate electrode layer 103 may be polycrystalline silicon, having a thickness ranging from hundreds of Angstroms to thousands of Angstroms.
  • the gate electrode layer 103 may be formed by Low Pressure Chemical Vapor Deposition (LPCVD).
  • the gate dielectric layer 102 and the gate electrode layer 103 are patterned using a resist mask, to form a gate structure.
  • the gate structure includes the gate dielectric layer 102 and the gate electrode layer 103.
  • the region of the substrate 101 on opposite sides of and separated by the gate structure are referred to herein as a source region and a drain region of the semiconductor substrate 101.
  • a first implantation 105 is performed to implant first ions into the source region and the drain region using the gate structure as a mask.
  • the first implantation may be performed with an accelerating energy ranging from 10 Kev to 30
  • a first implantation region 104 is formed by the first implantation.
  • the first ions may be boron fluoride ions.
  • a second implantation 106 is performed to implant second ions into the first implantation region 104 using the gate structure as a mask.
  • the second implantation may be performed with an accelerating energy ranging from 30
  • the second ions may be tetravalent ions.
  • the second ions may be silicon or germanium.
  • the second implantation is performed to cause amorphization in the first implantation region, so that crystal structures in the first implantation region may be disordered, which may limit diffusion of subsequent-implanted ions.
  • the amorphization may be performed using silicon ions with an energy of 40 Kev and a dose of 9E15/cm .
  • a third implantation 107 is performed to implant third ions into the amorphized first implantation region 104 using the gate structure as a mask.
  • the third implantation may be performed with an accelerating energy ranging from 5 Kev to 12 Kev and a dose ranging from lE13/cm 2 to lE14/cm 2 .
  • the third ions may be boron ions. As a result, an ultra-shallow junction structure is formed.
  • the energy of boron ions may be 10 Kev, and the dose may be 5.0E13/cm .
  • a method is provided according to an embodiment for forming a PMOS transistor.
  • the method includes:
  • Step S201 providing a semiconductor substrate
  • Step S202 forming a gate structure on the semiconductor substrate, which defines a source region and a drain region of the substrate separated by the gate structure and on respective sides thereof;
  • Step S203 performing a first implantation to implant first ions into the source region and the drain region by using the gate structure as a mask, to form a first implantation region;
  • Step S204 performing a second implantation to implant second ions into the first implantation region by using the gate structure as a mask, to amorphize the first implantation region;
  • Step S205 performing a third implantation to implant third ions into the amorphized first implantation region by using the gate structure as a mask, thereby forming an ultra-shallow junction structure;
  • Step S206 forming sidewall spacers on both sides of the gate structure
  • Step S207 heavily-doping the source region and the drain region, to form a source and a drain;
  • Step S208 performing thermal processing of the semiconductor substrate, to form a PMOS transistor.
  • the method for forming the ultra-shallow junction structure in the PMOS transistor is similar to the embodiment described above with respect to Figs. 2-6.
  • steps S203 through S205 generally correspond to steps SI 02 through SI 04, respectively.
  • the description of the method for forming a PMOS in accordance with the second embodiment does not repeat the description of the previously described steps for forming an ultra-shallow junction, but assumes previous performance of those steps.
  • the method for forming the PMOS transistor of the present embodiment may start with an ultra-shallow junction structure similar to the ultra-shallow junction structure in Fig. 6.
  • sidewall spacers 106 are formed on both sides of the gate structure formed of the gate dielectric layer 102 and the gate electrode 103.
  • the method for forming the sidewall spacers 106 may include: forming a dielectric layer (not shown) on the semiconductor substrate 101 and etching back the dielectric layer.
  • the dielectric layer (not shown) may be formed by Low Pressure Chemical Vapor Deposition (LPCVD).
  • LPCVD Low Pressure Chemical Vapor Deposition
  • the dielectric layer may have a thickness greater than the height of the gate electrode 103, for facilitating the etch back.
  • the dielectric layer may be silicon oxide, or have an Oxide-Nitride-Oxide (ONO) structure.
  • the sidewall spacers 106 may be used for protecting the gate electrode 103.
  • a source 111 and a drain 112 are formed by implanting ions into the source region and the drain region using the gate structure as a mask.
  • the implanted ions are P-type, e.g., boron or arsenic ions.
  • the implantation may be performed at a dose having an order of magnitude in the range of 10 14 -10 15 /cm 2 , and an energy in the range of 10-100 keV.
  • thermal processing would be performed on the semiconductor substrate to complete forming the PMOS transistor.
  • the thermal processing may include performing spike annealing of the semiconductor substrate structure.
  • the spike annealing may activate dopant ions, and recover crystal structure of the semiconductor substrate damaged due to ion implantation.
  • the spike annealing may include: heating the semiconductor substrate to a certain temperature; maintaining the temperature for a period of time; rapidly increasing the temperature; and immediately cooling down when a peak temperature is reached.
  • Key parameters of the spike annealing include the peak temperature of a temperature curve, dwell time of the peak temperature, and temperature divergence (i.e., time of the annealing temperature maintained near to the peak temperature).
  • the peak temperature of spike annealing may range from 1000 to 1100 0 C.

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A method for forming an ultra-shallow junction includes implanting first ions into a semiconductor substrate(101), to form a first implantation region(104); implanting second ions into the first implantation region(104) to amorphize the first implantation region(104); and implanting third ions into the amorphized first implantation region, to form an ultra-shallow junction structure.

Description

Ultra-shallow junction and method for forming the same
Technology Field
[0001] The present disclosure relates to the field of semiconductor technology and, more particularly, to an ultra-shallow junction and a method for forming the same and a PMOS transistor.
Background of the Disclosure
[0002] Ion implantation is an impurity doping technique widely used in forming a variety of semiconductor devices and integrated circuits. The amount of ions implanted by an ion beam into a semiconductor substrate and their distribution can be accurately adjusted by controlling the current and voltage of the ion beam.
[0003] Feature size of semiconductor devices becomes smaller as the technology advances. Vertical size of a device (i.e., depth of the device) needs to be reduced as horizontal size (i.e., linewidth represented by the feature size) of the device shrinks. Consistent with this need, ion implementation is used to form shallow junctions or ultra-shallow junctions, e.g., a lightly-doped source region or a lightly-doped drain region of a Metal-Oxide-Semiconductor (MOS) transistor.
[0004] Threshold voltage of a MOS transistor is a parameter that reflects performance of the MOS transistor. The threshold voltage of the MOS transistor may be improved by enhancing substrate bias effect, also known as body effect.
[0005] The substrate bias effect can be provided for a PMOS transistor, if its substrate and its source are reverse biased (i.e., a negative voltage is applied to the P substrate) such that a depletion region in the substrate becomes thicker, causing an increase in fixed electric charges in the depletion layer. The increase of the electric charges in the depletion layer leads to a reduction of mobile electric charges in the channel, for a balance requirement of charges on both sides of a gate capacitance. Therefore, the reduction of mobile electric charges in the channel results in degraded electric conductivity. Improvement of gate voltage may increase the electric charges on the gate, thus maintaining electric conductivity level. For a device, the threshold voltage of the PMOS transistor is increased by substrate bias.
[0006] The body effect may be characterized using a body effect parameter γ . A higher body effect γ parameter represents a greater body effect and a higher threshold voltage. The body effect parameter γ may be determined by the following equation:
Figure imgf000003_0001
[0007] wherein 0 is vacuum permittivity, ^ is a quantity of elementary charges, is an ion doping concentration in the channel region, and Cox [s a capacitance per unit of area of the gate dielectric layer.
[0008] The body effect parameter γ may be improved by increasing the ion doping concentration in the channel region.
[0009] may be increased by increasing the distance between the source and the drain. When the distance between the source and the drain increases, impurity diffusion in the source and the drain can be better controlled, such that the amount of electric charges in the depletion layer is reduced, thereby increasing ^a and improving the body effect.
[0010] The body effect can also be improved by thickening sidewall spacers. However, this may reduce the saturation drain current, affecting other electric parameters of the MOS device.
Summary of the Disclosure
[0011] In accordance with the present disclosure, there is provided a method for forming an ultra-shallow junction. The method includes:
implanting first ions into a semiconductor substrate, to form a first implantation region;
implanting second ions into the first implantation region, to amorphize the first implantation region; and
implanting third ions into the amorphized first implantation region, to form an ultra-shallow junction structure.
[0012] In accordance with the present disclosure, there is also provided a method for forming a PMOS transistor. The method includes:
forming a gate structure on a semiconductor substrate, wherein a source region and a drain region are defined in the substrate on opposite sides of the gate structure;
implanting first ions into the source region and the drain region by using the gate structure as a mask, to form a first implantation region;
implanting second ions into the first implantation region by using the gate structure as a mask, to amorphize the first implantation region; and
implanting third ions into the amorphized first implantation region by using the gate structure as a mask, to form an ultra-shallow junction structure. [0013] In accordance with the present disclosure, there is also provided an ultra-shallow junction. The ultra-shallow junction includes:
a semiconductor substrate; and
a junction structure in the substrate, the junction structure including a first ion implantation region including an amorphized structure; and
second ions implanted into the amorphized structure.
[0014] In accordance with the present disclosure, there is also provided a method for manufacturing a PMOS transistor. The method includes:
implanting first ions into a source region and a drain region of a substrate;
implanting second ions into regions of the first ion implanting region; and implanting third ions into regions of the second ion implanting.
[0015] Features and advantages consistent with the present disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present disclosure. Such features and advantages will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
Brief Description of the Drawings
[0016] Fig. 1 illustrates a flow chart of a method for forming an ultra-shallow junction structure according to an embodiment;
[0017] Fig. 2 to Fig. 6 illustrate cross-sectional views of a method for forming an ultra-shallow junction structure according to an embodiment;
[0018] Fig. 7 illustrates a flow chart of a method for forming a PMOS transistor according to an embodiment;
[0019] Fig. 8 and Fig. 9 illustrate cross-sectional views of a method for forming a PMOS transistor according to an embodiment.
Detailed Description of the Embodiments
[0020] Technical details are described below for the person skilled in the art to understand the disclosure. However, the present disclosure may be implemented in a variety of ways other than those described herein, and various modifications may be made without departing from the scope of the present disclosure. Therefore, the disclosure is not limited to the embodiments described herein. [0021] A method disclosed herein of forming an ultra-shallow junction may include implantation of boron fluoride ions before amorphization of a substrate. The method takes advantage of easier diffusion of fluoride ions in, for example, a crystalline silicon than in amorphous silicon. Silicon-oxygen bonds in a gate dielectric layer on a surface of the substrate may be more easily broken by the fluoride ions. Oxygen ions separated from the broken silicon-oxygen bonds may oxidize the substrate silicon near the gate dielectric layer, which increases thickness of the gate dielectric layer.
[0022] As reviously described, the equation defines the body effect parameter:
Figure imgf000006_0001
[0023] An increase in the thickness of the gate dielectric layer will lead to a reduction of Cox ^ [ Q -s the capacitance per unit area of the gate dielectric layer. Therefore, the body effect, and thus the threshold voltage, can be improved by increasing the thickness of the gate dielectric layer.
[0024] Moreover, as boron fluoride ions are heavier than boron ions, they may block subsequent boron ions from diffusing, so as to control horizontal diffusion of boron. Such limiting of horizontal diffusion may further improve the body effect, and thus the threshold voltage.
[0025] Fig. 1 illustrates a flow chart of a method for forming an ultra-shallow junction structure according to an embodiment of the present disclosure. The method includes:
[0026] Step S 101 : providing a semiconductor substrate;
[0027] Step SI 02: implanting first ions into the semiconductor substrate, to form a first implantation region;
[0028] Step SI 03: implanting second ions into the first implantation region, to amorphize the first implantation region;
[0029] Step SI 04: implanting third ions into the amorphized first implantation region, to form an ultra-shallow junction structure.
[0030] Fig. 2 to Fig. 6 are schematic cross-sectional views of a device in various stages of the method for forming an ultra-shallow junction structure according to an embodiment of the disclosure. The present embodiment is described with an example by which a Lightly Doped Drain (LDD) of a PMOS transistor is formed as an ultra-shallow junction structure.
[0031] As shown in Fig. 2, a semiconductor substrate 101 is provided. The semiconductor substrate 101 may be monocrystalline silicon or silicon-germanium, or Silicon On Insulator (SOI). Alternatively, the semiconductor substrate 101 may include other materials such as III- V compound semiconductors, e.g., gallium arsenide.
[0032] An N-type well and a channel region (not shown) are formed in the semiconductor substrate 101. An isolation structure (not shown) may also be formed in the semiconductor substrate 101. Such an isolation structure may be, for example, a LOCOS region formed by local oxidation, or a shallow trench isolation structure.
[0033] As shown in Fig. 3, a gate dielectric layer 102 is formed on a surface of the semiconductor substrate 101. The gate dielectric layer 102 may be silicon oxide, silicon nitride or a High-k dielectric material. The gate dielectric layer 102 may have a thickness ranging from tens of Angstroms to hundreds of Angstroms. The gate dielectric layer 102 may be formed by, for example, thermal oxidation, Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or Plasma Enhanced Chemical Vapor Deposition (PECVD).
[0034] Referring to Fig. 3, a gate electrode layer 103 is formed over the gate dielectric layer 102. The gate electrode layer 103 may be polycrystalline silicon, having a thickness ranging from hundreds of Angstroms to thousands of Angstroms. The gate electrode layer 103 may be formed by Low Pressure Chemical Vapor Deposition (LPCVD).
[0035] Next, the gate dielectric layer 102 and the gate electrode layer 103 are patterned using a resist mask, to form a gate structure. The gate structure includes the gate dielectric layer 102 and the gate electrode layer 103. The region of the substrate 101 on opposite sides of and separated by the gate structure are referred to herein as a source region and a drain region of the semiconductor substrate 101.
[0036] As shown in Fig. 4, a first implantation 105 is performed to implant first ions into the source region and the drain region using the gate structure as a mask. The first implantation may be performed with an accelerating energy ranging from 10 Kev to 30
Kev and a dose ranging from lE15/cm 2 to 3E15/cm 2. A first implantation region 104 is formed by the first implantation. In one embodiment, the first ions may be boron fluoride ions.
[0037] As shown in Fig. 5, a second implantation 106 is performed to implant second ions into the first implantation region 104 using the gate structure as a mask. The second implantation may be performed with an accelerating energy ranging from 30
Kev to 60 Kev and a dose ranging from lE15/cm 2 to 9E15/cm 2 , so as to amorphize the first implantation region 104. The second ions may be tetravalent ions. In one embodiment, the second ions may be silicon or germanium.
[0038] The second implantation is performed to cause amorphization in the first implantation region, so that crystal structures in the first implantation region may be disordered, which may limit diffusion of subsequent-implanted ions.
[0039] As an example, the amorphization may be performed using silicon ions with an energy of 40 Kev and a dose of 9E15/cm .
[0040] Next, as shown in Fig. 6, a third implantation 107 is performed to implant third ions into the amorphized first implantation region 104 using the gate structure as a mask. The third implantation may be performed with an accelerating energy ranging from 5 Kev to 12 Kev and a dose ranging from lE13/cm2 to lE14/cm2. The third ions may be boron ions. As a result, an ultra-shallow junction structure is formed.
[0041] As an example of the third implantation 107, the energy of boron ions may be 10 Kev, and the dose may be 5.0E13/cm .
[0042] As shown in Fig. 7, a method is provided according to an embodiment for forming a PMOS transistor. The method includes:
[0043] Step S201 : providing a semiconductor substrate;
[0044] Step S202: forming a gate structure on the semiconductor substrate, which defines a source region and a drain region of the substrate separated by the gate structure and on respective sides thereof;
[0045] Step S203: performing a first implantation to implant first ions into the source region and the drain region by using the gate structure as a mask, to form a first implantation region;
[0046] Step S204: performing a second implantation to implant second ions into the first implantation region by using the gate structure as a mask, to amorphize the first implantation region;
[0047] Step S205: performing a third implantation to implant third ions into the amorphized first implantation region by using the gate structure as a mask, thereby forming an ultra-shallow junction structure;
[0048] Step S206: forming sidewall spacers on both sides of the gate structure;
[0049] Step S207: heavily-doping the source region and the drain region, to form a source and a drain;
[0050] Step S208: performing thermal processing of the semiconductor substrate, to form a PMOS transistor.
[0051] The method for forming the ultra-shallow junction structure in the PMOS transistor is similar to the embodiment described above with respect to Figs. 2-6. For example, steps S203 through S205 generally correspond to steps SI 02 through SI 04, respectively. Accordingly, the description of the method for forming a PMOS in accordance with the second embodiment does not repeat the description of the previously described steps for forming an ultra-shallow junction, but assumes previous performance of those steps. Accordingly, the method for forming the PMOS transistor of the present embodiment may start with an ultra-shallow junction structure similar to the ultra-shallow junction structure in Fig. 6.
[0052] As shown in Fig. 8, sidewall spacers 106 are formed on both sides of the gate structure formed of the gate dielectric layer 102 and the gate electrode 103. The method for forming the sidewall spacers 106 may include: forming a dielectric layer (not shown) on the semiconductor substrate 101 and etching back the dielectric layer. The dielectric layer (not shown) may be formed by Low Pressure Chemical Vapor Deposition (LPCVD). The dielectric layer may have a thickness greater than the height of the gate electrode 103, for facilitating the etch back. The dielectric layer may be silicon oxide, or have an Oxide-Nitride-Oxide (ONO) structure. The sidewall spacers 106 may be used for protecting the gate electrode 103.
[0053] As shown in Fig. 9, a source 111 and a drain 112 are formed by implanting ions into the source region and the drain region using the gate structure as a mask. In one embodiment, the implanted ions are P-type, e.g., boron or arsenic ions. The implantation may be performed at a dose having an order of magnitude in the range of 1014-1015/cm2, and an energy in the range of 10-100 keV.
[0054] After the implantation in Fig. 9, thermal processing would be performed on the semiconductor substrate to complete forming the PMOS transistor.
[0055] The thermal processing may include performing spike annealing of the semiconductor substrate structure. The spike annealing may activate dopant ions, and recover crystal structure of the semiconductor substrate damaged due to ion implantation. The spike annealing may include: heating the semiconductor substrate to a certain temperature; maintaining the temperature for a period of time; rapidly increasing the temperature; and immediately cooling down when a peak temperature is reached. Key parameters of the spike annealing include the peak temperature of a temperature curve, dwell time of the peak temperature, and temperature divergence (i.e., time of the annealing temperature maintained near to the peak temperature). In one embodiment, the peak temperature of spike annealing may range from 1000 to 1100 0 C.
[0056] Tests have shown that with the method according to the present disclosure, the body effect parameter of the PMOS transistor can be doubled, thereby doubling the threshold voltage of the PMOS transistor.
[0057] Embodiments described above are not to limit the scope of the invention. Those skilled in the art may use the methods and technical disclosure described herein to make various alternations and modifications to the disclosure without departing from the spirit and scope of the invention. Therefore, any simple modifications, equivalents or adjustments to the embodiments above based on the technical essence of the disclosure and without departing from the technical solution of the present disclosure should be considered to be included in the scope of the invention.

Claims

1. A method for forming an ultra-shallow junction, comprising:
implanting first ions into a semiconductor substrate, to form a first implantation region;
implanting second ions into the first implantation region to amorphize the first implantation region; and
implanting third ions into the amorphized first implantation region, to form an ultra-shallow junction structure.
2. The method according to claim 1, wherein the implanting the first ions comprises implanting boron fluoride ions.
3. The method according to claim 1, wherein the implanting the first ions comprises implanting the first ions with energy in a range from 10 Kev to 30 Kev, and a dose in a range from lE15/cm2 to 3E15/cm2.
4. The method according to claim 1, wherein the implanting the second ions comprises implanting tetravalent ions.
5. The method according to claim 1, wherein the implanting the second ions comprises implanting the second ions with energy in a range from 30 Kev to 60 Kev, and a dose in a range from lE15/cm 2 to 9E15/cm 2.
6. The method according to claim 1, wherein the implanting the third ions comprises implanting boron ions.
7. The method to claim 1, wherein the implanting the third ions comprises implanting the third ions with energy in a range from 0.5 Kev to 12 Kev, and a dose in a range from lE13/cm2 to lE14/cm2.
8. A method for forming a PMOS transistor, comprising:
forming a gate structure on a semiconductor substrate, wherein a source region and a drain region are defined in the substrate on opposite sides of the gate structure;
implanting first ions into the source region and the drain region by using the gate structure as a mask, to form a first implantation region;
implanting second ions into the first implantation region by using the gate structure as a mask, to amorphize the first implantation region; and
implanting third ions into the amorphized first implantation region by using the gate structure as a mask, to form an ultra-shallow junction structure.
9. The method according to claim 8, wherein the implanting the first ions comprises implanting boron fluoride ions.
10. The method according to claim 8, wherein the implanting the first ions comprises implanting the first ions with energy in a range from 10 Kev to 30 Kev, and a dose in a range from lE15/cm 2 to 3E15/cm 2.
11. The method according to claim 8, wherein the implanting the second ions comprises implanting tetravalent ions.
12. The method according to claim 8, wherein the implanting the second ions comprises implanting the second ions with energy in a range from 30 Kev to 60 Kev, and a dose in a range from lE15/cm 2 to 9E15/cm 2.
13. The method according to claim 8, wherein the implanting the third ions comprises implanting boron ions.
14. The method according to claim 8, wherein the implanting the third ions comprises implanting the third ions with energy in a range from 0.5 Kev to 12 Kev, and a dose in a range from lE13/cm2 to lE14/cm2.
15. An ultra-shallow junction, comprising:
a semiconductor substrate; and
a junction structure in the substrate, the junction structure including afirst ion implantation region including an amorphized structure; and second ions implanted into the amorphized structure.
16. The ultra-shallow junction according to claim 15, further comprising third ions implanted to form the amorphized structure into the first implantation region.
17. A method for manufacturing a PMOS transistor, comprising:
implanting first ions into a source region and a drain region of a substrate ;
implanting second ions into regions of the first ion implanting; and
implanting third ions into regions of the second ion implanting.
18. The method according to claim 17, wherein the implanting second ions includes implanting tetravalent ions.
19. The method according to claim 17, further comprising:
forming a gate structure on the substrate, wherein
the source region and the drain region are formed in the substrate on opposite sides of the gate structure;
wherein the implanting the second ions includes amorphizing the first ion implanted regions; and
wherein the implanting the third ions includes implanting the third ions into the amorphized first ion implanted regions.
PCT/CN2010/079240 2009-12-01 2010-11-29 Ultra-shallow junction and method for forming the same Ceased WO2011066786A1 (en)

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CN106328505B (en) * 2015-07-01 2019-07-30 中芯国际集成电路制造(上海)有限公司 Method of forming a semiconductor structure
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