WO2011064786A1

WO2011064786A1 - Adaptive biasing of driver circuit

Info

Publication number: WO2011064786A1
Application number: PCT/IN2009/000692
Authority: WO
Inventors: Raja Prabhu J.; Ankit Seedher; Shyam Somayajula S.
Original assignee: St-Ericsson India Pvt.Ltd.; St-Ericsson Sa
Priority date: 2009-11-30
Filing date: 2009-11-30
Publication date: 2011-06-03

Abstract

Methods and systems for adaptive biasing of a driver circuit (102) are described. A driver circuit (102) comprises a pull-up and a pull-down stack. The pull-up and pull-down stack includes at least one pull-up transistor (210) and at least one pull-down transistor (212), respectively. The pull-up and the pull-down transistor (210, 212) are each coupled in series to a plurality of cascode transistors. An output (114) of the driver circuit (102) is compared to at least one reference voltage. Based on the comparing, a gate-bias voltage of at least one of the cascode transistors is changed.

Description

ADAPTIVE BIASING OF DRIVER CIRCUIT

TECHNICAL FIELD

[0001] The subject matter described herein, relates, in general, to a driver circuit and, in particular, to adaptive biasing of an output stage of the driver circuit.

BACKGROUND

[0002] Currently available electronic systems include one or more driver circuits. A driver circuit is generally used to drive or operate another circuit or a load. Such a driver circuit includes an amplifier and other electronic circuit elements. Examples of amplifiers include class-A, class-B, class-AB, class C, class-D, etc. Typically, the class-D amplifiers are used in a large number of applications because of their high power efficiency and low power dissipation. The class-D amplifiers provide a digital switching output, and are preferred for high voltage audio applications.

[0003] Conventional amplifiers include semi-conducting devices such as Metal-

Oxide Semiconductor (MOS) transistors. These transistors, such as NMOS and PMOS, can be implemented through fabrication on an integrated circuit (IC) chip. Presently, a large number of such semi-conducting devices are fabricated on the same IC chip. Furthermore, major portions or functional sub-blocks of the IC chip operate on a lower supply voltage (for example, with respect to Vbat). This necessitates scaling down the size of the semiconducting devices for better performance, for example, with respect to area, power, etc. In such transistors, application of high voltage across drain-to-source of the semi-conducting devices may lead to Hot-Carrier-Injection (HCI). Also, a high voltage across gate-to-drain and gate-to-source may cause the semi-conducting devices to loose Gate-Oxide-Integrity (GOI). More specifically, HCI and GOI become prominent for the class-D amplifiers, in the high voltage audio applications.

[0004] Increasing the size features of the semi-conducting devices might solve the above problem, but it is undesirable. Furthermore, presently existing techniques involve application using limited gate-to-source bias voltage to avoid GOI, and the use of cascode semi-conducting device in series to prevent HCI stresses on the semi-conducting devices. Such techniques still cause HCI stresses on the cascoded semi-conducting device, leading to its degradation.

SUMMARY

[0005] The subject matter described herein is directed towards an electronic circuit configured to provide adaptive biasing to a driver circuit. The driver circuit comprises a pull-up and a pull-down stack. The pull-up and pull-down stack includes a pull-up and a pull-down transistor each coupled to a plurality of cascode transistors, respectively. An output of the driver circuit is compared to reference voltages to generate a switching signal. Based on the switching signal, a gate-bias voltage of at least one of the cascode transistors in the driver circuit is changed to a set of pre-determined fixed bias voltages.

[0006] These and other features, aspects, and advantages of the present subject matter will be better understood with reference to the following description and appended claims. This summary is provided to introduce a selection of concepts. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used for to limiting the scope of the claimed subject matter.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the drawings to reference like features and components.

[0008] FIG. 1 illustrates an exemplary system for adaptive biasing of a driver circuit, in accordance with an embodiment of the present subject matter.

[0009] FIG. 2 illustrates an exemplary driver circuit present in the exemplary system for adaptive biasing of the exemplary driver circuit, in accordance with an embodiment of the present subject matter.

[0010] FIG. 3 illustrates an exemplary implementation of a stack of three pulldown transistors, in accordance with an embodiment of the present subject matter.

[0011] FIG. 4 illustrates an exemplary implementation of a stack of three pull-up transistors, in accordance with an embodiment of the present subject matter. [0012] FIG. 5 illustrates an exemplary method for adaptive biasing of the driver circuit, in accordance with an embodiment of the present subject matter.

DETAILED DESCRIPTION

[0013] Systems and methods for adaptive biasing of a driver circuit are described. A driver circuit is an electrical circuit that generates an output based on an input for driving or running another electrical circuit. Such driver circuits can be utilized in a number of conventional applications, such as in audio systems. For example, in audio systems, the driver circuits are used for driving load elements, such as a speaker.

[0014] In present day systems, the driver circuit is implemented using semiconductor-based transistors. Some of the most common uses of the transistors include amplification and switching of electrical signals. Examples of transistors include, but are not limited to, NMOS transistors, PMOS transistors, BJTs, etc. Typically, transistors have at least three terminals through which they cormect to other devices. During operation of such a transistor, a current injected into one tenninal or voltage applied across two terminals controls the current in the other two terminals or voltage generated across the other two terminals of the transistor under appropriate bias conditions. For the NMOS and PMOS transistors, voltage between the gate terminal and the source terminal controls the drain current and the voltage generated across the source terminal and drain terminal under appropriate bias conditions. A minimum voltage level (referred to as threshold voltage Vj) is required between the gate terrninal and the source terminal of the transistor for it to start conducting. The transistors are generally made from alternating layers of an n-type and a p-type semi-conducting material resulting in p-n junctions that may act as diodes. These junctions can be arranged to form either an n-p-n or a p-n-p layer. Applying a diode voltage, i.e., V_dio_de, is required to conduct across the p-n junction diodes.

[0015] As mentioned previously, the transistors can be used in driver circuits. An example of such a driver circuit includes a class-D amplifier. The transistors in the class-D amplifiers function in a switching mode. Therefore, the transistors are in an on-state or in an off-state, at any given instant of time, thereby generating a digital switching signal based on an input signal. The digital switching signal may be understood to be a binary signal having a high and a low voltage level. The class-D amplifiers have high power efficiency and low heat dissipation. Due to such advantages, the class-D amplifiers are widely used for a variety of applications such as in audio systems, etc. It should be noted that most of these applications involve dealing with high voltages.

[0016] As mentioned, the transistors in the class-D amplifiers function in the switching mode. For this purpose, the class-D amplifiers generally includes PMOS and NMOS transistors in series, with the PMOS transistors providing a high voltage level output, and the NMOS transistors providing a low voltage level output. These levels are provided by a power supply (V_DD) and ground voltage rails of an output stage of the class- D amplifier through the appropriate conduction of the PMOS and NMOS transistors. To ensure that the power supply and the ground voltage are never shorted, a certain non- overlap time interval is introduced between the on-state of NMOS and PMOS transistors. ^' This non-overlap time interval is also referred to as a dead-time interval. The class-D amplifiers, as mentioned previously, can be used for driving loads, such as speakers, that are inductive in nature. As a consequence, during the dead time interval, depending on the average output current direction, the output of the driver circuit will go to (VDD + dMe) or - diode because of the conduction of the parasitic PN diodes associated with the PMOS or NMOS transistors, respectively.

[0017] As mentioned previously, the class-D amplifiers can be used for high voltage applications. The driver circuit when used for high voltage applications result in the transistors being subjected to Hot-Carrier-Injection (HCI) and Gate-Oxide-Integrity (GOI) stresses. Hot Carrier Injection (or HCI) generally occurs when the voltage across the drain terminal and the source terminal is more than a maximum stress voltage VD, for a given device process technology. This results in the degradation of the transistor and negatively affects performance.

[0018] Stress related to HCI occurs when the charge carriers in the transistors, such as electrons and holes for NMOS and PMOS respectively, under large channel electric field due to large voltage between drain and source terminals, gain sufficient kinetic energy. In the presence of the vertical gate electric field, these excited charge carriers get embedded into the gate-oxide layer resulting in improper functioning of the transistors, such as an increase in the threshold voltage V_T, increase in the on-resistance of the devices, etc. Such continued effects result in the degradation of the MOSFETs. For the class-D amplifiers that are being used to drive inductive loads at a high-voltage, HCI stresses generally appear in the output stage transistors during the dead-time interval.

[0019] Furthermore, in some cases, during operation of the driver circuit, a high voltage may be applied across the gate-oxide layer in the MOSFETs, for example across the gate terminal and the source terminal or the gate terminal and the drain terminal of the transistor. During normal operation of the MOSFETs, the path between the gate-oxide layers is non-conducting. However, application of a high voltage creates a conducting path between the gate-oxide layers. This phenomenon results in Gate-Oxide Stress or GOI stress across the gate-oxide layers causing breakdown of the gate-oxide of the MOSFETs, leading to its failure.

[0020] In order to operate optimally in high voltage ranges, amplifiers and therefore, the transistors should be better resistant to the effects of HCI and GOI. Conventional systems tend to solve this problem using processes, such as high voltage device process technology, which are expensive and less effective against the effect of HCI and GOI.

[0021] To overcome the challenges as identified above, the present subject matter describes systems and methods for implementing adaptive biasing of the transistors. The adaptive biasing results in the transistors being resistant to effects such as HCI and GOI stresses. To implement the adaptive biasing of the transistors, an output signal obtained in the output stage of the driver circuit, such as a class-D amplifier, is compared to one or more reference voltages. Furthermore, a voltage being applied at the gate terminal of the transistors in the driver circuit is changed to a set of pre-determined fixed bias voltages based on the comparison. This prevents any high voltages from inducing HCI and GOI stresses in the transistors. In one implementation, the voltage is changed to a selected voltage from the set of pre-determined fixed bias voltages, whenever the output signal of the output stage is found to be high enough to induce HCI and GOI related stresses in the transistors. By changing the voltage applied at the gate terminal to the selected voltage from the set of pre-determined fixed bias voltages, the transistors in the driver circuit avoid HCI and GOI stresses at all times during operation making the driver circuits functional in a wider voltage range.

[0022] While aspects of described systems and methods for the adaptive biasing of the driver circuit can be implemented in any number of different environments, and/or configurations, the embodiments are described in the context of the following exemplary circuit configurations. The descriptions and details of well-known components are omitted for simplicity of the description. Although the devices are explained herein as certain N- channel and P-channel devices, it can be appreciated that complementary devices are also possible in accordance with the present subject matter. It will be appreciated by those skilled in the art that the words during, while, and when as used herein are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as a propagation delay, between the reaction that is initiated by the initial action.

EXEMPLARY SYSTEMS

[0023] Fig. 1 illustrates a system 100 for adaptive biasing of a driver circuit, as per one embodiment of the present subject matter. The working of the system 100 is described in detail in conjunction with Fig. 2. Fig. 2 provides an example of the driver circuit in the form of the class-D amplifier. It will be appreciated by a person skilled in the art that the driver circuit as depicted in Fig. 2 is only for illustration and that the same driver circuit can, in another implementation, be realized in ways known in the art. It should in no way be construed as a limitation of the present subject matter.

[0024] Returning to Fig. 1, the system 100 includes a driver circuit 102, a comparison circuit 104, a reference voltage generator 106, a biasing circuit, for example a level shifter circuit 108, and a fixed bias circuit or a switcher circuit 110. The fixed bias circuit or a switcher circuit 110 will be hereby referred to as the fixed bias circuit 110. As can be seen from Fig. 1, each of the above mentioned components are operably connected to each other. As mentioned previously, driver circuits, such as the driver circuit 102, can be used in electronic circuits for driving or operating other electrical component (not shown in Fig. 1). The driver circuit 102 receives an input signal 1 12 to provide an output signal 1 14. In one implementation, the input signal 112 is an analog signal.

[0025] In one implementation, the driver circuit 102 is based on a class-D amplifier, as is shown in Fig. 2. Conventional class-D amplifiers perform signal processing in two stages namely, an input stage and an output stage. The input stage receives an input signal, say the input signal 112, and converts it into a input stage signal. The output stage receives the input stage signal generated in the input stage and generates a high voltage level output, such as the power supply voltage V_DD₅ or the low voltage level output, such as the ground voltage, of the output stage of the class-D amplifier. An example of the output generated is the output signal 114. For example, the signal processing in the input stage can be performed by an input stage circuitry 202, and the signal processing in the output stage can be performed by an output stage circuitry 204. During operation the input stage circuitry 202 receives the input signal 112, and converts the input signal 1 12 to the input stage signal, such as an input stage signal 206. In one implementation, the input stage signal 206 is a differential switching signal. It would be appreciated that the input stage circuitry 202 can be realized by methods that are conventionally known.

[0026] The input stage signal 206 generated is sent to the output stage circuitry 204 for further processing. The output stage circuitry 204 generates a high power output digital signal based on the input stage signal 206 received from the input stage circuitry 202. In one implementation, two non-overlapping signals are generated based on the input stage signal 206 for generating the high voltage level output. For example, this may be implemented by using a non-overlapping circuitry.

[0027] The output stage circuitry 204 of the class-D amplifier, as shown in Fig. 2, comprises a transistor stack 208. The transistor stack 208 further includes a pull-up stack of transistors and a pull-down stack of transistors, both of which are coupled in series. The pull-up stack of transistors takes the output of the output stage circuitry 204 to a supply voltage, such as the power supply voltage VDD- Similarly, the pull-down stack of transistors takes the output of the output stage circuitry 204 to a ground voltage. In one implementation, the pull-up stack of transistors includes PMOS transistors and the pulldown stack of transistors includes NMOS transistors. In another implementation, the output stage circuitry 204 includes a pair of the transistor stack 208 for receiving the input stage signal 206 in a differential mode.

[0028] The pull-up stack of transistors also includes a pull-up transistor 210 coupled in series to at least two pull-up cascode transistors such as a pull-up cascode transistor 214-1 and a pull-up cascode transistor 214-2. Similarly, the pull-down stack of transistors includes a pull-down transistor 212 coupled in series to at least two pull-down cascode transistors such as a pull-down cascode transistor 216-1 and a pull-down cascode transistor 216-2. It should be understood that the pull-up and the pull-down cascode transistors can also be referred to as the cascode transistors. The pull-up transistor 210 and the pull-down transistor 212 receive the input stage signal 206 from the input stage circuitry 202 at their respective gate-terminals. Based on the received input stage signal 206, the transistor stack 208 generates the output signal 114 at terminal 218.

[0029] Returning to Fig. 1, the output signal 114 of the driver circuit 102 is provided to the comparison circuit 104. The comparison circuit 104 compares the output signal 114 to reference voltages 116. In one implementation, the reference voltages 116 are generated by the reference voltage generator 106. In one implementation, the reference voltages 116 includes two voltage values, one each for the pull-up and the pull-down stack of transistors. The comparison circuit 104 then compares the output signal 114, received from the driver circuit 102, with the reference voltages 116 to generate a switching signal 118. It will be noted that the switching signal 118 obtained from the comparison circuit 104 differs for the NMOS and the PMOS transistors. Furthermore, the switching signal 118 produced by the comparison circuit 104 refers to signals that correspond both to the pull-up and the pull-down stack of transistors of the driver circuit 102. These are explained in greater detail in conjunction with Fig. 3 and 4.

[0030] In one implementation, the switching signal 118 associated with the NMOS and the PMOS transistors are clipped based on the reference voltages 116 provided by the reference voltage generator 106. [0031] The switching signal 1 18 is fed to a level shifter circuit 108. The level shifter circuit 108 generates a level shifted signal 120 and changes a bias voltage 122 of the driver circuit 102 being provided by the fixed bias circuit 1 10. In one implementation, the bias voltage 122 is the gate terminal voltage of at least one of the plurality of transistors in the driver circuit 102. For example, gate terminal voltage of the pull-up cascode transistor 214-1 and the pull-down cascode transistor 216-1 is changed so that the drain to source terminal voltage remains below the maximum stress voltage V_D for all the transistors thereby avoiding HCI and GOI stresses. As mentioned previously, the driver circuit 102 includes one or more transistors. The fixed bias circuit 110, therefore, provides the bias voltage 122 to one or more of the transistors in the driver circuit 102. For example, the gate-terminal of the pull-up cascode transistor 214-2 and the pull-down cascode transistor 216-2 is provided with the bias voltage 122. It should be noted that the bias voltage 122 supplied may be different for the pull-up and the pull-down cascode transistors.

[0032] Fig. 3 illustrates an exemplary implementation of the present subject matter for a stack of three pull-down transistors. As mentioned previously, the stack of pull-down transistors can include the pull-down transistor 212 and two or more pull-down cascode transistors such as the pull-down cascode transistor 216-1 and the pull-down cascode transistor 216-2. In one implementation, the stack of pull-down transistors includes two pull-down cascode transistors.

[0033] As mentioned previously, the pull-down transistor 212 receives the input stage signal 206 at its gate terminal, while the pull-down cascode transistor 216-2 receives the bias voltage 122 at its gate terminal. In the description for the present implementation, as illustrated in Fig. 3, the bias voltage 122 supplied to the gate terminal of the pull-down cascode transistor 216-2 is (VD+VT). It will be appreciated that any other appropriate value for the fixed gate terminal voltage can also be provided.

[0034] The comparison circuit 104 includes a clipping circuit 302 coupled in series with an inverter circuit 304. In one implementation, the clipping circuit 302 has at least two input terminals. The output signal 114 from the driver circuit 102 is fed back to one of the input terminals of the clipping circuit 302. On the other terminal of the clipping circuit 302 a reference clipping voltage Vi is provided. The clipping circuit 302 limits the output signal 114 based on the reference clipping voltage Vi to generate a clipped signal 316. The generated clipped signal 316 is a clipped version of the output signal 114, but with a lower limit, Vi. For example, during operation, when the output signal 1 14 varies between 0 to (VDD + _dio_de), the output signal 1 14 is clipped by the clipping circuit 302 to generate the clipped signal 316 that varies between Vj to (VDD + V_di_0de)(if is greater than zero volts), hi one implementation, the clipping circuit 302 further includes a pair of transistors 308 and 310. The back gate connections for the PMOS clipping transistors as depicted in Fig. 3 are for reliable high- voltage clipping operation.

[0035] The clipped signal 316 is further provided to the inverter circuit 304. The inverter circuit 304 includes inverters 312 and 314 operated at an upper and a lower limiting voltage. For example, the upper limiting voltage can be set to VDD while the lower limiting voltage can be set to the reference clipping voltage Vi of the clipping circuit 302. The inverter circuit 304 generates a pull-down switching signal, such as the switching signal 118, based on a pull-down reference voltage and the clipped signal 316. The switching signal 118 generated by the inverter circuit 304 is either equal to the upper or the lower limiting voltage. The pull-down reference voltage is based on the upper and the lower limiting voltage. In one implementation, the pull-down reference voltage can be a switching threshold voltage of the inverter 312.

[0036] The pull-down switching signal, such as the switching signal 118, generated by the inverter circuit 304 is provided to the level shifter circuit 108. The level shifter circuit 108, based on the pull-down switching signal such as the switching signal 118, changes the gate-terminal voltage of the cascode pull-down transistor 216-1. More specifically, the inverter circuit 304 generates the pull-down switching signal such as the switching signal 118 changing from Vi to VDD- The level shifter circuit 108, based on the pull-down switching signal such as the switching signal 118, changes the gate terminal voltage of the cascode pull-down transistor 216-1 from the fixed gate terminal voltage (VD+VT) supplied to the gate terminal of the pull-down cascode transistor 216-2 to the supply voltage VDD- It will be appreciated that any other appropriate reference voltage other than VDD can also be used for biasing the pull-down cascode transistor 216-1 based on the requirement.

[0037] FIG. 4 illustrates an exemplary implementation of the present subject matter for a stack of three pull-up transistors. As mentioned previously, the stack of pull-up transistors includes the pull-up transistor 210 and two or more pull-up cascode transistors such as the pull-up cascode transistor 214-1 and the pull-up cascode transistor 214-2.

[0038] As mentioned previously, the pull-up transistor 210 receives the input stage signal 206 at its gate terminal, while the pull-up cascode transistor 214-2 receives a fixed gate terminal voltage, such as the bias voltage 122, at the gate terminal. For this particular implementation, the fixed gate terminal voltage supplied to the gate terminal of the pull-up cascode transistor 214-2 is (VDD-VD-V_T). It will be appreciated that any other appropriate value for the fixed gate terminal voltage can also be provided.

[0039] The comparison circuit 104 includes a clipping circuit 402 coupled in series with an inverter circuit 404. In one implementation, the clipping circuit 402 has at least two input terminals. The output signal 114 from the driver circuit 102 is fed back to one of the input terminals of the clipping circuit 402. On the other terminal of the clipping circuit 402 a reference clipping voltage V₂ is provided. As mentioned previously, the clipping circuit 402 limits the output signal 114 based on the reference clipping voltage V₂ to generate a clipped signal 416. The generated clipped signal 416 is a clipped version of the output signal 114, with an upper limit of V₂. For example, during operation, when the output signal 114 varies between -Vdiode and VDD, the output signal 114 is clipped by the clipping circuit 402 to generate the clipped signal 416 that varies between -Vdiode and V₂ (assuming V₂ is less than VD_D)

[0040] In one implementation, the clipping circuit 402 further includes a pair of transistors 408 and 410. As an example, the pair of transistors 408 and 410 shown are NMOS transistors. The back gate connections for the pair of transistors 408 and 410, as depicted in Fig.4, provide for reliable high- voltage application.

[0041] The clipped signal 416 is further provided to the inverter circuit 404. The inverter circuit 404 includes inverters 412 and 414 operated at an upper and a lower limiting voltage. For example, the upper limiting voltage can be set to V₂, while the lower limiting voltage is set to zero volts. The inverter circuit 404 generates a pull-up switching signal, such as the switching signal 118, based on a pull-up reference voltage and the clipped signal 416. The pull-up switching signal such as the switching signal 118 generated by the inverter circuit 404 is either equal to the upper or the lower limiting voltage. The pull-up reference voltage is based on the upper and the lower limiting voltage. In one implementation, the pull-up reference voltage can be a switching threshold voltage of the inverter 412.

[0042] The pull-up switching signal such as the switching signal 118 generated by the inverter circuit 404 is provided to the level shifter circuit 108. The level shifter circuit 108, based on the pull-up switching signal such as the switching signal 118, changes the gate-terminal voltage of the pull-up cascode transistor 214-1. For example, the inverter circuit 404 generates the pull-up switching signal such as the switching signal 118 changing from 0 to V₂. The level shifter circuit 108, based on the pull-up switching signal the switching signal 118, changes the gate terminal voltage of the pull-up cascode transistor 214-1 from the fixed gate terminal voltage (V_DD- V_D -V_T) supplied to the gate terminal of the pull-up cascode transistor 214-2 to zero volts. It will be appreciated that any other appropriate reference voltage other than ground voltage can also be used for biasing the pull-up cascode transistor 214-1, based on the requirement.

[0043] Although Fig. 1 shows only a single comparison circuit 104, it may, however, be understood by persons skilled in the art that separate implementations of the comparison circuit 104, each for the pull-up and the pull-down stack of transistors as shown in Fig. 3 and Fig.4, are also covered.

[0044] Fig. 5 describes an exemplary method 500 for adaptive biasing of the driver circuit. Fig. 5 is described in reference to Fig. 1-4. The exemplary method may be described in general context of electrical circuits.

[0045] The order in which the method is described is not intended to be construed as a limitation, and any number of the described method blocks can be combined in any order to implement the method, or an alternative method. Additionally, individual blocks may be deleted from the method without departing f om the spirit and scope of the subject matter described herein.

[0046] At block 502, an output voltage, for example obtained from the output stage of the class-D amplifier, is clipped based on reference voltage ranges. For example, the output signal 114 is clipped by the clipping circuit 302 below the reference clipping voltage V_\ to generate the clipped output 316, and the output signal 114 is clipped by the clipping circuit 402 above the reference clipping voltage V₂ to generate the clipped output 416.

[0047] At block 504, the output voltage clipped above the reference clipping voltage, is compared to a pull-up reference voltage to generate a pull-up switching signal. In an implementation, the output signal 114 is clipped above the reference clipping voltage V₂ to generate the clipped output 416. The clipped output 416 is compared with the pull-up reference voltage 116 to generate the pull-up switching signal such as the switching signal 118. In one implementation, the clipped signal 416 is further provided to the inverter circuit 404 within the comparison circuit 104. The inverter circuit 404 generates the pull- up switching signal such as the switching signal 118 changing from 0 to V₂.

[0048] At block 506, the pull-up switching signal is received and the gate terminal voltage of the pull-up cascode transistor is changed to the set of pre-deterrnined fixed-bias voltages. In an implementation, the gate terminal voltage of the pull-up cascode transistor 214-1 is changed by the level shifter circuit 108 based on the pull-up switching signal such as the switching signal 118. For example, the level shifter circuit 108, based on the pull-up switching signal such as the switching signal 118, changes the gate terminal voltage of the pull-up cascode transistor 214-1 from the fixed gate terminal voltage (V_DD- V_D -V_T) supplied to the gate terminal of the pull-up cascode transistor 214-2 to zero volts.

[0049] At block 508, the output voltage clipped below the reference clipping voltage is compared to a pull-down reference voltage to generate a pull-down switching signal. In an implementation, the output signal 114 is clipped below the reference clipping voltage i to generate the clipped signal 316. The clipped signal 316 is compared with the pull-down reference voltage 116 to generate the pull-down switching signal such as the switching signal 118. In one implementation, clipped signal 316 is further provided to the inverter circuit 304. Furthermore, the inverter circuit 304 generates the pull-down switching signal such as the switching signal 118 changing from Vi to V_DD.

[0050] At block 510, the pull-down switching signal is received and the gate terminal voltage of the pull-down cascode transistor is changed to the set of predetermined fixed bias voltages. In an implementation, the gate terminal voltage of the pulldown cascode transistor 216-1 is changed by the level shifter circuit 108 based on the pulldown switching signal such as the switching signal 118. For example, the level shifter circuit 108, based on the pull-down switching signal such as the switching signal 118, changes the gate terminal voltage of the pull-down cascode transistor 216-1 from the fixed gate terminal voltage (V_D+VT) supplied to the gate terminal of the pull-down cascode transistor 216-2 to the supply voltage V_DD.

CONCLUSION

[0051] Although implementations for adaptive biasing of the driver circuit, have been described in language specific to structural features and/or methods, it is to be understood that the subject of the appended claims is not necessarily limited to the specific features or methods described. Rather, the specific features and methods are disclosed as exemplary implementations.

Claims

I/We Claim:

1. A system comprising:

a driver circuit (102) comprising a pull-up stack and a pull-down stack, wherein the pull-up stack and the pull-down stack include at least one pull-up transistor (210) and at least one pull-down transistor (212) respectively, and wherein each of the pull-up transistor (210) and the pull-down transistor (212) is coupled to a plurality of cascode transistors;

a comparison circuit (104) configured to receive an output (114) from the driver circuit (102) and compare the output (114) with at least one reference voltage (116); and

a biasing circuit configured to change a gate terminal voltage of at least one of the plurality of cascode transistors based at least in part on the comparison of the output (114) with the at least one reference voltage (116).

2. The system as claimed in claim 1, wherein the comparison circuit (104) comprises a clipping circuit configured to clip the output (114) to a value, based on at least two reference clipping voltages.

3. The system as claimed in claim 2, wherein the clipping circuit (302) is configured to clip, for the pull-down stack, the output (114) below greatest of the at least two reference clipping voltages.

4. The system as claimed in claim 2, wherein the clipping circuit (402) is configured to clip, for the pull-up stack, the output (114) above smallest of the at least two reference clipping voltages.

5. The system as claimed in claim 1, wherein the comparison circuit (104) comprises an inverter circuit configured to limit the output (114) to a switching signal based on the at least one reference voltage (116).

6. The system as claimed in claim 5, wherein the inverter circuit (304) is configured to limit the output (114) for the pull-down stack to a pull-down switching signal based on a pull-down reference voltage.

7. The system as claimed in claim 5, wherein the inverter circuit (404) is configured to limit the output (114) for the pull-up stack to a pull-up switching signal based on a pull-up reference voltage.

8. The system as claimed in claim 5, wherein the inverter circuit comprises at least two inverters coupled in series.

9. The system as claimed in claim 1, wherein the biasing circuit comprises a level shifter circuit (108) configured to change the gate terminal voltage of the at least one of the plurality of cascode transistors based on the comparison with the at least one reference voltage (116).

10. A method comprising:

comparing an output voltage from a driver circuit (102) with at least one reference voltage, wherein the driver circuit (102) comprises a pull-up stack and a pull-down stack, and wherein the pull-up stack includes a pull-up transistor (210) and a plurality of pull-up cascode transistors (214) coupled in series, and wherein the pull-down stack includes a pull-down transistor (212) and a plurality of pulldown cascode transistors (216) coupled in series; and

changing, based on the comparing, a gate terminal voltage of at least one of the plurality of cascode transistors to at least one fixed bias voltage corresponding to the at least one reference voltage.

11. The method of claim 10, wherein the comparing further comprises clipping the output voltage from the driver circuit (102) for the pull-down stack below a reference clipping voltage.

12. The method of claim 10, wherein the comparing further comprises clipping the output voltage from the driver circuit (102) for the pull-up stack above a reference clipping voltage.

13. A method for biasing a driver circuit ( 102), the method comprising:

comparing an output voltage from a driver circuit (102) to a pull-up reference voltage, wherein the driver circuit (102) comprises a pull-up stack and a pull-down stack, and wherein the pull-up stack includes a pull-up transistor (210) and a plurality of pull-up cascode transistors (214) coupled in series, and wherein the pull-down stack includes a pull-down transistor (212) and a plurality of pulldown cascode transistors (216) coupled in series;

changing, based on the comparing to the pull-up reference voltage, a gate terminal voltage of at least one of the plurality of pull-up cascode transistors to a voltage from a set of first fixed bias voltages;

comparing the output voltage from the driver circuit (102) to a pull-down reference voltage; and

changing, based on the comparing to the pull-down reference voltage, the gate terminal voltage of at least one of the plurality of pull-down cascode transistors to a voltage from a set of second fixed bias voltages.

14. The method of claim 13, wherein the comparing further comprises:

clipping the output voltage from the driver circuit (102) to a comparison range; and

comparing the output voltage from the driver circuit (102) to the at least one reference voltage.

15. The method of claim 14, wherein the clipping further comprises clipping the output voltage from the driver circuit (102) above a reference clipping voltage for the pull- up stack.

16. The method of claim 14, wherein the clipping further comprises clipping the output voltage from the driver circuit (102) below a reference clipping voltage for the pulldown stack.

17. The method of claim 13, wherein changing the gate terminal voltage of the at least one of the plurality of pull-up cascode transistors comprises level-shifting of an output generated based on the comparing to the pull-up reference voltage.

18. The method of claim 13, wherein changing the gate terminal voltage of the at least one of the plurality of pull-down cascode transistors comprises level-shifting of an output generated based on the comparing to the pull-down reference voltage.