WO2011061296A1 - Method for producing stacks on a plurality of levels of silicon chip assemblies - Google Patents

Method for producing stacks on a plurality of levels of silicon chip assemblies Download PDF

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Publication number
WO2011061296A1
WO2011061296A1 PCT/EP2010/067843 EP2010067843W WO2011061296A1 WO 2011061296 A1 WO2011061296 A1 WO 2011061296A1 EP 2010067843 W EP2010067843 W EP 2010067843W WO 2011061296 A1 WO2011061296 A1 WO 2011061296A1
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chips
plurality
plate
method
chip
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PCT/EP2010/067843
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French (fr)
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Laurent Clavelier
Barbara Charlet
Cioccio Léa Di
Thomas Signamarcheix
Marc Zussy
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Commissariat à l'énergie atomique et aux énergies alternatives
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Abstract

The invention relates to a microelectronic device provided with at least one given level comprising a plurality of chips (C1,…,Cn) stacked on another plurality of chips (C' 1,…, C' n) of a lower level; the method includes steps of: producing a first plurality of chips on a first plate (100), electrically testing the chips (C1,…, Cn) of the first plurality of chips so as to locate one or more defective chip(s) (C2) on the first plate, attaching a temporary substrate (101-102) to the first plurality of chips, separating the chips from one another by forming trenches (120) around the chips, which pass through the first plate and expose the temporary substrate, removing said defective chip(s), assembling the first plurality of chips to a second plurality of chips (C' 1,…, C' n) resting on a second plate (200).

Description

METHOD FOR PRODUCING STACKS ON MANY LEVELS OF ELECTRONIC CHIP SETS

DESCRIPTION

TECHNICAL AREA

The invention relates to the field of microelectronics and more particularly that of the production of devices having chips or integrated circuits supporting stacks.

It brings improvements in performance against commonly known type of process "wafer to wafer" (plate to plate) and in terms of speed of implementation vis-à-vis the type commonly known processes "chip to wafer "(chip on board).

PRIOR ART

It is known to carry a stack commonly called "3D stacking" of multiple integrated circuits or more chips.

For this one can, according to a commonly known method "W2W" (for wafer to wafer), superposing a plurality of plates (wafer according to anlo terminology) of several chips or circuits integrated (s) that have been formed (s) at the same time on the same support, the plates then being optionally cut.

Such a method is problematic in terms of performance of functional circuits. Called efficiency of a plate, the ratio of number of considered functional chips on the plate and the total number of chips of the plate.

When stacking N plates having an individual performance Yi, a device is obtained whose total yield Y is Y = Yi = Yi = ox ix Yi = 2 x ··· x

A stack of two plates each having a 80% yield and a total yield of 64%.

When seeking to stack more than 2 chips, the total yield drops rapidly and may be too low.

The result, which is generally rather chose to implement a postponement chip on a wafer, once they have been extracted by cutting another wafer, tested and sorted.

This other method, commonly called "C2W" (for "chip to wafer") has the drawback of being longer to implement than the W2W method to achieve as many chips stacks.

For stacking chips of 1 cm 2 on a plate of 200 mm and producing a stack of chips 300 on the surface of a plate, the method may have a total length which may be for example of the order of several hours.

There arises the problem of finding a new method of making a device comprising a plurality of stacked chips. STATEMENT OF INVENTION

The invention relates to a method for making a microelectronic device provided with at least one level having a plurality of chips stacked on another plurality of chips at a lower level.

The method comprises steps of:

- providing a first plate having a first plurality of chips,

- functional test of the chips of the first plurality of chips in order to locate one or more die (s) defective (s) of the first plate and to identify functional chips,

- fixing on the first plurality of chips of a temporary support,

- separation of the chips to each other by forming trenches around the chip, the trench extending through the first plate fleas being held by the temporary support,

- assembly of functional chips of the first plurality of chips with a second plurality of chips based on a second plate.

Defective chips by means of chips that do not meet one or more predetermined criteria, such as appearance, and / or electrical operation, and / or surface quality.

In contrast, the functional chips are those which correspond to the (x) test (s) predetermined (s). Advantageously, the defective chips are removed prior to assembly of functional chips.

After assembly, opposite at least one data chip of the second plurality of chips include at least one free slot left following removal of a defective chip, the method may further comprise,

- removing the temporary support,

- another assembly of another chip opposite said given chip.

The other chip can be obtained by:

- providing a plurality of chips on a plate,

- fixing chips on a temporary support,

- separation of the chips to each other by cutting the temporary support and said plate.

The temporary support may be attached to the first plurality of chips via a bonding layer.

Prior to said separating step, a step of thinning the first wafer may have been performed.

Alternatively, the defective chips can undergo a treatment to make them compatible with subsequent assembly, for example with chips placed opposite. This can be achieved for example by etching to bring the defective chips indented one assembly plane with another medium or by a suitable surface treatment makes the surface of the defective chips incompatible with bonding implemented in a subsequent assembly with another medium.

According to one possibility, the method may further comprise, prior to said separation step or said setting step:

- the realization of conductive elements extending through the first plate and in contact with the chips of the first plurality of chips,

- carrying out a first plurality of conductive pads on the first plate connected to the conductive elements respectively.

Connecting elements for example of such vias (through conductive elements) and / or pads (conductive pads) may also be performed after removal of the temporary support.

During assembly of the first plurality of chips with the second plurality of chips, the first plurality of conductive pads of conductive pads can be brought into contact with a second plurality of conductive pads flea respectively connected to conductive pads the second plurality of chips.

The other conductive pads and said conductive pads can still be assembled by molecular bonding called "direct bonding", such as a copper-copper bonding.

The method may further comprise after said assembling step of: delaying a third plurality of chips on the first plurality of chips. The process may be repeated several times. Prior to said transfer, it is possible a third plurality of conductive pads on the chips of the first plurality of chips connected to said conductive members respectively, the chips of the third plurality of chips being carried on the conductive pads of the third plurality of conductive pads .

BRIEF DESCRIPTION OF DRAWINGS

The present invention will be better understood on reading the description of example embodiments given purely for illustrative and non limitative, with reference to the accompanying drawings in which:

- Figures 1A-1K illustrate an exemplary method according to the invention for producing a microelectronic device comprising at least one plurality of superimposed chips to another plurality of chips.

Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the passage from one figure to another.

The different parts shown in the figures are not necessarily to a uniform scale, to make the figures more legible.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

An example of process according to the invention will now be given in connection with Figures 1A-1K. The method starting material may be a semiconductor Wl plate (English "wafer") on which a plurality of integrated circuits or chips Cl, ..., Cn have been achieved (s) (Figure 1A).

The chips or integrated circuits are for example memories (flash, DRAM, SRAM ...), or processor cores, or CMOS circuits, or imaging, or micro electromechanical systems (MEMS) or micro-optical systems (MOEMS).

We firstly sends a functionality test, for example an electric test, of each of the chips of the plate in order to locate optionally, one or more defective chips.

We carried out a bonding of the plate Wl to a temporary support 102 by means of a bonding layer 101 located, for example, on the temporary substrate 102. The bonding layer 101 covers the chips Cl, ..., Cn.

This bonding layer can be, for example, resin-based or wax.

The temporary substrate 102 may be formed of at least one rigid layer, for example based on a semiconductor material such as Si (Figure 1B).

One can then produce a thinning of the rear face of the plate Wl, that is to say the opposite side to that on which the circuits or chips Cl, ..., Cn have been formed (s).

This thinning may be achieved for example by grinding and / or lapping and / or dry etching. A thinning technique fracture at a buried fragile zone created for example by implantation of gaseous species can also be implemented.

Can then form conductive members 110 passing through the plate Wl.

These conductor elements 110 commonly known as TSV elements (TSV for 'Through Silicon Via ") may be made by forming holes through the plate Wl and chips Cl, ..., Cn, and then filling the holes with a metallic material such as for example copper.

Prior to filling metallic material, a step of forming an insulating contour on the hole walls and eventually on the tapered surface, can be performed to electrically isolate the conductive elements of the plate.

The conductive elements 110 TSV can thus pass through the plate and integrated circuits Cl, ..., Cn (Figure le). The conductive elements 110 TSV may be in contact with the integrated circuits of the connections on the front panel.

Then we can form pads 112 conductors (commonly referred to as "pads") on the rear panel, for example based on copper, in contact with the conductive elements 110 TSV.

The pads 112 can be insulated from each other with a layer of dielectric material 115 (Figure 1C).

This is followed by separation of chips Ci, ..., C n, to form around the latter, trenches 120 through Wi plate and exposing the bonding layer 101. This separation can be effected for example by sawing and / or by etching and / or cutting with a laser (Figure 1D).

Can then cash out any defective chips, using for example a map established previously during the functional test step and to a location of valid chips and one or more defective chips.

Alternatively, the defective chips can undergo a treatment to make them incompatible with the assembly which follows, for example etching to the indent of the assembly plane or a processing area adapted making the surface of the incompatible defective chips with the type of adhesive used.

In the example shown in Figure 1E is removed the chip C 2 that has been identified as defective.

The withdrawal can be done for example through a type of equipment commonly known as "pick and place" with the mapping done previously, for example using a heating head to make the removal easier.

Then carried out an assembly Wi plate with another plate W 2 having a plurality of chips or integrated circuits C'i, ..., C 'n and covered with insulated conductive pads 212 to each other by an insulating layer 215 , for example based on S1O 2 (Figure 1F). This assembly may be accomplished by direct bonding of the pads 112 of the plate Wl on the pads 212 of the other plate W2 (Figure 1G).

Bonding by molecular adhesion (without the addition of adhesive) may be implemented. If the pads 112 and 212 are made from copper, bonding can be achieved copper-copper type as described in the article "Direct Copper Bonding, Characterization and Its interests for 3D Integration" Gueguen et al. Journal of The Electrochemical Society, 156 _10_ H772- H776 _2009.

To perform molecular bonding, an activation of the surface of the pads may have been previously performed, for example using smoothing processing by polishing and / or chemical cleaning and / or plasma treatment.

One can for example be carried out before the step of cutting a chemical mechanical polishing surface and then activating the surface after plasma cutting, based on He / ¾ for example.

Then sends a removal of the temporary support 102 and the bonding layer 101, for example by flow of the bonding layer? for example through an external thermal and / or initiation of a lateral frictional movement. It may alternatively proceed by lapping.

It is also possible to produce the conductive elements 110 through TSV at this stage of the process. Depending on the number of defective chips that have been detected and removed beforehand Wl of the first plate, one or more locations Ei may have been left free on the latter.

In the example shown in Figure 1H, E2 a location corresponding to the area where the defective chip C2 was, is left free.

At this location, at least one contact pad 212 is exposed.

One can then carry out a bonding of a chip c "2 at the location left free E2.

This bonding may be implemented after carrying out an activation of the surface of the contact pad 212.

The or bonded chips (s) to the free slots can be from the same type of structure as that described above in connection with Figure 1D, but in which one has performed a complete separation of the chips, so that the trenches have been formed (s) through the bonding layer 101 and the support 102 temporarily.

In the example shown in Figure II, the chip C '2, which sticks to the free space E2, is itself joined to a portion of temporary support 102. It then sends a withdrawal of said portion of temporary support 102 and the bonding layer 101 (Figure 1J).

Then carried out (Figure 1K) depositing an electrically insulating layer 315, for example based on S1O 2, which can then planarizing polishing by mechanical lapping and / or CMP ( "Chemical Mechanical Polishing" chemical mechanical polishing) and / or chemical etching (wet or dry).

Then, openings are formed in the insulating layer 315 opposite the chips C 'i, ..., C'n which is filled with metallic material, for example copper, to form contact pads 312.

The structure thus produced can then serve as a support for receiving one or more other levels of stacking chips, repeating certain steps of the method which has just been described.

We can thus make a connection on both sides of the WI layer to facilitate 3D integration.

In such a process carried all chips are functional.

The manufacturing efficiency is improved compared to the process W2W. In terms of implementation speed, this process is also faster to implement than C2W type of process, in which the chips one by one we should stick together on a chip.

For some applications, such as flash drives, it can be provided to stack up to 16 chip levels.

Claims

1. A method of making a microelectronic device provided with at least one level having a first plurality of chips (Ci, ..., C n) stacked on a second plurality of chips (C 'i, C' n) a lower level, the method comprising the steps of:
- providing a first plurality of chips (Ci, ..., C n) on a first plate (Wi),
- test chips (Ci, ..., C n) of the first plurality of chips in order to locate one or more die (s) defective (s) (C 2) on the first plate,
- fixing on the first plurality of chips of a temporary support (102),
- separation of the chips to each other by forming trenches (120) around the chip, the trench extending through the first plate (Wi), the chips are still held by the temporary support,
- assembly of the first plurality of chips with the second plurality of chips (c 1 ', c' n) based on a second plate (W 2) of a first plurality of conductive pads of conductive pads being assembled by gluing molecular adhesion, for example of copper-copper bonding, with conductive pads (212) of a second plurality of conductive pads respectively connected to the chips of the second plurality of chips,
- withdrawal of the temporary support (102), - depositing an electrically insulating layer (315), on assembly of the first plurality of chips with the second plurality of chips, and forming, in said layer, of a third plurality of conductive pads (312) next to chips of the first plurality of chips,
this method further comprising, prior to said separation step or said setting step:
- the realization of first conductive elements (110) extending through the first plate (WI) and in contact with the chips (Cl, ..., Cn) of the first plurality of chips,
- carrying out a first plurality of conductive pads (115) on the first plate connected to the first conductive elements, respectively.
2. The method of claim 1, further comprising between said partition and said assembly: the removal of the or said (s) chip (s) defective (s).
3. The method of claim 2, wherein, after assembly, compared to at least one data chip (C'2) from the second plurality of chips include at least one open slot (E 2) left after the withdrawal of a defective chip (C 2) during said step of removing, the method further comprising, after removing the temporary support, another assembly, in said free space (E 2), another chip (C'2) next to said given chip of the second plurality of chips.
4. The method of claim 3, said other chip (C'2) having been obtained by:
- providing a plurality of chips on a plate,
- fixing chips on a temporary support,
- separation of the chips to each other by cutting the temporary support and said plate.
5. A method according to one of claims 1 to 4, the support (102) being temporarily fixed (101) to the first plurality of chips via a bonding layer (101).
6. A method according to one of claims 1 to 5, further comprising, prior to said separation step, a step of thinning the first wafer (WI).
7. A method according to one of claims 1 to 6, further comprising after said step of assembling: postponing a third plurality of chips on the first plurality of chips.
8. The method of claim 7, wherein the chips of the third plurality of chips are transferred to the conductive pads of the third plurality of conductive pads (312).
PCT/EP2010/067843 2009-11-20 2010-11-19 Method for producing stacks on a plurality of levels of silicon chip assemblies WO2011061296A1 (en)

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