WO2011061296A1 - Method for producing stacks on a plurality of levels of silicon chip assemblies - Google Patents

Method for producing stacks on a plurality of levels of silicon chip assemblies Download PDF

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Publication number
WO2011061296A1
WO2011061296A1 PCT/EP2010/067843 EP2010067843W WO2011061296A1 WO 2011061296 A1 WO2011061296 A1 WO 2011061296A1 EP 2010067843 W EP2010067843 W EP 2010067843W WO 2011061296 A1 WO2011061296 A1 WO 2011061296A1
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WIPO (PCT)
Prior art keywords
chips
plurality
plate
chip
conductive pads
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PCT/EP2010/067843
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French (fr)
Inventor
Laurent Clavelier
Barbara Charlet
Léa Di Cioccio
Thomas Signamarcheix
Marc Zussy
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Commissariat à l'énergie atomique et aux énergies alternatives
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Publication date
Priority to FR0958234 priority Critical
Priority to FR0958234A priority patent/FR2953065A1/en
Application filed by Commissariat à l'énergie atomique et aux énergies alternatives filed Critical Commissariat à l'énergie atomique et aux énergies alternatives
Publication of WO2011061296A1 publication Critical patent/WO2011061296A1/en

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Abstract

The invention relates to a microelectronic device provided with at least one given level comprising a plurality of chips (C1,…,Cn) stacked on another plurality of chips (C' 1,…, C' n) of a lower level; the method includes steps of: producing a first plurality of chips on a first plate (100), electrically testing the chips (C1,…, Cn) of the first plurality of chips so as to locate one or more defective chip(s) (C2) on the first plate, attaching a temporary substrate (101-102) to the first plurality of chips, separating the chips from one another by forming trenches (120) around the chips, which pass through the first plate and expose the temporary substrate, removing said defective chip(s), assembling the first plurality of chips to a second plurality of chips (C' 1,…, C' n) resting on a second plate (200).

Description

 METHOD FOR MAKING STACKS ON MULTIPLE LEVELS OF ELECTRONIC CHIP ASSEMBLIES

DESCRIPTION

TECHNICAL AREA

The invention relates to the field of microelectronics and more particularly to the production of devices comprising chip support stacks or integrated circuits.

 It brings improvements in terms of efficiency compared to processes of the type commonly called "wafer to wafer" and in terms of speed of implementation vis-à-vis the type of process commonly called "chip to wafer" "(Chip on plate).

PRIOR ART

It is known to make a stack commonly known as "stacking 3D", several integrated circuits or several chips.

 For this purpose, it is possible, according to a method commonly known as "W2W" (for wafer to wafer), to superpose several plates (wafer according to the terminology) of several chips or integrated circuits (e) s that have been formed (e) s at the same time on the same support, the plates being then optionally cut.

Such a method poses a problem in terms of performance of the functional circuits. The yield of a plate is the ratio between the number of chips considered functional on this plate and the total number of chips of this plate.

 When stacking N plates with an individual yield of Yi, we obtain a device whose total efficiency Y is Y = Yi = o x Yi = i x Yi = 2 x ··· x

A stack of two plates each having a yield of 80%, gives a total yield of 64%.

 When stacking more than 2 chips, the total yield drops quickly and may be too low.

 As a result, we generally choose to implement a transfer of chips on a wafer, once they were extracted by cutting another wafer, tested and sorted.

 This other method, commonly known as "C2W" (for "chip to wafer") has the disadvantage of being longer to implement than the W2W method to achieve as many chip stacks.

To stack 1 cm 2 chips on a 200 mm plate and to carry out a stack of 300 chips on the surface of a plate, the method can have a total duration that can be for example of the order of several hours.

There is the problem of finding a new method for producing a device comprising a plurality of stacked chips. STATEMENT OF THE INVENTION

The invention relates to a method for producing a microelectronic device having at least one level comprising a plurality of chips stacked on another plurality of chips of a lower level.

 The method comprises steps of:

provide a first plate comprising a first plurality of chips,

 functional test of the chips of the first plurality of chips in order to locate one or more defective chips on the first plate and to identify the functional chips,

 fixing on the first plurality of chips a temporary support,

 separation of the chips from one another by trench formation around the chips, the trenches passing through the first plate, the chips being held by the temporary support,

 assembling the functional chips of the first plurality of chips with a second plurality of chips resting on a second plate.

 Faulty chips are chips that do not meet one or more predetermined criteria, for example appearance, and / or electrical operation, and / or surface quality.

In contrast, the functional chips are those that meet the predetermined criterion (s). Advantageously, the defective chips are removed before assembly of the functional chips.

 After assembly, facing at least one given chip of the second plurality of chips is at least one free slot left following the removal of a defective chip, the method may further comprise,

 - the withdrawal of the temporary support,

 another assembly of another chip opposite said given chip.

 The other chip may have been obtained by:

- Realization of a plurality of chips on a plate,

 - fixing the chips on a temporary support,

 - Chip separation between them by cutting the temporary support and said plate.

 The temporary medium can be attached to the first plurality of chips via a bonding layer.

 Prior to said separation step, a thinning step of the first plate may have been performed.

Alternatively, the defective chips may undergo processing to make them incompatible with a subsequent assembly, for example with bullets placed next. This can be achieved for example by etching to put the defective chips back from an assembly plane with another support or by a suitable surface treatment making the defective chip surface incompatible with a bonding implemented during a subsequent assembly with another support.

 According to one possibility, the method may further comprise, prior to said separation step or said fixing step:

 the production of conducting elements crossing the first plate and in contact with the chips of the first plurality of chips,

 - Realizing a first plurality of conductive pads on the first plate respectively connected to the conductive elements.

 Connection elements for example vias type (conductive elements through) and / or pads (conductive pads) can also be made after removal of the temporary support.

 When assembling the first plurality of chips with the second plurality of chips, the conductive pads of the first plurality of conductive pads may be brought into contact with conductive pads of a second plurality of conductive pads connected respectively to the chip chips. the second plurality of chips.

 The conductive pads and said other conductive pads can be assembled by molecular bonding bonding also called "direct bonding", such as a copper-copper bonding.

The method may further comprise, after said assembly step: the transfer of a third plurality of chips to the first plurality of chips. The process can be repeated several times. Prior to said report, it is possible to make a third plurality of conductive pads on the chips of the first plurality of chips respectively connected to said conductive elements, the chips of the third plurality of chips being transferred to the conductive pads of the third plurality of conductive pads. .

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be better understood on reading the description of exemplary embodiments given, purely by way of indication and in no way limiting, with reference to the appended drawings in which:

 - Figures 1A-1K illustrate an example of the method according to the invention for producing a microelectronic device comprising at least a plurality of chips superimposed on another plurality of chips.

 Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the passage from one figure to another.

 The different parts shown in the figures are not necessarily in a uniform scale, to make the figures more readable.

DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS

An example of a method according to the invention will now be given in conjunction with FIGS. 1A-1K. The starting material of the process may be a wafer plate W1 on which a plurality of integrated circuits or chips C1,..., Cn have been made (FIG. 1A).

 The chips or integrated circuits can be for example memories (flash, DRAM, SRAM, ...), or cores of processors, or CMOS type circuits, or imagers, or electromechanical micro-systems (MEMS), or optical micro-systems (MOEMS).

 First of all, a functionality test, for example an electrical test, of each of the chips of the plate is carried out in order to possibly locate one or more defective chips.

 The plate W1 is then bonded to a temporary support 102 by means of a bonding layer 101 located, for example, on the temporary support 102. The bonding layer 101 covers the chips C1,. Cn.

 This bonding layer may be, for example, based on resin or wax.

 The temporary support 102 may be formed of at least one rigid layer for example based on a semiconductor material such as Si (FIG. 1B).

 One can then perform a thinning of the rear face of the plate W1, that is to say the face opposite to that on which circuits or chips Cl, ..., Cn were formed (e) s.

This thinning can be achieved for example by grinding and / or lapping and / or dry etching. A thinning technique by fracture at a buried fragile zone created for example by implantation of gaseous species can also be implemented.

 Conductive elements 110 passing through plate W1 can then be formed.

 These conductive elements 110 commonly called TSV elements (TSV for "Through Silicon Via") can be made by forming holes through the W1 plate and the chips Cl, ..., Cn, then filling the holes using a metallic material such as for example copper.

 Prior to the filling of metallic material, a step of forming an insulating contour on the walls of the holes and possibly on the thinned surface may be carried out in order to electrically insulate the conductive elements of the plate.

 The conductive elements 110 TSV can thus pass through the plate and the integrated circuits C1,..., Cn (FIG. The conductive elements 110 TSV may be in contact with connections of the integrated circuits located on the front face.

 Then, one can form pads 112 (commonly called "pads") on the rear face, for example based on copper, in contact with the conductive elements 110 TSV.

 The pads 112 may be isolated from each other by means of a layer of dielectric material 115 (FIG. 1C).

Chips Ci,..., C n are then separated by forming around trenches 120 crossing the plate Wi and unveiling the bonding layer 101. This separation can be performed for example by sawing and / or etching and / or cutting with a laser (Figure 1D).

 It is then possible to remove any defective chips, for example using a mapping previously established during the functional test step and allowing a location of the valid chips and one or more defective chips.

 Alternatively, the defective chips may undergo processing to make them incompatible with the assembly that will follow, for example an etching to set them back from the assembly plane or a suitable surface treatment making the surface of faulty chips incompatible with the type of collage implemented.

In the example shown in FIG. 1E, the chip C 2 which has been identified as defective is removed.

 The withdrawal can be carried out for example by means of a type of equipment commonly called "pick and place" having the mapping previously performed, for example using a heating head to make disassembly easier.

Then, an assembly of the plate Wi is carried out with another plate W 2 comprising a plurality of chips or integrated circuits C'i, ..., C ' n and covered with conductive pads 212 insulated from each other by an insulating layer 215 , for example based on S10 2 (FIG. 1F). This assembly can be achieved by direct bonding of the pads 112 of the plate W1 on the pads 212 of the other plate W2 (Figure 1G).

 Bonding by molecular adhesion (without glue) can be implemented. In the case where the pads 112 and 212 are copper-based, the bonding may be of the copper-copper type as described in the article "Copper Direct-Bonding Characterization and its Interests for 3D Integration" Gueguen et al., Journal of the Electrochemical Society, 156 _10_H772- H776 _2009.

 To perform a molecular bonding, activation of the surface of the pads may have been previously performed, for example using polishing smoothing treatment and / or chemical cleaning and / or plasma treatment.

 For example, it is possible, before the cutting step, to perform a chemical-mechanical surface polishing and then to activate the surface after plasma cutting, based on He / ¾ for example.

 The temporary support 102 and the bonding layer 101 are then removed, for example by creep of the bonding layer. for example by external thermal stress and / or the initiation of a lateral friction movement. It can alternatively proceed by running-in.

It is also possible to make conducting elements crossing 110 TSV at this stage of the process. Depending on the number of defective chips that have been detected and removed before the first plate W1, one or more locations Ei may have been left free on the latter.

 In the example shown in Figure 1H, a location E2 corresponding to the area where the faulty chip C2 was, is left free.

 At this location, at least one contact pad 212 is unveiled.

It is then possible to glue a chip c " 2 to the location E2 left free.

 This bonding can be implemented after activating the surface of the contact pad 212.

 The chip (s) bonded to the free locations may be from the same type of structure as that described previously in connection with FIG. 1D, but in which a complete separation of the chips has been carried out, so that trenches have been made. (s) through the bonding layer 101 and the temporary support 102.

In the example shown in FIG. II, the chip C ' 2 , which is glued to the free slot E2, is itself assembled to a temporary support portion 102. A withdrawal of said portion of temporary support 102 and the bonding layer 101 (FIG. 1J).

Next, (FIG. 1K) a deposit of an electrically insulating layer 315, for example based on SiO 2 , which can then be made flat by polishing mechanical lapping and / or CMP (CMP for "Chemical Mechanical Polishing" and / or chemical etching (wet or dry).

 Then, openings are formed in the insulating layer 315 facing chips C 'i, ..., C'n that is filled with metal material, for example copper, to form contact pads 312.

 The structure thus produced can then serve as a support for receiving one or more other levels of stacking chips, by repeating certain steps of the method just described.

 It is thus possible to make a connection on both sides of the W1 layer to facilitate 3D integration.

 In such a method all reported chips are functional.

 The manufacturing efficiency is thus improved compared to the W2W process. In terms of speed of implementation, this method is also faster to implement than a method of C2W type, in which one chip should be glued one by one on a set of chips.

 For some applications such as flash drives, it can be expected to stack up to 16 levels of chips.

Claims

A method of producing a microelectronic device having at least a given level comprising a first plurality of chips (Ci, ..., C n ) stacked on a second plurality of chips (C ' i, c ' n ) of a lower level, the method comprising steps of:
supplying a first plurality of chips (Ci, ..., C n ) on a first plate (Wi),
chip test (Ci, ..., C n ) of the first plurality of chips in order to locate one or more defective chips (C 2 ) on the first plate,
 fixing on the first plurality of chips of a temporary support (102),
 separating the chips from one another by forming trenches (120) around the chips, the trenches crossing the first plate (Wi), the chips being still held by the temporary support,
- assembling the first plurality of chips with the second plurality of chips (c ' 1, c ' n) resting on a second plate (W 2 ), conductive pads of a first plurality of conductive pads being assembled, by bonding by molecular adhesion, for example of the copper-copper bonding type, with conductive pads (212) of a second plurality of conductive pads respectively connected to the chips of the second plurality of chips,
a withdrawal of the temporary support (102), a deposition of an electrically insulating layer (315), on the assembly of the first plurality of chips with the second plurality of chips, and forming, in that layer, a third plurality of conductive pads (312) facing chips of the first plurality of chips,
 this method further comprising, prior to said separation step or said fixing step:
 - Realizing first conductive elements (110) passing through the first plate (W1) and in contact with the chips (C1, ..., Cn) of the first plurality of chips,
 - Realizing a first plurality of conductive pads (115) on the first plate respectively connected to the first conductive elements.
2. Method according to claim 1, further comprising between said separation and said assembly: removal of said defective chip (s).
3. Method according to claim 2, wherein, after assembly, facing at least one given chip (C'2) of the second plurality of chips, there is at least one free slot (E 2 ) left following the withdrawal of a defective chip (C 2 ) during said step of removing, the method further comprising, after removal of the temporary support, another assembly, in said free location (E 2 ), of another chip (C'2) next to said given chip of the second plurality of chips.
4. Method according to claim 3, said other chip (C'2) having been obtained by:
 - Realization of a plurality of chips on a plate,
 - fixing the chips on a temporary support,
 - Chip separation between them by cutting the temporary support and said plate.
5. Method according to one of claims 1 to 4, the support (102) temporary being fixed (101) to the first plurality of chips via a bonding layer (101).
6. Method according to one of claims 1 to 5, further comprising, prior to said separation step, a thinning step of the first plate (Wl).
7. Method according to one of claims 1 to 6, further comprising after said assembly step: the transfer of a third plurality of chips to the first plurality of chips.
8. The method of claim 7, wherein the chips of the third plurality of chips are carried on the conductive pads of the third plurality of conductive pads (312).
PCT/EP2010/067843 2009-11-20 2010-11-19 Method for producing stacks on a plurality of levels of silicon chip assemblies WO2011061296A1 (en)

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