WO2011061296A1 - Method for producing stacks on a plurality of levels of silicon chip assemblies - Google Patents

Method for producing stacks on a plurality of levels of silicon chip assemblies Download PDF

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Publication number
WO2011061296A1
WO2011061296A1 PCT/EP2010/067843 EP2010067843W WO2011061296A1 WO 2011061296 A1 WO2011061296 A1 WO 2011061296A1 EP 2010067843 W EP2010067843 W EP 2010067843W WO 2011061296 A1 WO2011061296 A1 WO 2011061296A1
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WIPO (PCT)
Prior art keywords
chips
plate
chip
conductive pads
temporary support
Prior art date
Application number
PCT/EP2010/067843
Other languages
French (fr)
Inventor
Laurent Clavelier
Barbara Charlet
Léa Di Cioccio
Thomas Signamarcheix
Marc Zussy
Original Assignee
Commissariat à l'énergie atomique et aux énergies alternatives
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Publication of WO2011061296A1 publication Critical patent/WO2011061296A1/en

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Definitions

  • the invention relates to the field of microelectronics and more particularly to the production of devices comprising chip support stacks or integrated circuits.
  • stacking 3D stacking 3D
  • W2W wafer to wafer
  • W2W wafer to wafer
  • the yield of a plate is the ratio between the number of chips considered functional on this plate and the total number of chips of this plate.
  • C2W Chip to wafer
  • the method can have a total duration that can be for example of the order of several hours.
  • the invention relates to a method for producing a microelectronic device having at least one level comprising a plurality of chips stacked on another plurality of chips of a lower level.
  • the method comprises steps of:
  • Faulty chips are chips that do not meet one or more predetermined criteria, for example appearance, and / or electrical operation, and / or surface quality.
  • the functional chips are those that meet the predetermined criterion (s).
  • the defective chips are removed before assembly of the functional chips.
  • the method may further comprise,
  • the other chip may have been obtained by:
  • the temporary medium can be attached to the first plurality of chips via a bonding layer.
  • a thinning step of the first plate may have been performed prior to said separation step.
  • the defective chips may undergo processing to make them incompatible with a subsequent assembly, for example with bullets placed next. This can be achieved for example by etching to put the defective chips back from an assembly plane with another support or by a suitable surface treatment making the defective chip surface incompatible with a bonding implemented during a subsequent assembly with another support.
  • the method may further comprise, prior to said separation step or said fixing step:
  • Connection elements for example vias type (conductive elements through) and / or pads (conductive pads) can also be made after removal of the temporary support.
  • the conductive pads of the first plurality of conductive pads may be brought into contact with conductive pads of a second plurality of conductive pads connected respectively to the chip chips. the second plurality of chips.
  • the conductive pads and said other conductive pads can be assembled by molecular bonding bonding also called "direct bonding", such as a copper-copper bonding.
  • the method may further comprise, after said assembly step: the transfer of a third plurality of chips to the first plurality of chips.
  • the process can be repeated several times. Prior to said report, it is possible to make a third plurality of conductive pads on the chips of the first plurality of chips respectively connected to said conductive elements, the chips of the third plurality of chips being transferred to the conductive pads of the third plurality of conductive pads. .
  • FIGS. 1A-1K illustrate an example of the method according to the invention for producing a microelectronic device comprising at least a plurality of chips superimposed on another plurality of chips.
  • the starting material of the process may be a wafer plate W1 on which a plurality of integrated circuits or chips C1,..., Cn have been made (FIG. 1A).
  • the chips or integrated circuits can be for example memories (flash, DRAM, SRAM, ...), or cores of processors, or CMOS type circuits, or imagers, or electromechanical micro-systems (MEMS), or optical micro-systems (MOEMS).
  • memories flash, DRAM, SRAM, ...)
  • CMOS type circuits or imagers
  • MEMS electromechanical micro-systems
  • MOEMS optical micro-systems
  • a functionality test for example an electrical test, of each of the chips of the plate is carried out in order to possibly locate one or more defective chips.
  • the plate W1 is then bonded to a temporary support 102 by means of a bonding layer 101 located, for example, on the temporary support 102.
  • the bonding layer 101 covers the chips C1,. Cn.
  • This bonding layer may be, for example, based on resin or wax.
  • the temporary support 102 may be formed of at least one rigid layer for example based on a semiconductor material such as Si (FIG. 1B).
  • This thinning can be achieved for example by grinding and / or lapping and / or dry etching.
  • a thinning technique by fracture at a buried fragile zone created for example by implantation of gaseous species can also be implemented.
  • Conductive elements 110 passing through plate W1 can then be formed.
  • These conductive elements 110 commonly called TSV elements can be made by forming holes through the W1 plate and the chips Cl, ..., Cn, then filling the holes using a metallic material such as for example copper.
  • a step of forming an insulating contour on the walls of the holes and possibly on the thinned surface may be carried out in order to electrically insulate the conductive elements of the plate.
  • the conductive elements 110 TSV can thus pass through the plate and the integrated circuits C1,..., Cn (FIG.
  • the conductive elements 110 TSV may be in contact with connections of the integrated circuits located on the front face.
  • pads 112 commonly called “pads”
  • the rear face for example based on copper, in contact with the conductive elements 110 TSV.
  • the pads 112 may be isolated from each other by means of a layer of dielectric material 115 (FIG. 1C).
  • Chips Ci,..., C n are then separated by forming around trenches 120 crossing the plate Wi and unveiling the bonding layer 101. This separation can be performed for example by sawing and / or etching and / or cutting with a laser ( Figure 1D).
  • the defective chips may undergo processing to make them incompatible with the assembly that will follow, for example an etching to set them back from the assembly plane or a suitable surface treatment making the surface of faulty chips incompatible with the type of collage implemented.
  • the withdrawal can be carried out for example by means of a type of equipment commonly called "pick and place” having the mapping previously performed, for example using a heating head to make disassembly easier.
  • an assembly of the plate Wi is carried out with another plate W 2 comprising a plurality of chips or integrated circuits C'i, ..., C ' n and covered with conductive pads 212 insulated from each other by an insulating layer 215 , for example based on S10 2 (FIG. 1F).
  • This assembly can be achieved by direct bonding of the pads 112 of the plate W1 on the pads 212 of the other plate W2 ( Figure 1G).
  • the bonding may be of the copper-copper type as described in the article "Copper Direct-Bonding Characterization and its Interests for 3D Integration” Gueguen et al., Journal of the Electrochemical Society, 156 _10_H772- H776 _2009.
  • activation of the surface of the pads may have been previously performed, for example using polishing smoothing treatment and / or chemical cleaning and / or plasma treatment.
  • the temporary support 102 and the bonding layer 101 are then removed, for example by creep of the bonding layer. for example by external thermal stress and / or the initiation of a lateral friction movement. It can alternatively proceed by running-in.
  • conducting elements crossing 110 TSV at this stage of the process.
  • one or more locations Ei may have been left free on the latter.
  • This bonding can be implemented after activating the surface of the contact pad 212.
  • the chip (s) bonded to the free locations may be from the same type of structure as that described previously in connection with FIG. 1D, but in which a complete separation of the chips has been carried out, so that trenches have been made. (s) through the bonding layer 101 and the temporary support 102.
  • the chip C ' 2 which is glued to the free slot E2, is itself assembled to a temporary support portion 102. A withdrawal of said portion of temporary support 102 and the bonding layer 101 (FIG. 1J).
  • FIG. 1K a deposit of an electrically insulating layer 315, for example based on SiO 2 , which can then be made flat by polishing mechanical lapping and / or CMP (CMP for "Chemical Mechanical Polishing” and / or chemical etching (wet or dry).
  • CMP Chemical Mechanical Polishing
  • the structure thus produced can then serve as a support for receiving one or more other levels of stacking chips, by repeating certain steps of the method just described.
  • this method is also faster to implement than a method of C2W type, in which one chip should be glued one by one on a set of chips.

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Abstract

The invention relates to a microelectronic device provided with at least one given level comprising a plurality of chips (C1,…,Cn) stacked on another plurality of chips (C' 1,…, C' n) of a lower level; the method includes steps of: producing a first plurality of chips on a first plate (100), electrically testing the chips (C1,…, Cn) of the first plurality of chips so as to locate one or more defective chip(s) (C2) on the first plate, attaching a temporary substrate (101-102) to the first plurality of chips, separating the chips from one another by forming trenches (120) around the chips, which pass through the first plate and expose the temporary substrate, removing said defective chip(s), assembling the first plurality of chips to a second plurality of chips (C' 1,…, C' n) resting on a second plate (200).

Description

PROCEDE DE REALISATION D'EMPILEMENTS SUR PLUSIEURS NIVEAUX D'ENSEMBLES DE PUCES ELECTRONIQUES  METHOD FOR MAKING STACKS ON MULTIPLE LEVELS OF ELECTRONIC CHIP ASSEMBLIES
DESCRIPTION DESCRIPTION
DOMAINE TECHNIQUE TECHNICAL AREA
L' invention concerne le domaine de la microélectronique et plus particulièrement celui de la réalisation de dispositifs comportant des empilements de support de puces ou de circuits intégrés. The invention relates to the field of microelectronics and more particularly to the production of devices comprising chip support stacks or integrated circuits.
Elle apporte des améliorations en termes de rendement par rapport aux procédés de type communément appelé « wafer to wafer » (plaque sur plaque) et en termes de rapidité de mise en œuvre vis-à-vis des procédés de type communément appelé « chip to wafer » (puce sur plaque) .  It brings improvements in terms of efficiency compared to processes of the type commonly called "wafer to wafer" and in terms of speed of implementation vis-à-vis the type of process commonly called "chip to wafer" "(Chip on plate).
ART ANTÉRIEUR PRIOR ART
Il est connu de réaliser un empilement communément appelé « stacking 3D », de plusieurs circuits intégrés ou de plusieurs puces. It is known to make a stack commonly known as "stacking 3D", several integrated circuits or several chips.
Pour cela on peut, selon un procédé communément appelé « W2W » (pour wafer to wafer) , superposer plusieurs plaques (wafer selon la terminologie anlo-saxonne) de plusieurs puces ou circuits intégré (e) s qui ont été formé (e) s en même temps sur le même support, les plaques étant ensuite éventuellement découpées.  For this purpose, it is possible, according to a method commonly known as "W2W" (for wafer to wafer), to superpose several plates (wafer according to the terminology) of several chips or integrated circuits (e) s that have been formed (e) s at the same time on the same support, the plates being then optionally cut.
Un tel procédé pose problème en termes de rendement des circuits fonctionnels. On appelle rendement d'une plaque, le ratio entre nombre de puces jugées fonctionnelles sur cette plaque et le nombre de puces total de cette plaque. Such a method poses a problem in terms of performance of the functional circuits. The yield of a plate is the ratio between the number of chips considered functional on this plate and the total number of chips of this plate.
Lorsqu'on empile N plaques ayant un rendement individuel de Yi, on obtient un dispositif dont le rendement total Y est Y = Yi=o x Yi=i x Yi=2 x ··· x  When stacking N plates with an individual yield of Yi, we obtain a device whose total efficiency Y is Y = Yi = o x Yi = i x Yi = 2 x ··· x
Un empilement de deux plaques ayant chacune un rendement de 80%, donne ainsi un rendement total de 64%. A stack of two plates each having a yield of 80%, gives a total yield of 64%.
Lorsqu'on cherche à empiler plus de 2 puces, le rendement total chute rapidement et peut s'avérer trop faible.  When stacking more than 2 chips, the total yield drops quickly and may be too low.
Il en résulte, que l'on choisi plutôt généralement de mettre en œuvre un report de puces sur un wafer, une fois qu'elles ont été extraites par découpe d'un autre wafer, testées et triées.  As a result, we generally choose to implement a transfer of chips on a wafer, once they were extracted by cutting another wafer, tested and sorted.
Cette autre méthode, communément appelée « C2W » (pour « chip to wafer ») a comme inconvénient d'être plus longue à mettre en œuvre que la méthode W2W pour réaliser autant d'empilements de puces.  This other method, commonly known as "C2W" (for "chip to wafer") has the disadvantage of being longer to implement than the W2W method to achieve as many chip stacks.
Pour empiler des puces de 1 cm2 sur une plaque de 200 mm et réaliser un empilement de 300 puces sur la surface d'une plaque, le procédé peut avoir une durée totale qui peut être par exemple de l'ordre de plusieurs heures. To stack 1 cm 2 chips on a 200 mm plate and to carry out a stack of 300 chips on the surface of a plate, the method can have a total duration that can be for example of the order of several hours.
Il se pose le problème de trouver un nouveau procédé de réalisation d'un dispositif comportant une pluralité de puces empilées. EXPOSÉ DE L' INVENTION There is the problem of finding a new method for producing a device comprising a plurality of stacked chips. STATEMENT OF THE INVENTION
L' invention concerne un procédé de réalisation d'un dispositif microélectronique doté d'au moins un niveau donné comportant une pluralité de puces empilées sur une autre pluralité de puces d'un niveau inférieur . The invention relates to a method for producing a microelectronic device having at least one level comprising a plurality of chips stacked on another plurality of chips of a lower level.
Le procédé comprend des étapes consistant à : The method comprises steps of:
- fournir une première plaque comportant une première pluralité de puces, provide a first plate comprising a first plurality of chips,
- test fonctionnel des puces de la première pluralité de puces afin de localiser une ou plusieurs puce (s) défectueuse ( s ) sur la première plaque et à identifier les puces fonctionnelles,  functional test of the chips of the first plurality of chips in order to locate one or more defective chips on the first plate and to identify the functional chips,
- fixation sur la première pluralité de puces d'un support temporaire,  fixing on the first plurality of chips a temporary support,
- séparation des puces entre elles par formation de tranchées autour des puces, les tranchées traversant la première plaque les puces étant tenues par le support temporaire,  separation of the chips from one another by trench formation around the chips, the trenches passing through the first plate, the chips being held by the temporary support,
- assemblage des puces fonctionnelles de la première pluralité de puces avec une deuxième pluralité de puces reposant sur une deuxième plaque.  assembling the functional chips of the first plurality of chips with a second plurality of chips resting on a second plate.
Par puces défectueuses, on entend des puces qui ne répondent pas à un ou plusieurs critères prédéterminés, par exemple d'aspect, et/ou de fonctionnement électrique, et/ou de qualité de surface.  Faulty chips are chips that do not meet one or more predetermined criteria, for example appearance, and / or electrical operation, and / or surface quality.
Par opposition, les puces fonctionnelles sont celles qui répondent au (x) critère (s) prédéterminé (s) . Avantageusement, les puces défectueuses sont retirées avant l'assemblage des puces fonctionnelles . In contrast, the functional chips are those that meet the predetermined criterion (s). Advantageously, the defective chips are removed before assembly of the functional chips.
Après assemblage, en regard d'au moins une puce donnée de la deuxième pluralité de puces figure au moins un emplacement libre laissé suite au retrait d'une puce défectueuse, le procédé peut comprendre en outre,  After assembly, facing at least one given chip of the second plurality of chips is at least one free slot left following the removal of a defective chip, the method may further comprise,
- le retrait du support temporaire,  - the withdrawal of the temporary support,
- un autre assemblage d'une autre puce en regard de ladite puce donnée.  another assembly of another chip opposite said given chip.
L'autre puce peut avoir été obtenue par : The other chip may have been obtained by:
- réalisation d'une pluralité de puces sur une plaque, - Realization of a plurality of chips on a plate,
- fixation des puces sur un support temporaire,  - fixing the chips on a temporary support,
- séparation des puces entre elles par découpe du support temporaire et de ladite plaque.  - Chip separation between them by cutting the temporary support and said plate.
Le support temporaire peut être fixé à la première pluralité de puces par l'intermédiaire d'une couche de collage.  The temporary medium can be attached to the first plurality of chips via a bonding layer.
Préalablement à ladite étape de séparation, une étape d'amincissement de la première plaque peut avoir été effectuée.  Prior to said separation step, a thinning step of the first plate may have been performed.
En variante, les puces défectueuses peuvent subir un traitement afin de les rendre incompatibles avec un assemblage ultérieur, par exemple avec des puces mises en regard. Cela peut être réalisé par exemple par gravure pour mettre les puces défectueuses en retrait d'un plan d'assemblage avec un autre support ou par un traitement de surface adapté rendant la surface des puces défectueuses incompatible avec un collage mis en œuvre lors d'un assemblage ultérieur avec un autre support. Alternatively, the defective chips may undergo processing to make them incompatible with a subsequent assembly, for example with bullets placed next. This can be achieved for example by etching to put the defective chips back from an assembly plane with another support or by a suitable surface treatment making the defective chip surface incompatible with a bonding implemented during a subsequent assembly with another support.
Selon une possibilité, le procédé peut comprendre en outre, préalablement à ladite étape de séparation ou à ladite étape de fixation :  According to one possibility, the method may further comprise, prior to said separation step or said fixing step:
- la réalisation d'éléments conducteurs traversant la première plaque et en contact avec les puces de la première pluralité de puces,  the production of conducting elements crossing the first plate and in contact with the chips of the first plurality of chips,
- la réalisation d'une première pluralité de plots conducteurs sur la première plaque connectés respectivement aux éléments conducteurs.  - Realizing a first plurality of conductive pads on the first plate respectively connected to the conductive elements.
Des éléments de connexion par exemple de type vias (éléments conducteurs traversant) et/ou pads (plots conducteurs) peuvent également être réalisés après retrait du support temporaire.  Connection elements for example vias type (conductive elements through) and / or pads (conductive pads) can also be made after removal of the temporary support.
Lors de l'assemblage de la première pluralité de puces avec la deuxième pluralité de puces, les plots conducteurs de la première pluralité de plots conducteurs peuvent être mis en contact avec des plots conducteurs d'une deuxième pluralité de plots conducteurs connectés respectivement aux puces de la deuxième pluralité de puces.  When assembling the first plurality of chips with the second plurality of chips, the conductive pads of the first plurality of conductive pads may be brought into contact with conductive pads of a second plurality of conductive pads connected respectively to the chip chips. the second plurality of chips.
Les plots conducteurs et lesdits autres plots conducteurs peuvent être assemblés par collage par adhérence moléculaire encore appelé « collage direct », tel qu'un collage cuivre-cuivre.  The conductive pads and said other conductive pads can be assembled by molecular bonding bonding also called "direct bonding", such as a copper-copper bonding.
Le procédé peut comprendre en outre après ladite étape d'assemblage : le report d'une troisième pluralité de puces sur la première pluralité de puces. Le procédé peut être réitéré plusieurs fois. Préalablement audit report, on peut réaliser une troisième pluralité de plots conducteurs sur les puces de la première pluralité de puces connectés respectivement aux dits éléments conducteurs, les puces de la troisième pluralité de puces étant reportées sur les plots conducteurs de la troisième pluralité de plots conducteurs. The method may further comprise, after said assembly step: the transfer of a third plurality of chips to the first plurality of chips. The process can be repeated several times. Prior to said report, it is possible to make a third plurality of conductive pads on the chips of the first plurality of chips respectively connected to said conductive elements, the chips of the third plurality of chips being transferred to the conductive pads of the third plurality of conductive pads. .
BRÈVE DESCRIPTION DES DESSINS BRIEF DESCRIPTION OF THE DRAWINGS
La présente invention sera mieux comprise à la lecture de la description d'exemples de réalisation donnés, à titre purement indicatif et nullement limitatif, en faisant référence aux dessins annexés sur lesquels : The present invention will be better understood on reading the description of exemplary embodiments given, purely by way of indication and in no way limiting, with reference to the appended drawings in which:
- les figures 1A-1K illustrent un exemple de procédé suivant l'invention de réalisation d'un dispositif microélectronique comprenant au moins une pluralité de puces superposées à une autre pluralité de puces .  - Figures 1A-1K illustrate an example of the method according to the invention for producing a microelectronic device comprising at least a plurality of chips superimposed on another plurality of chips.
Des parties identiques, similaires ou équivalentes des différentes figures portent les mêmes références numériques de façon à faciliter le passage d'une figure à l'autre.  Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the passage from one figure to another.
Les différentes parties représentées sur les figures ne le sont pas nécessairement selon une échelle uniforme, pour rendre les figures plus lisibles .  The different parts shown in the figures are not necessarily in a uniform scale, to make the figures more readable.
EXPOSÉ DÉTAILLÉ DE MODES DE RÉALISATION PARTICULIERS DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS
Un exemple de procédé suivant l'invention va à présent être donné en liaison avec les figures 1A-1K. Le matériau de départ du procédé peut être une plaque Wl semi-conductrice (en anglais « wafer ») sur laquelle une pluralité de circuits intégrés ou de puces Cl,...,Cn ont été réalisé (e) s (figure 1A) . An example of a method according to the invention will now be given in conjunction with FIGS. 1A-1K. The starting material of the process may be a wafer plate W1 on which a plurality of integrated circuits or chips C1,..., Cn have been made (FIG. 1A).
Les puces ou circuits intégrés peuvent être par exemple des mémoires (flash, DRAM, SRAM,...), ou des cœurs de processeurs, ou des circuits de type CMOS, ou des imageurs, ou des micro-systèmes électromécaniques (MEMS), ou des micro-systèmes optiques (MOEMS) .  The chips or integrated circuits can be for example memories (flash, DRAM, SRAM, ...), or cores of processors, or CMOS type circuits, or imagers, or electromechanical micro-systems (MEMS), or optical micro-systems (MOEMS).
On réalise tout d'abord un test de fonctionnalité, par exemple un test électrique, de chacune des puces de la plaque afin de localiser éventuellement, une ou plusieurs puces défectueuses.  First of all, a functionality test, for example an electrical test, of each of the chips of the plate is carried out in order to possibly locate one or more defective chips.
On effectue ensuite un collage de la plaque Wl à un support temporaire 102 par l'intermédiaire d'une couche de collage 101 située, par exemple, sur le support temporaire 102. La couche de collage 101 recouvre les puces Cl,...,Cn.  The plate W1 is then bonded to a temporary support 102 by means of a bonding layer 101 located, for example, on the temporary support 102. The bonding layer 101 covers the chips C1,. Cn.
Cette couche de collage peut être, par exemple, à base de résine ou de cire.  This bonding layer may be, for example, based on resin or wax.
Le support temporaire 102 peut être formé d'au moins une couche rigide par exemple à base d'un matériau semi-conducteur tel que du Si (figure 1B) .  The temporary support 102 may be formed of at least one rigid layer for example based on a semiconductor material such as Si (FIG. 1B).
On peut réaliser ensuite un amincissement de la face arrière de la plaque Wl, c'est-à-dire de la face opposée à celle sur laquelle les circuits ou puces Cl,...,Cn ont été formé (e) s.  One can then perform a thinning of the rear face of the plate W1, that is to say the face opposite to that on which circuits or chips Cl, ..., Cn were formed (e) s.
Cet amincissement peut être réalisé par exemple par meulage et/ou rodage et/ou gravure sèche. Une technique d'amincissement par fracture au niveau d'une zone fragile enterrée créée par exemple par implantation d'espèces gazeuses peut également être mise en œuvre. This thinning can be achieved for example by grinding and / or lapping and / or dry etching. A thinning technique by fracture at a buried fragile zone created for example by implantation of gaseous species can also be implemented.
On peut former ensuite des éléments conducteurs 110 traversant la plaque Wl .  Conductive elements 110 passing through plate W1 can then be formed.
Ces éléments conducteurs 110 communément appelés éléments TSV (TSV pour « Through Silicon Via ») peuvent être réalisés par formation de trous traversant la plaque Wl et les puces Cl,...,Cn, puis remplissage des trous à l'aide d'un matériau métallique tel que par exemple du cuivre.  These conductive elements 110 commonly called TSV elements (TSV for "Through Silicon Via") can be made by forming holes through the W1 plate and the chips Cl, ..., Cn, then filling the holes using a metallic material such as for example copper.
Préalablement au remplissage de matériau métallique, une étape de formation d'un contour isolant sur les parois des trous et éventuellement sur la surface amincie, peut être réalisée afin d'isoler électriquement les éléments conducteurs de la plaque.  Prior to the filling of metallic material, a step of forming an insulating contour on the walls of the holes and possibly on the thinned surface may be carried out in order to electrically insulate the conductive elements of the plate.
Les éléments conducteurs 110 TSV peuvent ainsi traverser la plaque et les circuits intégrés Cl,...,Cn (figure le) . Les éléments conducteurs 110 TSV peuvent être en contact avec des connexions des circuits intégrés situés en face avant.  The conductive elements 110 TSV can thus pass through the plate and the integrated circuits C1,..., Cn (FIG. The conductive elements 110 TSV may be in contact with connections of the integrated circuits located on the front face.
Ensuite, on peut former des plots 112 conducteurs (communément appelés « pads ») en face arrière, par exemple à base de cuivre, en contact avec les éléments conducteurs 110 TSV.  Then, one can form pads 112 (commonly called "pads") on the rear face, for example based on copper, in contact with the conductive elements 110 TSV.
Les plots 112 peuvent être isolés entre eux à l'aide d'une couche de matériau diélectrique 115 (figure 1C) .  The pads 112 may be isolated from each other by means of a layer of dielectric material 115 (FIG. 1C).
On effectue ensuite une séparation des puces Ci,...,Cn, en formant autour de ces dernières, des tranchées 120 traversant la plaque Wi et dévoilant la couche de collage 101. Cette séparation peut être effectuée par exemple par sciage et/ou par gravure et/ou par découpe à l'aide d'un laser (figure 1D) . Chips Ci,..., C n are then separated by forming around trenches 120 crossing the plate Wi and unveiling the bonding layer 101. This separation can be performed for example by sawing and / or etching and / or cutting with a laser (Figure 1D).
On peut effectuer ensuite un retrait d'éventuelles puces défectueuses, à l'aide par exemple d'une cartographie établie précédemment lors de l'étape de test fonctionnel et permettant une localisation des puces valides et d'une ou plusieurs puces défectueuses.  It is then possible to remove any defective chips, for example using a mapping previously established during the functional test step and allowing a location of the valid chips and one or more defective chips.
En variante, les puces défectueuses peuvent subir un traitement afin de les rendre incompatibles avec l'assemblage qui va suivre, par exemple une gravure pour les mettre en retrait du plan d'assemblage ou un traitement de surface adapté rendant la surface des puces défectueuses incompatible avec le type de collage mis en œuvre.  Alternatively, the defective chips may undergo processing to make them incompatible with the assembly that will follow, for example an etching to set them back from the assembly plane or a suitable surface treatment making the surface of faulty chips incompatible with the type of collage implemented.
Dans l'exemple représenté sur la figure 1E, on retire la puce C2 qui a été identifiée comme défectueuse . In the example shown in FIG. 1E, the chip C 2 which has been identified as defective is removed.
Le retrait peut être effectué par exemple grâce à un équipement de type communément appelé « pick and place » disposant de la cartographie réalisée précédemment, en utilisant par exemple une tête chauffante afin de rendre le démontage plus aisé.  The withdrawal can be carried out for example by means of a type of equipment commonly called "pick and place" having the mapping previously performed, for example using a heating head to make disassembly easier.
Ensuite, on effectue un assemblage de la plaque Wi avec une autre plaque W2 comportant une pluralité de puces ou de circuits intégrés C'i,...,C'n et recouverte de plots conducteurs 212 isolés entre eux par une couche isolante 215, par exemple à base de S1O2 (figure 1F) . Cet assemblage peut être réalisé par collage direct des plots 112 de la plaque Wl sur les plots 212 de l'autre plaque W2 (figure 1G) . Then, an assembly of the plate Wi is carried out with another plate W 2 comprising a plurality of chips or integrated circuits C'i, ..., C ' n and covered with conductive pads 212 insulated from each other by an insulating layer 215 , for example based on S10 2 (FIG. 1F). This assembly can be achieved by direct bonding of the pads 112 of the plate W1 on the pads 212 of the other plate W2 (Figure 1G).
Un collage par adhésion moléculaire (sans apport de colle) peut être mis en œuvre. Dans le cas où les plots 112 et 212 sont à base de cuivre, le collage réalisé peut être de type cuivre-cuivre tel que décrit dans l'article « Copper Direct-Bonding Characterization and its interests for 3D Intégration » Gueguen et al., Journal of The Electrochemical Society, 156 _10_ H772- H776 _2009.  Bonding by molecular adhesion (without glue) can be implemented. In the case where the pads 112 and 212 are copper-based, the bonding may be of the copper-copper type as described in the article "Copper Direct-Bonding Characterization and its Interests for 3D Integration" Gueguen et al., Journal of the Electrochemical Society, 156 _10_H772- H776 _2009.
Pour effectuer un collage moléculaire, une activation de la surface des plots peut avoir été préalablement réalisée, par exemple à l'aide de traitement de lissage par polissage et/ou de nettoyage chimique et/ou de traitement par plasma.  To perform a molecular bonding, activation of the surface of the pads may have been previously performed, for example using polishing smoothing treatment and / or chemical cleaning and / or plasma treatment.
On peut par exemple avoir réalisé avant l'étape de découpe un polissage mécano-chimique de surface puis activer la surface après découpe par plasma, à base de He/¾ par exemple.  For example, it is possible, before the cutting step, to perform a chemical-mechanical surface polishing and then to activate the surface after plasma cutting, based on He / ¾ for example.
On réalise ensuite un retrait du support temporaire 102 et de la couche de collage 101, par exemple par fluage de la couche de collage ? par exemple par le biais d'une sollicitation thermique extérieure et/ou l'initiation d'un mouvement de friction latérale. On peut en variante procéder par rodage .  The temporary support 102 and the bonding layer 101 are then removed, for example by creep of the bonding layer. for example by external thermal stress and / or the initiation of a lateral friction movement. It can alternatively proceed by running-in.
Il est possible également de réaliser des éléments conducteurs traversant 110 TSV à ce stade du procédé. En fonction du nombre de puces défectueuses qui ont été détectées et retirées préalablement de la première plaque Wl, un ou plusieurs emplacements Ei peuvent avoir été laissés libres sur cette dernière. It is also possible to make conducting elements crossing 110 TSV at this stage of the process. Depending on the number of defective chips that have been detected and removed before the first plate W1, one or more locations Ei may have been left free on the latter.
Dans l'exemple représenté sur la figure 1H, un emplacement E2 correspondant à la zone où la puce défectueuse C2 se trouvait, est laissé libre.  In the example shown in Figure 1H, a location E2 corresponding to the area where the faulty chip C2 was, is left free.
A cet emplacement, au moins un plot de contact 212 est dévoilé.  At this location, at least one contact pad 212 is unveiled.
On peut ensuite effectuer un collage d'une puce c"2 à l'emplacement E2 laissé libre. It is then possible to glue a chip c " 2 to the location E2 left free.
Ce collage peut être mis en œuvre après avoir effectué une activation de la surface du plot de contact 212.  This bonding can be implemented after activating the surface of the contact pad 212.
La ou les puces collée (s) aux emplacements libres peuvent être issues du même type de structure que celle décrite précédemment en liaison avec la figure 1D, mais dans laquelle on a effectué une séparation complète des puces, de sorte que des tranchées ont été réalisée (s) à travers la couche de collage 101 et le support 102 temporaire.  The chip (s) bonded to the free locations may be from the same type of structure as that described previously in connection with FIG. 1D, but in which a complete separation of the chips has been carried out, so that trenches have been made. (s) through the bonding layer 101 and the temporary support 102.
Dans l'exemple représenté sur la figure II, la puce C'2, que l'on colle à l'emplacement libre E2, est elle-même assemblée à une portion de support temporaire 102. On réalise alors un retrait de ladite portion de support temporaire 102 et de la couche de collage 101 (figure 1J) . In the example shown in FIG. II, the chip C ' 2 , which is glued to the free slot E2, is itself assembled to a temporary support portion 102. A withdrawal of said portion of temporary support 102 and the bonding layer 101 (FIG. 1J).
On effectue ensuite (figure 1K) un dépôt d'une couche électriquement isolante 315, par exemple à base de S1O2, que l'on peut ensuite rendre plane par polissage rodage mécanique et/ou CMP (CMP pour « Chemical Mechanical Polishing », polissage mécano- chimique) et/ou attaque chimique (humide ou sèche). Next, (FIG. 1K) a deposit of an electrically insulating layer 315, for example based on SiO 2 , which can then be made flat by polishing mechanical lapping and / or CMP (CMP for "Chemical Mechanical Polishing" and / or chemical etching (wet or dry).
Puis, on forme des ouvertures dans la couche isolante 315 en regard des puces C' i,...,C'n que l'on remplit de matériau métallique, par exemple du cuivre, afin de former des plots de contact 312.  Then, openings are formed in the insulating layer 315 facing chips C 'i, ..., C'n that is filled with metal material, for example copper, to form contact pads 312.
La structure ainsi réalisée peut alors servir de support destiné à recevoir un ou plusieurs autres niveaux d'empilement de puces, en réitérant certaines étapes du procédé qui vient d'être décrit.  The structure thus produced can then serve as a support for receiving one or more other levels of stacking chips, by repeating certain steps of the method just described.
On peut ainsi réaliser une connectique sur les deux faces de la couche Wl pour faciliter l'intégration 3D.  It is thus possible to make a connection on both sides of the W1 layer to facilitate 3D integration.
Dans un tel procédé toutes les puces reportées sont fonctionnelles.  In such a method all reported chips are functional.
Le rendement de fabrication est donc amélioré par rapport au procédé W2W. En termes de rapidité de mise en œuvre, ce procédé est également plus rapide à mettre en œuvre qu'un procédé de type C2W, dans lequel on devrait coller les puces une par une sur un ensemble de puce.  The manufacturing efficiency is thus improved compared to the W2W process. In terms of speed of implementation, this method is also faster to implement than a method of C2W type, in which one chip should be glued one by one on a set of chips.
Pour certaines applications telles que les disques flash, il peut être prévu d'empiler jusqu'à 16 niveaux de puces.  For some applications such as flash drives, it can be expected to stack up to 16 levels of chips.

Claims

REVENDICATIONS
1. Procédé de réalisation d'un dispositif microélectronique doté d' au moins un niveau donné comportant une première pluralité de puces (Ci,...,Cn) empilées sur une deuxième pluralité de puces (C'i, c' n) d'un niveau inférieur, le procédé comprenant des étapes de : A method of producing a microelectronic device having at least a given level comprising a first plurality of chips (Ci, ..., C n ) stacked on a second plurality of chips (C ' i, c ' n ) of a lower level, the method comprising steps of:
- fourniture d'une première pluralité de puces (Ci,...,Cn) sur une première plaque (Wi) , supplying a first plurality of chips (Ci, ..., C n ) on a first plate (Wi),
- test des puces (Ci,...,Cn) de la première pluralité de puces afin de localiser une ou plusieurs puce (s) défectueuse ( s ) (C2) sur la première plaque, chip test (Ci, ..., C n ) of the first plurality of chips in order to locate one or more defective chips (C 2 ) on the first plate,
- fixation sur la première pluralité de puces d'un support temporaire (102),  fixing on the first plurality of chips of a temporary support (102),
- séparation des puces entre elles par formation de tranchées (120) autour des puces, les tranchées traversant la première plaque (Wi) , les puces étant encore maintenues par le support temporaire,  separating the chips from one another by forming trenches (120) around the chips, the trenches crossing the first plate (Wi), the chips being still held by the temporary support,
- assemblage de la première pluralité de puces avec la deuxième pluralité de puces (c' 1 , c'n) reposant sur une deuxième plaque (W2) , des plots conducteurs d'une première pluralité de plots conducteurs étant assemblés, par collage par adhérence moléculaire, par exemple de type collage cuivre-cuivre, avec des plots conducteurs (212) d'une deuxième pluralité de plots conducteurs connectés respectivement aux puces de la deuxième pluralité de puces, - assembling the first plurality of chips with the second plurality of chips (c ' 1, c ' n) resting on a second plate (W 2 ), conductive pads of a first plurality of conductive pads being assembled, by bonding by molecular adhesion, for example of the copper-copper bonding type, with conductive pads (212) of a second plurality of conductive pads respectively connected to the chips of the second plurality of chips,
- un retrait du support temporaire (102), - un dépôt d'une couche électriquement isolante (315), sur l'assemblage de la première pluralité de puces avec la deuxième pluralité de puces, et la formation, dans cette couche, d'une troisième pluralité de plots conducteurs (312) en regard de puces de la première pluralité de puces, a withdrawal of the temporary support (102), a deposition of an electrically insulating layer (315), on the assembly of the first plurality of chips with the second plurality of chips, and forming, in that layer, a third plurality of conductive pads (312) facing chips of the first plurality of chips,
ce procédé comprenant en outre, préalablement à ladite étape de séparation ou à ladite étape de fixation:  this method further comprising, prior to said separation step or said fixing step:
- la réalisation de premiers éléments conducteurs (110) traversant la première plaque (Wl) et en contact avec les puces (Cl,...,Cn) de la première pluralité de puces,  - Realizing first conductive elements (110) passing through the first plate (W1) and in contact with the chips (C1, ..., Cn) of the first plurality of chips,
- la réalisation d'une première pluralité de plots conducteurs (115) sur la première plaque connectés respectivement aux premiers éléments conducteurs.  - Realizing a first plurality of conductive pads (115) on the first plate respectively connected to the first conductive elements.
2. Procédé selon la revendication 1, comprenant en outre entre ladite séparation et ledit assemblage : le retrait de la ou des dite (s) puce (s) défectueuse ( s ) . 2. Method according to claim 1, further comprising between said separation and said assembly: removal of said defective chip (s).
3. Procédé selon la revendication 2, dans lequel, après assemblage, en regard d'au moins une puce donnée (C'2) de la deuxième pluralité de puces figure au moins un emplacement libre (E2) laissé suite au retrait d'une puce défectueuse (C2) lors de ladite étape de retrait, le procédé comprenant en outre, après le retrait du support temporaire, un autre assemblage, dans ledit emplacement libre (E2) , d'une autre puce (C'2) en regard de ladite puce donnée de la deuxième pluralité de puces. 3. Method according to claim 2, wherein, after assembly, facing at least one given chip (C'2) of the second plurality of chips, there is at least one free slot (E 2 ) left following the withdrawal of a defective chip (C 2 ) during said step of removing, the method further comprising, after removal of the temporary support, another assembly, in said free location (E 2 ), of another chip (C'2) next to said given chip of the second plurality of chips.
4. Procédé selon la revendication 3, ladite autre puce (C'2) ayant été obtenue par : 4. Method according to claim 3, said other chip (C'2) having been obtained by:
- réalisation d'une pluralité de puces sur une plaque,  - Realization of a plurality of chips on a plate,
- fixation des puces sur un support temporaire,  - fixing the chips on a temporary support,
- séparation des puces entre elles par découpe du support temporaire et de ladite plaque.  - Chip separation between them by cutting the temporary support and said plate.
5. Procédé selon l'une des revendications 1 à 4, le support (102) temporaire étant fixé (101) à la première pluralité de puces par l'intermédiaire d'une couche de collage (101). 5. Method according to one of claims 1 to 4, the support (102) temporary being fixed (101) to the first plurality of chips via a bonding layer (101).
6. Procédé selon l'une des revendications 1 à 5, comprenant en outre, préalablement à ladite étape de séparation, une étape d'amincissement de la première plaque (Wl) . 6. Method according to one of claims 1 to 5, further comprising, prior to said separation step, a thinning step of the first plate (Wl).
7. Procédé selon l'une des revendications 1 à 6, comprenant en outre après ladite étape d'assemblage : le report d'une troisième pluralité de puces sur la première pluralité de puces. 7. Method according to one of claims 1 to 6, further comprising after said assembly step: the transfer of a third plurality of chips to the first plurality of chips.
8. Procédé selon la revendication 7, dans lequel les puces de la troisième pluralité de puces sont reportées sur les plots conducteurs de la troisième pluralité de plots conducteurs (312). 8. The method of claim 7, wherein the chips of the third plurality of chips are carried on the conductive pads of the third plurality of conductive pads (312).
PCT/EP2010/067843 2009-11-20 2010-11-19 Method for producing stacks on a plurality of levels of silicon chip assemblies WO2011061296A1 (en)

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