WO2011055169A1 - Response to wearout in an electronic device - Google Patents

Response to wearout in an electronic device Download PDF

Info

Publication number
WO2011055169A1
WO2011055169A1 PCT/IB2009/054942 IB2009054942W WO2011055169A1 WO 2011055169 A1 WO2011055169 A1 WO 2011055169A1 IB 2009054942 W IB2009054942 W IB 2009054942W WO 2011055169 A1 WO2011055169 A1 WO 2011055169A1
Authority
WO
WIPO (PCT)
Prior art keywords
electronic device
component
set forth
state
wearout
Prior art date
Application number
PCT/IB2009/054942
Other languages
French (fr)
Inventor
Michael Priel
Anton Rozen
Yossi Shoshany
Original Assignee
Freescale Semiconductor, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor, Inc. filed Critical Freescale Semiconductor, Inc.
Priority to CN200980162323.8A priority Critical patent/CN102597906B/en
Priority to US13/500,700 priority patent/US8698552B2/en
Priority to EP09851059.7A priority patent/EP2496999B1/en
Priority to PCT/IB2009/054942 priority patent/WO2011055169A1/en
Publication of WO2011055169A1 publication Critical patent/WO2011055169A1/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2855Environmental, reliability or burn-in testing
    • G01R31/2856Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/004Error avoidance

Definitions

  • This invention relates to an electronic device comprising a first component susceptible to a wearout effect, operation of which first component depends on an operating parameter; and a second component having an on-state and an off-state.
  • the invention also relates to a method of operating such an electronic device.
  • a wearout effect in this context is understood to be any long-term variation of the properties of the electronic device that is produced by operating the device.
  • wearout phenomena include negative bias temperature instability (NBTI), time-dependent dielectric breakdown (TDDB), hot carriers injection (HCI), and electromigration (EM).
  • NBTI negative bias temperature instability
  • TDDB time-dependent dielectric breakdown
  • HCI hot carriers injection
  • EM electromigration
  • wearout effects may manifest themselves by an increase of latency in integrated circuits during the lifetime of the integrated circuit.
  • US 2008/0036487 A1 therefore proposes detecting signal generation latency and generating a wearout response.
  • the wearout response can take a variety of different forms such as reducing the operating frequency, increasing the operating voltage, and others.
  • the present invention provides an electronic device and a method as described in the accompanying claims.
  • Figure 1 shows a schematic plot of a threshold voltage and an operating voltage as functions of time.
  • Figure 2 shows a schematic plot of the threshold voltage and an adapted operating voltage as functions of time.
  • Figure 3 shows a schematic outline of an electronic device according to a first embodiment.
  • Figure 4 shows a schematic outline of an electronic device according to a second embodiment.
  • Figure 5 is a schematic flow chart of a method of adapting an operating voltage.
  • Figure 6 shows a schematic plot of experimental data illustrating a reduction in power consumption.
  • a threshold voltage V th of a semiconductor device e.g. a transistor
  • the accumulated time t is understood to be the total time during which the device was in an on-state since e.g. fabrication or first use of the device.
  • the threshold voltage V th is the minimum voltage required for operating the device.
  • the threshold voltage V th increases monotonically as a function of the accumulated time t. This behaviour is a typical wearout effect of negative bias temperature instability (NBTI). Other wearout phenomena may result in similar or in different variations of the threshold voltage.
  • NBTI negative bias temperature instability
  • a constant voltage V 1 i ⁇ n st may be applied at the device.
  • the constant voltage V 1 iCon st is chosen greater than a constant minimum voltage V min .
  • the minimum voltage V min is given by the threshold voltage V th at accumulated time t max .
  • the wearout behaviour of the threshold voltage V th i.e. the function V th (t) may be known or can be determined, e.g. experimentally.
  • V th a method of determining NBTI of a p-channel metal-oxide-semiconductor (PMOS) transistor is described in US 2003/0231028 A1.
  • the operating voltage can be adapted to the wearout behaviour of the threshold voltage V th .
  • the operating voltage V-i thus increases monotonically as prescribed by the threshold voltage V th .
  • the time-dependent operating voltage V-i is lower than the constant operating voltage V 1 i Con st described above with reference to Figure 1. A reduction in power consumption during the lifetime of the device can thus be achieved.
  • the electronic device 10 may, for example, be one of the following: an integrated circuit, a microprocessor, a computer processor, a telephone, a navigation device (10), an audio device (10), a video device (10), and any combination thereof.
  • the device 10 comprises a first component 12, a second component 14, a time estimator 16, a controller 18, a DC voltage provider 20, and a DC-DC converter 22.
  • the first component 12 is an integrated circuit
  • the second component 14 is a central processing unit (CPU).
  • the CPU may also be an integrated circuit.
  • the second component 14 comprises the time estimator 16 and the controller 18.
  • the time estimator 16 and the controller 18 are not necessarily distinct components of the CPU 14, indeed they may represent functionalities of the CPU 14. They may be implemented by dedicated circuitry and/or by software stored in a memory (not shown) of the CPU 14.
  • the DC power provider 20 may be a battery. It provides a constant supply voltage V 0 for powering both the CPU 14 and the DC-DC voltage converter 22.
  • the DC-DC voltage converter 22 generates an operating voltage V-i for powering the integrated circuit 12. Operation of the first component 12 thus depends on an operating parameter, namely, the operating voltage V-
  • the first component 12 is susceptible to a wearout effect.
  • the wearout effect may be due to at least one of the following phenomena: negative bias temperature instability (NBTI), time- dependent dielectric breakdown (TDDB), hot carriers injection (HCI), and electromigration (EM). Because of the expected wearout effect, adapting the operating parameter V-i during the lifetime of the device 10 may be advantageous.
  • NBTI negative bias temperature instability
  • TDDB time- dependent dielectric breakdown
  • HCI hot carriers injection
  • EM electromigration
  • An off-state is a state in which the device in question is "off” in the sense of "switched off or “inactive” or “not powered".
  • the electronic device 10 comprises a time estimator 16 for updating an estimate of an accumulated time the second component 14 was in the on-state. Restated in a simplified manner, the time estimator counts the total time during which the second device is in the on-state.
  • the electronic device 10 further comprises a controller 18 for controlling the operating parameter (in the example, the voltage V-i) on the basis of the accumulated time estimate so as to respond to the expected wearout effect. It is pointed out that the wearout effect itself is not necessarily detected or determined.
  • the first component 12 may have an on-state correlated to the on-state of the second component 14. More particularly, the electronic device 10 may be such that when the second component 14 is in its on-state, the first component 12 has a probability greater than 50% of being in its on-state. In this case the estimate of the accumulated time the second component 14 was in the on-state may be a particularly reliable estimate of an accumulated time the first component 12 was in the on-state.
  • the controller 18 is configured for increasing the voltage V-i as a function of the accumulated time estimate.
  • the operating parameter may be a voltage correction applied at the first component 12, and the controller 18 may be configured for increasing the voltage correction as a function of the accumulated time estimate. More generally, the operating parameter may be a level or amplitude or correction value of one of the following: a voltage applied at the first component 12, an electric current fed to the first component 12, and a power provided to the first component 12.
  • the electronic device 10 comprises a clock generator (not shown) for generating a clock signal.
  • the time estimator 16 comprises a counter (not shown) which is triggered by the clock signal.
  • the counter has a range of at least t_max/T_clk, where the time t_max is one of the following: one week, one month, three months, one year, three years, ten years, thirty years, and a hundred years.
  • the counter may thus be configured for counting during the entire lifetime without wrapping around to zero.
  • the electronic device 10 may be configured such that the accumulated time estimate is conserved while the electronic device is not powered.
  • the time estimator 16 may comprise a non volatile memory for memorizing the accumulated time estimate.
  • the non-volatile memory may be, for example, a flash memory or an EEPROM.
  • the counter may, for example, be provided by a dedicated counter, e.g. a Secure Real Time Counter (SRTC), in an always-on power domain, or by a dedicated counter coupled to a chip or external memory (e.g. flash memory) for memorizing the count, or by a software counter coupled to a chip or external memory (e.g. flash memory) for memorizing the count.
  • SRTC Secure Real Time Counter
  • the electronic device 10 does not comprise any means for resetting the accumulated time estimate.
  • the electronic device 10 may comprise verification means for verifying whether the accumulated time estimate provided by the time estimator 16 is to be trusted. This can be relevant in view of possible attempts by hackers of resetting a system clock, e.g. a Secure Real Time Counter (SRTC). Such attempts may aim at violating Digital Rights Management (DRM). If the time estimator 16 depends on the SRTC, the accumulated time estimate might be reset by resetting the SRTC.
  • the verification means may comprise a fuse (not shown) that is likely to be blown when a voltage is applied to the time estimator 16. Software can check the state of the fuse (blown or not blown) before working with the accumulated time estimate.
  • the controller 18 comprises a non-volatile memory (not shown) containing data for enabling the controller 18 to determine a nominal value of the operating parameter on the basis of the accumulated time estimate.
  • the data may be provided in the form of, for example, a digital look-up table or a software definition of a mathematical function, e.g. a polynomial or exponential.
  • the controller 18 then controls the DC-DC voltage converter 22 to output an operating voltage V-i substantially equal to the nominal value determined by the controller 18.
  • the controller 18 checks the accumulated time estimate at regular intervals. Depending on the clock period T_clk, those intervals may be considerably larger than the clock period T_clk.
  • the electronic device 10 further comprises a temperature recorder (not shown) for recording values of a temperature of the electronic device 10.
  • Controller 18 is configured for controlling the operating parameter on the basis of both the accumulated time estimate and the recorded temperature values so as to respond to the expected wearout.
  • the operating voltage V-i (or more generally, the operating parameter) can thus be controlled on the basis of a "history" of the temperature.
  • the temperature recorder may comprise a sensor in thermal contact with the first component 12. More generally, it is noted that a physical quantity may have an influence on the wearout effect.
  • the electronic device 10 may therefore comprise a recorder for chronologically recording values of the physical quantity, and the controller 18 may be configured for controlling the operating parameter on the basis of both the accumulated time estimate and the recorded values of the physical quantity so as to respond to the expected wearout effect.
  • the physical quantity may, for example, be a voltage, a frequency, or a temperature.
  • an electronic device 10 in accordance with a second embodiment. It differs substantially from the electronic device 10 discussed above with reference to Figure 3 only in that the first component 12 and the second component 14 are the same. In the example, it is thus the CPU 14 which is susceptible to a wearout effect, and the time estimator 16 provides an estimate of the accumulated time the CPU 12 is in an on-state. Based on the accumulated time estimate, the controller 18 determines a corresponding nominal voltage V-i(t) which is applied to the CPU 12 by the DC-DC converter 22. In both the first and the second embodiments, the dependence of the nominal voltage V-i on the accumulated time t may be predefined as a function of the expected wearout effect.
  • Figure 6 presents data taken from LMX51 measurements on a system on a chip.
  • the total power consumed by the device is the sum of a dynamic power and a leakage power.
  • Graphs 602, 606, and 610 in the plot refer respectively to the total power, the leakage power, and the dynamic power measured in an approach in which the operating voltage (supply voltage) was kept fixed at a high level corresponding to the required minimum voltage near the end of the lifetime of the device ("non-compensated approach").
  • Graphs 604, 608, and 612 analogously indicate, respectively, the total power, the leakage power, and the dynamic power in an approach in which the supply voltage was adapted as a function of an estimated accumulated time as described above with reference to Figures 2 to 5 (“compensated approach").
  • the power follows from a fifty millivolt supply voltage elevation (1.05 volt to 1 volt) required to meet reliability considerations.
  • the dynamic power was obtained from Dhrystone benchmark measurements in a range of 1.05 volt to 1 volt in the compensated approach and at 1 volt in the non-compensated approach.
  • the leakage power was determined at a fast process corner (ff corner) of a 125 degrees Celsius junction (automotive) with an assumed 15 % leakage current due to aging or wearout processes.
  • ff corner fast process corner
  • automotive automotive
  • connections may be a type of connection suitable to transfer signals from or to the respective nodes, units or devices, for example via intermediate devices. Accordingly, unless implied or stated otherwise the connections may for example be direct connections or indirect connections.
  • the operating parameter in the embodiments described above is a voltage
  • the invention is readily applicable to other types of operating parameters, such as electric current, power, electric capacity, and inductivity.
  • the conductors as discussed herein may be illustrated or described in reference to being a single conductor, a plurality of conductors, unidirectional conductors, or bidirectional conductors. However, different embodiments may vary the implementation of the conductors. For example, separate unidirectional conductors may be used rather than bidirectional conductors and vice versa. Also, plurality of conductors may be replaced with a single conductor that transfers multiple signals serially or in a time multiplexed manner. Likewise, single conductors carrying multiple signals may be separated out into various different conductors carrying subsets of these signals. Therefore, many options exist for transferring signals.
  • any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components.
  • any two components so associated can also be viewed as being “operably connected,” or “operably coupled,” to each other to achieve the desired functionality.
  • system 10 are circuitry located on a single integrated circuit or within a same device.
  • system 10 may include any number of separate integrated circuits or separate devices interconnected with each other.
  • controller 18 may be located on a same integrated circuit as components 12 and 14 or on a separate integrated circuit or located within another peripheral or slave discretely separate from other elements of system 10.
  • Voltage provider 20 and DC-DC voltage converter 22 may also be located on separate integrated circuits or devices.
  • system 10 or portions thereof may be soft or code representations of physical circuitry or of logical representations convertible into physical circuitry.
  • system 10 may be embodied in a hardware description language of any appropriate type.
  • the invention is not limited to physical devices or units implemented in nonprogrammable hardware but can also be applied in programmable devices or units able to perform the desired device functions by operating in accordance with suitable program code.
  • the devices may be physically distributed over a number of apparatuses, while functionally operating as a single device.
  • devices functionally forming separate devices may be integrated in a single physical device.
  • any reference signs placed between parentheses shall not be construed as limiting the claim.
  • the word 'comprising' does not exclude the presence of other elements or steps then those listed in a claim.
  • the terms "a” or "an,” as used herein, are defined as one or more than one.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Environmental & Geological Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Quality & Reliability (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

An electronic device (10) comprises a first component (12) susceptible to a wearout effect, operation of which first component (12) depends on an operating parameter (V1), and a second component (14) having an on-state and an off-state. The electronic device (10) further comprises a time estimator (16) for updating an estimate of an accumulated time the second component (14) was in the on-state; and a controller (18) for controlling the operating parameter on the basis of the accumulated time estimate so as to respond to the expected wearout effect. The first component (12) and the second component (14) may be the same, or the first component (12) may have an on-state correlated to the on-state of the second component (14). The operating parameter may, for example, be a level or amplitude or correction value of one of the following: a voltage applied at the first component (12), an electric current fed to the first component (12), and a power provided to the first component (12). A method of operating such an electronic device (10) is also disclosed.

Description

Title: Response to wearout in an electronic device
Description Field of the invention
This invention relates to an electronic device comprising a first component susceptible to a wearout effect, operation of which first component depends on an operating parameter; and a second component having an on-state and an off-state.
The invention also relates to a method of operating such an electronic device.
Background of the invention
Electronic devices and in particular semiconductor devices are often known to be susceptible to wearout effects. A wearout effect in this context is understood to be any long-term variation of the properties of the electronic device that is produced by operating the device. Examples of such wearout phenomena include negative bias temperature instability (NBTI), time-dependent dielectric breakdown (TDDB), hot carriers injection (HCI), and electromigration (EM). Although the mechanisms behind these phenomena are not necessarily fully understood, they are of practical importance, since they may require adapting operating parameters of the electronic device during the lifetime of the device.
For example, wearout effects may manifest themselves by an increase of latency in integrated circuits during the lifetime of the integrated circuit. US 2008/0036487 A1 therefore proposes detecting signal generation latency and generating a wearout response. The wearout response can take a variety of different forms such as reducing the operating frequency, increasing the operating voltage, and others.
Summary of the invention
The present invention provides an electronic device and a method as described in the accompanying claims.
Specific embodiments of the invention are set forth in the dependent claims.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
Brief description of the drawings
Further details, aspects and embodiments of the invention will be described, by way of example only, with reference to the drawings. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
Figure 1 shows a schematic plot of a threshold voltage and an operating voltage as functions of time.
Figure 2 shows a schematic plot of the threshold voltage and an adapted operating voltage as functions of time. Figure 3 shows a schematic outline of an electronic device according to a first embodiment. Figure 4 shows a schematic outline of an electronic device according to a second embodiment.
Figure 5 is a schematic flow chart of a method of adapting an operating voltage.
Figure 6 shows a schematic plot of experimental data illustrating a reduction in power consumption.
Detailed description of the preferred embodiments
Referring to Figure 1 , there is illustrated, by way of example, a threshold voltage Vth of a semiconductor device, e.g. a transistor, as a function of an accumulated time t. The accumulated time t is understood to be the total time during which the device was in an on-state since e.g. fabrication or first use of the device. The threshold voltage Vth is the minimum voltage required for operating the device. In the example, the threshold voltage Vth increases monotonically as a function of the accumulated time t. This behaviour is a typical wearout effect of negative bias temperature instability (NBTI). Other wearout phenomena may result in similar or in different variations of the threshold voltage. In order to operate the device during a specified time interval [0,tmax], where tmax may represent the lifetime of the device, a constant voltage V1 i∞nst may be applied at the device. The constant voltage V1 iConst is chosen greater than a constant minimum voltage Vmin. The minimum voltage Vmin is given by the threshold voltage Vth at accumulated time tmax.
For a given type of device, the wearout behaviour of the threshold voltage Vth, i.e. the function Vth(t), may be known or can be determined, e.g. experimentally. For example, a method of determining NBTI of a p-channel metal-oxide-semiconductor (PMOS) transistor is described in US 2003/0231028 A1.
Alternatively, instead of providing a constant operating voltage V1 iConst, the operating voltage can be adapted to the wearout behaviour of the threshold voltage Vth. This is illustrated with reference to Figure 2. The operating voltage V-i shown therein is controlled as a function of the actual or expected threshold voltage Vth according to V-i(t) = Vth(t) + Δ\/ where Δ\/ is a constant safety margin. The operating voltage V-i thus increases monotonically as prescribed by the threshold voltage Vth. As a consequence, the time-dependent operating voltage V-i is lower than the constant operating voltage V1 i Const described above with reference to Figure 1. A reduction in power consumption during the lifetime of the device can thus be achieved.
It is expected that other applications exist in which an operating parameter (for example, but not necessarily, a voltage) can be advantageously adapted in response to an expected wearout effect. In particular there may be such other applications in which no reduction in power consumption is achieved.
Referring now to Figure 3, there is illustrated an example of an electronic device 10 according to a first embodiment. The electronic device 10 may, for example, be one of the following: an integrated circuit, a microprocessor, a computer processor, a telephone, a navigation device (10), an audio device (10), a video device (10), and any combination thereof. The device 10 comprises a first component 12, a second component 14, a time estimator 16, a controller 18, a DC voltage provider 20, and a DC-DC converter 22. In the example, the first component 12 is an integrated circuit, while the second component 14 is a central processing unit (CPU). The CPU may also be an integrated circuit. In the example, the second component 14 comprises the time estimator 16 and the controller 18. The time estimator 16 and the controller 18 are not necessarily distinct components of the CPU 14, indeed they may represent functionalities of the CPU 14. They may be implemented by dedicated circuitry and/or by software stored in a memory (not shown) of the CPU 14. The DC power provider 20 may be a battery. It provides a constant supply voltage V0 for powering both the CPU 14 and the DC-DC voltage converter 22. The DC-DC voltage converter 22 generates an operating voltage V-i for powering the integrated circuit 12. Operation of the first component 12 thus depends on an operating parameter, namely, the operating voltage V-| .
The first component 12 is susceptible to a wearout effect. The wearout effect may be due to at least one of the following phenomena: negative bias temperature instability (NBTI), time- dependent dielectric breakdown (TDDB), hot carriers injection (HCI), and electromigration (EM). Because of the expected wearout effect, adapting the operating parameter V-i during the lifetime of the device 10 may be advantageous. The following solution is proposed, wherein it is assumed that the second component 14 has an on-state and an off-state. An on-state is a state in which the device in question (here, the second component), is "on" in the sense of "switched on" or "powered" or "active". An off-state is a state in which the device in question is "off" in the sense of "switched off or "inactive" or "not powered". The electronic device 10 comprises a time estimator 16 for updating an estimate of an accumulated time the second component 14 was in the on-state. Restated in a simplified manner, the time estimator counts the total time during which the second device is in the on-state. The electronic device 10 further comprises a controller 18 for controlling the operating parameter (in the example, the voltage V-i) on the basis of the accumulated time estimate so as to respond to the expected wearout effect. It is pointed out that the wearout effect itself is not necessarily detected or determined.
The first component 12 may have an on-state correlated to the on-state of the second component 14. More particularly, the electronic device 10 may be such that when the second component 14 is in its on-state, the first component 12 has a probability greater than 50% of being in its on-state. In this case the estimate of the accumulated time the second component 14 was in the on-state may be a particularly reliable estimate of an accumulated time the first component 12 was in the on-state.
In the example shown, the controller 18 is configured for increasing the voltage V-i as a function of the accumulated time estimate. Alternatively, the operating parameter may be a voltage correction applied at the first component 12, and the controller 18 may be configured for increasing the voltage correction as a function of the accumulated time estimate. More generally, the operating parameter may be a level or amplitude or correction value of one of the following: a voltage applied at the first component 12, an electric current fed to the first component 12, and a power provided to the first component 12. In the example, the electronic device 10 comprises a clock generator (not shown) for generating a clock signal. The clock signal is periodic and has a clock period T_clk = 1/f_clk where f_clk is the clock frequency. The time estimator 16 comprises a counter (not shown) which is triggered by the clock signal. The counter has a range of at least t_max/T_clk, where the time t_max is one of the following: one week, one month, three months, one year, three years, ten years, thirty years, and a hundred years. The counter may thus be configured for counting during the entire lifetime without wrapping around to zero. Furthermore, the electronic device 10 may be configured such that the accumulated time estimate is conserved while the electronic device is not powered. To this end, the time estimator 16 may comprise a non volatile memory for memorizing the accumulated time estimate. The non-volatile memory may be, for example, a flash memory or an EEPROM. The counter may, for example, be provided by a dedicated counter, e.g. a Secure Real Time Counter (SRTC), in an always-on power domain, or by a dedicated counter coupled to a chip or external memory (e.g. flash memory) for memorizing the count, or by a software counter coupled to a chip or external memory (e.g. flash memory) for memorizing the count.
In an exemplary embodiment, the electronic device 10 does not comprise any means for resetting the accumulated time estimate. Furthermore, the electronic device 10 may comprise verification means for verifying whether the accumulated time estimate provided by the time estimator 16 is to be trusted. This can be relevant in view of possible attempts by hackers of resetting a system clock, e.g. a Secure Real Time Counter (SRTC). Such attempts may aim at violating Digital Rights Management (DRM). If the time estimator 16 depends on the SRTC, the accumulated time estimate might be reset by resetting the SRTC. The verification means may comprise a fuse (not shown) that is likely to be blown when a voltage is applied to the time estimator 16. Software can check the state of the fuse (blown or not blown) before working with the accumulated time estimate.
In the example, the controller 18 comprises a non-volatile memory (not shown) containing data for enabling the controller 18 to determine a nominal value of the operating parameter on the basis of the accumulated time estimate. The data may be provided in the form of, for example, a digital look-up table or a software definition of a mathematical function, e.g. a polynomial or exponential. The controller 18 then controls the DC-DC voltage converter 22 to output an operating voltage V-i substantially equal to the nominal value determined by the controller 18. According to a specific embodiment, the controller 18 checks the accumulated time estimate at regular intervals. Depending on the clock period T_clk, those intervals may be considerably larger than the clock period T_clk.
In the present example, the electronic device 10 further comprises a temperature recorder (not shown) for recording values of a temperature of the electronic device 10. Controller 18 is configured for controlling the operating parameter on the basis of both the accumulated time estimate and the recorded temperature values so as to respond to the expected wearout. The operating voltage V-i (or more generally, the operating parameter) can thus be controlled on the basis of a "history" of the temperature. The temperature recorder may comprise a sensor in thermal contact with the first component 12. More generally, it is noted that a physical quantity may have an influence on the wearout effect. The electronic device 10 may therefore comprise a recorder for chronologically recording values of the physical quantity, and the controller 18 may be configured for controlling the operating parameter on the basis of both the accumulated time estimate and the recorded values of the physical quantity so as to respond to the expected wearout effect. The physical quantity may, for example, be a voltage, a frequency, or a temperature.
Referring now to Figure 4, there is shown an electronic device 10 in accordance with a second embodiment. It differs substantially from the electronic device 10 discussed above with reference to Figure 3 only in that the first component 12 and the second component 14 are the same. In the example, it is thus the CPU 14 which is susceptible to a wearout effect, and the time estimator 16 provides an estimate of the accumulated time the CPU 12 is in an on-state. Based on the accumulated time estimate, the controller 18 determines a corresponding nominal voltage V-i(t) which is applied to the CPU 12 by the DC-DC converter 22. In both the first and the second embodiments, the dependence of the nominal voltage V-i on the accumulated time t may be predefined as a function of the expected wearout effect.
Referring now to Figure 5, a method of operating an electronic device 10 as discussed above with reference to Figures 3 and 4 comprises: providing an estimate of an accumulated time the second component 14 was in the on-state; and controlling the operating parameter on the basis of the accumulated time estimate so as to respond to the expected wearout effect. If the second device 14 is in its on-state (step S1 ), a counter in the time estimator advances by one (step S2). An accumulated time estimate t is determined as t:=N T_clk (step S3). Based on the accumulated time estimate t thus determined, a nominal voltage V-i(t) is determined (step S4). The nominal voltage V-i(t) may be a predefined function of t. In subsequent step S5, the thus determined voltage V-i(t) is applied at the first component 12. The process then returns to step S1.
Figure 6 presents data taken from LMX51 measurements on a system on a chip. The total power consumed by the device is the sum of a dynamic power and a leakage power. Graphs 602, 606, and 610 in the plot refer respectively to the total power, the leakage power, and the dynamic power measured in an approach in which the operating voltage (supply voltage) was kept fixed at a high level corresponding to the required minimum voltage near the end of the lifetime of the device ("non-compensated approach"). Graphs 604, 608, and 612 analogously indicate, respectively, the total power, the leakage power, and the dynamic power in an approach in which the supply voltage was adapted as a function of an estimated accumulated time as described above with reference to Figures 2 to 5 ("compensated approach"). In both approaches, the power follows from a fifty millivolt supply voltage elevation (1.05 volt to 1 volt) required to meet reliability considerations. The dynamic power was obtained from Dhrystone benchmark measurements in a range of 1.05 volt to 1 volt in the compensated approach and at 1 volt in the non-compensated approach. The leakage power was determined at a fast process corner (ff corner) of a 125 degrees Celsius junction (automotive) with an assumed 15 % leakage current due to aging or wearout processes. Clearly, the compensated approach results in reduced power consumption as compared to the compensated approach. In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims. For example, the connections may be a type of connection suitable to transfer signals from or to the respective nodes, units or devices, for example via intermediate devices. Accordingly, unless implied or stated otherwise the connections may for example be direct connections or indirect connections.
While the operating parameter in the embodiments described above is a voltage, the invention is readily applicable to other types of operating parameters, such as electric current, power, electric capacity, and inductivity.
The conductors as discussed herein may be illustrated or described in reference to being a single conductor, a plurality of conductors, unidirectional conductors, or bidirectional conductors. However, different embodiments may vary the implementation of the conductors. For example, separate unidirectional conductors may be used rather than bidirectional conductors and vice versa. Also, plurality of conductors may be replaced with a single conductor that transfers multiple signals serially or in a time multiplexed manner. Likewise, single conductors carrying multiple signals may be separated out into various different conductors carrying subsets of these signals. Therefore, many options exist for transferring signals.
Because the apparatus implementing the present invention is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details have not been explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.
Although the invention has been described with respect to specific conductivity types or polarity of potentials, skilled artisans appreciated that conductivity types and polarities of potentials may be reversed.
Some of the above embodiments, as applicable, may be implemented using a variety of different information processing systems. For example, although Figure 3 and the discussion thereof describe an exemplary information processing architecture, this exemplary architecture is presented merely to provide a useful reference in discussing various aspects of the invention. Of course, the description of the architecture has been simplified for purposes of discussion, and it is just one of many different types of appropriate architectures that may be used in accordance with the invention. Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements.
Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. In an abstract, but still definite sense, any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as "associated with" each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being "operably connected," or "operably coupled," to each other to achieve the desired functionality.
Also for example, in one embodiment, the illustrated elements of system 10 are circuitry located on a single integrated circuit or within a same device. Alternatively, system 10 may include any number of separate integrated circuits or separate devices interconnected with each other. For example, controller 18 may be located on a same integrated circuit as components 12 and 14 or on a separate integrated circuit or located within another peripheral or slave discretely separate from other elements of system 10. Voltage provider 20 and DC-DC voltage converter 22 may also be located on separate integrated circuits or devices. Also for example, system 10 or portions thereof may be soft or code representations of physical circuitry or of logical representations convertible into physical circuitry. Thus, system 10 may be embodied in a hardware description language of any appropriate type.
Furthermore, those skilled in the art will recognize that boundaries between the functionality of the above described operations merely illustrative. The functionality of multiple operations may be combined into a single operation, and/or the functionality of a single operation may be distributed in additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.
Also, the invention is not limited to physical devices or units implemented in nonprogrammable hardware but can also be applied in programmable devices or units able to perform the desired device functions by operating in accordance with suitable program code. Furthermore, the devices may be physically distributed over a number of apparatuses, while functionally operating as a single device. Also, devices functionally forming separate devices may be integrated in a single physical device.
However, other modifications, variations and alternatives are also possible. The specifications and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.
In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word 'comprising' does not exclude the presence of other elements or steps then those listed in a claim. Furthermore, the terms "a" or "an," as used herein, are defined as one or more than one. Also, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an." The same holds true for the use of definite articles. Unless stated otherwise, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

Claims
1 . An electronic device (10) comprising
a first component (12) susceptible to a wearout effect, operation of which first component
(12) depends on an operating parameter (V1 );
a second component (14) having an on-state and an off-state;
a time estimator (16) for updating an estimate of an accumulated time the second component (14) was in the on-state; and
a controller (18) for controlling the operating parameter on the basis of the accumulated time estimate so as to respond to the expected wearout effect.
2. The electronic device (10) as set forth in claim 1 , wherein the first component (12) and the second component (14) are the same, or wherein the first component (12) has an on-state correlated to the on-state of the second component (14).
3. The electronic device (10) as set forth in claim 1 or 2, wherein the operating parameter is a level or amplitude or correction value of one of the following: a voltage applied at the first component (12), an electric current fed to the first component (12), and a power provided to the first component (12).
4. The electronic device (10) as set forth in any of the preceding claims, wherein the operating parameter is a voltage or voltage correction applied at the first component (12), and the controller (18) is configured for increasing the voltage or voltage correction as a function of the accumulated time estimate.
5. The electronic device (10) as set forth in any of the preceding claims, wherein the time estimator (16) comprises a counter for being triggered by a clock signal.
6. The electronic device (10) as set forth in claim 5, wherein the electronic device (10) comprises a clock generator for generating the clock signal, the clock signal having a clock period T_clk, and the counter having a range of at least t_max / T_clk, where the time t_max is one of the following: one week, one month, three months, one year, three years, ten years, thirty years, and a hundred years.
7. The electronic device (10) as set forth in any of the preceding claims, configured such that the accumulated time estimate is conserved while the electronic device (10) is not powered.
8. The electronic device (10) as set forth in any of the preceding claims, wherein the time estimator (16) comprises a non-volatile memory for memorizing the accumulated time estimate.
9. The electronic device (10) as set forth in any of the preceding claims, wherein the electronic device (10) does not comprise any means for resetting the accumulated time estimate.
10. The electronic device (10) as set forth in any of the preceding claims, wherein the controller (18) comprises a non-volatile memory containing data for enabling the controller (18) to determine a nominal value of the operating parameter on the basis of the accumulated time estimate.
1 1. The electronic device (10) as set forth in any of the preceding claims, wherein the wearout effect is due to at least one of the following phenomena: negative bias temperature instability (NBTI), time-dependent dielectric breakdown (TDDB), hot carriers injection (HCI), and electromigration (EM).
12. The electronic device (10) as set forth in any of the preceding claims, wherein a physical quantity has an influence on the wearout effect and the electronic device (10) comprises a recorder for chronologically recording values of the physical quantity, and wherein the controller (18) is configured for controlling the operating parameter on the basis of both the accumulated time estimate and the recorded values of the physical quantity so as to respond to the expected wearout effect.
13. The electronic device (10) as set forth in any of the preceding claims, wherein the electronic device (10) is configured for being powered by a battery (20).
14. The electronic device (10) as set forth in any of the preceding claims, wherein the electronic device (10) is one of the following: an integrated circuit, a microprocessor, a computer processor, a telephone, a navigation device (10), an audio device (10), a video device (10), and any combination thereof.
15. A method of operating an electronic device (10), wherein the electronic device (10) comprises
a first component (12) susceptible to a wearout effect, operation of which first component (12) depends on an operating parameter; and
a second component (14) having an on-state and an off-state;
wherein the method comprises
providing an estimate of an accumulated time the second component (14) was in the on- state; and
controlling the operating parameter on the basis of the accumulated time estimate so as to respond to the expected wearout effect.
PCT/IB2009/054942 2009-11-06 2009-11-06 Response to wearout in an electronic device WO2011055169A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN200980162323.8A CN102597906B (en) 2009-11-06 2009-11-06 To the response of the loss in electron device
US13/500,700 US8698552B2 (en) 2009-11-06 2009-11-06 Response to wearout in an electronic device
EP09851059.7A EP2496999B1 (en) 2009-11-06 2009-11-06 Response to wearout in an electronic device
PCT/IB2009/054942 WO2011055169A1 (en) 2009-11-06 2009-11-06 Response to wearout in an electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2009/054942 WO2011055169A1 (en) 2009-11-06 2009-11-06 Response to wearout in an electronic device

Publications (1)

Publication Number Publication Date
WO2011055169A1 true WO2011055169A1 (en) 2011-05-12

Family

ID=43969609

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2009/054942 WO2011055169A1 (en) 2009-11-06 2009-11-06 Response to wearout in an electronic device

Country Status (4)

Country Link
US (1) US8698552B2 (en)
EP (1) EP2496999B1 (en)
CN (1) CN102597906B (en)
WO (1) WO2011055169A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103197717B (en) * 2013-02-28 2015-11-25 华为技术有限公司 Adaptive voltage method of adjustment, chip and system
US9378803B2 (en) * 2013-03-15 2016-06-28 Qualcomm Incorporated System and method to regulate operating voltage of a memory array
DE102015116094A1 (en) 2015-09-23 2017-03-23 Intel IP Corporation An apparatus and method for predicting a future state of an electronic component
CN108074368B (en) * 2016-11-11 2021-05-07 基德科技公司 Fiber-based monitoring of temperature and/or smoke conditions at electronic components
EP3444691B1 (en) * 2017-06-27 2021-09-15 Schneider Electric Systems USA, Inc. Sensor service prediction

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6775624B2 (en) * 2001-10-19 2004-08-10 International Business Machines Corporation Method and apparatus for estimating remaining life of a product
US20050188230A1 (en) * 2004-02-20 2005-08-25 International Business Machines Corporation System and method of controlling power consumption in an electronic system
US20080036487A1 (en) * 2006-08-09 2008-02-14 Arm Limited Integrated circuit wearout detection
WO2008066058A1 (en) * 2006-11-30 2008-06-05 Kabushiki Kaisha Toshiba Memory system

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6476632B1 (en) 2000-06-22 2002-11-05 International Business Machines Corporation Ring oscillator design for MOSFET device reliability investigations and its use for in-line monitoring
US6653856B1 (en) 2002-06-12 2003-11-25 United Microelectronics Corp. Method of determining reliability of semiconductor products
US20060049886A1 (en) * 2004-09-08 2006-03-09 Agostinelli Victor M Jr On-die record-of-age circuit
US7592876B2 (en) * 2005-12-08 2009-09-22 Intel Corporation Leakage oscillator based aging monitor
GB2440764B (en) * 2006-08-09 2011-03-02 Advanced Risc Mach Ltd Integrated circuit wearout detection
US7689377B2 (en) * 2006-11-22 2010-03-30 Texas Instruments Incorporated Technique for aging induced performance drift compensation in an integrated circuit
FR2912257B1 (en) * 2007-02-02 2009-03-06 Commissariat Energie Atomique METHOD AND CIRCUIT FOR IMPROVING THE LIFETIME OF FIELD EFFECT TRANSISTORS
US7581201B2 (en) 2007-02-28 2009-08-25 International Business Machines Corporation System and method for sign-off timing closure of a VLSI chip
US20090160515A1 (en) 2007-12-19 2009-06-25 James Douglas Warnock Auto-tracking clock circuitry
US8098536B2 (en) * 2008-01-24 2012-01-17 International Business Machines Corporation Self-repair integrated circuit and repair method
US8248095B2 (en) * 2009-10-30 2012-08-21 Apple Inc. Compensating for aging in integrated circuits

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6775624B2 (en) * 2001-10-19 2004-08-10 International Business Machines Corporation Method and apparatus for estimating remaining life of a product
US20050188230A1 (en) * 2004-02-20 2005-08-25 International Business Machines Corporation System and method of controlling power consumption in an electronic system
US20080036487A1 (en) * 2006-08-09 2008-02-14 Arm Limited Integrated circuit wearout detection
WO2008066058A1 (en) * 2006-11-30 2008-06-05 Kabushiki Kaisha Toshiba Memory system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2496999A4 *

Also Published As

Publication number Publication date
EP2496999A4 (en) 2013-04-24
EP2496999A1 (en) 2012-09-12
CN102597906B (en) 2016-02-03
US20120206183A1 (en) 2012-08-16
US8698552B2 (en) 2014-04-15
CN102597906A (en) 2012-07-18
EP2496999B1 (en) 2014-06-04

Similar Documents

Publication Publication Date Title
US10110060B2 (en) Semiconductor device
CN109390903B (en) Digital line protection with power supply voltage droop safety
KR100824828B1 (en) Method for verifying smart battery failures by measuring input charging voltage and associated system
EP2496999B1 (en) Response to wearout in an electronic device
US9275718B2 (en) Semiconductor devices with periodic signal generation circuits and semiconductor systems including the same
CN106575515B (en) Dynamic margin for controlling custom circuit and memory tunes
KR101443419B1 (en) Method and circuit for preventing high voltage memory disturb
US9246323B2 (en) Current controller and protection circuit
US20050201188A1 (en) Method and apparatus for improving performance margin in logic paths
KR101782137B1 (en) Power on reset circuit
US20110181315A1 (en) Adaptive Device Aging Monitoring and Compensation
US20150124544A1 (en) Semiconductor devices and semiconductor systems including the same
EP2954615A1 (en) Integrated circuit identification and dependability verification using ring oscillator based physical unclonable function and age detection circuitry
US9519013B2 (en) Mode-controlled voltage excursion detector apparatus and a method of operating thereof
TWI514410B (en) Current providing circuit and voltage providing circuit
WO2013095429A1 (en) Apparatus, method, and system for adaptive compensation of reverse temperature dependence
US20150130502A1 (en) Circuit and method for detecting a fault attack
JP5581147B2 (en) Monitoring the operation of electronic circuits
US20190072588A1 (en) Low-power voltage detection circuit
US20130093486A1 (en) Integrated circuit having latch-up recovery circuit
US7145823B2 (en) Method and apparatus to implement a temperature control mechanism on a memory device
US20120229183A1 (en) Power-on reset circuit and electronic device having the same
US20120187985A1 (en) Low Power Brown Out Detector
US9048661B2 (en) Battery protection circuits
CA3038145C (en) Power management integrated circuit

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200980162323.8

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09851059

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 13500700

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 2009851059

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE