WO2011046373A2 - Non-contact type light emitting diode - Google Patents

Non-contact type light emitting diode Download PDF

Info

Publication number
WO2011046373A2
WO2011046373A2 PCT/KR2010/007038 KR2010007038W WO2011046373A2 WO 2011046373 A2 WO2011046373 A2 WO 2011046373A2 KR 2010007038 W KR2010007038 W KR 2010007038W WO 2011046373 A2 WO2011046373 A2 WO 2011046373A2
Authority
WO
WIPO (PCT)
Prior art keywords
layer
electrode
light emitting
emitting diode
clad
Prior art date
Application number
PCT/KR2010/007038
Other languages
French (fr)
Korean (ko)
Other versions
WO2011046373A3 (en
Inventor
홍진표
이종현
남혜원
이상효
이준석
Original Assignee
한양대학교 산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 한양대학교 산학협력단 filed Critical 한양대학교 산학협력단
Publication of WO2011046373A2 publication Critical patent/WO2011046373A2/en
Publication of WO2011046373A3 publication Critical patent/WO2011046373A3/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • H01L33/18—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate

Definitions

  • the present invention relates to a light emitting diode, and more particularly to a light emitting diode having a conical photoactive layer.
  • a light emitting diode is a device that emits light by recombination of electrons and holes in a photoactive layer. Ideally, the recombination of electrons and holes occurs by direct transition, but in the form of indirect transitions where some energy is converted to heat within the actual crystal structure.
  • the power supply to the light emitting diode is in the form of DC. That is, a DC voltage having a constant level is supplied through rectification and decompression of the supplied AC power, through which the light emitting diode performs a light emitting operation.
  • An object of the present invention for solving the above problems is to provide a light emitting diode having a cone-shaped photoactive layer formed inside the pinhole.
  • the first electrode formed on the substrate; A first clad layer formed on the first electrode; An insulating layer formed on the first clad layer; A pin hole penetrating the insulating layer; A photoactive layer formed in the pin hole and formed on the first clad layer; A second clad clad layer formed on the photoactive layer; And it provides a light emitting diode comprising a second electrode formed on the insulating layer.
  • the present invention for achieving the above object, the first electrode formed on the substrate; An insulating layer formed on the first electrode; An under cut pin hole penetrating the insulating layer; A first clad layer formed in the pin hole and formed on the first electrode; A photoactive layer formed on the first clad layer; A second clad clad layer formed on the photoactive layer; And it provides a light emitting diode comprising a second electrode formed on the insulating layer.
  • the above object of the present invention is also achieved through the provision of a light emitting diode in which a plurality of pin holes are formed on the same substrate, and a photoactive layer formed in each pin hole through two electrodes performs a light emitting operation.
  • the second clad layer and the second electrode have a non-contact state.
  • the discharge phenomenon can be induced, and high voltage power can be directly used for the light emitting diode.
  • FIG. 1 is a perspective view showing a light emitting diode according to a first embodiment of the present invention.
  • FIG. 2 to 5 are cross-sectional views illustrating a method of manufacturing the light emitting diode shown in FIG. 1 according to the first embodiment of the present invention.
  • FIG. 6 is a cross-sectional view illustrating a light emitting diode according to a second embodiment of the present invention.
  • FIG. 7 is a cross-sectional view showing another light emitting diode according to the present invention.
  • FIG. 1 is a perspective view showing a light emitting diode according to a first embodiment of the present invention.
  • the first electrode 110 and the first cladding layer 120 are sequentially formed on the substrate 100.
  • An insulating layer 130 is formed on the first cladding layer 120, and a plurality of pin holes 140 are formed in the insulating layer 130.
  • the photoactive layer 150 and the second cladding layer 160 are formed in the inner space of the pinhole 140.
  • the photoactive layer 150 is formed on the first clad layer 120 inside the pinhole 140, and the second clad layer 160 has a substantially conical shape and is formed on the photoactive layer 150. .
  • a second electrode 170 is formed on the insulating layer 130, and the second electrode 170 is formed on the insulating layer 130 except for the pin holes 140.
  • the substrate 100 is an insulating material, and the deformation is not generated by the formation of the electrodes 110 and 170, the cladding layers 120 and 160, and the photoactive layer 150 in a subsequent manufacturing process. Anything you have will be possible. Therefore, when light generated in the photoactive layer 150 must pass through the substrate 100, sapphire, zinc oxide, silicon carbide, glass, or the like may be used, and the light may be formed in the open space of the pin-hole 140. When emitted through the outside, a material having a predetermined reflectance can be used. For example, a silicon substrate may be used. In the case of using a silicon substrate, silicon oxide may be interposed between the silicon substrate and the first electrode 110.
  • the first electrode 110 is formed on the substrate 100.
  • the first electrode 110 is formed over the entire surface of the substrate 100.
  • the first electrode 110 may be any conductive material, as long as it is a material capable of electrically contacting the first cladding layer 120 with the ohmic contact.
  • the first electrode 110 may be variously selected according to the conductivity type of the first cladding layer 120 formed thereafter, but considering a wire bonding process that may occur in a packaging process, an appropriate metallic material may be used. Is preferably selected.
  • the first clad layer 120 is formed on the first electrode 110.
  • the first clad layer 120 may have an n-type or p-type conductivity.
  • the first cladding layer 120 may be gallium nitride-based or zinc oxide-based.
  • an insulating layer 130 is formed on the first cladding layer 120.
  • the insulating layer 130 may be any insulating material, but is preferably selected as a material suitable for forming the pin hole 140.
  • the pinhole 140 formed through the insulating layer 130 is formed by etching the insulating layer 130. Therefore, the insulating layer 130 should be selected of a material having a chemical composition different from that of the lower first cladding layer 120.
  • the insulating layer 130 is made of silicon oxide.
  • an insulator having a predetermined reflectance can be used in addition to the above.
  • the insulating layer 130 should have an etching selectivity with the lower first cladding layer 120.
  • the photoactive layer 150 and the second cladding layer 160 are formed in the pinhole 140 penetrating the insulating layer 130.
  • the photoactive layer 150 has a structure for performing a light emitting operation. Therefore, it may be formed of an intrinsic semiconductor, and may be formed of a quantum dot structure or a multi-quantum well structure. For example, when a multi-quantum well structure is employed in the photoactive layer 150 and the first cladding layer 120 and the second cladding layer 160 are gallium nitride series, the photoactive layer 150 is a gallium nitride barrier layer. Indium gallium nitride may be used as the well layer.
  • the conical second cladding layer 160 is formed on the photoactive layer 150.
  • the second clad layer 160 has a conductivity type complementary to the first clad layer 120. That is, when the first cladding layer 120 is p-type, the second cladding layer 160 is n-type, and when the first cladding layer 120 is n-type, the second cladding layer 160 is p-type. It consists of.
  • the second electrode 170 is formed on the insulating layer 130.
  • the second electrode 170 is formed over the insulating layer 130 other than the pin hole 140. That is, the second electrode 170 is formed to open the upper portion of the pin hole 140.
  • FIG. 2 to 5 are cross-sectional views illustrating a method of manufacturing the light emitting diode shown in FIG. 1 according to the first embodiment of the present invention.
  • the first electrode 110, the first cladding layer 120, and the insulating layer 130 are sequentially stacked on the substrate 100.
  • the first electrode 110 is preferably composed of Ti / Au or Cr / Au, and when the first cladding layer 120 is p-type, Ni / Au or Cr Preferably composed of / Au.
  • Au is preferably formed first, and Ti or Cr is formed on the Au.
  • the light emitting diode when the light emitting diode is formed of gallium nitride series and has n-type conductivity, a group IV element such as Si is used as the dopant. Moreover, when it has p-type conductivity, group II elements, such as Mg, are used as a dopant.
  • the light emitting diode of the present embodiment is composed of zinc oxide series and has n-type conductivity
  • a group IIIA or IVA element is used as a dopant
  • a group IIIA or IIA element is used. It is preferably used as a dopant.
  • the first clad layer 120 may be formed through various methods, but it is preferable to use a MOCVD process.
  • the insulating layer 130 may be any non-conductive material as long as the material has an etching selectivity with the first clad layer 120.
  • the pin hole 140 is formed by etching the insulating layer 130.
  • the pin hole 140 penetrates the insulating layer 130 and is formed to expose a portion of the surface of the lower first clad layer 120.
  • the pin hole 140 is preferably formed by etching the insulating layer 130 in the shape of an undercut.
  • a photoresist is applied to the entire insulating layer 130, and a photoresist pattern for opening the region where the pinhole 140 is to be formed using a conventional photolithography process is used.
  • the pin hole 140 is formed by performing etching using the formed photoresist pattern as an etching mask.
  • the pin hole 140 preferably has an undercut shape.
  • the etching may use wet etching. In the case of using dry etching, the etching may be performed after the inclination at a predetermined angle rather than arranging the substrate on which the insulating layer 130 is formed perpendicular to the etching direction of the etching gas.
  • Forming the pinhole 140 in the form of an undercut is that the material constituting the photoactive layer 150 or the second cladding layer 160 is attached to the sidewalls of the pinhole 140 in a process of forming a film later. This is to minimize the phenomenon.
  • the photoactive layer 150 and the second cladding layer 160 are formed in the pinhole 140 formed in the form of under cut.
  • a material constituting the photoactive layer 150 is applied to the entire surface of the substrate on which the pinhole 140 is formed. If the photoactive layer 150 has a multi-quantum well structure, the barrier layer and the well layer are alternately formed. At this time, the barrier layer has a relatively high band gap and the well layer has a relatively low band gap, thereby exhibiting a quantum confinement effect.
  • the photoactive layer 150 described above is formed on the surface of the insulating layer 130, and is also formed in the undercut fin hole 140. However, the photoactive layer 150 formed inside the pinhole 140 due to the undercut shape is formed in a structure in which contact with the sidewall of the insulating layer 130 is avoided.
  • the second cladding layer 160 is formed on the previously formed photoactive layer 150.
  • the second clad layer 160 has a complementary conductivity with that of the first clad layer 120. That is, when the first cladding layer 120 is n-type, the second cladding layer 160 is p-type, and when the first cladding layer 120 is p-type, the second cladding layer 160 is n-type. It consists of.
  • the dopant according to the material and conductivity of the second cladding layer 160 is the same as described in the first cladding layer 120.
  • the second cladding layer 160 has a substantially conical shape. This is due to the phenomenon that the inlet of the pinhole 140 is reduced by the material forming the photoactive layer 150 formed on the insulating layer 130 and the material forming the second cladding layer 160.
  • the formation of the photoactive layer 150 and the second cladding layer 160 in the pinhole 140 is caused by the shape of the pinhole 140 having an undercut. That is, the photoactive layer 150 and the second cladding layer 160 are prevented from contacting the inner sidewall of the insulating layer 130 by the undercut pin hole 140, and the second cladding layer 160 is conical. It will have the shape of.
  • the material of the photoactive layer 150 and the material of the second cladding layer 160 remaining on the insulating layer 130 formed in FIG. 4 are removed. Removal of the film remaining on the insulating layer 130 is performed by chemical mechanical polishing or etching. Chemical mechanical polishing proceeds until the surface of the insulating layer 130 is exposed to remove the film on the insulating layer 130. In addition, the etching may be performed by dry etching or wet etching. However, during the etching process, the photoresist may remain in the pinhole 140 to act as an etching mask.
  • the second electrode 170 is formed on the insulating layer 130.
  • the second electrode 170 may be any conductive material, but is preferably made of Cu or Au.
  • the second electrode 170 is coated on the insulating layer 130 except for the pin hole 140.
  • Deposition masks may be used for this selective application, and lift off techniques through photoresist may be used.
  • the lift-off technique can be configured as follows.
  • photoresist is applied to the entire surface of the substrate on which the photoactive layer 150 and the second clad layer 160 are formed in the pin hole 140.
  • the photoresist is applied to fill the inside of the pin hole 140 and have a predetermined height from the insulating layer 130.
  • the photoresist formed in the upper region of the pin hole 140 is left, and the photoresist formed in the upper region of the insulating layer 130 is removed.
  • the film materials formed on the insulating layer 130 of FIG. 4 are removed by chemical mechanical polishing or the like. Therefore, the surface of the insulating layer 130 is exposed by removing the photoresist.
  • an electrode material is applied to the substrate in which the photoresist remains only on the pinhole 140 region. Subsequently, when the remaining photoresist is removed through etching, the electrode material formed on the photoresist formed on the pinhole 140 region is also removed. Accordingly, the second electrode 170 in which only the electrode material on the insulating layer 130 remains is formed.
  • one of the two electrodes 110 and 170 for supplying power to the photoactive layer 150 and the clad layers 120 and 160 is in contact with the clad layer. That is, in the present embodiment, the second clad layer 160 and the second electrode 170 are configured to be in physically non-contact state.
  • the second cladding layer 160 has a substantially conical shape, when a predetermined potential difference is applied to the first electrode 110 and the second electrode 170, Concentration of the electric field occurs at the end of the cone, which is the second cladding layer 160. The concentration of the electric field causes an electrostatic discharge phenomenon between the second cladding layer 160 and the non-contact second electrode 170. Therefore, charges are transferred from the second cladding layer 160 to the second electrode 170 or transmitted from the second electrode 170 to the second cladding layer 160 by the electrostatic discharge phenomenon.
  • the technical configuration of the present invention is to connect the power of 110V or 220V directly to the electrode of the light emitting diode to perform the light emitting operation. That is, the electrostatic discharge phenomenon may occur when the voltage applied is a high voltage.
  • the generated electric field induces a discharge phenomenon between the second cladding layer 160 and the second electrode 170, and thus the first electrode 110 and the first electrode 110.
  • a current flows between the second electrodes 170.
  • recombination of electrons and holes occurs in the photoactive layer 150 through the flow of current, and light emission is performed.
  • a plurality of pin holes 140 may be provided on the substrate 100. Therefore, the photoactive layer 150 and the second cladding layer 160 inside the pin hole 140 are also provided in plural on the substrate 100. Therefore, a plurality of light emitting diodes that perform light emitting operations on one substrate 100 is provided. That is, the first electrode 110 is formed on the entire surface of the substrate 100, is connected to the first cladding layer 120 of each light emitting diode, and the second electrode 170 is also an insulating layer on the substrate 100. 130 is formed on the entire surface. Accordingly, the plurality of photoactive layers may be driven by the two electrodes 110 and 170. Through this, high brightness of the light emitting diode can be realized.
  • phosphors may be individually applied to each pin hole.
  • the phosphor may be applied to a specific film surface, and the entire film may be attached to the front surface of the substrate to implement a specific color.
  • FIG. 6 is a cross-sectional view illustrating a light emitting diode according to a second embodiment of the present invention.
  • a first electrode 210 is formed on a substrate 200.
  • An insulating layer 220 is formed on the first electrode 210, and a plurality of pin holes 230 penetrating the insulating layer 220 are formed.
  • the first cladding layer 240, the photoactive layer 250, and the second cladding layer 260 are formed in the internal space of the pinhole 230.
  • the light emitting diode of FIG. 6 has the same structure as that of the first embodiment except that the first cladding layer 240 is provided inside the pin hole 230. Therefore, the first cladding layer 240 has a feature that is individually provided for each pin hole 230.
  • the method of manufacturing the light emitting diode illustrated in FIG. 6 includes forming the first electrode 210, forming the insulating layer 220, forming the pin hole 230, and forming the pin hole 230 on the substrate 200.
  • the first cladding layer 240, the photoactive layer 250, and the second cladding layer 260 are sequentially formed, and the second electrode 270 is formed on the insulating layer 220.
  • the first cladding layer 120 is stacked on the first electrode 110, and the plurality of pinholes 140 are disposed on the first cladding layer 120, and each pin hole is disposed.
  • the structure in which the photoactive layer 150 and the second cladding layer 160 are disposed inside the 140 is disclosed.
  • a plurality of pin holes 230 are disposed on the first electrode 210, and the first clad layer 240, the photoactive layer 250, and the first cladding hole 230 are disposed in the respective pin holes 230.
  • the cladding layer 260 is disposed.
  • the first electrode 210 is entirely coated on the substrate 200, and the insulating layer 220 is formed on the formed first electrode 210. Subsequently, a plurality of under cut pin holes 230 are formed through selective etching of the insulating layer 220.
  • the first cladding layer 240, the photoactive layer 250, and the second cladding layer 260 are sequentially formed using a conventional deposition process.
  • the first cladding layer, the photoactive layer, and the second cladding layer applied on the insulating layer 220 are removed. If the second electrode 270 is formed on the insulating layer 220 from which the films are removed, the light emitting diode illustrated in FIG. 6 may be manufactured.
  • the substrate 200, the electrodes 210 and 270, the clad layers 240 and 260, the insulating layer 220, and the photoactive layer 250 disclosed in FIG. 6 may be made of the same material as described in the first embodiment. Form.
  • a process of removing the photoactive layer and the clad layer formed on the insulating layer has been described, but the process may be omitted. That is, the second electrode may be formed in a state where the photoactive layer, the cladding layer, etc. formed on the insulating layer remain.
  • FIG. 7 is a cross-sectional view showing another light emitting diode according to the present invention.
  • the substrate 300, the first electrode 310, the clad layers 340 and 360, the insulating layer 370, and the photoactive layer 350 are the same as illustrated in FIGS. 5 and 6.
  • the second electrode 370 has the characteristics of a transparent electrode, and the second cladding layer 360 is in physical contact with the second electrode 370. Therefore, the light emitting diode shown in FIG. 7 may be driven using a DC power supply.
  • the second electrode may be an inorganic conductive oxide film such as ITO, IZO, or TO (Tin Oxide), or may be an organic conductive film such as polyaniline.
  • the second clad layer and the second electrode are formed in a non-contact state. Therefore, there is an advantage that the high voltage can be directly used compared to the conventional contact type light emitting diode. In addition, if combined with an appropriate stop, it has the advantage that the light emitting operation can be performed by connecting directly to the AC power source.
  • the second clad layer and the second electrode may be implemented in a contact state, and may be driven using a DC power supply.

Abstract

Disclosed is a light emitting diode with an electrode and a clad layer which are not in contact with each other. A first electrode is formed on a substrate and a first clad layer is formed on an upper part of the first electrode. A plurality of pin holes are formed by selectively etching an insulating layer formed on an upper part of the first clad layer. A photoactive layer is formed in an inside of each pin hole and a second clad layer is formed on an upper part of the photoactive layer. A second electrode is formed on an upper part of the insulating layer and the second clad layer and the second electrode are not in contact with each other. A high voltage can be applied to a light emitting diode therethrough. In addition, the present invention can obtain high luminance by forming a plurality of individual light emitting structures in a narrow area.

Description

비접촉 타입의 발광 다이오드Non-contact type light emitting diode
본 발명은 발광 다이오드에 관한 것으로, 더욱 상세하게는 원뿔 모양의 광활성층을 가지는 발광 다이오드에 관한 것이다.The present invention relates to a light emitting diode, and more particularly to a light emitting diode having a conical photoactive layer.
발광 다이오드는 광활성층 내에서 전자와 정공의 재결합에 의해 빛을 방출하는 소자이다. 이상적인 경우, 전자와 정공의 재결합은 직접 천이에 의해 발생하나, 실제의 결정 구조 내에서는 일부의 에너지가 열로 변환되는 간접 천이 형식으로 이루어지기도 한다.A light emitting diode is a device that emits light by recombination of electrons and holes in a photoactive layer. Ideally, the recombination of electrons and holes occurs by direct transition, but in the form of indirect transitions where some energy is converted to heat within the actual crystal structure.
최근에 발광 다이오드는 질화갈륨 계열의 상용화와 함께 고휘도를 실현하고 있다. 또한, YAG, TAG 및 Silicate 계열의 형광체의 개발을 통해 백색 조명을 실현하고 있는 상황이다. 다양한 분야에 걸친 발광 다이오드의 산업상의 적용을 위해서는 고휘도의 실현, 공급 전원의 AC화가 이루어져야 한다.In recent years, light emitting diodes have achieved high brightness along with the commercialization of gallium nitride series. In addition, YAG, TAG, and Silicate-based phosphors are being developed to realize white illumination. For industrial application of light emitting diodes in various fields, high brightness and AC power supply have to be achieved.
고휘도를 실현하기 위해 발광 다이오드의 에피/칩 공정에서의 많은 기술적 진보가 이루어지고 있다. 이는 기판의 배향, 버퍼층의 재질과 형성, 다중양자우물 구조의 채용 등에 의해 실현되고 있으며, 최근에는 기존의 질화갈륨 계열 이외에 산화아연 계열에 대한 연구가 활발히 진행되고 있다.Many technological advances have been made in the epi / chip process of light emitting diodes in order to achieve high brightness. This is realized by the orientation of the substrate, the material and the formation of the buffer layer, the adoption of a multi-quantum well structure, etc. Recently, research on zinc oxide series in addition to the existing gallium nitride series has been actively conducted.
기본적으로 발광 다이오드가 고휘도를 실현하기 위해서는 칩 레벨에서 높은 광추출 효율이 이루어져야 하나, 이를 위해서는 높은 수준의 전력이 공급되어야 하며, 방열 구조가 패키징을 통해서 이루어져야 한다. 통상적으로 발광 다이오드에 대한 전력공급은 DC의 형태로 이루어진다. 즉, 공급되는 AC 전원에 대한 정류 및 감압을 통해 일정한 레벨을 가진 DC 전압을 공급하고, 이를 통해 발광 다이오드는 발광동작을 수행하게 된다.Basically, in order for the light emitting diode to realize high brightness, high light extraction efficiency must be achieved at the chip level, but for this, a high level of power must be supplied and a heat dissipation structure must be achieved through packaging. Typically the power supply to the light emitting diode is in the form of DC. That is, a DC voltage having a constant level is supplied through rectification and decompression of the supplied AC power, through which the light emitting diode performs a light emitting operation.
최근에는 AC 전원에 대한 정류와 감압을 수행하는 반도체 소자를 발광 다이오드와 동일한 패키지에 실장하고 있다. 따라서, 외부에서 인지할 때는 하나의 디바이스가 AC 전원을 수신하고, 발광동작을 수행하는 양상을 가지게 된다.Recently, semiconductor devices which perform rectification and decompression on an AC power supply are mounted in the same package as a light emitting diode. Therefore, when recognized from the outside, one device receives AC power and has a light emitting operation.
그러나, 실제로는 서로 다른 제조공정을 통해 개별적으로 형성된 적어도 2개의 칩이 동일한 패키지에 실장된 것에 불과하다. 따라서, 패키징 시의 와이어 본딩, 하부 기판에서의 패터닝, 복잡한 몰딩 과정 등의 문제가 상존하고 있는 상황이다.In practice, however, at least two chips formed separately from different manufacturing processes are mounted in the same package. Therefore, problems such as wire bonding at the time of packaging, patterning at the lower substrate, complicated molding process, and the like exist.
상술한 문제점을 해결하기 위한 본 발명의 목적은 핀 홀 내부에 원뿔 형태의 광활성층이 형성된 발광 다이오드를 제공하는데 있다.An object of the present invention for solving the above problems is to provide a light emitting diode having a cone-shaped photoactive layer formed inside the pinhole.
상기 목적을 달성하기 위한 본 발명은, 기판 상에 형성된 제1 전극; 상기 제1 전극 상에 형성된 제1 클래드층; 상기 제1 클래드층 상에 형성된 절연층; 상기 절연층을 관통하는 핀 홀; 상기 핀 홀 내에 형성되고, 상기 제1 클래드층 상에 형성된 광활성층; 상기 광활성층 상에 형성된 원뿔 형상의 제2 클래드층; 및 상기 절연층 상에 형성된 제2 전극을 포함하는 발광 다이오드를 제공한다.The present invention for achieving the above object, the first electrode formed on the substrate; A first clad layer formed on the first electrode; An insulating layer formed on the first clad layer; A pin hole penetrating the insulating layer; A photoactive layer formed in the pin hole and formed on the first clad layer; A second clad clad layer formed on the photoactive layer; And it provides a light emitting diode comprising a second electrode formed on the insulating layer.
또한, 상기 목적을 달성하기 위한 본 발명은, 기판 상에 형성된 제1 전극; 상기 제1 전극 상에 형성된 절연층; 상기 절연층을 관통하는 언더 컷 형상의 핀 홀; 상기 핀 홀 내에 형성되고, 상기 제1 전극 상에 형성된 제1 클래드층; 상기 제1 클래드층 상에 형성된 광활성층; 상기 광활성층 상에 형성된 원뿔 형상의 제2 클래드층; 및 상기 절연층 상에 형성된 제2 전극을 포함하는 발광 다이오드를 제공한다.In addition, the present invention for achieving the above object, the first electrode formed on the substrate; An insulating layer formed on the first electrode; An under cut pin hole penetrating the insulating layer; A first clad layer formed in the pin hole and formed on the first electrode; A photoactive layer formed on the first clad layer; A second clad clad layer formed on the photoactive layer; And it provides a light emitting diode comprising a second electrode formed on the insulating layer.
본 발명의 상기 목적은, 동일한 기판 상에 다수개의 핀 홀들이 형성되고, 2개의 전극들을 통해 각각의 핀 홀에 형성된 광활성층이 발광동작을 수행하는 발광 다이오드의 제공을 통해서도 달성된다.The above object of the present invention is also achieved through the provision of a light emitting diode in which a plurality of pin holes are formed on the same substrate, and a photoactive layer formed in each pin hole through two electrodes performs a light emitting operation.
상술한 본 발명에 따르면, 제2 클래드층과 제2 전극은 비접촉 상태를 가진다. 비접촉 상태인 제2 클래드층과 제2 전극 사이의 간격을 조절하여 방전현상을 유도하고 이를 통해 고전압 전원을 발광 다이오드에 직접 이용할 수 있다.According to the present invention described above, the second clad layer and the second electrode have a non-contact state. By controlling the distance between the second cladding layer and the second electrode in a non-contact state, the discharge phenomenon can be induced, and high voltage power can be directly used for the light emitting diode.
또한, 하나의 전극 상에 다수의 발광 구조가 형성되므로, 높은 휘도를 달성할 수 있다.In addition, since a plurality of light emitting structures are formed on one electrode, high luminance can be achieved.
도 1은 본 발명의 제1 실시예에 따른 발광 다이오드를 도시한 사시도이다.1 is a perspective view showing a light emitting diode according to a first embodiment of the present invention.
도 2 내지 도 5는 본 발명의 제1 실시예에 따라 상기 도 1에 도시된 발광 다이오드의 제조방법을 설명하기 위한 단면도들이다.2 to 5 are cross-sectional views illustrating a method of manufacturing the light emitting diode shown in FIG. 1 according to the first embodiment of the present invention.
도 6은 본 발명의 제2 실시예에 따른 발광 다이오드를 도시한 단면도이다.6 is a cross-sectional view illustrating a light emitting diode according to a second embodiment of the present invention.
도 7은 본 발명에 따른 다른 발광 다이오드를 도시한 단면도이다.7 is a cross-sectional view showing another light emitting diode according to the present invention.
본 발명은 다양한 변경을 가할 수 있고 여러 가지 형태를 가질 수 있는 바, 특정 실시예들을 도면에 예시하고 본문에 상세하게 설명하고자 한다. 그러나, 이는 본 발명을 특정한 개시 형태에 대해 한정하려는 것이 아니며, 본 발명의 사상 및 기술 범위에 포함되는 모든 변경, 균등물 내지 대체물을 포함하는 것으로 이해되어야 한다. 각 도면을 설명하면서 유사한 참조부호를 유사한 구성요소에 대해 사용하였다.As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.
다르게 정의되지 않는 한, 기술적이거나 과학적인 용어를 포함해서 여기서 사용되는 모든 용어들은 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에 의해 일반적으로 이해되는 것과 동일한 의미를 가지고 있다. 일반적으로 사용되는 사전에 정의되어 있는 것과 같은 용어들은 관련 기술의 문맥 상 가지는 의미와 일치하는 의미를 가지는 것으로 해석되어야 하며, 본 출원에서 명백하게 정의하지 않는 한, 이상적이거나 과도하게 형식적인 의미로 해석되지 않는다. Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.
이하, 첨부한 도면들을 참조하여, 본 발명의 바람직한 실시예를 보다 상세하게 설명하고자 한다. Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.
제1 실시예First embodiment
도 1은 본 발명의 제1 실시예에 따른 발광 다이오드를 도시한 사시도이다.1 is a perspective view showing a light emitting diode according to a first embodiment of the present invention.
도 1을 참조하면, 기판(100) 상에는 제1 전극(110) 및 제1 클래드층(120)이 순차적으로 형성된다. 상기 제1 클래드층(120) 상부에는 절연층(130)이 형성되며, 절연층(130)에는 이를 관통하는 다수의 핀 홀들(140)이 형성된다. 또한, 핀 홀(140)의 내부 공간에는 광활성층(150)과 제2 클래드층(160)이 형성된다. Referring to FIG. 1, the first electrode 110 and the first cladding layer 120 are sequentially formed on the substrate 100. An insulating layer 130 is formed on the first cladding layer 120, and a plurality of pin holes 140 are formed in the insulating layer 130. In addition, the photoactive layer 150 and the second cladding layer 160 are formed in the inner space of the pinhole 140.
상기 광활성층(150)은 핀 홀(140) 내부에서 상기 제1 클래드층(120) 상부에 형성되며, 상기 제2 클래드층(160)은 대략 원뿔 모양을 가지며 광활성층(150) 상부에 형성된다. 또한, 절연층(130) 상부에는 제2 전극(170)이 형성되며, 상기 제2 전극(170)은 핀 홀들(140)을 제외한 절연층(130)의 상부에 형성된다.The photoactive layer 150 is formed on the first clad layer 120 inside the pinhole 140, and the second clad layer 160 has a substantially conical shape and is formed on the photoactive layer 150. . In addition, a second electrode 170 is formed on the insulating layer 130, and the second electrode 170 is formed on the insulating layer 130 except for the pin holes 140.
먼저, 상기 기판(100)은 절연성 재질이면서, 이후의 제조공정에서 전극들(110, 170), 클래드층들(120, 160) 및 광활성층(150)의 형성에 의해 변형이 발생되지 않는 특성을 가진 것이라면 어느 것이나 가능할 것이다. 따라서, 광활성층(150)에서 발생된 광이 기판(100)을 투과하여야 하는 경우, 사파이어, 산화아연, 실리콘카바이드 또는 글래스 등이 사용될 수 있으며, 광이 핀-홀(140)의 개방된 공간을 통해 외부로 방출되는 경우, 소정의 반사율을 가진 재료가 사용될 수 있다. 예컨대, 실리콘 기판이 사용될 수 있는데, 실리콘 기판을 사용하는 경우, 실리콘 기판과 제1 전극(110) 사이는 실리콘 산화물이 개재될 수 있다.First, the substrate 100 is an insulating material, and the deformation is not generated by the formation of the electrodes 110 and 170, the cladding layers 120 and 160, and the photoactive layer 150 in a subsequent manufacturing process. Anything you have will be possible. Therefore, when light generated in the photoactive layer 150 must pass through the substrate 100, sapphire, zinc oxide, silicon carbide, glass, or the like may be used, and the light may be formed in the open space of the pin-hole 140. When emitted through the outside, a material having a predetermined reflectance can be used. For example, a silicon substrate may be used. In the case of using a silicon substrate, silicon oxide may be interposed between the silicon substrate and the first electrode 110.
제1 전극(110)은 기판(100) 상에 형성된다. 상기 제1 전극(110)은 기판(100) 전면에 걸쳐 형성된다. 또한, 상기 제1 전극(110)은 전도성 재질로써, 제1 클래드층(120)과 전기적으로 오믹 콘택을 수행할 수 있는 물질이라면 어느 것이나 가능할 것이다. 다만, 상기 제1 전극(110)은 이후에 형성되는 제1 클래드층(120)의 전도형에 따라 다양하게 선택될 수 있겠으나, 패키징 공정에서 발생할 수 있는 와이어 본딩 과정을 감안하여 적절한 금속성의 재료로 선택됨이 바람직하다.The first electrode 110 is formed on the substrate 100. The first electrode 110 is formed over the entire surface of the substrate 100. In addition, the first electrode 110 may be any conductive material, as long as it is a material capable of electrically contacting the first cladding layer 120 with the ohmic contact. However, the first electrode 110 may be variously selected according to the conductivity type of the first cladding layer 120 formed thereafter, but considering a wire bonding process that may occur in a packaging process, an appropriate metallic material may be used. Is preferably selected.
상기 제1 전극(110) 상부에는 제1 클래드층(120)이 형성된다. 상기 제1 클래드층(120)은 n형 또는 p형의 전도성을 가질 수 있다. 또한, 상기 제1 클래드층(120)은 질화갈륨 계열 또는 산화아연 계열일 수 있다.The first clad layer 120 is formed on the first electrode 110. The first clad layer 120 may have an n-type or p-type conductivity. In addition, the first cladding layer 120 may be gallium nitride-based or zinc oxide-based.
계속해서, 제1 클래드층(120) 상부에는 절연층(130)이 형성된다. 상기 절연층(130)은 절연성 재질이라면 어느 것이나 가능할 것이나, 핀 홀(140)을 형성하기에 적합한 재질로 선택됨이 바람직하다. 상기 절연층(130)을 관통하여 형성되는 핀 홀(140)은 절연층(130)의 식각에 의해 형성된다. 따라서, 상기 절연층(130)은 하부의 제1 클래드층(120)과 화학적 조성을 달리하는 재질로 선택되어야 한다. 본 실시예에서는 상기 절연층(130)을 실리콘 산화물로 구성한다. 다만, 이외에도 소정의 반사율을 가진 절연체가 사용될 수 있음은 당업자에게 주지의 사실이라 할 것이다. 다만, 재료의 선택시, 절연층(130)은 하부의 제1 클래드층(120)과 식각선택비를 가져야만 한다.Subsequently, an insulating layer 130 is formed on the first cladding layer 120. The insulating layer 130 may be any insulating material, but is preferably selected as a material suitable for forming the pin hole 140. The pinhole 140 formed through the insulating layer 130 is formed by etching the insulating layer 130. Therefore, the insulating layer 130 should be selected of a material having a chemical composition different from that of the lower first cladding layer 120. In this embodiment, the insulating layer 130 is made of silicon oxide. However, it will be known to those skilled in the art that an insulator having a predetermined reflectance can be used in addition to the above. However, when the material is selected, the insulating layer 130 should have an etching selectivity with the lower first cladding layer 120.
절연층(130)을 관통하는 핀 홀(140) 내부에는 광활성층(150)과 제2 클래드층(160)이 형성된다.The photoactive layer 150 and the second cladding layer 160 are formed in the pinhole 140 penetrating the insulating layer 130.
광활성층(150)은 발광동작을 수행하는 구조로 구성된다. 따라서, 진성 반도체로 구성될 수 있으며, 양자점 구조 또는 다중양자우물 구조로 형성될 수 있다. 예컨대, 다중양자우물 구조가 광활성층(150)에 채용되고, 제1 클래드층(120) 및 제2 클래드층(160)이 질화갈륨 계열인 경우, 상기 광활성층(150)은 장벽층으로 질화갈륨, 우물층으로 인듐질화갈륨이 사용될 수 있다.The photoactive layer 150 has a structure for performing a light emitting operation. Therefore, it may be formed of an intrinsic semiconductor, and may be formed of a quantum dot structure or a multi-quantum well structure. For example, when a multi-quantum well structure is employed in the photoactive layer 150 and the first cladding layer 120 and the second cladding layer 160 are gallium nitride series, the photoactive layer 150 is a gallium nitride barrier layer. Indium gallium nitride may be used as the well layer.
상기 광활성층(150) 상부에는 원뿔형의 제2 클래드층(160)이 형성된다. 상기 제2 클래드층(160)은 제1 클래드층(120)과 상보적인 전도형을 가진다. 즉, 제1 클래드층(120)이 p형인 경우, 제2 클래드층(160)은 n형으로 구성되며, 제1 클래드층(120)이 n형인 경우, 제2 클래드층(160)은 p형으로 구성된다. The conical second cladding layer 160 is formed on the photoactive layer 150. The second clad layer 160 has a conductivity type complementary to the first clad layer 120. That is, when the first cladding layer 120 is p-type, the second cladding layer 160 is n-type, and when the first cladding layer 120 is n-type, the second cladding layer 160 is p-type. It consists of.
또한, 절연층(130)의 상부에는 제2 전극(170)이 형성된다. 상기 제2 전극(170)은 핀 홀(140) 이외의 절연층(130) 상부에 걸쳐 형성된다. 즉, 제2 전극(170)은 핀 홀(140) 상부를 개방하는 형태로 형성된다.In addition, the second electrode 170 is formed on the insulating layer 130. The second electrode 170 is formed over the insulating layer 130 other than the pin hole 140. That is, the second electrode 170 is formed to open the upper portion of the pin hole 140.
도 2 내지 도 5는 본 발명의 제1 실시예에 따라 상기 도 1에 도시된 발광 다이오드의 제조방법을 설명하기 위한 단면도들이다.2 to 5 are cross-sectional views illustrating a method of manufacturing the light emitting diode shown in FIG. 1 according to the first embodiment of the present invention.
도 2를 참조하면, 기판(100) 상에 제1 전극(110), 제1 클래드층(120) 및 절연층(130)을 순차적으로 적층한다. Referring to FIG. 2, the first electrode 110, the first cladding layer 120, and the insulating layer 130 are sequentially stacked on the substrate 100.
상기 제1 전극(110)은 제1 클래드층(120)이 n형인 경우, Ti/Au 또는 Cr/Au로 구성됨이 바람직하며, 제1 클래드층(120)이 p형인 경우, Ni/Au 또는 Cr/Au로 구성됨이 바람직하다. 예컨대, 제1 클래드층(120)이 n형인 경우, Au를 먼저 형성하고, Au 상부에 Ti 또는 Cr을 형성함이 바람직하다.When the first cladding layer 120 is n-type, the first electrode 110 is preferably composed of Ti / Au or Cr / Au, and when the first cladding layer 120 is p-type, Ni / Au or Cr Preferably composed of / Au. For example, when the first cladding layer 120 is n-type, Au is preferably formed first, and Ti or Cr is formed on the Au.
또한, 제1 클래드층(120)은 발광 다이오드가 질화갈륨 계열로 구성되고, n형의 전도성을 가지는 경우, Si 등의 Ⅳ족 원소를 도판트로 이용한다. 또한, p형의 전도성을 가지는 경우, Mg 등의 Ⅱ족 원소를 도판트로 이용한다.In addition, in the first cladding layer 120, when the light emitting diode is formed of gallium nitride series and has n-type conductivity, a group IV element such as Si is used as the dopant. Moreover, when it has p-type conductivity, group II elements, such as Mg, are used as a dopant.
만일, 본 실시예의 발광 다이오드가 산화아연 계열로 구성되고, n형의 전도성을 가지는 경우, ⅢA 족 또는 ⅣA 족 원소가 도판트로 이용되고, p형의 전도성을 가지는 경우, ΙA족 또는 ⅡA족 원소가 도판트로 이용됨이 바람직하다. 또한, 상기 제1 클래드층(120)은 다양한 방법을 통해서 형성될 수 있겠으나, MOCVD 공정을 이용함이 바람직하다.If the light emitting diode of the present embodiment is composed of zinc oxide series and has n-type conductivity, a group IIIA or IVA element is used as a dopant, and a group IIIA or IIA element is used. It is preferably used as a dopant. In addition, the first clad layer 120 may be formed through various methods, but it is preferable to use a MOCVD process.
계속해서 제1 클래드층(120) 상부에는 절연층(130)이 형성된다. 상기 절연층(130)은 비전도성 재질로 상기 제1 클래드층(120)과 식각선택비를 가진 물질이라면 어느 것이나 가능할 것이다.Subsequently, an insulating layer 130 is formed on the first cladding layer 120. The insulating layer 130 may be any non-conductive material as long as the material has an etching selectivity with the first clad layer 120.
도 3을 참조하면, 절연층(130)에 대한 식각을 수행하여 핀 홀(140)을 형성한다. 상기 핀 홀(140)은 절연층(130)을 관통하고, 하부의 제1 클래드층(120)의 표면 일부를 노출시키는 형태로 형성된다. 이외에 핀 홀(140)은 절연층(130)을 언더 컷의 형상으로 식각하여 형성됨이 바람직하다. Referring to FIG. 3, the pin hole 140 is formed by etching the insulating layer 130. The pin hole 140 penetrates the insulating layer 130 and is formed to expose a portion of the surface of the lower first clad layer 120. In addition, the pin hole 140 is preferably formed by etching the insulating layer 130 in the shape of an undercut.
언더 컷 형태의 핀 홀(140)을 형성하기 위해서 절연층(130) 전체에 대해 포토레지스트를 도포하고 통상의 포토리소그래피 공정을 이용하여 핀 홀(140)이 형성될 영역을 오픈하는 포토레지스트 패턴을 형성한다. 형성된 포토레지스트 패턴을 식각 마스크로 이용하여 식각을 수행하여 핀 홀(140)을 형성한다. 상기 핀 홀(140)은 언더 컷 형태를 가짐이 바람직하다. 언더 컷 형태의 핀 홀(140)을 형성하기 위해, 식각은 습식 식각을 이용할 수 있다. 만일, 건식 식각을 이용하는 경우, 에칭 가스의 식각 방향에 수직으로 절연층(130)이 형성된 기판을 배열하기 보다는 소정의 각도로 기울기를 가지도록 한 후, 식각을 진행함이 바람직하다.In order to form the undercut pinhole 140, a photoresist is applied to the entire insulating layer 130, and a photoresist pattern for opening the region where the pinhole 140 is to be formed using a conventional photolithography process is used. Form. The pin hole 140 is formed by performing etching using the formed photoresist pattern as an etching mask. The pin hole 140 preferably has an undercut shape. In order to form the undercut pin hole 140, the etching may use wet etching. In the case of using dry etching, the etching may be performed after the inclination at a predetermined angle rather than arranging the substrate on which the insulating layer 130 is formed perpendicular to the etching direction of the etching gas.
핀 홀(140)을 언더 컷의 형태로 형성하는 것은 이후에 진행되는 막질의 형성 과정에서 광활성층(150) 또는 제2 클래드층(160)을 구성하는 물질이 핀 홀(140)의 측벽에 부착되는 현상을 최소화하기 위한 것이다.Forming the pinhole 140 in the form of an undercut is that the material constituting the photoactive layer 150 or the second cladding layer 160 is attached to the sidewalls of the pinhole 140 in a process of forming a film later. This is to minimize the phenomenon.
도 4를 참조하면, 언더 컷의 형태로 형성된 핀 홀(140) 내부에 광활성층(150) 및 제2 클래드층(160)을 형성한다.Referring to FIG. 4, the photoactive layer 150 and the second cladding layer 160 are formed in the pinhole 140 formed in the form of under cut.
먼저, 광활성층(150)을 구성하는 물질을 핀 홀(140)이 형성된 기판의 전면에 도포한다. 만일 상기 광활성층(150)이 다중양자우물 구조인 경우, 장벽층 및 우물층이 서로 번갈아가며 형성되는 구조가 된다. 이때, 장벽층은 상대적으로 높은 밴드갭을 가지고 우물층은 상대적으로 낮은 밴드갭을 가지게 되어, 양자구속 효과를 나타내게 된다.First, a material constituting the photoactive layer 150 is applied to the entire surface of the substrate on which the pinhole 140 is formed. If the photoactive layer 150 has a multi-quantum well structure, the barrier layer and the well layer are alternately formed. At this time, the barrier layer has a relatively high band gap and the well layer has a relatively low band gap, thereby exhibiting a quantum confinement effect.
상술한 광활성층(150)은 절연층(130)의 표면에 형성되고, 언더 컷 형상의 핀 홀(140) 내부에도 형성된다. 다만, 언더 컷 형상에 의해 핀 홀(140) 내부에 형성되는 광활성층(150)은 절연층(130)의 측벽과는 접촉이 회피되는 구조로 형성된다.The photoactive layer 150 described above is formed on the surface of the insulating layer 130, and is also formed in the undercut fin hole 140. However, the photoactive layer 150 formed inside the pinhole 140 due to the undercut shape is formed in a structure in which contact with the sidewall of the insulating layer 130 is avoided.
계속해서 기 형성된 광활성층(150) 상부에 제2 클래드층(160)이 형성된다. 상기 제2 클래드층(160)은 제1 클래드층(120)과 상보적인 전도성을 가진다. 즉, 제1 클래드층(120)이 n형이면, 제2 클래드층(160)은 p형으로 구성되고, 제1 클래드층(120)이 p형이면, 제2 클래드층(160)은 n형으로 구성된다. 또한, 제2 클래드층(160)의 물질 및 전도성에 따른 도판트는 제1 클래드층(120)에서 설명된 바와 동일하다.Subsequently, the second cladding layer 160 is formed on the previously formed photoactive layer 150. The second clad layer 160 has a complementary conductivity with that of the first clad layer 120. That is, when the first cladding layer 120 is n-type, the second cladding layer 160 is p-type, and when the first cladding layer 120 is p-type, the second cladding layer 160 is n-type. It consists of. In addition, the dopant according to the material and conductivity of the second cladding layer 160 is the same as described in the first cladding layer 120.
또한, 제2 클래드층(160)은 대략 원뿔형의 형상을 가지게 된다. 이는 절연층(130) 상부에 동시에 형성되는 광활성층(150)을 구성하는 물질과 제2 클래드층(160)을 형성하는 물질에 의해 핀 홀(140)의 입구가 줄어든 현상에 기인한다.In addition, the second cladding layer 160 has a substantially conical shape. This is due to the phenomenon that the inlet of the pinhole 140 is reduced by the material forming the photoactive layer 150 formed on the insulating layer 130 and the material forming the second cladding layer 160.
상술한 핀 홀(140) 내의 광활성층(150)과 제2 클래드층(160)의 형성은 핀 홀(140)의 형상이 언더 컷을 가짐에 기인한다. 즉, 언더 컷 형상의 핀 홀(140)에 의해 광활성층(150)과 제2 클래드층(160)은 절연층(130)의 내부 측벽과 접촉이 회피되며, 제2 클래드층(160)은 원뿔형의 형상을 가지게 된다.The formation of the photoactive layer 150 and the second cladding layer 160 in the pinhole 140 is caused by the shape of the pinhole 140 having an undercut. That is, the photoactive layer 150 and the second cladding layer 160 are prevented from contacting the inner sidewall of the insulating layer 130 by the undercut pin hole 140, and the second cladding layer 160 is conical. It will have the shape of.
계속해서 도 5를 참조하면, 상기 도 4에서 형성된 절연층(130) 상부에 잔류하는 광활성층(150) 물질과 제2 클래드층(160) 물질을 제거한다. 절연층(130) 상부에 잔류하는 막질의 제거는 화학적 기계적 연마 또는 식각을 통해서 수행된다. 화학적 기계적 연마는 절연층(130)의 표면이 노출될 때까지 진행하여 절연층(130) 상부의 막질을 제거한다. 또한, 식각은 건식 식각 또는 습식 식각으로 진행될 수 있다. 다만, 식각 공정시에 핀 홀(140) 영역은 포토레지스트가 잔류하여 식각 마스크로 작용하게 함이 바람직하다.5, the material of the photoactive layer 150 and the material of the second cladding layer 160 remaining on the insulating layer 130 formed in FIG. 4 are removed. Removal of the film remaining on the insulating layer 130 is performed by chemical mechanical polishing or etching. Chemical mechanical polishing proceeds until the surface of the insulating layer 130 is exposed to remove the film on the insulating layer 130. In addition, the etching may be performed by dry etching or wet etching. However, during the etching process, the photoresist may remain in the pinhole 140 to act as an etching mask.
절연층(130) 상부에 막질들이 제거되면, 절연층(130) 상부에 제2 전극(170)을 형성한다. 상기 제2 전극(170)은 전도성 물질이라면 어느 것이나 가능할 것이나, Cu 또는 Au로 구성됨이 바람직하다. 또한, 상기 제2 전극(170)은 핀 홀(140)을 제외한 절연층(130) 상부에 도포된다. 이러한 선택적 도포를 위해 증착 마스크를 사용할 수도 있고, 포토레지스트를 통한 리프트 오프 기술을 사용할 수 있다. 특히, 리프트 오프 기술은 다음과 같이 구성할 수 있다.When the films are removed from the insulating layer 130, the second electrode 170 is formed on the insulating layer 130. The second electrode 170 may be any conductive material, but is preferably made of Cu or Au. In addition, the second electrode 170 is coated on the insulating layer 130 except for the pin hole 140. Deposition masks may be used for this selective application, and lift off techniques through photoresist may be used. In particular, the lift-off technique can be configured as follows.
먼저, 핀 홀(140) 내부에 광활성층(150) 및 제2 클래드층(160)이 형성된 기판 전면에 대해 포토레지스트를 도포한다. 특히, 핀 홀(140) 내부를 매립하고, 절연층(130)으로부터 소정의 높이를 가지도록 포토레지스트는 도포된다. 이어서, 핀 홀(140) 상부 영역에 형성된 포토레지스트를 잔류시키고, 절연층(130) 상부 영역에 형성된 포토레지스트를 제거한다. 이미, 상기 도 4의 절연층(130) 상부에 형성된 막질들은 화학적 기계적 연마 등에 의해 제거된 상태이다. 따라서, 포토레지스트의 제거에 의해 절연층(130)의 표면은 노출된다.First, photoresist is applied to the entire surface of the substrate on which the photoactive layer 150 and the second clad layer 160 are formed in the pin hole 140. In particular, the photoresist is applied to fill the inside of the pin hole 140 and have a predetermined height from the insulating layer 130. Subsequently, the photoresist formed in the upper region of the pin hole 140 is left, and the photoresist formed in the upper region of the insulating layer 130 is removed. Already, the film materials formed on the insulating layer 130 of FIG. 4 are removed by chemical mechanical polishing or the like. Therefore, the surface of the insulating layer 130 is exposed by removing the photoresist.
계속해서, 핀 홀(140) 영역 상부에만 포토레지스트가 잔류하는 기판에 대해 전극물질을 도포한다. 이어서, 잔류하는 포토레지스트를 에슁 등을 통해 제거하면, 핀 홀(140) 영역 상에 형성된 포토레지스트 상부에 형성된 전극물질도 제거된다. 따라서, 절연층(130) 상부의 전극물질만 잔류하게 되는 제2 전극(170)이 형성된다.Subsequently, an electrode material is applied to the substrate in which the photoresist remains only on the pinhole 140 region. Subsequently, when the remaining photoresist is removed through etching, the electrode material formed on the photoresist formed on the pinhole 140 region is also removed. Accordingly, the second electrode 170 in which only the electrode material on the insulating layer 130 remains is formed.
상술한 구성을 가지는 발광 다이오드는 광활성층(150) 및 클래드층들(120, 160)에 전력을 공급하는 2개의 전극들(110, 170) 중 하나는 클래드층과 비접촉인 상태가 된다. 즉, 본 실시예에서는 제2 클래드층(160)과 제2 전극(170)은 물리적으로 비접촉인 상태로 구성된다. 그러나, 상기 도 1 및 도 5에 개시된 바와 같이 제2 클래드층(160)은 대략 원뿔형의 형상을 하고 있으므로, 제1 전극(110)과 제2 전극(170)에 소정의 전위차를 인가하는 경우, 제2 클래드층(160)인 원뿔의 끝부분에서 전계의 집중이 일어난다. 이러한 전계의 집중은 제2 클래드층(160)과 비접촉인 제2 전극(170) 사이의 정전 방전 현상을 일으킨다. 따라서, 정전 방전 현상에 의해 전하는 제2 클래드층(160)으로부터 제2 전극(170)으로 전달되거나, 제2 전극(170)으로부터 제2 클래드층(160)으로 전달된다.In the light emitting diode having the above-described configuration, one of the two electrodes 110 and 170 for supplying power to the photoactive layer 150 and the clad layers 120 and 160 is in contact with the clad layer. That is, in the present embodiment, the second clad layer 160 and the second electrode 170 are configured to be in physically non-contact state. However, as shown in FIGS. 1 and 5, since the second cladding layer 160 has a substantially conical shape, when a predetermined potential difference is applied to the first electrode 110 and the second electrode 170, Concentration of the electric field occurs at the end of the cone, which is the second cladding layer 160. The concentration of the electric field causes an electrostatic discharge phenomenon between the second cladding layer 160 and the non-contact second electrode 170. Therefore, charges are transferred from the second cladding layer 160 to the second electrode 170 or transmitted from the second electrode 170 to the second cladding layer 160 by the electrostatic discharge phenomenon.
이러한 본 발명의 기술적 구성은 110V 또는 220V의 전원을 직접 발광 다이오드의 전극에 연결하여 발광 동작을 수행하도록 한다. 즉, 정전 방전 현상은 인가되는 전압이 높은 전압일 경우에 발생할 수 있다. 또한, AC 전원의 인가 시에 전위의 시간적 변경에 따라, 발생되는 전계는 제2 클래드층(160)과 제2 전극(170) 사이의 방전 현상을 유도하고, 이를 통하여 제1 전극(110)과 제2 전극(170) 사이의 전류의 흐름이 발생한다. 또한, 전류의 흐름을 통해 광활성층(150)에서는 전자와 정공의 재결합이 발생하고, 발광 동작이 수행된다.The technical configuration of the present invention is to connect the power of 110V or 220V directly to the electrode of the light emitting diode to perform the light emitting operation. That is, the electrostatic discharge phenomenon may occur when the voltage applied is a high voltage. In addition, according to the temporal change of the potential when the AC power is applied, the generated electric field induces a discharge phenomenon between the second cladding layer 160 and the second electrode 170, and thus the first electrode 110 and the first electrode 110. A current flows between the second electrodes 170. In addition, recombination of electrons and holes occurs in the photoactive layer 150 through the flow of current, and light emission is performed.
상술한 구성에서 핀 홀(140)은 기판(100) 상에 다수개로 구비될 수 있다. 따라서, 핀 홀(140) 내부의 광활성층(150) 및 제2 클래드층(160)도 기판(100) 상에 다수개로 구비된다. 따라서, 하나의 기판(100)에서 발광 동작을 수행하는 발광 다이오드는 다수개로 구비된다. 즉, 제1 전극(110)은 기판(100) 상에 전면적으로 형성되며, 각각의 발광 다이오드의 제1 클래드층(120)과 연결되며, 제2 전극(170)도 기판(100) 상의 절연층(130) 상부에 전면적으로 형성된다. 따라서, 2개의 전극(110, 170)으로 다수의 광활성층을 구동할 수 있다. 이를 통해 발광 다이오드의 고휘도를 구현할 수 있다. In the above-described configuration, a plurality of pin holes 140 may be provided on the substrate 100. Therefore, the photoactive layer 150 and the second cladding layer 160 inside the pin hole 140 are also provided in plural on the substrate 100. Therefore, a plurality of light emitting diodes that perform light emitting operations on one substrate 100 is provided. That is, the first electrode 110 is formed on the entire surface of the substrate 100, is connected to the first cladding layer 120 of each light emitting diode, and the second electrode 170 is also an insulating layer on the substrate 100. 130 is formed on the entire surface. Accordingly, the plurality of photoactive layers may be driven by the two electrodes 110 and 170. Through this, high brightness of the light emitting diode can be realized.
특히, 특정의 컬러나 화이트를 구현하고자 하는 경우, 각각의 핀 홀에 형광체를 개별적으로 도포할 수 있다. 또한, 특정의 필름 표면에 형광체를 도포하고, 필름 전체를 상기 기판의 전면에 부착하여 특정의 컬러를 구현할 수 있다.In particular, when a specific color or white is to be realized, phosphors may be individually applied to each pin hole. In addition, the phosphor may be applied to a specific film surface, and the entire film may be attached to the front surface of the substrate to implement a specific color.
제2 실시예Second embodiment
도 6은 본 발명의 제2 실시예에 따른 발광 다이오드를 도시한 단면도이다.6 is a cross-sectional view illustrating a light emitting diode according to a second embodiment of the present invention.
도 6을 참조하면, 제2 실시예에 따른 발광 다이오드는 기판(200) 상에는 제1 전극(210)이 형성된다. 상기 제1 전극(210) 상부에는 절연층(220)이 형성되며, 절연층(220)에는 이를 관통하는 다수의 핀 홀들(230)이 형성된다. 또한, 핀 홀(230)의 내부 공간에는 제1 클래드층(240), 광활성층(250)과 제2 클래드층(260)이 형성된다. Referring to FIG. 6, in the light emitting diode according to the second embodiment, a first electrode 210 is formed on a substrate 200. An insulating layer 220 is formed on the first electrode 210, and a plurality of pin holes 230 penetrating the insulating layer 220 are formed. In addition, the first cladding layer 240, the photoactive layer 250, and the second cladding layer 260 are formed in the internal space of the pinhole 230.
즉, 도 6에 개시된 발광 다이오드는 제1 클래드층(240)이 핀 홀(230) 내부에 구비된 것을 제외하고는 상기 제1 실시예에 도시된 구조와 동일하다. 따라서, 제1 클래드층(240)은 핀 홀(230)마다 개별적으로 구비되는 특징을 가진다.That is, the light emitting diode of FIG. 6 has the same structure as that of the first embodiment except that the first cladding layer 240 is provided inside the pin hole 230. Therefore, the first cladding layer 240 has a feature that is individually provided for each pin hole 230.
또한, 상기 도 6에 도시된 발광 다이오드의 제조방법은 기판(200) 상에 제1 전극(210)의 형성, 절연층(220)의 형성과 핀 홀(230)의 형성, 핀 홀(230) 내부에 제1 클래드층(240)/광활성층(250)/제2 클래드층(260)의 순차적 형성, 절연층(220) 상부에 제2 전극(270)의 형성 순으로 진행된다.In addition, the method of manufacturing the light emitting diode illustrated in FIG. 6 includes forming the first electrode 210, forming the insulating layer 220, forming the pin hole 230, and forming the pin hole 230 on the substrate 200. The first cladding layer 240, the photoactive layer 250, and the second cladding layer 260 are sequentially formed, and the second electrode 270 is formed on the insulating layer 220.
즉, 제1 실시예에서는 제1 전극(110) 상부에 제1 클래드층(120)을 적층하고, 제1 클래드층(120) 상부에 다수의 핀 홀들(140)이 배치되고, 각각의 핀 홀(140) 내부에 광활성층(150)과 제2 클래드층(160)이 배치되는 구조를 개시하였다. 반면, 제2 실시예에서는 제1 전극(210) 상부에 다수의 핀 홀들(230)이 배치되고, 각각의 핀 홀(230) 내부에 제1 클래드층(240), 광활성층(250) 및 제2 클래드층(260)이 배치되는 구조이다.That is, in the first embodiment, the first cladding layer 120 is stacked on the first electrode 110, and the plurality of pinholes 140 are disposed on the first cladding layer 120, and each pin hole is disposed. The structure in which the photoactive layer 150 and the second cladding layer 160 are disposed inside the 140 is disclosed. On the other hand, in the second embodiment, a plurality of pin holes 230 are disposed on the first electrode 210, and the first clad layer 240, the photoactive layer 250, and the first cladding hole 230 are disposed in the respective pin holes 230. The cladding layer 260 is disposed.
또한, 제조방법에서 제2 실시예에서는 기판(200) 상에 제1 전극(210)을 전면 도포하고, 형성된 제1 전극(210) 상부에 절연층(220)을 형성한다. 계속해서, 절연층(220)에 대한 선택적 식각을 통해 언더 컷 형상의 핀 홀들(230)을 다수개 형성한다.In the second embodiment, the first electrode 210 is entirely coated on the substrate 200, and the insulating layer 220 is formed on the formed first electrode 210. Subsequently, a plurality of under cut pin holes 230 are formed through selective etching of the insulating layer 220.
형성된 핀 홀(230)에는 통상의 증착 공정을 이용하여 제1 클래드층(240), 광활성층(250) 및 제2 클래드층(260)을 순차적으로 형성한다. 또한, 절연층(220) 상부에 도포된 제1 클래드층, 광활성층 및 제2 클래드층을 제거한다. 막질들이 제거된 절연층(220) 상부에 제2 전극(270)을 형성하면, 상기 도 6에 도시된 발광 다이오드를 제조할 수 있다.In the formed pinhole 230, the first cladding layer 240, the photoactive layer 250, and the second cladding layer 260 are sequentially formed using a conventional deposition process. In addition, the first cladding layer, the photoactive layer, and the second cladding layer applied on the insulating layer 220 are removed. If the second electrode 270 is formed on the insulating layer 220 from which the films are removed, the light emitting diode illustrated in FIG. 6 may be manufactured.
상기 도 6에 개시된 기판(200), 전극(210, 270), 클래드층(240, 260), 절연층(220) 및 광활성층(250)은 상기 제1 실시예에 개시된 바와 동일한 재료를 사용하여 형성한다. 또한, 제1 실시예와 제2 실시예에서는 절연층 상부에 형성된 광활성층 및 클래드층 등을 제거하는 공정이 설명되었으나, 상기 공정은 생략될 수 있다. 즉, 절연층 상부에 형성된 광활성층과 클래드층 등을 잔류시킨 상태에서 제2 전극을 형성할 수도 있다.The substrate 200, the electrodes 210 and 270, the clad layers 240 and 260, the insulating layer 220, and the photoactive layer 250 disclosed in FIG. 6 may be made of the same material as described in the first embodiment. Form. In addition, in the first and second embodiments, a process of removing the photoactive layer and the clad layer formed on the insulating layer has been described, but the process may be omitted. That is, the second electrode may be formed in a state where the photoactive layer, the cladding layer, etc. formed on the insulating layer remain.
도 7은 본 발명에 따른 다른 발광 다이오드를 도시한 단면도이다.7 is a cross-sectional view showing another light emitting diode according to the present invention.
도 7을 참조하면, 기판(300), 제1 전극(310), 클래드층(340, 360), 절연층(370) 및 광활성층(350)은 도 5 및 도 6에 도시된 바와 동일하다. 다만, 제2 전극(370)은 투명전극의 특징을 가지고, 제2 클래드층(360)은 제2 전극(370)과 물리적으로 접촉한다. 따라서, 도 7에 도시된 발광 다이오드는 DC 전원을 이용하여 구동할 수 있다. 상기 제2 전극은 ITO, IZO 또는 TO(Tin Oxide) 등의 무기 전도성 산화막일 수 있으며, 폴리아닐린 등의 유기 전도막일 수도 있다. Referring to FIG. 7, the substrate 300, the first electrode 310, the clad layers 340 and 360, the insulating layer 370, and the photoactive layer 350 are the same as illustrated in FIGS. 5 and 6. However, the second electrode 370 has the characteristics of a transparent electrode, and the second cladding layer 360 is in physical contact with the second electrode 370. Therefore, the light emitting diode shown in FIG. 7 may be driven using a DC power supply. The second electrode may be an inorganic conductive oxide film such as ITO, IZO, or TO (Tin Oxide), or may be an organic conductive film such as polyaniline.
본 발명에서 제2 클래드층과 제2 전극은 비접촉 상태로 형성된다. 따라서, 기존의 접촉식인 발광 다이오드에 비해 고전압을 직접 이용할 수 있은 잇점이 있다. 또한, 적절한 정류장치와 결합한다면, AC 전원과 직접 연결하여 발광 동작을 수행할 수 있는 잇점을 가진다.In the present invention, the second clad layer and the second electrode are formed in a non-contact state. Therefore, there is an advantage that the high voltage can be directly used compared to the conventional contact type light emitting diode. In addition, if combined with an appropriate stop, it has the advantage that the light emitting operation can be performed by connecting directly to the AC power source.
또한, 실시의 형태에 따라 제2 클래드층과 제2 전극은 접촉 상태로 구현되고, 이를 통해 DC 전원을 이용하여 구동할 수 있다. 다수의 핀홀 내부에 구비되는 발광 다이오드를 통해 실질적인 면광원을 구현할 수 있는 잇점이 있다.In addition, according to the exemplary embodiment, the second clad layer and the second electrode may be implemented in a contact state, and may be driven using a DC power supply. There is an advantage that a real surface light source can be realized through light emitting diodes provided in the plurality of pinholes.

Claims (12)

  1. 기판 상에 형성된 제1 전극;A first electrode formed on the substrate;
    상기 제1 전극 상에 형성된 제1 클래드층;A first clad layer formed on the first electrode;
    상기 제1 클래드층 상에 형성된 절연층;An insulating layer formed on the first clad layer;
    상기 절연층을 관통하는 핀 홀;A pin hole penetrating the insulating layer;
    상기 핀 홀 내에 형성되고, 상기 제1 클래드층 상에 형성된 광활성층;A photoactive layer formed in the pin hole and formed on the first clad layer;
    상기 광활성층 상에 형성된 원뿔 형상의 제2 클래드층; 및A second clad clad layer formed on the photoactive layer; And
    상기 절연층 상에 형성된 제2 전극을 포함하는 발광 다이오드.A light emitting diode comprising a second electrode formed on the insulating layer.
  2. 제1항에 있어서, 상기 핀 홀은 일체화된 상기 제1 클래드층 상부에 다수개 형성되는 것을 특징으로 하는 발광 다이오드.The light emitting diode of claim 1, wherein a plurality of the pin holes are formed on the integrated first clad layer.
  3. 제1항에 있어서, 상기 핀 홀은 언더 컷의 형상을 가지는 것을 특징으로 하는 발광 다이오드.The light emitting diode of claim 1, wherein the pin hole has an undercut shape.
  4. 제1항에 있어서, 상기 제2 클래드층과 상기 제2 전극은 물리적으로 비접촉인 것을 특징으로 하는 발광 다이오드.The light emitting diode of claim 1, wherein the second clad layer and the second electrode are physically non-contact.
  5. 제1항에 있어서, 상기 광활성층은 질화갈륨 계열 또는 산화아연 계열인 것을 특징으로 하는 발광 다이오드.The light emitting diode of claim 1, wherein the photoactive layer is gallium nitride series or zinc oxide series.
  6. 기판 상에 형성된 제1 전극;A first electrode formed on the substrate;
    상기 제1 전극 상에 형성된 절연층;An insulating layer formed on the first electrode;
    상기 절연층을 관통하는 언더 컷 형상의 핀 홀;An under cut pin hole penetrating the insulating layer;
    상기 핀 홀 내에 형성되고, 상기 제1 전극 상에 형성된 제1 클래드층;A first clad layer formed in the pin hole and formed on the first electrode;
    상기 제1 클래드층 상에 형성된 광활성층;A photoactive layer formed on the first clad layer;
    상기 광활성층 상에 형성된 원뿔 형상의 제2 클래드층; 및A second clad clad layer formed on the photoactive layer; And
    상기 절연층 상에 형성된 제2 전극을 포함하는 발광 다이오드.A light emitting diode comprising a second electrode formed on the insulating layer.
  7. 제6항에 있어서, 상기 핀 홀은 일체화된 상기 제1 전극 상에 다수개로 형성되고, 상기 제2 클래드층과 상기 제2 전극은 물리적으로 비접촉인 것을 특징으로 하는 발광 다이오드.The light emitting diode of claim 6, wherein a plurality of the pin holes are formed on the integrated first electrode, and the second clad layer and the second electrode are physically non-contact.
  8. 동일한 기판 상에 다수개의 핀 홀들이 형성되고, 2개의 전극들을 통해 각각의 핀 홀에 형성된 광활성층이 발광동작을 수행하는 발광 다이오드.A light emitting diode in which a plurality of pin holes are formed on the same substrate, and a photoactive layer formed in each pin hole through two electrodes performs a light emitting operation.
  9. 제8항에 있어서, 상기 2개의 전극들중 적어도 하나의 전극은 상기 광활성층 상부에 형성되는 원뿔형의 클래드층과 물리적 비접촉 상태인 것을 특징으로 하는 발광 다이오드.The light emitting diode of claim 8, wherein at least one of the two electrodes is in physical non-contact state with a conical cladding layer formed on the photoactive layer.
  10. 제9항에 있어서, 상기 원뿔형의 클래드층과 비접촉 상태인 상기 전극 사이는 고전압의 인가시, 방전에 의해 전하의 이동이 이루어지는 것을 특징으로 하는 발광 다이오드.10. The light emitting diode according to claim 9, wherein a charge is transferred between the conical cladding layer and the electrode in a non-contact state by discharge upon application of a high voltage.
  11. 제9항에 있어서, 상기 핀 홀은 언더 컷 형상으로 구비되고, 상기 핀 홀 내부는 상기 광활성층 및 상기 원뿔형의 클래드층을 포함하는 것을 특징으로 하는 발광 다이오드.10. The light emitting diode of claim 9, wherein the pin hole has an undercut shape, and the pin hole includes the photoactive layer and the conical clad layer.
  12. 제8항에 있어서, 상기 2개의 전극들중 하나의 전극은 상기 광활성층 상부에 형성되는 원뿔형의 클래드층과 물리적으로 접촉 상태이며, 상기 클래드층과 접촉하는 전극은 투명 전도성 재질인 것을 특징으로 하는 발광 다이오드.The method of claim 8, wherein one of the two electrodes is in physical contact with the conical cladding layer formed on the photoactive layer, and the electrode in contact with the cladding layer is made of a transparent conductive material. Light emitting diode.
PCT/KR2010/007038 2009-10-16 2010-10-14 Non-contact type light emitting diode WO2011046373A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020090098566A KR101593693B1 (en) 2009-10-16 2009-10-16 Light Emitting Diode of Non-Contact Type
KR10-2009-0098566 2009-10-16

Publications (2)

Publication Number Publication Date
WO2011046373A2 true WO2011046373A2 (en) 2011-04-21
WO2011046373A3 WO2011046373A3 (en) 2011-07-14

Family

ID=43876711

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2010/007038 WO2011046373A2 (en) 2009-10-16 2010-10-14 Non-contact type light emitting diode

Country Status (2)

Country Link
KR (1) KR101593693B1 (en)
WO (1) WO2011046373A2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970013441A (en) * 1995-08-21 1997-03-29 빈센트 비. 인그라시아 Method for manufacturing organic light emitting diode matrix
US5953362A (en) * 1997-12-15 1999-09-14 Pamulapati; Jagadeesh Strain induce control of polarization states in vertical cavity surface emitting lasers and method of making same
JP2000236111A (en) * 1999-02-15 2000-08-29 Matsushita Electric Works Ltd Light source equipment
KR20040029301A (en) * 2001-08-22 2004-04-06 소니 가부시끼 가이샤 Nitride semiconductor element and production method for nitride semiconductor element
US20090242914A1 (en) * 2008-03-26 2009-10-01 Foxconn Technology Co., Ltd. Led assembly with high heat dissipating capability

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970013441A (en) * 1995-08-21 1997-03-29 빈센트 비. 인그라시아 Method for manufacturing organic light emitting diode matrix
US5953362A (en) * 1997-12-15 1999-09-14 Pamulapati; Jagadeesh Strain induce control of polarization states in vertical cavity surface emitting lasers and method of making same
JP2000236111A (en) * 1999-02-15 2000-08-29 Matsushita Electric Works Ltd Light source equipment
KR20040029301A (en) * 2001-08-22 2004-04-06 소니 가부시끼 가이샤 Nitride semiconductor element and production method for nitride semiconductor element
US20090242914A1 (en) * 2008-03-26 2009-10-01 Foxconn Technology Co., Ltd. Led assembly with high heat dissipating capability

Also Published As

Publication number Publication date
WO2011046373A3 (en) 2011-07-14
KR20110041640A (en) 2011-04-22
KR101593693B1 (en) 2016-02-15

Similar Documents

Publication Publication Date Title
EP2074667B1 (en) Light emitting diode having light emitting cell with different size and light emitting device thereof
WO2012023662A1 (en) Light emitting diode having multi-cell structure and manufacturing method thereof
US7732825B2 (en) AC light emitting diode
WO2016153213A1 (en) Light emitting diode package and lighting device
WO2017014512A1 (en) Light-emitting element
WO2016080710A1 (en) Electrode assembly comprising micro-led elements and method for manufacturing same
WO2014092448A1 (en) Light-emitting diode with improved light extraction efficiency
WO2011126248A2 (en) Light emitting diode and method of fabricating the same
WO2014208896A1 (en) Vertical organic light-emitting transistor and organic led illumination apparatus having the same
WO2017057978A1 (en) Light emitting device
WO2019059561A1 (en) Light-emitting diode having multiple tunnel junction structures
WO2020036423A1 (en) Light-emitting device
CN102169937A (en) Light emitting diode, light emitting diode package, method of manufacturing light emitting diode and illumination system
WO2012091245A1 (en) Light emitting module having wafer with integrated power supply device
WO2016003205A1 (en) Light emitting element
WO2013015472A1 (en) Semiconductor light-emitting device and method for manufacturing same
WO2012057482A2 (en) Vertical-type light-emitting diode cell array, and method for manufacturing same
WO2012039527A1 (en) High efficiency light emitting diode
WO2013141421A1 (en) Horizontal power led device and method for manufacturing same
WO2016052929A1 (en) Light emitting diode comprising porous transparent electrode
WO2019045435A1 (en) Light emitting diode apparatus and method of manufacturing the same
WO2013137554A1 (en) Light-emitting device and method for manufacturing same
WO2012091275A1 (en) Light-emitting diode and method for manufacturing same
WO2015068980A1 (en) Nitride semiconductor ultraviolet light-emitting device
WO2017116094A1 (en) Light-emitting element

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10823612

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10823612

Country of ref document: EP

Kind code of ref document: A2