WO2011036817A1

WO2011036817A1 - Magnetic memory

Info

Publication number: WO2011036817A1
Application number: PCT/JP2009/066829
Authority: WO
Inventors: 純夫池川; 尚治下村
Original assignee: 株式会社東芝
Priority date: 2009-09-28
Filing date: 2009-09-28
Publication date: 2011-03-31

Abstract

A magnetic memory is provided with: a magnetoresistive effect element comprising a first magnetic layer wherein a magnetization direction is constant, a second magnetic layer wherein the magnetization direction is variable, and an interlayer provided between the first magnetic layer and the second magnetic layer; an error detection and correction circuit which detects whether first data written into the magnetoresistive effect element contains an error and which when the first data contains the error, outputs second data wherein the error is corrected; a writing circuit which generates a first writing current having a first pulse width or a second writing current having a second pulse width larger than the first pulse width and applies the same to the magnetoresistive effect element; and a control circuit which controls the writing circuit to apply the second writing current to the magnetoresistive effect element when writing the second data into the magnetoresistive effect element.

Description

Magnetic memory

The present invention relates to a magnetic memory.

Recently, a magnetoresistive random access memory (MRAM) using a magnetic tunnel junction element (hereinafter referred to as an MTJ element) has attracted attention.

There is a spin injection magnetization reversal method as one of the data write methods of MRAM. In the spin injection magnetization reversal method, a current (write current) greater than or equal to the current value in the MTJ element is passed. In reading data, a current (read current) is passed through the MTJ element.

Conventionally, it has been considered that the magnetization reversal process of the MTJ element by supplying current (spin injection) can be represented by a simple thermal activation process. However, immediately after the start of current supply to the MTJ element, there is a time when the reversal probability is almost zero, and a magnetization reversal process in which the reversal probability increases after a certain time has been newly proposed. (For example, refer nonpatent literature 1).

In the spin injection type MRAM, the current value of the write current is set to a current value larger than a threshold value (hereinafter referred to as an inversion threshold value) at which magnetization reversal is caused by spin injection, and the read current value is A current value smaller than the inversion threshold is set.

However, the inversion threshold varies from element to element due to variations in characteristics of a plurality of MTJ elements constituting the MRAM. In addition, when data is repeatedly written to the same MTJ element, there is a phenomenon that the inversion threshold value for the element fluctuates.

Therefore, a write failure at the time of data writing, a read disturbance due to a read current at the time of reading data, a failure in which magnetization is reversed due to a thermal disturbance at the time of data retention, and a retention failure occur. As described above, since the magnetization reversal of the MTJ element (magnetic material) is a stochastic phenomenon, a defect occurs during the operation of the MRAM.

In order to deal with these defects, an MRAM in which an error correcting code (ECC: Error Correction Coding) is applied to data reading has been studied (for example, see Patent Document 1).

In the technique disclosed in Patent Document 1, even if error correction is performed on read data, the error of the generated data remains in the data itself stored in the MRAM. For this reason, every time data is read, error correction is performed, and the operation speed is reduced. Further, in the normal error detection and correction technique, if there are errors of a predetermined number of bits or more in data (blocks) of a predetermined size, correction cannot be performed.

US Pat. No. 7,370,260

The present invention proposes a technique for improving the reliability and operating characteristics of a magnetic memory.

A magnetic memory according to an example of the present invention includes a first magnetic layer whose magnetization direction is unchanged, a second magnetic layer whose magnetization direction is variable, and a gap between the first magnetic layer and the second magnetic layer. And detecting whether or not the first data written in the magnetoresistive effect element includes an error, and when the first data includes an error, the An error detection and correction circuit for outputting second data in which an error is corrected, a first write current having a first pulse width, and a second write having a second pulse width longer than the first pulse width A write circuit that generates one of the currents and causes the magnetoresistive effect element to flow, and when writing the second data to the magnetoresistive effect element, causes the second write current to flow to the magnetoresistive effect element Control the writing circuit And a control circuit.

According to the present invention, the reliability and operating characteristics of the magnetic memory can be improved.

1 is a diagram showing a basic example of a magnetic memory according to an embodiment. The figure which shows the pulse waveform of write-in electric current. The figure which shows an example of a magnetoresistive effect element. The figure which shows an example of a magnetoresistive effect element. The figure for demonstrating the magnetization reversal model which concerns on embodiment. The figure for demonstrating the magnetization reversal model which concerns on embodiment. The figure for demonstrating the magnetization reversal model which concerns on embodiment. The figure for demonstrating the magnetization reversal model which concerns on embodiment. The figure for demonstrating the magnetization reversal model which concerns on embodiment. The figure for demonstrating the magnetization reversal model which concerns on embodiment. The figure for demonstrating the dependence of the magnetization reversal with respect to the pulse width of an electric current. The figure for demonstrating the dependence of the magnetization reversal with respect to the pulse width of an electric current. The figure for demonstrating the dependence of the magnetization reversal with respect to the pulse width of an electric current. 1 is a block diagram showing a configuration example of a magnetic memory according to an embodiment. The figure which shows the structural example of a main memory. The figure which shows the structural example of a memory cell. The figure which shows the pulse waveform of a write current and a read current. 6 is a flowchart illustrating an operation example of the magnetic memory according to the embodiment. The figure for demonstrating the effect with respect to the magnetic memory which concerns on embodiment. The figure for demonstrating the effect with respect to the magnetic memory which concerns on embodiment. The figure for demonstrating the effect with respect to the magnetic memory which concerns on embodiment. 6 is a flowchart illustrating an operation example of the magnetic memory according to the embodiment. The block diagram which shows the modification of the magnetic memory which concerns on embodiment. The block diagram which shows the modification of the magnetic memory which concerns on embodiment. 6 is a flowchart illustrating an operation example of the magnetic memory according to the embodiment.

Hereinafter, embodiments for carrying out examples of the present invention will be described in detail with reference to the drawings. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given as necessary.

[Embodiment]
(1) Basic example
A basic example of a magnetic memory according to an embodiment of the present invention will be described with reference to FIGS.

FIG. 1 shows an example of the configuration of the magnetic memory according to the present embodiment.

As shown in FIG. 1, the magnetic memory includes a magnetoresistive effect element 1 and a switch Tr in the main memory 50. The magnetoresistive effect element 1 and the switch Tr constitute one memory cell. The magnetoresistive effect element 1 is used as a memory element. The switch Tr is used as a selection element for the magnetoresistive effect element 1.

The magnetoresistive effect element 1 is connected to two bit lines BL and bBL. One end of the magnetoresistive effect element 1 is connected to the bit line BL, and the other end of the magnetoresistive effect element 1 is connected to the bit line bBL via the switch Tr.

The switch Tr is, for example, a field effect transistor (FET). Hereinafter, the switch Tr is referred to as a selection transistor Tr. One end (source / drain) of the current path of the selection transistor Tr is connected to the other end of the magnetoresistive effect element 1, and the other end (source / drain) of the current path of the selection transistor Tr is connected to the bit line bBL. . A control terminal (gate) of the selection transistor Tr is connected to the word line WL. For example, the word line WL extends in a direction crossing the extending direction of the bit lines BL and bBL. When writing data, the write currents I _w1 and I _w2 shown in FIG. 2 flow between the two bit lines BL and bBL and are supplied to the magnetoresistive effect element 1.

3 and 4 are cross-sectional views showing the configuration of the magnetoresistive effect element 1. FIG. As the magnetoresistive effect element 1, for example, an MTJ (magnetic tunnel junction) element using a change in magnetoresistance due to a spin-polarized tunnel effect is used. Hereinafter, the magnetoresistive effect element 1 is referred to as an MTJ element 1.

The MTJ element 1 has a stacked structure in which reference layers (also referred to as magnetization invariant layers) 11A and 11B, intermediate layers (nonmagnetic layers) 12A and 12B, and storage layers (also referred to as magnetization free layers) 13A and 13B are sequentially stacked. Have. The reference layers 11A and 11B and the memory layers 13A and 13B may be stacked in reverse order.

In the MTJ element 1 shown in FIG. 3, the easy magnetization directions of the reference layer 11A and the storage layer 13A are parallel to the film surface. The MTJ element 1 shown in FIG. 3 is called an in-plane magnetization type MTJ element.
In the MTJ element 1 shown in FIG. 4, the easy magnetization directions of the reference layer 11B and the storage layer 13B are perpendicular to the film surface (or the laminated surface). The MTJ element shown in FIG. 3 is called a perpendicular magnetization type MTJ element.
The magnetic layer with in-plane magnetization has a magnetic anisotropy in the in-plane direction, and the magnetic layer with perpendicular magnetization has a magnetic anisotropy in the direction perpendicular to the film surface. When the perpendicular magnetization type is used for the MTJ element 1, it is not necessary to control the element shape to determine the magnetization direction as in the in-plane magnetization type, and it is sufficient even if the volumes of the storage layers 13A and 13B are reduced. Therefore, there is an advantage that it is suitable for miniaturization of memory cells.

The storage layers 13A and 13B have variable (reversed) magnetization (or spin) directions. The reference layers 11A and 11B have the same magnetization direction (fixed). “The magnetization directions of the reference layers 11A and 11B are unchanged” means that the magnetization reversal current (inversion threshold) used to reverse the magnetization directions of the storage layers 13A and 13B is applied to the reference layers 11A and 11B. This means that the magnetization directions of the reference layers 11A and 11B do not change when they are flowed. Therefore, in the MTJ element 1, by using a magnetic layer having a large inversion threshold as the reference layers 11A and 11B and using a magnetic layer having a smaller inversion threshold than the reference layers 11A and 11B as the storage layers 13A and 13B, The MTJ element 1 including the storage layers 13A and 13B having a variable magnetization direction and the reference layers 11A and 11B having a fixed magnetization direction is realized.

As a method of fixing the magnetization of the reference layers 11A and 11B, an antiferromagnetic layer (not shown) is provided adjacent to the reference layers 11A and 11B, and the reference layers 11A and 11B are exchanged with the antiferromagnetic layer. The magnetization direction of the reference layers 11A and 11B can be fixed by the coupling. However, in the perpendicular magnetization type MTJ element, an antiferromagnetic layer (not shown) may not be provided adjacent to the reference layer 11A. The planar shape of the MTJ element 1 is not particularly limited, and any of a circle, an ellipse, a square, a rectangle, and the like may be used. Further, the shape may be a shape in which square corners or rectangular corners are rounded, or a shape with missing corners.

The reference layers 11A and 11B and the storage layers 13A and 13B are made of a magnetic material having a high coercive force, and preferably have a high magnetic anisotropic energy density of, for example, 1 × 10 ⁶ erg / cc or more.

The

intermediate layers

12A and 12B are made of a non-magnetic material, and for example, an insulator, a semiconductor, a metal, or the like can be used. When an insulator or a semiconductor is used for the intermediate layer 12, the intermediate layer 12 is called a tunnel barrier layer.

Note that each of the reference layers 11A and 11B and the storage layers 13A and 13B is not limited to a single layer as illustrated, and may have a stacked structure including a plurality of ferromagnetic layers. Each of the reference layers 11A and 11B and the storage layers 13A and 13B includes three layers of a first ferromagnetic layer / a nonmagnetic layer / a second ferromagnetic layer. An antiferromagnetic coupling structure in which the magnetization directions are in an antiparallel state (magnetic coupling (exchange coupling)) may be used, or the first and second ferromagnetic layers may have a magnetization direction in a parallel state. A (exchange-coupled) ferromagnetic coupling structure may be used.

Further, the MTJ element 1 may have a double junction structure. The MTJ element 1 having a double junction structure has a stacked structure in which a first reference layer, a first intermediate layer, a storage layer, a second intermediate layer, and a second reference layer are stacked in this order. Such a double junction structure has an advantage that it is easy to control the magnetization reversal of the storage layers 13A and 13B by spin injection.

The write circuit 2 is connected to the bit line BL. When writing data to the MTJ element 1, the write circuit 2 generates write currents I _w1 and I _{w2 and} passes the generated currents I _w1 and I _w2 between the bit lines BL and bBL. The write currents I _w1 and I _w2 flow through the MTJ element 1. The write circuit 2 flows the write currents I _w1 and I _w2 bidirectionally from one end of the MTJ element 1 to the other end or from the other end of the MTJ element 1 to one end. The operation of the writing circuit 2 is controlled by a control circuit 51 described later.

FIG. 2 shows an example of a pulse waveform of the write current. In FIG. 2, the current value of the write current is shown as an absolute value. Based on the control circuit 51, the write circuit 2 supplies either the write current I _w1 having the pulse width T _wp1 or the write current I _w2 having the pulse width T _wp2 to the MTJ element 1. Write currents I _w1 and I _w2 flow through the MTJ element 1. Pulse width _{T wp2} is longer than the pulse width _{T wp1.}

In the present embodiment, the pulse width of the current is defined by the full width at half maximum (FWHM) of the pulse. The pulse widths T _wp1 and T _wp2 of the write currents I _w1 and I _w2 are pulse widths based on a value i _w / 2 that is ½ of the maximum current value i _w . The pulse width T _wp1 of the write current I _w1 is a period between the time t _ab and the time t _cd . Time _{t ab} is the time period _{t a} and the rise of the rise of the pulse current _{I w1} is started is completed _{t b} substantially intermediate time, the time _{t cd} is the fall of the pulse current _{I w1} is started This is a substantially intermediate time between the time t _c and the time t _{d when} the falling ends.

Pulse width _{T wp2} of the write current _{I w2} is the period between time _{t 12} and time _{t 34.} Time ₁₂ is substantially intermediate the rise time is the time to start t ₁ and time t ₂ when the rising ends of the pulse current I _w2, the time t ₃₄ is the time the fall of the pulse current Iw2 starts t ₃ and falling is substantially intermediate time period ending t _4.

The write current I _w1 and the write current I _w2 have, for example, the same current value iw. The current value i _w is set to be not less than the inversion threshold value i _th of the storage layer and less than the inversion threshold value of the reference layer.

The error detection and correction circuit 52 detects whether or not there is an error in the data (hereinafter referred to as write data) stored (or held) by the MTJ element 1. The error detection and correction circuit 52 corrects the error when there is an error in the data. The corrected data (hereinafter referred to as corrected data) is written again in the MTJ element 1.

The control circuit 51 controls the operation of the entire magnetic memory. The control circuit 51 performs the operation of the write circuit 2 so as to supply either the write current I _w1 or the write current I _w2 to the MTJ element 1 according to the operation status of the MTJ element 1 and the error detection / correction circuit 52. Control.

The control circuit 51 generates and outputs a write current I _w2 having a longer pulse width T _wp2 when writing correction data to the MTJ element 1 than when writing data input from the outside. To control the operation. When writing data input from the outside to the MTJ element 1, the control circuit 51 controls the operation of the write circuit 2 so as to generate and output a write current I _w1 having a pulse width T _wp1 .

Hereinafter, the low resistance state and the high resistance state of the MTJ element 1 and data writing by spin injection will be described. As shown in FIGS. 3 and 4, a write current I (current I _w1 or current I _{w2 in} FIG. 2) flows in the MTJ element 1 when data is written. The write current I flows bidirectionally in the MTJ element 1 according to the data to be written. Of course, the direction in which the current flows is opposite to the direction in which the electrons move.

A parallel state (low resistance state) in which the magnetization directions of the reference layers 11A and 11B and the storage layers 13A and 13B are parallel will be described.

Majority electrons among the electrons that have passed through the reference layers 11A and 11B have a spin parallel to the magnetization direction of the reference layers 11A and 11B. As the spin angular momentum of the majority electrons moves to the storage layers 13A and 13B, spin torque is applied to the storage layers 13A and 13B, and the magnetization directions of the storage layers 13A and 13B are the magnetization directions of the reference layers 11A and 11B. Aligned in parallel. With this parallel arrangement, the MTJ element 1 has the smallest resistance value. This case is treated as “0” data, for example.

Next, an antiparallel state (high resistance state) in which the magnetization directions of the reference layers 11A and 11B and the storage layers 13A and 13B are antiparallel will be described.

Among the electrons reflected by the reference layers 11A and 11B, the majority electron has a spin antiparallel to the magnetization direction of the reference layers 11A and 11B. As the spin angular momentum of the majority electrons moves to the storage layers 13A and 13B, spin torque is applied to the storage layers 13A and 13B, and the magnetization directions of the storage layers 13A and 13B are the magnetization directions of the reference layers 11A and 11B. And anti-parallel. In the antiparallel arrangement, the MTJ element 1 has the largest resistance value. This case is treated as “1” data, for example.

Hereinafter, the spin-injection magnetization reversal model of this embodiment will be described with reference to FIGS.

FIG. 5 shows the time dependence of the magnetization reversal probability in the spin injection magnetization reversal model described in the present embodiment. The horizontal axis in FIG. 5 indicates time (unit: nsec (nanosecond)). The vertical axis in FIG. 5 corresponds to the magnetization reversal probability. However, when the magnetization reversal probability is indicated by “P”, Log ₁₀ (1-P) is indicated on the vertical axis of FIG. “1-P” indicates a probability that magnetization is not reversed (data is not written). The magnetization reversal probability is the probability that the magnetization direction of the storage layer is reversed when a certain current is passed through a certain MTJ element.

Each characteristic curve shown in FIG. 5 is a result obtained by a micromagnetic simulation using an LLG (Landau-Liftshitz-Gilbert) equation. Each parameter used for this simulation is as follows.
The MTJ element used for the simulation is a perpendicular magnetization type MTJ element. The film thickness of the MTJ element is set to 2.2 nm, and the diameter of the MTJ element is set to 30 nm. The magnetization of the storage layer is perpendicular to the film surface, the magnetic layer has a magnetic anisotropy energy Ku of 3.5 Merg / cc, and the storage layer has a saturation magnetization Ms of 500 emu / cc. The energy barrier ΔEa is 86 k _B T (k _B : Boltzmann constant, T: absolute temperature). The energy barrier ΔEa indicates the size of the energy barrier that must be exceeded in the process of reversing the MTJ element from the parallel state to the antiparallel state or from the antiparallel state to the parallel state. The temperature (absolute temperature) T is set to 300K. The range of the current density J flowing through the MTJ element is set to 2.8 to 4 MA / cm ² . The simulation is executed using the current density ratio J / J _C (22 nsec, midpoint) within the range of 0.934 to 1.436. “J” indicates the current density of the pulse current, and “J _C (22 nsec, midpoint)” indicates that the MTJ element has a write width of 22 nsec when data is written to the MTJ element. The current density at which the magnetization reversal probability of the storage layer is 0.5 is shown.

FIG. 5 also shows a first-order approximate characteristic line (dotted line in the figure) for the characteristic curve obtained from the simulation using each current density ratio of 0.934 to 1.436.

Based on the characteristic curves shown in FIG. 5, the spin injection magnetization reversal probability P (t) can be approximately expressed as (Equation 1).

“P (t)” indicates the probability that the magnetization of the storage layer is reversed when a current pulse having a pulse width t is passed through the MTJ element. “F ₀ ” is the frequency at which the MTJ element receives thermal energy (phonon) per unit time. “F ₀ ” is about 1 × 10 ⁹ Hz. “I” indicates the current value of the pulse current, and “I _C0 ” indicates the magnetization reversal current at 0 K (absolute temperature) when the pulse width is set in the time of receiving one phonon (about 1 ns). Current value. In (Formula 1), “n” is a constant of 1.5 to 2.

As shown in FIG. 5, the probability Log ₁₀ (1-P) shows a negative value with respect to the change of time. In the spin injection magnetization reversal model shown in FIG. 5 and (Equation 1), immediately after the pulse current is applied to the MTJ element, the reversal of the magnetization of the storage layer does not occur, and the reversal of the magnetization occurs after the dead time t ₀ has elapsed. Be started.

The spin injection magnetization reversal model of this embodiment will be described with reference to FIGS. 6 to 10, an example of a process in which the normalized magnetization Mz of the magnetic layer (storage layer) is reversed from 1 to −1 in the spin injection magnetization reversal used in the magnetic memory will be described. Here, the time during which the magnetization Mz in the z-axis (vertical) direction changes from 1 to around −1 after the write current starts to flow through the MTJ element is called a switching time T _sw .

Since the magnetization reversal of the magnetic material is a stochastic phenomenon, the switching time T _sw fluctuates every time even when a write current of the same magnitude is supplied to the same magnetic material. That is, when data is written to a certain MTJ element using a current having a certain pulse width, the switching current I _sw (inversion threshold i _th ) fluctuates every time. Understanding these phenomena is important for reducing write failures.
In spin transfer magnetization reversal, which is one of the write principles of a magnetic memory (for example, MRAM), spin transfer magnetization reversal described in the present embodiment is composed of the following three stages. That is, in the spin transfer magnetization reversal of this embodiment, the switching time T _sw is decomposed into three.

FIG. 6 schematically shows the spin injection magnetization reversal model in the present embodiment.

In the spin injection magnetization reversal model shown in FIG. 6, the first stage is that the magnetization of each magnetic particle in the magnetic layer (storage layer) is precessed separately, and then the magnetic particles in the magnetic layer are precessed. This is the stage until the phases of magnetization are aligned and work together to start precession. In the present embodiment, the phase of magnetization of each magnetic grain in the magnetic layer is aligned and precesses together is called “coherent precession”. The time from the state where the magnetizations precessed separately until the start of coherent _precession is called the coherent time t _coh .

In the coherent time t _coh , the magnetization Mz decreases from 1 to about 0.95. In the coherent time t _coh , under the influence of phonons, the magnetization tends to become a coherent precession, but returns to a discrete precession. Therefore, the coherent time t _coh fluctuates greatly.

In the second stage, coherent precession is amplified. This time is called an amplification time t _amp . The magnetization Mz decreases from 0.95 to about 0.8. At the amplification time t _amp , under the influence of phonons, the magnetization precession is slightly amplified and attenuated. Therefore, the amplification time t _amp also fluctuates. The sum of the first stage time t _coh and the second stage time t _amp is referred to as “incubation delay time t _id ”. When the diameter of the MTJ element is smaller than the single domain diameter Ds, the incubation delay time t _id fluctuates greatly. The times t _coh and t _amp of the first and second stages are times _until the magnetization Mz starts to decrease greatly and the main stage of magnetization reversal occurs, and this time is relatively long in the spin injection magnetization reversal. Therefore, the times t _coh and t _amp required for the first and second stages are called incubation delay times.

In the third stage, the precession of magnetization is further amplified and magnetization reversal occurs with the help of thermal disturbance. At this stage, the thermal activation process is mainly dominant, and the magnetization Mz decreases from 0.8 to around -1. This time is called the reversal time _trv . When the diameter of the MTJ element is smaller than the single domain diameter Ds, the fluctuation of the reversal time t _rv is small. When the diameter of the MTJ element is larger than the single domain diameter Ds, the inversion time t _rv fluctuates to the same extent as the incubation delay time t _id .

As described above, the coherent time t _coh, which is the first stage, is from the state where the magnetization _precesses in the storage layer of the MTJ element to the start of precession where the magnetization phases are aligned. It was found that it was time.

Then, at the reversal time t _rv following the coherent time t _coh and the amplification time t _amp , magnetization reversal is started by the thermal activation process.

Such a magnetization reversal model was verified by FIG. 5 and the following experiment and simulation.

FIG. 7 is a graph obtained by analyzing one of the simulation results based on the LLG equation of the spin injection magnetization reversal of the perpendicular magnetization type MTJ element used in FIG.
The simulation was performed using, for example, a cell showing 32 magnetizations in the storage layer (magnetic layer). The cell corresponds to a magnetic grain contained in the magnetic layer. In FIG. 7, the horizontal axis represents time (unit: nsec).

In FIG. 7, a characteristic line indicated by a broken line corresponds to the left axis Mz-ave. 7 represents an average value Mz-ave (unit: au (arbitrary unit)) of z components (vertical components) of magnetization. In Mz-ave of the z component of magnetization, “1” indicates that the magnetization is directed upward with respect to the film surface of the storage layer, and “−1” indicates that the magnetization is with respect to the film surface of the storage layer. It shows a state of facing down.
In the initial state (0 nsec) of the simulation shown in FIG. 7, the average value Mz-ave of the magnetization is substantially 1, and the magnetization is in the upward direction perpendicular to the film surface of the MTJ element. Then, at 0 nsec, the supply of the magnetization reversal current to the storage layer was started, and the process until the magnetization was reversed by spin injection and the average value Mz-ave became approximately −1 was verified.

In the simulation shown in FIG. 7, the average value Mz-ave of the magnetization hardly changes during the period from 0 nsec to 2.5 nsec. This can be regarded as a period in which the magnetization (spin) of the storage layer is not reversed.

In FIG. 7, the characteristic curve indicated by the solid line corresponds to the right axis σΦ and indicates the phase variation of the precession of 32 magnetizations in the storage layer.
FIG. 8 schematically shows a single magnetization cell. As shown in FIG. 8, the direction of magnetization can be expressed in polar coordinates using two declination angles θ and Φ. As shown in FIG. 8, the magnetization of the perpendicular magnetization film precesses around the film surface perpendicular direction (z axis) as the rotation axis. The phase of precession in the equatorial plane c is defined as the declination angle Φ. In addition, the angle formed by the inclination of the magnetization M and the z-axis during precession is defined as a declination angle θ.
The phase variation of the precession is obtained by examining the variation of the declination Φ. However, the declination Φ shown in polar coordinates becomes discontinuous or multivalued with a period of + π or −π. For this reason, if the phase dispersion (phase variation) is calculated simply by using the declination Φ, an accurate calculation result cannot be obtained at a portion where the numerical values are discontinuous.
Therefore, in this embodiment, the phase variance σΦ is calculated by expressing the phase of the precession as a complex number, that is, “Φ = cosφ + isinφ”, instead of the declination Φ, and the phase variation is obtained. Thus, by expressing the argument Φ using complex numbers, the problem caused by numerical discontinuity is solved, and phase variations can be calculated relatively easily. The phase dispersion σΦ is expressed by the following (Expression 2) and (Expression 3).

“N” in (Equation 3) indicates the number of magnetizations (number of cells) included in the storage layer, which is 32 in this example. “Σ” in (Expression 3) indicates that the sum (total value) of all the magnetizations (32 in this example) included in the storage layer is calculated. “*” In (Expression 3) indicates a conjugate complex number. “￣” in (Expression 3) and (Expression 4) indicates an average value of all the magnetization cells (32 in this example) in the storage layer. Therefore, “μ” in (Expression 3) indicates an average value of “Φ” of all the magnetizations in the storage layer.

9 and 10 schematically show the magnetization cells arranged in the storage layer 17. 9 and 10 show an example in which a plurality of cells 18 are two-dimensionally arranged. However, this is for the sake of simplification of description and is not limited to this. is there.

For example, as shown in FIG. 9, when the phases of the magnetizations 19 of the cells 18 in the storage layer 17 are all random, the phase dispersion σΦ indicates “1”. On the other hand, as shown in FIG. 10, when the phases of all the magnetizations 19 in the storage layer 14 are perfectly aligned and the value of the declination “Φ” is the same, the phase dispersion σΦ is “0”. Indicates.
As shown in FIG. 7, the phase dispersion σΦ of the magnetization in the storage layer rapidly decreases, the time when the magnetization becomes a coherent precession, the magnetization starts to reverse, and the average value Mz-ave of the magnetization is The phenomenon that the average value Mz-ave starts decreasing after reaching about 0.95 is linked. For this reason, the coherent time t _coh is considered to be the time from when the precession of magnetization becomes discrete as shown in FIG. 9 to the coherent precession as shown in FIG. be able to.

Note that a period t ′ in FIG. 7 corresponds to a time until a coherent precession movement is reached. However, even when the simulation is repeated under the same conditions, the period t ′ from the initial state until the coherent precession is realized varies. However, the phenomenon that magnetization reversal is started when the phase of magnetization in the storage layer is aligned and coherent precession is realized is reproduced.

The period t ′ in the spin injection magnetization reversal is a coherent state in which the phase of precession of each magnetization 18 is aligned from the state where the phase of precession of each magnetization 18 is not aligned (see FIG. 9) in the storage layer 17. It can be regarded as the time until the transition to (see FIG. 10). Then, when a period (time) t _coh until the coherent _precession is _reached and a period (time) t _amp until the coherent precession is amplified, the _{process proceeds} to the thermal activation process, and the MTJ element It can be said that the spin inversion of the storage layer is substantially started.
The time until the magnetization precession becomes a coherent motion depends on the magnitude of the current I. When the magnitude of the current I decreases, the time until the magnetization precession becomes a coherent motion is To increase.

There is a period (time) t ′ until the coherent precession is realized, and after the coherent precession is realized, a finite time from the start of the spin inversion to the completion of the spin inversion. Exists. Therefore, in consideration of those periods (time), the time t ₀ in (Equation 1) is included in the parameters of the spin injection magnetization reversal model described in this embodiment.
Here, the condition for completing the spin injection magnetization reversal is that the spin of the memory layer does not return to the original state even when the current (pulse current) is turned off, and is reversed to the end. This means that in FIG. 8, the direction of magnetization rotates to the equator plane c, and the perpendicular component Mz of magnetization becomes “0”.

As described above, the magnetization reversal takes a finite time and the time fluctuates. In other words, the spin injection magnetization reversal has a first stage, a second stage, and a third stage (see FIG. 6). For this reason, in the spin transfer magnetization reversal, there is a time t ₀ when the magnetization reversal probability does not increase so much at the initial stage of the magnetization reversal. The time t ₀ is shown in FIG. 5 and (Equation 1). For example, in an MTJ element using a perpendicular magnetization film, when the diameter of the element is smaller than the single domain diameter, the time (period) t ₀ is approximately expressed by (Equation 4).

In (Expression 4), “J _write ” indicates the current density of the write current, and “J _C0 ” indicates 0 K (absolute temperature) when the pulse width is set in the time for receiving one phonon (about 1 ns). ) Shows the current density of the magnetization reversal current.

FIG. 11 shows the time dependence of the magnetization reversal probability similarly to FIG. 5, and shows the time dependence of the magnetization reversal probability of the MTJ element under the same conditions as FIG. Note that the result shown in FIG. 11 is calculated by micromagnetic simulation using the LLG equation. The horizontal axis in FIG. 11 indicates time, and the vertical axis in FIG. 11 indicates Log ₁₀ (1-P) as in FIG.

In FIG. 11, characteristic lines J1 and J2 indicate magnetization reversal probabilities in the case where write currents having current density J1 and current density J2 are used. The characteristic lines J1 and J2 correspond to the primary approximate line of the magnetization reversal model of the present embodiment shown in (Equation 1). The current density J1 is 3.8 MA / cm ² and the current density J2 is 4.0 MA / cm ² .

The characteristic line A is an approximate line of a magnetization reversal model by a conventional simple thermal activation process. A conventional magnetization reversal model by a thermal activation process is represented by (Equation 5).

The time shown on the horizontal axis in FIG. 11 is the time (period) during which current is supplied to the MTJ element, and corresponds to the pulse width of the write current. “ΔT1” and “ΔT2” in FIG. 11 correspond to periods in which the pulse widths of the write currents having the current densities J1 and J2 are increased by about 7%, respectively.

As shown in FIG. 11, it can be seen that the probability that the magnetization does not reverse (1-P) decreases by an order of magnitude when the pulse width is increased by about 7% in the write currents having the current densities J1 and J2. If the pulse width of the write current is increased by about 14% to 15%, the probability that data cannot be written decreases by about two digits.

In the spin injection magnetization reversal model of (Equation 1) used in this embodiment, the write failure occurrence probability LOG ₁₀ (1-P) has a write current higher than that of the conventional spin injection magnetization reversal model shown in (Equation 5). It greatly depends on the pulse width.

Therefore, in the MRAM to which the spin injection magnetization reversal is applied, it is effective to increase the pulse width of the write current in order to reduce the write failure occurrence probability Log ₁₀ (1-P).

In FIG. 12 and FIG. 13, the characteristic line indicated by the solid line corresponds to the magnetization reversal model of the present embodiment shown in Expression (1), where ΔE / kBT in (Expression 1) is “60” and n is “2”. ", _{t 0} is" are respectively set to 7nsec ".

FIG. 12 shows the change of the magnetization reversal current (switching current) fluctuation σ (I _sw ) / I _sw with respect to the pulse width of the write current. In FIG. 12, the vertical axis corresponds to the fluctuation of the inversion threshold current, and the horizontal axis corresponds to the supply time of the inversion threshold current, that is, the pulse width _Twp of the write current. FIG. 13 shows a change in the switching current I _sw where the inversion probability is 0.5 with respect to the pulse width of the write current. In FIG. 13, the switching current I _sw is indicated by a current ratio I _sw / I _c0 .

12 and 13, the characteristic lines indicated by broken lines indicate the fluctuation σ (I _sw ) / I _sw and the current ratio I _sw / I _c0 of the magnetization reversal model shown in (Equation 5), respectively. .

As shown in FIG. 12, when a current is supplied to a certain MTJ element, the magnetization reversal model (Equation 1) of this embodiment has a fluctuation σ (I _sw ) / in comparison with the magnetization reversal model (Equation 5). It is shown that I _sw greatly depends on the current pulse width T _wp , and the fluctuation σ (I _sw ) / I _sw decreases as the pulse width T _wp increases.

Also in FIG. 13, the switching current I _sw supplied to a certain MTJ element depends on the pulse width T _{wp of the} current, and when the pulse width T _wp becomes longer, the rate of change becomes smaller.

Thus, also from the results shown in FIG. 12 and FIG. 13, by increasing the current pulse width T _wp , fluctuations in the write current to the MTJ element (memory layer) are reduced, and data write failures are reduced. I understand that well.

There is a means to increase the current value of the write current in order to reduce the probability of occurrence of a failure in which data cannot be normally written, but this has the following two drawbacks. First, the write current has an upper limit due to circuit restrictions such as the size of the selection transistor. Second, when the current value of the write current is increased, a write failure due to an excessive write current called back-hopping occurs. For these reasons, increasing the current value of the write current is not necessarily effective for reducing write defects.

Therefore, it is preferable to increase the pulse width of the write current and write data to the MTJ element. However, using a write current having a long pulse width for all data writing means that the data writing time becomes long. Therefore, high-speed operation, which is one of the advantages of a magnetic memory, for example, MRAM, is impaired. Therefore, it is necessary to devise another method so that the time required for data processing does not become excessively long.

In the magnetic memory according to the embodiment of the present invention, data stored (written) in the magnetoresistive effect element (MTJ element) 1 is output, and the output data is written back to the magnetoresistive effect element 1. In addition, a write current having a long pulse width is used. Data write-back (rewrite) is performed mainly when an error in data is corrected.

As shown in FIGS. 1 and 2, the magnetic memory according to the embodiment of the present invention includes an error detection and correction circuit 52 that detects and corrects an error in data output from the main memory 50. In addition, the magnetic memory of this embodiment includes a control circuit 51 having a function 53 for controlling the pulse widths of the write currents I _w1 and I _w2 .

In the magnetic memory according to the present embodiment, when data input from the outside is normally written to the MTJ element 1 in the main memory 50, a write current I _w1 having a certain pulse width T _wp1 is supplied to the MTJ element 1. For example, the pulse width T _wp1 corresponds to the dead time t ₀ or more shown in FIG. 5 and (Equation 1), and the sum of the coherent time t _coh and the amplification time t _amp shown in FIG. delay time t _id ) or more.

In the magnetic memory of the present embodiment, the error detection / correction circuit 52 performs error detection and correction on the data stored in the MTJ element 1 at the time of data writing or data reading. Then, the magnetic memory according to the present embodiment again writes the data corrected by the error detection / correction circuit 2 to the MTJ element 1 in the main memory 50.

The control circuit 51 in the magnetic memory according to the present embodiment determines whether data input from the outside is written or corrected data is written back.

When the corrected data is written back to the MTJ element 1, the control circuit 51 writes data corrected with _respect to the pulse width T _wp1 of the write current I _w1 based on the error detection and correction by the error detection and correction circuit 52. _Therefore , the operation of the write circuit 2 is controlled so as to increase the pulse width T _wp2 of the write current I _w2 for this purpose.

As described above, in the magnetic memory of this embodiment, the data input from the outside uses the write current I _w1 with the pulse width T _wp1 , and the data with the error corrected uses the pulse width T _wp2 ( A write current I _w2 of> T _wp1 ) is used.

As a result, the correction of data is performed, and when the corrected data is written back to the MTJ element 1, the write current I _w2 having a long pulse width T _wp2 is used, thereby reducing the probability that a write failure will occur. To do. For this reason, in the magnetic memory of this embodiment, the occurrence of defects in the data written to the MTJ element 1 is reduced.

Then, by correcting an error in data stored in the MTJ element 1, write defects, read disturbs and retention defects that occur in the magnetoresistive effect element 1 in the main memory 50 are corrected. That is, in the magnetic memory of this embodiment, data defects in the main memory 50 are reduced and malfunctions are reduced. Here, the defect (or error) is an error of 1-bit data, which is often correctable by an error detection and correction technique. If the number of defects included in one block exceeds a certain number (for example, two or more), correction cannot be performed even using an error detection and correction technique. In this embodiment, the fact that a defect cannot be relieved by using an error detection and correction technique is called a malfunction.

In addition, the magnetic memory according to the present embodiment increases the pulse width of the write current only when writing the error-corrected data back to the MTJ element 1. Therefore, the operation time of the magnetic memory, in particular, the write operation time does not become excessively long. Therefore, the high speed performance of the magnetic memory is not impaired.

Therefore, the magnetic memory according to the embodiment of the present invention has improved operation reliability and improved operation characteristics.

[Configuration example]
A configuration example of the magnetic memory according to the embodiment of the present invention will be described with reference to FIGS. 14 to 22. (1) Circuit
A configuration example of a circuit of the magnetic memory according to the embodiment of the present invention will be described with reference to FIGS. The magnetic memory of this configuration example is, for example, a magnetic random access memory (MRAM).

As shown in FIG. 14, the MRAM of this configuration example includes a main memory 50. The main memory 50 has a function of writing data to a memory cell (MTJ element 1) in the main memory 50 and a function of reading data from a memory cell (MTJ element 1) in the main memory 50.

FIG. 15 shows an example of the internal configuration of the main memory 50, showing the circuit configuration in the vicinity of the memory cell array of the MRAM.

A plurality of memory cells MC are arranged in an array in the memory cell array 20.

FIG. 16 is a diagram showing an example of the structure of the memory cell MC provided in the memory cell array 20. The upper end of the MTJ element 1 is connected to the upper bit line 32 via the upper electrode 31. The lower end of the MTJ element 1 is connected to the source / drain diffusion layer 37a of the selection transistor Tr via the lower electrode 33, the lead wiring 34, and the plug 35. The source / drain diffusion layer 37 b of the selection transistor Tr is connected to the lower bit line 42 via the plug 41.

On the semiconductor substrate (channel region) 36 between the source / drain diffusion layer 37a and the source / drain diffusion layer 37b, a gate electrode 39 is formed via a gate insulating film 38. The gate electrode of the selection transistor Tr functions as the word line WL.

Note that at least one of the lower electrode 33 and the extraction electrode 34 may be omitted. For example, when the lower electrode 33 is omitted, the MTJ element 1 is formed on the lead wiring 34. When the lead wiring 34 is omitted, the lower electrode 33 is formed on the plug 35. Further, when the lower electrode 33 and the extraction electrode 34 are omitted, the MTJ element 1 is formed on the plug 35.

The word line WL extends in the row direction and is connected to the gate of the selection transistor Tr constituting the memory cell MC.

One end of the word line WL is connected to the row control circuit 4. The row control circuit 4 performs a selection operation on the word line WL.

The bit lines BL and bBL extend in the column direction. One end of the MTJ element 1 is connected to the bit line BL, and the bit line bBL is connected to one end of the current path of the selection transistor Tr. The two bit lines BL and bBL constitute one set of bit line pairs.

Column control circuits 3A and 3B are connected to one end and the other end of the bit lines BL and bBL.

The

write circuits

2A and 2B are connected to one end and the other end of the bit lines BL and bBL via the column control circuits 3A and 3B. The

write circuits

2A and 2B each include a source circuit such as a current source or a voltage source for generating the write currents I _w1 and I _w2 and a sink circuit for absorbing the write current. The

write circuits

2A and 2B are electrically isolated from the bit lines BL and bBL when the write operation is not executed.

The operations of the

write circuits

2A and 2B are controlled by the control circuit 51 and a write pulse width control circuit 53 described later, and output write currents I _w1 and I _w2 shown in FIG. When writing data, the

write circuits

2A and 2B supply write currents I _w1 and I _w2 to the MTJ element 1. Write currents I _w1 and I _w2 flow through the MTJ element 1.

The current values i _w of the write currents I _w1 and I _w2 may be the same between the two currents I _w1 and I _w2 or may be different from each other.

In FIG. 17, the write currents I _w1 and I _w2 have the same current value. The current values i _w of the write currents I _w1 and I _w2 are preferably equal to or greater than the maximum value i _th among the inversion thresholds of the plurality of MTJ elements included in the memory cell array 20. The write current I _w1 has a predetermined pulse width T _wp1 , and the write current I _w2 has a pulse width T _wp2 longer than the pulse width T _wp1 . For example, a value equal to or greater than time t ₀ is used as the pulse width T _{wp1, and} is set based on, for example, (Equation 4). Further, the pulse width T _wp2 is set to a value longer by about 7% to 10% than the pulse width T _wp1 , for example.

As described above, the pulse widths T _wp1 and T _wp2 of the write currents I _w1 and I _w2 are defined by the full width at half maximum of the pulse-shaped write current.

The read circuit 5 is connected to one end of the bit lines BL and bBL via the column control circuit 3B. Readout circuit 5 includes, voltage or current source for generating a read current I _r, a sense amplifier for sensing and amplifying a read signal, and a latch circuit for temporarily holding data. The read circuit 5 is electrically isolated from the bit lines BL and bBL when the read operation is not executed.

The read circuit 5, a read operation, outputs the read current I _r. Figure 17 shows the waveform of the read current I _r is. For example, the maximum value of the current value i _r of the read current I _r is set to a value smaller than the inversion threshold value i _th . For example, the current value i _r of the read current I _r is constantly output during a period from the time when the pulse current rise ends to the time when the fall starts. For example, the pulse width T _rp of the read current I _r is defined by the full width at half maximum of the pulse current. For example, the pulse width T _rp may be shorter than the pulse width T _wp1 of the write current I _w1 and may be shorter than the dead time t ₀ . Thereby, in the MRAM of this configuration example, occurrence of read disturb may be reduced. However, not limited thereto, the read current current value _{i r} of _{I r} is sufficiently smaller than the inversion threshold _{i th,} the pulse width of the read current _I pulse width _r _{T rp} is write currents _I _{w1, I w2} It may be T _wp1 , T _wp2 or more.

Data reading is performed by passing a read current I _R in the MTJ element 1. When the resistance value in the parallel state is “R0” and the resistance value in the antiparallel state is “R1”, the value defined by “(R1−R0) / R0” is referred to as a magnetoresistance ratio (MR ratio). The magnetoresistance ratio varies depending on the material constituting the MTJ element 1 and the process conditions, but can take a value of several tens to several hundreds.

The information stored in the MTJ element 1 is read by detecting the fluctuation amount of the read current (bit line potential) caused by this MR ratio.

In the column control circuits 3A and 3B, a switch circuit for controlling the conduction state between the bit lines BL and bBL and the

write circuits

2A and 2B, and a switch circuit for controlling the conduction state between the bit lines BL and bBL and the read circuit 5 are provided. Is provided.

During the write operation, in the column control circuits 3A and 3B, the switch circuit connected to the memory cell MC to be written is turned on, and the other switch circuits are turned off. In addition, the row control circuit 4 turns on the selection transistor Tr in the selected memory cell MC. Then, a write current having a direction corresponding to the write data is supplied to the selected memory cell MC. When writing data, one of the

write circuits

2A and 2B is on the source side, and the

other write circuit

2B and 2A is on the sink side, depending on the direction of current flow.

The MRAM of this configuration example includes an error detection / correction circuit 52. The error detection / correction circuit 52 has a function of detecting whether or not an error is included in the data output from the main memory 50 to the circuit 52 and a function of correcting an error included in the data.

For example, the error detection / correction circuit 52 includes an encoding unit 61, an error detection unit 62, an error correction unit 63, and a decoding unit 64.

The encoding unit 61 adds a code (redundant bit) for detecting and correcting a data error to the data DT1 input from the outside via the buffer memory 54. Hereinafter, the code added to the data by the encoding unit 61 is referred to as an error detection / correction code.

The encoding unit 61 outputs the data nDT with the error detection code added thereto to the main memory 50. The data nDT is handled as write data to be written to the selected cell in the main memory 50. Also. The encoding unit 61 outputs a control signal (first control signal) NWC to the write pulse width control circuit 53 when an error detection code is added to the input data DT1.

The control signal NWC is generated in the write pulse width control circuit 53 and the main memory 50 so as to generate and output a write current I _w1 having a pulse width T _wp1 when data nDT inputted from the outside is written in the main memory 50. This is a signal for controlling the operation of the

write circuits

2A and 2B. Hereinafter, the control signal NWC is referred to as a normal write signal NWC.

The error detection unit 62 uses the error detection code of the data rDT output from the main memory 50 to check whether the data rDT read from the main memory 50 includes an error. When the data rDT includes an error, the error detection unit 62 outputs data erd including the error to the error correction unit 63. On the other hand, when the data rDT does not include an error, the error detection unit 62 outputs the data rDT to the decoding unit 64.

The error correction unit 63 corrects the error when the read data rDT includes an error. The error correction unit 63 outputs data (hereinafter referred to as correction data) cDT in which the error is corrected to the main memory 50 and the decoding unit 64. The correction data cDT output to the main memory 50 is written into a predetermined memory cell in the main memory 50. The correction data cDT is written, for example, in the same memory cell (MTJ element) that is stored before being corrected.

The error correction unit 63 outputs a control signal (second control signal) RWC to the write pulse width control circuit 53 when the correction data is output to the main memory 50.

Control signal RWC, when writing back corrected data CDT in the main memory 50, a pulse width _{T wp2} of the current _{I w2} used to write correction data CDT, longer than the pulse width _{T wp1} of normal write current _{I w1} As described above, this is a signal for controlling the operation of the write pulse width control circuit 53 and the

write circuits

2A and 2B in the main memory 50. As a result, when the data (corrected data cDT) once output from the main memory 50 is written again in the main memory 50 in the MRAM chip, the write current I _w2 having the long pulse width T _wp2 shown in FIG. Used for data writing. Hereinafter, the control signal RWC is referred to as a rewrite signal RWC.

The decoding unit 64 decodes the data rDT and cDT output from the error detection unit 62 or the error correction unit 63 during the read operation. Then, the decoding unit 64 outputs the decoded data to the buffer memory 54.

In the MRAM of this configuration example, the error detection / correction circuit 52 detects and corrects an error included in the data using, for example, an extended Hamming code as an error detection / correction technique. When the extended Hamming code is used, the error detection and correction code includes a Hamming code having a predetermined number of bits and a parity bit. However, other error detection and correction techniques such as the Reed-Solomon method may be applied to the error detection and correction circuit 52.

Also, the MRAM of this configuration example includes a buffer memory 54, for example. The buffer memory 54 temporarily holds data DT1 input from the outside. The buffer memory 54 temporarily holds the data output from the main memory 50 via the error detection and correction circuit 52, and outputs the held data DT2 to the outside.

The buffer memory 54 may be MRAM, DRAM (Dynamic RAM), or SRAM (Static RAM). For example, when the buffer memory 54 is composed of an MRAM, it is desirable that the probability of writing failure occurring in the MRAM serving as the buffer memory 54 is lower than the probability of writing failure occurring in the MRAM serving as the main memory 50.

Therefore, in the MRAM used for the buffer memory 54, the size of the selection transistor (for example, the channel length) is preferably larger than the size of the selection transistor Tr of the MRAM used for the main memory 50. As a result, the current driving capability of the selection transistor in the buffer memory 54 is increased, and a sufficiently large write current can be supplied to the MTJ element in the buffer memory 54. Therefore, write defects in the buffer memory 54 are reduced.

Note that a memory cell having a 2Tr + 1MTJ configuration including one MTJ element and two selection transistors may be used for the MRAM serving as the buffer memory 54. In this case, since the two selection transistors are used for one MTJ element, the substantial size of the selection transistor in one memory cell is increased. Therefore, similarly to increasing the size of one select transistor, a sufficiently large write current can be supplied to the MTJ element in the buffer memory 54 even when a 2Tr + 1MTJ type memory cell is used. As a result, write defects in the buffer memory 54 can be reduced.

The MRAM of this configuration example includes a control circuit 51 and a write pulse width control circuit 53. The control circuit 51 controls the operation of the entire MRAM (chip) based on the command signal CMD and the address signal ADR input from the outside. The command signal CMD indicates operations on the main memory 50 such as data writing, data reading, and data erasing. The address signal ADR indicates the address of the memory cell to be operated.

The write pulse width control circuit 53 has a predetermined pulse width T _wp1 as shown in FIG. 17 when the error detection / correction circuit 52 writes the external data nDT added with the error detection / correction code to the main memory 50. The operation of the main memory 50, particularly the operations of the

write circuits

2A and 2B, is controlled so as to use the write current _Iw1 . Under the control of the write pulse width control circuit 53, the

write circuits

2A and 2B in the main memory 50A output a write current I _w1 having a pulse width T _wp1 when data is externally written. Writing using the writing current I _w1 having the pulse width T _wp1 is referred to as normal writing.

The write pulse width control circuit 53 makes the pulse width longer than the pulse width T _wp1 of the write current I _w1 when writing the error-corrected data cDT in the main memory 50, and the write current having the long pulse width T _wp2 The operation of the main memory 50, particularly the operation of the

write circuits

2A and 2B, is controlled so as to use _Iw2 . Under the control of the write pulse width control circuit 53, the

write circuits

2A and 2B in the main memory 50A output a write current I _w2 having a pulse width T _wp2 when writing the corrected data. Writing using the writing current I _w2 having the pulse width T _wp2 is called rewriting or writing back.

The control of the pulse widths T _wp1 and T _wp2 is a period in which the write pulse width control circuit 53 activates the

write circuits

2A and 2B, specifically, the

write circuits

2A and 2B are electrically connected to the selected cell. It is executed by controlling the period.

The operation of the write pulse width control circuit 53 is controlled by the control circuit 51 and two control signals NWC and RWC. As described above, the normal write signal NWC is output from the encoding unit 61 in the error detection / correction circuit 52 when an error detection / correction code is added to the input data. The rewrite signal RWC is output from the error correction unit 63 in the error detection / correction circuit 52 when the error of the data rDT is corrected. When the normal write signal NWC is input, the write pulse width control circuit 53 outputs a control signal pwcs for outputting a write current I _w1 having a pulse width T _wp1 to the main memory 50. Write pulse width control circuit 53, when the rewriting signal RWC is input, outputs a control signal pwcs for outputting the write current _{I w2} of the pulse width _{T wp2} the main memory 50. Hereinafter, the control signal pwcs is referred to as a pulse width control signal pwcs. Pulse width control signal pwcs is, by showing that the use of one of the pulse width T _wp1 or T _wp2, to the pulse width of the write current may be controlled, by the presence or absence of the input of the pulse width control signal pwcs, write The pulse width of the current may be controlled.

Note that the write pulse width control circuit 53 may be provided in the control circuit 51. Alternatively, the control circuit 51 may have the same function as the write pulse width control circuit 53 without providing the write pulse width control circuit 53, and two control signals NWC and RWC may be input to the control circuit 51. In addition to the configuration shown in FIG. 14, the MRAM of this configuration example may further include a command interface to which a command signal is input and an address buffer to which an address signal is input.

The MRAM according to the configuration example of the present embodiment uses a write current I _w1 having a pulse width T _wp1 when data input from the outside is normally written in the MTJ element 1. Further, the MRAM of this configuration example corrects an error in the data stored in the MTJ element 1 and increases the pulse width of the write current when the corrected data is written back to the MTJ element 1 and the pulse width T _wp1. A write current I _w2 having a longer pulse width T _wp2 is used.

As a result, the MRAM of this configuration example can reduce write defects even if the characteristics (for example, the inversion threshold value) vary among the plurality of MTJ elements in the memory cell array 20. Further, the MRAM of this configuration example has a long pulse width T _wp2 only when the data stored (written) in the MTJ element includes an error and the corrected data is written to the MTJ element 1 again. A write current _Iw2 is used. Therefore, the operation cycle of the MRAM does not become excessively long, and high speed performance is not impaired.

Therefore, in the magnetic memory according to the embodiment of the present invention, the operation reliability is improved and the operation speed is improved.

(2) Operation
The operation of the magnetic memory according to the embodiment of the present invention will be described with reference to FIGS. Hereinafter, the operation of the magnetic memory according to the present embodiment will be described with reference to FIGS. 14 to 17 showing the configuration of the magnetic memory. In the operation of the magnetic memory according to the present embodiment, a case will be described in which an error in data is detected and corrected using an extended Hamming code. However, it goes without saying that other error detection and correction techniques (for example, Reed-Solomon method) can be applied to the magnetic memory of this embodiment.

(A) Operation example 1
The operation example 1 of the magnetic memory (MRAM) according to the configuration example of the present embodiment will be described with reference to FIG. Here, as an operation example 1 of the MRAM of this configuration example, writing of data used in the MRAM of this configuration example will be described.

As shown in FIG. 18, when writing data, a command signal CMD indicating writing, an address signal ADR, and data DT1 to be written are input from the outside (step ST1). The command signal CMD and the address signal ADR are input into the control circuit 51, for example. The data DT1 is input to the buffer memory 54, for example. The data DT1 is stored in the buffer memory 54 (step ST2B). For example, the data DT1 is preferably stored in the buffer memory 54 with a block length (for example, 64 bits) of data (information bits) in the extended Hamming code as one unit.

The input data DT1 is stored in the buffer memory 54 and also input to the error detection / correction circuit 52 via the buffer memory 54. The data DT1 is input to the encoding unit 61 in the error detection / correction circuit 52. For example, 8 redundant bits are added to the data DT1 as an error detection / correction code by the encoding unit 61. Data nDT to which redundant bits are added is output from the encoding unit 61 to the main memory 50.

At this time, a control signal (normal write signal) NWC is output from the encoding unit 61 to the write pulse width control circuit 53.

The write pulse width control circuit 53 controls (adjusts) the pulse width of the write current for writing the data nDT based on the input normal write signal NWC. A control signal (pulse width control signal) pwcs for setting the pulse width of the write current to “T _wp1 ” is output from the write pulse width control circuit 53 to the main memory 50.

In the main memory 50, the word line indicated by the address signal ADR is activated by the row control circuit 4, and the bit line indicated by the address signal ADR is activated by the column control circuits 3A and 3B. The

write circuit

2A, 2B in the main memory 50 is controlled by a control signal pwcs, for example, it outputs the write current _{I w1} having a predetermined pulse width _{T wp1} shown in Figure 17.

The write current _{I w1} is, the bit lines BL, bBL flow, is supplied to the selected cell indicated by the address signal ADR (MTJ element), data nDT is written (step ST2A). In normal writing, the pulse width T _wp1 of the write current I _w1 for writing the data nDT is set to, for example, the dead time t ₀ or more shown in (Equation 4).

Thus, when writing data nDT output from the coding unit 61 to the selected cell in the main memory 50, the pulse width T _wp1 of the write current I _w1, for example, the minimum time required for reversing the magnetization ( A pulse width corresponding to (period) is used.

After writing the data nDT write current I _w1 main memory 50 using, for verification operation performed on the written data, the written data is read from the main memory 50 to the error detecting and correcting circuit 52 (step ST3 ). Here, the data read for verification is referred to as verification data.

The verify data rDT is input to the error detection unit 62 in the error detection / correction circuit 52. The error detection unit 62 checks whether or not the data rDT stored in the MTJ element 1 includes an error, using redundant bits (error detection / correction code) added to the verification data rDT (step ST4).

If an error is detected in the verify data rDT, the error is corrected (step ST5). The verify data rDT including an error is output from the error detection unit 62 to the error correction unit 63. The error of the verify data rDT is corrected by the error correction unit 63 based on the redundant bits. If there is no error in the data written to the MTJ element 1, the data writing is terminated (step ST7).

The error-corrected data (corrected data) cDT is output to the main memory 50 and written again into the MTJ element 1 in the memory cell array 20 (step ST6). The correction data cDT is normally overwritten at the same address as the address written before the verify operation. That is, the correction data cDT is written to the same MTJ element 1 before and after correction.

The writing of the corrected data (step ST6), the write current _{I w2} of long pulse width _{T wp2} than the pulse width _{T wp1} of the write current _{I w1} used for normal writing is used.

In this operation example 1, when the correction data cDT is written to the MTJ element 1, a control signal (rewrite signal) RWC indicating rewrite is sent from the error correction unit 63 in the error detection and correction circuit 52 to the write pulse width control circuit 53. Is output.

When the rewrite signal RWC is input to the write pulse width control circuit 53, a pulse width control signal pwcs for increasing the pulse width of the write current is output from the write pulse width control circuit 53 to the main memory 50. By the pulse width control signal pwcs, as shown in FIG. 17, the write current I _w2 having the pulse width T _wp2 (> T _wp1 ) is output from the write circuit in the main memory 50, and the write current I _w2 is selected. Supplied directly to the cell.

For example, in the loop of the write operation and the verify operation, the pulse width of the write current is controlled by the pulse width control signal pwcs so as to be 1.10 times the pulse width of the current used in the previous data write. The The increase rate for increasing the pulse width of the write current is not limited to 1.10 times, and may be in the range of about 1.07 times to 1.15 times, for example.

As described above, it is determined by the two control signals NWC and RWC output from the error detection and correction circuit 52 whether the data writing is normal writing or rewriting (writing back). Thus, it is determined whether the pulse width of the write current is set to a predetermined pulse width _Twp1 or longer than the pulse width _Twp1 .

When data is written, if a read command is input to data for which processing is being executed during detection, correction, and rewriting of the write data error, the data The data stored in the buffer memory 54 corresponding to is read out to the outside (step ST2B).

The correction data cDT written back in the main memory 50 (hereinafter referred to as rewrite data) is again subjected to the verify operation (step ST3). Therefore, the rewritten data is output again from the main memory 50, and it is checked whether there is an error in the data. If an error is detected in the rewritten data, the error is corrected, and the corrected data is rewritten and then verified again. If there is no error in the rewritten data, the data writing ends (step ST7).

Note that when the verify operation is repeatedly performed and data rewrite is performed a plurality of times, it is preferable to increase the pulse width of the write current each time the number of rewrites is repeated for one data. In this case, the pulse width of the write current may be increased at the same magnification (for example, 1.1 times). However, the pulse width may be increased only during the first rewrite, and the pulse width of the write current used for the second and subsequent rewrites may be the same as the pulse width of the first write current.

The loop for rewriting data may continue indefinitely until there is no data error. However, the data write loop is limited to a certain number of times, for example, 10 times, and if the data error is not eliminated even after 10 rewrite loops are performed, the MTJ element itself indicated by the selected address is not included. It is effective to determine that there is a defect and to change the correction data (write-back data) to be stored in another address of the main memory 50.

In the rewriting of data, only erroneous bits may be overwritten in one selected cell, or all bits included in one block may be overwritten in each corresponding selected cell. However, in order to suppress the power consumption of the magnetic memory, it is preferable to overwrite only the erroneous bits.

<Effect of Operation Example 1>
The effect of the operation example 1 of the magnetic memory (MRAM) of this embodiment will be described with reference to FIGS.

FIG. 19 shows a distribution of current values I _{c, mp} of the current supplied to the MTJ element. The current value I _{c, mp} indicates a current value at which the magnetization reversal probability of the storage layer of the MTJ element becomes 0.5 when data is written to the MTJ element using a write current having a certain pulse width.

In FIG. 19, a distribution C indicates a distribution of currents I _{c and mp to} be satisfied when data correction and rewriting are not executed. In this case, in order to reduce the occurrence probability of malfunction to a certain specification value or less, it is necessary to reduce the variation of the distribution C. A distribution D indicates a distribution when data correction and rewriting are executed. When the probability of malfunction occurrence is less than or equal to a certain specification value, the distribution D is corrected and rewritten, and therefore the variation may be larger than the distribution C.

FIG. 19 also shows the distribution of the write current _Iwr . In FIG. 19, the horizontal axis indicates the magnitudes of currents I _{c, mp} , and I _write , and the vertical axis indicates the existence probability.

As shown in FIG. 19, the distributions C and D of the currents I _{c and mp} secure predetermined margin regions MR and CR with respect to the distribution of the current I _wr . In the operation example 1 of the present embodiment, as shown in the distribution D of FIG. 19, the correction and rewriting of data is executed, so that the correction and rewriting of data indicated by the distribution C is not executed. There is an advantage that the tolerance of variation of the current I _{c, mp} is widened. That is, even if there is a large variation between bits (MTJ elements) in the memory cell array, the malfunction probability can be suppressed. In this embodiment, the malfunction is a defect that cannot be corrected by the error detection and correction technique. In the present embodiment, a defect that can be corrected by the error detection and correction technique is simply referred to as a defect, an error, or an error.

In a magnetic memory, for example, an MRAM, since the magnetization reversal of a magnetic material is a stochastic phenomenon, write failure, read disturb, retention failure, and the like occur. It is preferable that the total probability of malfunction caused by these is guaranteed to be 1000 FIT (FailuresailIn Time) or less per chip. Therefore, here, the effect of this operation example (write operation) is described assuming 1000 FIT / chip. Note that 1000 FIT / chip is a specification for a general DRAM soft error.

Here, in a 1-Gbit MRAM, for example, an extended Hamming code is used as an error detection / correction code, an 8-bit error detection / correction code (redundant bit) is added to 64-bit data (information bits), and 72 bits are 1 Let it be a block. In this case, the total number of blocks included in the MRAM is 1.68 × 10 ⁷ . When data writing and data reading are repeated alternately for 10 years for each block, the total number of times of writing is 3.15 × 10 ¹⁵ times. The total number of readings is also 3.15 × 10 ¹⁵ times.

In order to suppress the probability of simultaneous occurrence of 2-bit defects in one block to 1000 FIT / chip in one data write, a write defect in one write to one bit (one MTJ element) Is preferably 2 × 10 ⁻¹⁰ or less. In addition, in order to suppress the probability of simultaneous occurrence of 2-bit defects in one block to 1000 FIT / chip in one data read, the probability of occurrence of read disturbance q in one read for one bit q (Read) is preferably 2 × 10 ⁻¹⁰ or less.

Here, it is considered that the write failure becomes prominent in either “0” data write or “1” data write. Further, here, it is considered that the read disturb occurs only in either “0” data read or “1” data read.

Next, paying attention to an arbitrary block in the memory cell array, the probability of malfunction is considered.
The probability p ₁ (write) that a 1-bit write failure occurs in one block (72 bits) in one data write is represented by (Equation 6).

The probability p ₂₊ (write) in which a write failure occurs simultaneously in two blocks or more in one block and malfunctions is expressed by (Equation 7).

The probability p ₁ (read) that 1-bit read disturb occurs in one block in one data read is expressed by (Equation 8).

Further, the probability p ₂₊ (read) in which two or more bits are simultaneously generated in one block and a malfunction occurs is expressed by (Equation 9).

In data writing and data reading, the probability that a 1-bit write failure and a 1-bit read disturb occur in the same block and malfunctions is represented by (Equation 10).

The total probability of malfunctions can be expressed by (Equation 11) from the above probability of defects.

As described with reference to FIG. 17 and FIG. 18, data writing in the MRAM of this configuration example is performed by writing data from the outside into the MTJ element and then correcting the error included in the written data with the MTJ element. When the data is written again, the pulse width of the correction data write current is made longer than the pulse width of the external data write current. As a result, the probability p ₁ (write) of 1-bit write failure is sufficiently reduced.

For example, as described with reference to FIG. 11, when the pulse width is increased by 7% with respect to a pulse width of a certain write current, the probability of write failure p ₁ (write) is reduced to about 1/10 and the pulse width is reduced. When it becomes longer by about 14% to 15%, the probability of write failure p ₁ (write) decreases to about 1/100.

Therefore, in the same block, a 1-bit write failure occurs due to writing, and a 1-bit read disturb occurs due to reading, so that the probability of malfunction can be reduced to 1/100.

In a general memory (for example, DRAM), the probability of occurrence of a defect is set to p ₁ (write) = p ₁ (read) in order to disperse the risk of malfunction during writing and reading.

However, as shown in (Equation 11), the probability of occurrence of a malfunction, the correlation to the sum of the first bit of the writing failure probability p _{1 (write)} and 1 occurrence of bit read disturb probability p _{1 (read)} Therefore, if the occurrence probability p ₁ (write) of 1-bit write failure is sufficiently small, even if the occurrence probability p ₁ (read) of 1-bit read disturb is slightly increased, the operation of the MRAM is large. There is no adverse effect.

As described above, in operation example 1 of the MRAM of the present configuration example, if the write back corrected data to the main memory (MTJ element 1), by lengthening the pulse width of the write current, the writing failure probability p ₁ ( (write) is made sufficiently small.

As described above, when the pulse width of the write current is made 7% longer than a certain pulse width, the write failure occurrence probability p ₁ (write) is reduced to 1/10. As a result, the read disturb occurrence probability p ₁ (read) can be increased up to 1.9 times. When the pulse width of the write current is 14% to 15% longer than a certain pulse width, the probability of write failure p ₁ (write) is reduced to 1/100. As a result, the read disturb occurrence probability p ₁ (read) can be increased to 1.99 times.

Further, by being able to read disturb occurrence probability _{p 1} a (read) to 1.9 times, the current value _{i r} of the read current _{I r} shown in FIG. 17, it is 1.02 times. Therefore, in the memory cell array 20 in the main memory 50, because even variations in the resistance of the MTJ element (MR ratio) is increased, it can supply a relatively large read current I _r to the MTJ element, S for reading A sufficiently large / N ratio can be secured. As described above, since a relatively large read current can be used when reading data in accordance with the write operation of the MRAM of this configuration example, accurate data can be obtained even if the resistance value (MR ratio) of the MTJ element is small. Can be executed, and the tolerance of variation of the MTJ element 1 in the memory cell array 20 with respect to the reading can be increased.

Further, the fact that the write failure occurrence probability p ₁ (write) can be reduced to, for example, 1/100, as shown in FIG. 19, the current I _{c, mp is} applied to a plurality of MTJ elements 1 of the memory cell array 20. It means that the tolerance of the variation of the spread is widened. This will be described with reference to FIGS.

20 and 21, a phenomenon in which inversion threshold varies between the MTJ elements, and a setting example of a typical write current density inversion threshold current density J _c is taken into consideration the phenomenon that variation between MTJ element, Show.

In the example shown in FIG. 20, when the variation between the elements of the current density J _c is 3% data, the pulse width is written by the write current of 20 nsec. In FIG. 20, the average of the write failure occurrence probability q (write) at the write current density J _wr is set to be 1 × 10 ⁻¹⁰ .

In FIG. 20, the vertical axis indicates the probability, and the horizontal axis indicates the current density. Further, in FIG. 20, a characteristic line f1 represents the normal distribution of the variation among elements of the current density J _c, the characteristic line PA represents the probability of occurrence of writing failure, the product of the probability PA characteristic line S1 is a normal distribution f1 Is shown. A line J _wr indicates the current density of the set write current.

FIG. 21 shows a case where the pulse width of the write current used in the setting example shown in FIG. 20 is increased by 14%. In Figure 21, a characteristic line f2 represents a normal distribution of variation among elements of the current density J _c, the characteristic line PB indicate the probability of occurrence of writing failure, characteristic line S2 represents the product of a normal distribution f2 probability PB ing. A line J _wr indicates the current density of the set write current.

In Figure 21, variation among elements of the current density _{J c} is 5%. As shown in FIG. 21, when the pulse width of the write current is increased by 14%, even inter-element variations in the current density J _c is increased up to about 5%, normal distribution f1, f2 and probability PA, PB With reference to product values S1 and S2, the average of the occurrence probability q (write) of defects shown in FIG. 21 is about 1 × 10 ⁻¹⁰ . This value is substantially the same as the example shown in FIG.

As described above, by reducing the occurrence probability p ₁ (write) of the write failure by the operation example 1 (data writing) of the MRAM of the present configuration example, the tolerance of the inter-element variation of the current density J _c is 3 It corresponds to an increase from 5% to 5%.

As described above, write data input from the outside is stored in the main memory 50 and also temporarily stored in the buffer memory 54. Therefore, when a command signal CMD for reading data is input during a cycle in which detection, correction, and data write-back of data are executed, the data is read from the buffer memory 54. Therefore, the operation of the memory is not slowed down by the process of writing back the correction data. Therefore, the high-speed operation of the magnetic memory, for example, the MRAM is not impaired.

As described above, the magnetic memory according to the present embodiment writes data from the outside to the MTJ element 1 using the write current having the pulse width _{Twp1 when} writing data. Then, the magnetic memory according to the present embodiment verifies whether or not the data written in the MTJ element 1 has been normally written. When the written data includes an error, the magnetic memory according to the present embodiment corrects the error and writes the corrected data to the MTJ element again. Corrected data using the write current _{I w2} of long pulse width _{T wp2} than the pulse width _{T wp1,} written in the MTJ element 1. As a result, the time for writing data is not excessively lengthened, and the probability of writing failure is reduced.

Also, since the occurrence of write failures in the memory cell array of the main memory is reduced, the occurrence of malfunctions due to write failures, read disturbs and retention failures is also reduced.

Therefore, according to the magnetic memory according to the embodiment of the present invention, the reliability of the operation can be improved and the operation characteristics can be improved.

(B) Operation example 2
An operation example 2 of the magnetic memory (MRAM) according to the configuration example of this embodiment will be described with reference to FIG. Here, as operation example 2 of the MRAM of this configuration example, reading of data used in the MRAM of this configuration example will be described. In this operation example 2, the circuit configuration of the MRAM is the same as that of the operation example 1, and the common configuration and operation (steps) will be described as necessary.

FIG. 22 is a flowchart showing the data read operation of the MRAM in this configuration example.

First, as shown in FIG. 22, data is written to a selected cell (MTJ element 1) in the main memory 50 in an operation cycle of the MRAM (step ST10). This data is, for example, normal writing, that is, data written using the write current I _w1 having the pulse width T _wp1 shown in FIG. However, rewriting, i.e., it may be data that has been written using a write current I _w2 of the pulse width T _wp2 shown in Figure 17.

When reading data, a command signal CMD indicating a read command and an address signal ADR indicating a selected cell are input from the outside (step ST12). The command signal CMD and the address signal ADR are input into the control circuit 51, for example.

Data is output from the main memory 50 based on the control of the control circuit 51. In this operation example, the data output from the main memory 50 by the read command is called read data rDT.

Read data rDT is input to the error detector 62 in the error detection and correction circuit 52. The read data rDT including the error detection / correction signal (redundant bit) is inspected by the error detection unit 62 to determine whether or not it includes an error (step ST13).

If no error is detected in the read data rDT, the read data rDT is output to the decoding unit 64 without being corrected. The decryption unit 64 decrypts the input read data rDT. The decrypted data is temporarily stored in the buffer memory 54. Then, data DT2 is output from the buffer memory 54 to the outside of the chip (step ST14). As a result, when there is no error in the read data, the data reading ends.

On the other hand, when an error is detected in the read data rDT, the error is corrected (step ST15). The read data rDT is output to the error correction unit 63, and errors in the read data rDT are corrected by the error correction unit 63 based on the added redundant bits.

The corrected data is output to the decryption unit 64 and decrypted. The decoded correction data cDT is output to the outside as output data DT2 via the buffer memory 54 (step ST16). The correction data cDT is temporarily stored in the buffer memory 54 at the same time as being output to the outside (step ST17). When a read command for the data is input while the correction data cDT is being rewritten, the data stored in the buffer memory 54 is output to the outside.

At the time of reading data in this operation example, the correction data cDT is output to the outside, and the correction data cDT is written back to the main memory 50 (step ST18).
If corrected data cDT is written back to main memory 50 writes, for example, as the write current I _w2 shown in Figure 17, the pulse width T _wp2 of the write current I _w2 used for rewriting, usually used for writing than the pulse width _{T wp1} of the current _{I w1,} it is lengthened. This write current _{I w2,} correction data cDT is rewritten in the MTJ element 1.

The rewritten data cDT is read again from the main memory 50 (MTJ element 1) to the error detection unit 62, and it is checked whether there is an error (step ST19).

When the correction data cDT written back does not contain an error, the data correction and data rewriting at the time of data reading are completed.

When the rewritten data cDT includes an error again, the error of the data is corrected again (step ST20), and the corrected data is written in the main memory 50 again. For the second rewriting, it is effective to make the current pulse width longer than the first rewriting. For example, each time the number of data correction and rewrite loops (ST18 to ST20) is repeated, the pulse width of the write current is increased by 1.1 times. However, a write current having the same pulse width may be used for the first rewrite and the second and subsequent rewrites.

The data corrected during this rewrite loop (ST18 to ST20) is temporarily stored in, for example, the buffer memory 54 (step ST17). The stored data is rewritten at every rewrite loop.

And when there is no error in the data to be written back, the data rewriting is completed.

The rewrite loop (ST18 to ST20) may be continued until there is no data error, and the rewrite loop may be limited to a predetermined number of times (for example, 10 times). For example, if the error does not disappear even if rewriting is performed 10 times for the same address (MTJ element 1), changing the address to write to another address in the main memory 50 is possible in the memory cell array. It is effective to reduce the data defects.

<Effect of Operation Example 2>
Hereinafter, the effect of the operation example 2 of the magnetic memory (MRAM) of the present embodiment will be described. In addition, about the effect similar to the effect described in the operation example 1, description here is abbreviate | omitted.

When the data read from the MRAM described in this operation example 2 is applied to the MRAM, a write failure that has occurred during normal write can be corrected when the data is read.

Further, in the data reading in the second operation example, the pulse width of the write current used for rewriting is made longer than the pulse width of the write current used in normal writing, which occurs when data is written back by rewriting. Write defects can be reduced.

Furthermore, the data reading in this operation example 2 is also effective for a retention failure that occurs when data is retained due to thermal disturbance.

That is, according to the data reading in this operation example 2, a defective bit caused by a read disturb failure, a write failure, a retention failure, or the like can be corrected to a correct bit at an early stage. As a result, an error of 2 bits or more occurs in one block, and even if error detection and correction technology is used, it is possible to reduce the probability of malfunction that cannot correct data errors.

Similarly to the above-described operation example 1, only when the corrected data is rewritten, the high-speed operation of the MRAM is not impaired by increasing the pulse width of the write current.

[Modification]
A modification of the configuration and operation of the magnetic memory described in the configuration example will be described with reference to FIGS. In this modification, the same reference numerals are given to the same configurations as those described in the basic example and the configuration example, and detailed description thereof is omitted.

In FIG. 14, normal data writing and data rewriting at the time of correction are performed based on the control signals NWC and RWC output from the encoding unit 61 and the error correction unit 63 provided in the error detection and correction circuit 52, respectively. As described above, the pulse width of the write current is controlled.

On the other hand, instead of using the control signal, a determination signal (flag) added to the data may be used to determine whether normal writing or rewriting (data writing back).

FIG. 23 shows an internal configuration of an MRAM according to a modification of the present embodiment.
A determination signal for determining whether normal writing or correction writing is added to the data nDT and cDT. For example, when an error detection / correction code based on a normal Hamming code is used, 7 bits of redundant bits as an error detection / correction code are added to 64-bit data, and it is further determined whether normal writing or correction writing is performed. A 1-bit decision signal (hereinafter referred to as a decision bit) is added. In this case, 72-bit data is handled as one block. For example, when the determination bit is “0”, normal writing is indicated, and when the determination bit is “1”, correction writing is indicated.

The encoding unit 61 sets the determination bit to “0” when data wDT is input or output. The error correction unit 63 sets the determination bit to “1” when data rDT is input or output.

23, the write pulse width control circuit 53 is arranged adjacent to the main memory 50. For example, data nDT and cDT are input to the write pulse width control circuit 53 directly or via the main memory 50. Only the determination bits included in the data nDT and cDT may be input to the write pulse width control circuit 53.

The write pulse width control circuit 53 has a function of discriminating a determination bit included in one block of data. Depending on whether the determination bit is “1” or “0”, data writing is performed as normal writing or Determine correct write.

Thus, similar to the configuration shown in FIG. 14, the write pulse width control circuit 53 generates and outputs the write current I _w1 having the pulse width T _wp1 shown in FIG. The operation of the write circuit in the main memory 50 is controlled. Further, the write pulse width control circuit 53 generates and outputs a write current I _w2 having a pulse width T _wp2 longer than the pulse width T _wp1 shown in FIG. The operation of the write circuit is controlled.

In this way, it is possible to determine whether normal writing or rewriting is performed based on the determination bit included in the data written to the MTJ element, and writing data to the MTJ element using a write current having a predetermined pulse width according to the determination result. Can do.

Accordingly, it is not necessary to provide a new control signal to the MRAM chip, and accordingly, wiring for supplying the control signal is not required, so that the load on the entire control of the chip and the wiring layout in the chip is reduced.

One of the points of the MRAM according to the embodiment of the present invention is that a write current used for normal writing when data once read from the MTJ element 1 is written back to the MTJ element 1 in the operation cycle in the chip. Compared to I _w1 , the pulse width of the write current I _w2 used for rewriting is increased. As a result, the probability of occurrence of a write failure is reduced, and data errors in the main memory (memory cell array) are reduced.

The operation of increasing the pulse width of the write current when rewriting data can be applied to the refresh operation (memory holding operation) for the main memory 50.

FIG. 24 shows an internal configuration of an MRAM according to a modification of the present embodiment, and FIG. 25 shows a flowchart of an operation (refresh operation) of the MRAM according to the modification.

For example, as shown in FIG. 24, the MRAM in which the refresh operation of this modification is used includes a counter unit 59 that counts the number of times of reading.

As shown in FIG. 25, externally input data is written to the MTJ element in the main memory 50 (step ST21). At this time, the data wDT is written by normal writing, and a write current I _w1 having a pulse width T _wp1 shown in FIG. 17 is used for writing data.

Thereafter, when a read command is input, the data stored in the main memory 50 is read (step ST22). Note that error detection and correction may be performed on the read data, or error detection and correction may not be performed.

The counter unit 59 in the control circuit 51 counts the number of times data is read (step ST23). The counter unit 59 may count the input of a command signal CMD indicating a read command, or may count the output of data from the main memory 50.

The control circuit 51 compares the value (hereinafter referred to as a count value) N _n counted by the counter unit 59 with a reference value N _rfl for executing the refresh operation (step ST24).

When the count value N _n is equal to or _smaller than the reference value N _rfl , the refresh operation is not executed, and the next operation (for example, data reading) or the operation ends. Even at the end of the operation, the counted counter value N _n is held in the counter unit 59 as the counter value N _n−1 thus far.

On the other hand, the count value _{N n} is greater than the reference value _{N rfl,} refresh operation is executed (step ST25). After the data stored in the main memory 50 is read once by the refresh operation, the data is written back into the main memory 50 again. Note that error detection and correction may be performed during the refresh operation.

During the refresh operation, the data read from the main memory 50 is written back into the main memory 50 using the write current I _w2 having a pulse width longer than that when writing data from the outside (step ST26). ). That is, during the refresh operation, as shown in FIG. 17, the write current I _w2 having a pulse width T _wp2 longer than the pulse width T _wp1 is used for data write back to the main memory 50.

In the refresh operation, a control signal RFL indicating the refresh operation is input from the control circuit 51 to the write pulse width control circuit 53. Based on the control signal RFL, the write pulse width control circuit 53 controls the operation of the

write circuits

2A and 2B so as to increase the pulse width of the write current.

After the refresh operation using the write current I _w2 of long pulse width T _wp2, for example, reading of data in the next operation cycle is executed. Of course, the operation following the refresh operation may be data writing.

With the above operation, the refresh operation of the MRAM of this modification is completed.

As a result, it is possible to reduce the occurrence of defective data writing when data stored in the main memory 50 (MTJ element 1) is written back to the main memory 50 in the refresh operation. Further, only the data rewriting at the time of the refresh operation, the longer the pulse width T _wp2 of the write current I _w2 used therefor, by the pulse width of the write current is increased, the high-speed operation of the MRAM is impaired No.

[Others]
In an embodiment of the present invention, as shown in FIG. 2 and FIG. 17, the write current I _w2 for the write current I _w1 and rewrite for normal writing is set to the same current value. However, the pulse width T _wp2 of the write current I _w2 used for writing back the read data once to the MTJ element is the pulse width T _wp1 of the write current I _w1 for newly writing data from the outside to the MTJ element. If longer, the magnitudes of the current values of the two currents I _w1 and I _w2 may be different from each other.

The embodiment of the present invention has been described by taking as an example a magnetic memory (MRAM) in which a main memory is configured using a magnetoresistive element as a storage element. However, the present invention is not limited to this. For example, elements such as ReRAM (Resistive RAM) and PCRAM (Phase Change RAM) that store a device whose resistance value reversibly changes by controlling the pulse width of the write current (write voltage) are stored. It goes without saying that other memories used for the element can obtain the same effects as those described in the embodiment of the present invention.

The example of the present invention is not limited to the above-described embodiment, and can be embodied by modifying each component without departing from the scope of the invention. Various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above-described embodiments, or constituent elements of different embodiments may be appropriately combined.

50: main memory, 51: control circuit, 52: error detection and correction circuit, 53: write pulse width control circuit, 54: buffer memory, 20: memory cell array, 1: magnetoresistive effect element, 2, 2A, 2B: write circuit .

Claims

Magnetoresistance having a first magnetic layer whose magnetization direction is invariable, a second magnetic layer whose magnetization direction is variable, and an intermediate layer provided between the first magnetic layer and the second magnetic layer An effect element;
Error detection that detects whether or not the first data written in the magnetoresistive element includes an error, and outputs the second data in which the error is corrected when the first data includes an error A correction circuit;
A write circuit for generating one of a first write current having a first pulse width and a second write current having a second pulse width longer than the first pulse width and passing the generated current through the magnetoresistive element When,
A control circuit for controlling the write circuit so that the second write current flows through the magnetoresistive element when writing the second data to the magnetoresistive element;
A magnetic memory comprising:
When writing the first data to the magnetoresistive element,
2. The magnetic memory according to claim 1, wherein the control circuit controls the write circuit so that the first write current flows through the magnetoresistive element. 3.
The first pulse width is set to be equal to or greater than a total period of a period until the magnetization of the storage layer starts coherent precession and a period during which the coherent precession is amplified. The magnetic memory according to claim 2.
The magnetic memory according to claim 1, further comprising a buffer memory that temporarily stores third data corresponding to the first data.
The third data is read from the buffer memory when the reading of the first data is requested while the second data is being written to the magnetoresistive effect element. The magnetic memory according to claim 4.
When the first data is written to the magnetoresistive effect element, the error detection and correction circuit outputs a first control signal to the control circuit;
When the second data is written to the magnetoresistive effect element, the error detection and correction circuit outputs a second control signal to the control circuit;
The control circuit includes:
Controlling the write circuit so that the first write current flows through the magnetoresistive element when the first control signal is input;
Controlling the write circuit so that the second write current flows through the magnetoresistive element when the second control signal is input;
The magnetic memory according to claim 2.
Including a first determination signal indicating that the first data is written using the first write current;
A second determination signal indicating that the second data is written using the second write current;
The control circuit includes:
Controlling the write circuit to cause the first write current to flow through the magnetoresistive element in accordance with the first determination signal;
Controlling the write circuit so as to cause the second write current to flow through the magnetoresistive element in accordance with the second determination signal;
The magnetic memory according to claim 2.