JP4956640B2 - Magnetic memory - Google Patents

Description

  The present invention relates to a magnetic memory.

  In recent years, a magnetoresistive random access memory (MRAM) using a magnetic tunnel junction element (hereinafter referred to as an MTJ element) has attracted attention.

  One of the MRAM data writing methods is a spin injection magnetization reversal method. In the spin injection magnetization reversal method, a current (write current) greater than or equal to the current value in the MTJ element is passed. In reading data, a current (read current) is passed through the MTJ element.

  Conventionally, it has been considered that the magnetization reversal process of the MTJ element by supplying current (spin injection) can be represented by a simple thermal activation process. However, immediately after the start of current supply to the MTJ element, there is a time when the reversal probability is almost zero, and a magnetization reversal process in which the reversal probability increases after a certain time has been newly proposed. (For example, refer nonpatent literature 1).

  In the spin injection type MRAM, the current value of the write current is set to a current value larger than a threshold value (hereinafter referred to as an inversion threshold value) at which magnetization reversal is caused by spin injection, and the read current value is A current value smaller than the inversion threshold is set.

  However, the inversion threshold varies from element to element due to variations in characteristics of a plurality of MTJ elements constituting the MRAM. In addition, when data is repeatedly written to the same MTJ element, there is a phenomenon that the inversion threshold value for the element fluctuates.

  For this reason, a write failure at the time of data writing, a read disturbance due to a read current at the time of reading data, a failure in which magnetization is reversed due to a thermal disturbance at the time of data retention, and a retention failure occur. As described above, since the magnetization reversal of the MTJ element (magnetic material) is a stochastic phenomenon, a defect occurs during the operation of the MRAM.

  In order to cope with these defects, an MRAM in which an error correction code (ECC) is applied to data reading has been studied (for example, see Patent Document 1).

  In the technique disclosed in Patent Document 1, even if error correction is performed on read data, an error in the generated data remains in the data stored in the MRAM. For this reason, every time data is read, error correction is performed, and the operation speed is reduced. Further, in the normal error detection and correction technique, if there are errors of a predetermined number of bits or more in data (blocks) of a predetermined size, correction cannot be performed.

US Pat. No. 7,370,260

H. Tomita et al., Applied Physics Express, Vol. 1 (2008) 061303

  The present invention proposes a technique for improving the reliability and operating characteristics of a magnetic memory.

  A magnetic memory according to an example of the present invention includes a first magnetic layer whose magnetization direction is unchanged, a second magnetic layer whose magnetization direction is variable, and a gap between the first magnetic layer and the second magnetic layer. And detecting whether or not the first data written in the magnetoresistive effect element includes an error, and when the first data includes an error, the An error detection and correction circuit for outputting second data in which an error is corrected, a first write current having a first pulse width, and a second write having a second pulse width longer than the first pulse width A write circuit that generates one of the currents and causes the magnetoresistive effect element to flow, and when writing the second data to the magnetoresistive effect element, causes the second write current to flow to the magnetoresistive effect element To control the writing circuit It includes a control circuit, a.

  A magnetic memory according to an example of the present invention includes a first magnetic layer whose magnetization direction is unchanged, a second magnetic layer whose magnetization direction is variable, and a gap between the first magnetic layer and the second magnetic layer. And detecting whether or not the first data written in the magnetoresistive effect element includes a defect, and the first data includes a defect. A defect detection circuit for outputting second data that does not include a defect, a first write current having a first pulse width, and a second write current having a second pulse width longer than the first pulse width. A write circuit that generates one of them and flows the magnetoresistive effect element; and when writing the second data to the magnetoresistive effect element, the second write current is allowed to flow to the magnetoresistive effect element. Control circuit for controlling the writing circuit And, equipped with a.

  According to the present invention, the reliability and operating characteristics of a magnetic memory can be improved.

1 is a diagram showing a basic example of a magnetic memory according to an embodiment. The figure which shows the pulse waveform of write-in electric current. The figure which shows an example of a magnetoresistive effect element. The figure which shows an example of a magnetoresistive effect element. The figure for demonstrating the magnetization reversal model which concerns on embodiment. The figure for demonstrating the magnetization reversal model which concerns on embodiment. The figure for demonstrating the magnetization reversal model which concerns on embodiment. The figure for demonstrating the magnetization reversal model which concerns on embodiment. The figure for demonstrating the magnetization reversal model which concerns on embodiment. The figure for demonstrating the magnetization reversal model which concerns on embodiment. The figure for demonstrating the dependence of the magnetization reversal with respect to the pulse width of an electric current. The figure for demonstrating the dependence of the magnetization reversal with respect to the pulse width of an electric current. The figure for demonstrating the dependence of the magnetization reversal with respect to the pulse width of an electric current. 1 is a block diagram showing a configuration example of a magnetic memory according to an embodiment. The figure which shows the structural example of a main memory. The figure which shows the structural example of a memory cell. The figure which shows the pulse waveform of a write current and a read current. 6 is a flowchart illustrating an operation example of the magnetic memory according to the embodiment. The figure for demonstrating the effect with respect to the magnetic memory which concerns on embodiment. The figure for demonstrating the effect with respect to the magnetic memory which concerns on embodiment. The figure for demonstrating the effect with respect to the magnetic memory which concerns on embodiment. 6 is a flowchart illustrating an operation example of the magnetic memory according to the embodiment. 1 is a block diagram showing a configuration example of a magnetic memory according to an embodiment. 6 is a flowchart illustrating an operation example of the magnetic memory according to the embodiment. The figure for demonstrating the effect with respect to the magnetic memory which concerns on embodiment. The figure for demonstrating the effect with respect to the magnetic memory which concerns on embodiment. The figure for demonstrating the effect with respect to the magnetic memory which concerns on embodiment. The figure for demonstrating the effect with respect to the magnetic memory which concerns on embodiment. The figure for demonstrating the effect with respect to the magnetic memory which concerns on embodiment. The figure for demonstrating the effect with respect to the magnetic memory which concerns on embodiment. The block diagram which shows the modification of the magnetic memory which concerns on embodiment. The block diagram which shows the modification of the magnetic memory which concerns on embodiment. 6 is a flowchart illustrating an operation example of the magnetic memory according to the embodiment. The block diagram which shows the modification of the magnetic memory which concerns on embodiment.

  Hereinafter, embodiments for carrying out examples of the present invention will be described in detail with reference to the drawings. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given as necessary.

[Embodiment]
(1) Basic example
A basic example of a magnetic memory according to an embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 shows an example of the configuration of the magnetic memory according to the present embodiment.

  As shown in FIG. 1, the magnetic memory includes a magnetoresistive effect element 1 and a switch Tr in the main memory 50. The magnetoresistive effect element 1 and the switch Tr constitute one memory cell. The magnetoresistive effect element 1 is used as a memory element. The switch Tr is used as a selection element for the magnetoresistive effect element 1.

  The magnetoresistive effect element 1 is connected to two bit lines BL and bBL. One end of the magnetoresistive effect element 1 is connected to the bit line BL, and the other end of the magnetoresistive effect element 1 is connected to the bit line bBL via the switch Tr.

The switch Tr is, for example, a field effect transistor (FET). Hereinafter, the switch Tr is referred to as a selection transistor Tr. One end (source / drain) of the current path of the selection transistor Tr is connected to the other end of the magnetoresistive effect element 1, and the other end (source / drain) of the current path of the selection transistor Tr is connected to the bit line bBL. . A control terminal (gate) of the selection transistor Tr is connected to the word line WL. For example, the word line WL extends in a direction crossing the extending direction of the bit lines BL and bBL. When writing data, the write currents I _w1 and I _w2 shown in FIG. 2 flow between the two bit lines BL and bBL and are supplied to the magnetoresistive effect element 1.

  3 and 4 are cross-sectional views showing the configuration of the magnetoresistive element 1. FIG. As the magnetoresistive effect element 1, for example, an MTJ (magnetic tunnel junction) element that utilizes a change in magnetoresistance due to the spin-polarized tunnel effect is used. Hereinafter, the magnetoresistive effect element 1 is referred to as an MTJ element 1.

  The MTJ element 1 has a stacked structure in which reference layers (also referred to as magnetization invariant layers) 11A and 11B, intermediate layers (nonmagnetic layers) 12A and 12B, and storage layers (also referred to as magnetization free layers) 13A and 13B are sequentially stacked. Have. The reference layers 11A and 11B and the memory layers 13A and 13B may be stacked in reverse order.

In the MTJ element 1 shown in FIG. 3, the easy magnetization directions of the reference layer 11A and the storage layer 13A are parallel to the film surface. The MTJ element 1 shown in FIG. 3 is called an in-plane magnetization type MTJ element.
In the MTJ element 1 shown in FIG. 4, the easy magnetization directions of the reference layer 11B and the storage layer 13B are perpendicular to the film surface (or the laminated surface). The MTJ element shown in FIG. 4 is called a perpendicular magnetization type MTJ element.
The magnetic layer with in-plane magnetization has a magnetic anisotropy in the in-plane direction, and the magnetic layer with perpendicular magnetization has a magnetic anisotropy in the direction perpendicular to the film surface. When the perpendicular magnetization type is used for the MTJ element 1, it is not necessary to control the element shape to determine the magnetization direction as in the in-plane magnetization type, and sufficient memory can be stored even if the volume of the storage layer 13B is reduced. In order to maintain the retention characteristic, there is an advantage that it is suitable for miniaturization of the memory cell.

  The storage layers 13A and 13B have variable (reversed) magnetization (or spin) directions. The reference layers 11A and 11B have the same magnetization direction (fixed). “The magnetization directions of the reference layers 11A and 11B are unchanged” means that the magnetization reversal current (inversion threshold) used to reverse the magnetization directions of the storage layers 13A and 13B is applied to the reference layers 11A and 11B. This means that the magnetization directions of the reference layers 11A and 11B do not change when they are flowed. Therefore, in the MTJ element 1, by using a magnetic layer having a large inversion threshold as the reference layers 11A and 11B and using a magnetic layer having a smaller inversion threshold than the reference layers 11A and 11B as the storage layers 13A and 13B, The MTJ element 1 including the storage layers 13A and 13B having a variable magnetization direction and the reference layers 11A and 11B having a fixed magnetization direction is realized.

  As a method of fixing the magnetization of the reference layers 11A and 11B, an antiferromagnetic layer (not shown) is provided adjacent to the reference layers 11A and 11B, and the reference layers 11A and 11B are exchanged with the antiferromagnetic layer. The magnetization direction of the reference layers 11A and 11B can be fixed by the coupling. However, in the perpendicular magnetization type MTJ element, an antiferromagnetic layer (not shown) may not be provided adjacent to the reference layer 11A. The planar shape of the MTJ element 1 is not particularly limited, and any of a circle, an ellipse, a square, a rectangle, and the like may be used. Further, the shape may be a shape in which square corners or rectangular corners are rounded, or a shape with missing corners.

The reference layer 11B and the storage layer 13B are made of a magnetic material having a high coercive force, and preferably have a high magnetic anisotropy energy density of, for example, 1 × 10 ⁶ erg / cc or more.

  The intermediate layers 12A and 12B are made of a nonmagnetic material, and for example, an insulator, a semiconductor, a metal, or the like can be used. When an insulator or a semiconductor is used for the intermediate layer 12, the intermediate layer 12 is called a tunnel barrier layer.

  Note that each of the reference layers 11A and 11B and the storage layers 13A and 13B is not limited to a single layer as illustrated, and may have a laminated structure including a plurality of ferromagnetic layers. Each of the reference layers 11A and 11B and the storage layers 13A and 13B includes three layers of a first ferromagnetic layer / a nonmagnetic layer / a second ferromagnetic layer. An antiferromagnetic coupling structure in which the magnetization directions are in an antiparallel state (magnetic coupling (exchange coupling)) may be used, or the first and second ferromagnetic layers may have a magnetization direction in a parallel state. A (exchange-coupled) ferromagnetic coupling structure may be used.

  The MTJ element 1 may have a double junction structure. The MTJ element 1 having a double junction structure has a stacked structure in which a first reference layer, a first intermediate layer, a storage layer, a second intermediate layer, and a second reference layer are stacked in this order. Such a double junction structure has an advantage that it is easy to control the magnetization reversal of the storage layers 13A and 13B by spin injection.

The write circuit 2 is connected to the bit line BL. When writing data to the MTJ element 1, the write circuit 2 generates write currents I _w1 and I _{w2 and} passes the generated currents I _w1 and I _w2 between the bit lines BL and bBL. The write currents I _w1 and I _w2 flow through the MTJ element 1. The write circuit 2 flows the write currents I _w1 and I _w2 bidirectionally from one end of the MTJ element 1 to the other end or from the other end of the MTJ element 1 to one end. The operation of the writing circuit 2 is controlled by a control circuit 51 described later.

FIG. 2 shows an example of a pulse waveform of the write current. In FIG. 2, the current value of the write current is shown as an absolute value. Based on the control circuit 51, the write circuit 2 supplies either the write current I _w1 having the pulse width T _wp1 or the write current I _w2 having the pulse width T _wp2 to the MTJ element 1. Write currents I _w1 and I _w2 flow through the MTJ element 1. Pulse width _{T wp2} is longer than the pulse width _{T wp1.}

In the present embodiment, the pulse width of the current is defined by the full width at half maximum (FWHM) of the pulse. The pulse widths T _wp1 and T _wp2 of the write currents I _w1 and I _w2 are pulse widths based on a value i _w / 2 that is ½ of the maximum current value i _w . The pulse width T _wp1 of the write current I _w1 is a period between the time t _ab and the time t _cd . Time _{t ab} is the time period _{t a} and the rise of the rise of the pulse current _{I w1} is started is completed _{t b} substantially intermediate time, the time _{t cd} is the fall of the pulse current _{I w1} is started This is a substantially intermediate time between the time t _c and the time t _{d when} the falling ends.

Pulse width _{T wp2} of the write current _{I w2} is the period between time _{t 12} and time _{t 34.} Time t ₁₂ is substantially intermediate the rise time is the time to start t ₁ and time t ₂ when the rising ends of the pulse current I _w2, the time t _34, the time the fall of the pulse current Iw2 is started falling and t ₃ are substantially intermediate time period ending t _4.

The write current I _w1 and the write current I _w2 have, for example, the same current value iw. The current value i _w is set to be not less than the inversion threshold value i _th of the storage layer and less than the inversion threshold value of the reference layer.

  The error detection and correction circuit 52 detects whether or not there is an error in the data (hereinafter referred to as write data) stored (or held) by the MTJ element 1. The error detection and correction circuit 52 corrects the error when there is an error in the data. The corrected data (hereinafter referred to as corrected data) is written again in the MTJ element 1.

The control circuit 51 controls the operation of the entire magnetic memory. The control circuit 51 performs the operation of the write circuit 2 so as to supply either the write current I _w1 or the write current I _w2 to the MTJ element 1 according to the operation status of the MTJ element 1 and the error detection / correction circuit 52. Control.

The control circuit 51 generates and outputs a write current I _w2 having a longer pulse width T _wp2 when writing correction data to the MTJ element 1 than when writing data input from the outside. To control the operation. When writing data input from the outside to the MTJ element 1, the control circuit 51 controls the operation of the write circuit 2 so as to generate and output a write current I _w1 having a pulse width T _wp1 .

Hereinafter, the low resistance state and the high resistance state of the MTJ element 1 and data writing by spin injection will be described. At the time of writing data, a write current I (current I _w1 or current I _{w2 in} FIG. 2) flows in the MTJ element 1. The write current I (I _w1 , I _w2 ) flows bidirectionally in the MTJ element 1 according to the data to be written. Of course, the direction in which the current flows is opposite to the direction in which the electrons move.

  A parallel state (low resistance state) in which the magnetization directions of the reference layers 11A and 11B and the storage layers 13A and 13B are parallel will be described.

  Of the electrons that have passed through the reference layers 11A and 11B, the majority electron has a spin parallel to the magnetization direction of the reference layers 11A and 11B. When the majority electron spin angular momentum moves to the storage layers 13A and 13B, spin torque is applied to the storage layers 13A and 13B, and the magnetization directions of the storage layers 13A and 13B are the magnetization directions of the reference layers 11A and 11B. Aligned in parallel. With this parallel arrangement, the MTJ element 1 has the smallest resistance value. This case is treated as “0” data, for example.

  Next, an antiparallel state (high resistance state) in which the magnetization directions of the reference layers 11A and 11B and the storage layers 13A and 13B are antiparallel will be described.

  Of the electrons reflected by the reference layers 11A and 11B, the majority electron has a spin antiparallel to the magnetization direction of the reference layers 11A and 11B. When the majority electron spin angular momentum moves to the storage layers 13A and 13B, spin torque is applied to the storage layers 13A and 13B, and the magnetization directions of the storage layers 13A and 13B are the magnetization directions of the reference layers 11A and 11B. And anti-parallel. In the antiparallel arrangement, the MTJ element 1 has the largest resistance value. This case is treated as “1” data, for example.

  Hereinafter, the spin injection magnetization reversal model of this embodiment will be described with reference to FIGS.

FIG. 5 shows the time dependence of the magnetization reversal probability in the spin injection magnetization reversal model described in the present embodiment. The horizontal axis in FIG. 5 indicates time (unit: nsec (nanosecond)). The vertical axis in FIG. 5 corresponds to the magnetization reversal probability. However, when the magnetization reversal probability is indicated by “P”, Log ₁₀ (1-P) is indicated on the vertical axis of FIG. “1-P” indicates a probability that magnetization is not reversed (data is not written). The magnetization reversal probability is the probability that the magnetization direction of the storage layer is reversed when a certain current is passed through a certain MTJ element.

Each characteristic curve shown in FIG. 5 is a result obtained by a micromagnetic simulation using an LLG (Landau-Liftshitz-Gilbert) equation. Each parameter used for this simulation is as follows.
The MTJ element used for the simulation is a perpendicular magnetization type MTJ element. The film thickness of the MTJ element is set to 2.2 nm, and the diameter of the MTJ element is set to 30 nm. The magnetization of the storage layer is perpendicular to the film surface, the magnetic layer has a magnetic anisotropy energy Ku of 3.5 Merg / cc, and the storage layer has a saturation magnetization Ms of 500 emu / cc. The energy barrier ΔEa is 86 k _B T (k _B : Boltzmann constant, T: absolute temperature). The energy barrier ΔEa indicates the size of the energy barrier that must be exceeded in the process of reversing the MTJ element from the parallel state to the antiparallel state or from the antiparallel state to the parallel state. The temperature (absolute temperature) T is set to 300K. The range of the current density J flowing through the MTJ element is set to 2.8 to 4 MA / cm ² . The simulation is executed using the current density ratio J / J _C (22 nsec, midpoint) within the range of 0.934 to 1.436. “J” indicates the current density of the pulse current, and “J _C (22 nsec, midpoint)” indicates that the MTJ element has a write width of 22 nsec when data is written to the MTJ element. The current density at which the magnetization reversal probability of the storage layer is 0.5 is shown.

  FIG. 5 also shows first-order approximate characteristic lines (dotted lines in the figure) for characteristic curves obtained from simulations using current density ratios of 0.934 to 1.436.

Based on the characteristic curves shown in FIG. 5, the spin injection magnetization reversal probability P (t) can be approximately expressed as (Equation 1).

“P (t)” indicates the probability that the magnetization of the storage layer is reversed when a current pulse having a pulse width t is passed through the MTJ element. “F ₀ ” is the frequency at which the MTJ element receives thermal energy (phonon) per unit time. “F ₀ ” is about 1 × 10 ⁹ Hz. “I” indicates the current value of the pulse current, and “I _C0 ” is the current value of the magnetization reversal current at 0 K (absolute temperature). In (Formula 1), “n” is a constant of 1.5-2.

As shown in FIG. 5, the probability Log ₁₀ (1−P) shows a negative value with respect to a change in time. In the spin injection magnetization reversal model shown in FIG. 5 and (Equation 1), immediately after the pulse current is applied to the MTJ element, the reversal of the magnetization of the storage layer does not occur, and the reversal of the magnetization occurs after the dead time t ₀ has elapsed. Be started.

The spin injection magnetization reversal model of this embodiment will be described with reference to FIGS. 6 to 10, the process of reversing the normalized magnetization Mz of the magnetic layer (storage layer) from 1 to −1 in the spin injection magnetization reversal used in the magnetic memory will be described as an example. Here, the time during which the magnetization Mz in the z-axis (vertical) direction changes from 1 to around −1 after the write current starts to flow through the MTJ element is referred to as switching time T _sw .

Since the magnetization reversal of the magnetic material is a stochastic phenomenon, the switching time T _sw fluctuates every time even when a write current of the same magnitude is supplied to the same magnetic material. That is, when data is written to a certain MTJ element using a current having a certain pulse width, the switching current I _sw (inversion threshold i _th ) fluctuates every time. Understanding these phenomena is important for reducing write failures.
In spin transfer magnetization reversal, which is one of the write principles of a magnetic memory (for example, MRAM), spin transfer magnetization reversal described in the present embodiment is composed of the following three stages. That is, in the spin transfer magnetization reversal of this embodiment, the switching time T _sw is decomposed into three.

  FIG. 6 schematically shows a spin injection magnetization reversal model in the present embodiment.

In the spin injection magnetization reversal model shown in FIG. 6, the first stage is that the magnetization of each magnetic particle in the magnetic layer (storage layer) is precessed separately, and then the magnetic particles in the magnetic layer are precessed. This is the stage until the phases of magnetization are aligned and work together to start precession. In the present embodiment, the phase of magnetization of each magnetic grain in the magnetic layer is aligned and precesses together is called “coherent precession”. The time from the state where the magnetizations precessed separately until the start of coherent _precession is called the coherent time t _coh .

In the coherent time t _coh , the magnetization Mz decreases from 1 to about 0.95. In the coherent time t _coh , under the influence of phonons, the magnetization tends to become a coherent precession, but returns to a discrete precession. Therefore, the coherent time t _coh fluctuates greatly.

In the second stage, coherent precession is amplified. This time is called an amplification time t _amp . The magnetization Mz decreases from 0.95 to about 0.8. At the amplification time t _amp , under the influence of phonons, the magnetization precession is slightly amplified and attenuated. Therefore, the amplification time t _amp also fluctuates. The sum of the first stage time t _coh and the second stage time t _amp is referred to as “incubation delay time t _id ”. When the diameter of the MTJ element is smaller than the single domain diameter Ds, the incubation delay time t _id fluctuates greatly. The times t _coh and t _amp of the first and second stages are times _until the magnetization Mz starts to decrease greatly and the main stage of magnetization reversal occurs, and this time is relatively long in the spin injection magnetization reversal. Therefore, the times t _coh and t _amp required for the first and second stages are called incubation delay times.

In the third stage, the precession of magnetization is further amplified and magnetization reversal occurs with the help of thermal disturbance. At this stage, the thermal activation process is mainly dominant, and the magnetization Mz decreases from 0.8 to around -1. This time is called the reversal time _trv . When the diameter of the MTJ element is smaller than the single domain diameter Ds, the fluctuation of the reversal time t _rv is small. When the diameter of the MTJ element is larger than the single domain diameter Ds, the inversion time t _rv fluctuates to the same extent as the incubation delay time t _id .

As described above, the coherent time t _coh, which is the first stage, is from the state where the magnetization _precesses in the storage layer of the MTJ element to the start of precession where the magnetization phases are aligned. It was found that it was time.

Then, at the reversal time t _rv following the coherent time t _coh and the amplification time t _amp , magnetization reversal is started by the thermal activation process.

  Such a magnetization reversal model was verified by FIG. 5 and the following experiments and simulations.

FIG. 7 is a graph obtained by analyzing one of the simulation results based on the LLG equation of the spin injection magnetization reversal of the perpendicular magnetization type MTJ element used in FIG.
The simulation was performed using, for example, a cell showing 32 magnetizations in the storage layer (magnetic layer). The cell corresponds to a magnetic grain contained in the magnetic layer. In FIG. 7, the horizontal axis represents time (unit: nsec).

In FIG. 7, a characteristic line indicated by a broken line corresponds to the left axis Mz-ave. 7 represents the average value Mz-ave (unit: au (arbitrary unit)) of the z component (vertical component) of magnetization. In Mz-ave of the z component of magnetization, “1” indicates a state in which the magnetization is directed upward with respect to the film surface of the storage layer, and “−1” indicates that the magnetization is with respect to the film surface of the storage layer. It shows a state of facing down.
In the initial state (0 nsec) of the simulation shown in FIG. 7, the average value Mz-ave of the magnetization is substantially 1, and the magnetization is in the upward direction perpendicular to the film surface of the MTJ element. Then, at 0 nsec, supply of a magnetization reversal current to the storage layer was started, and the process until the magnetization was reversed by spin injection and the average value Mz-ave became approximately −1 was verified.

  In the simulation shown in FIG. 7, the average value Mz-ave of the magnetization hardly changes during the period from 0 nsec to 2.5 nsec. This can be regarded as a period in which the magnetization (spin) of the storage layer is not reversed.

In FIG. 7, the characteristic curve indicated by the solid line corresponds to the right axis σΦ and indicates the phase variation of the precession of 32 magnetizations in the storage layer.
FIG. 8 schematically shows a single magnetization cell. As shown in FIG. 8, the direction of magnetization can be expressed in polar coordinates using two declination angles θ and Φ. As shown in FIG. 8, the magnetization of the perpendicular magnetization film precesses around the film surface perpendicular direction (z axis) as the rotation axis. The phase of precession in the equatorial plane c is defined as the declination angle Φ. In addition, the angle formed by the inclination of the magnetization M and the z-axis during precession is defined as a declination angle θ.
The phase variation of the precession is obtained by examining the variation of the declination Φ. However, the argument Φ shown in polar coordinates becomes discontinuous or multivalued with a period of + π or −π. For this reason, if the phase dispersion (phase variation) is calculated simply by using the declination Φ, an accurate calculation result cannot be obtained at a portion where the numerical values are discontinuous.
Therefore, in this embodiment, the phase variance σΦ is calculated by expressing the phase of the precession as a complex number, that is, “Φ = cosφ + isinφ”, instead of the declination Φ, and the phase variation is obtained. Thus, by expressing the argument Φ using complex numbers, the problem caused by numerical discontinuity is solved, and phase variations can be calculated relatively easily. The phase dispersion σΦ is expressed by the following (Expression 2) and (Expression 3).

  “N” in (Equation 3) indicates the number of magnetizations (number of cells) included in the storage layer, which is 32 in this example. “Σ” in (Expression 3) indicates that the sum (total value) of all the magnetizations (32 in this example) included in the storage layer is calculated. “*” In (Expression 3) indicates a conjugate complex number. “￣” in (Expression 3) and (Expression 4) indicates an average value of all the magnetization cells (32 in this example) in the storage layer. Therefore, “μ” in (Expression 3) indicates an average value of “Φ” of all the magnetizations in the storage layer.

  9 and 10 schematically show the magnetization cells arranged in the storage layer 13. 9 and 10 show an example in which a plurality of cells 18 are two-dimensionally arranged. However, this is for the sake of simplification of description and is not limited to this. is there.

For example, as shown in FIG. 9, when the phases of the magnetizations 19 of the cells 18 in the storage layer 13 are all random, the phase dispersion σΦ indicates “1”. On the other hand, as shown in FIG. 10, when the phases of all the magnetizations 19 in the storage layer 13 are perfectly aligned and the value of the declination “Φ” is the same, the phase dispersion σΦ is “0”. Indicates.
As shown in FIG. 7, the phase dispersion σΦ of the magnetization in the storage layer rapidly decreases, the time when the magnetization becomes a coherent precession, the magnetization starts to reverse, and the average value Mz-ave of the magnetization is The phenomenon that the average value Mz-ave starts to decrease after reaching about 0.95 is linked. For this reason, the coherent time t _coh is considered to be the time from when the precession of magnetization becomes discrete as shown in FIG. 9 to the coherent precession as shown in FIG. be able to.

  Note that a period t ′ in FIG. 7 corresponds to a time until a coherent precession movement is reached. However, even when the simulation is repeated under the same conditions, the period t ′ from the initial state until the coherent precession is realized varies. However, the phenomenon that magnetization reversal is started when the phase of magnetization in the storage layer is aligned and coherent precession is realized is reproduced.

The period t ′ in the spin injection magnetization reversal is a coherent state in which the phases of precession of each magnetization 18 are aligned from a state where the phases of precession of each magnetization 18 are not aligned (see FIG. 9) in the storage layer 13. It can be regarded as the time until the transition to (see FIG. 10). Then, when a period (time) t _coh until the coherent _precession is _reached and a period (time) t _amp until the coherent precession is amplified, the _{process proceeds} to the thermal activation process, and the MTJ element It can be said that the spin inversion of the storage layer is substantially started.
The time until the magnetization precession becomes a coherent motion depends on the magnitude of the current I. When the magnitude of the current I decreases, the time until the magnetization precession becomes a coherent motion is To increase.

There is a period (time) t ′ until the coherent precession is realized, and after the coherent precession is realized, a finite time from the start of the spin inversion to the completion of the spin inversion. Exists. Therefore, in consideration of those periods (time), the time t ₀ in (Equation 1) is included in the parameters of the spin injection magnetization reversal model described in this embodiment.
Here, the condition for completing the spin injection magnetization reversal is that the spin of the memory layer does not return to the original state even when the current (pulse current) is turned off, and is reversed to the end. This means that in FIG. 8, the direction of magnetization rotates to the equator plane c, and the perpendicular component Mz of magnetization becomes “0”.

As described above, the magnetization reversal takes a finite time and the time fluctuates. In other words, the spin injection magnetization reversal has a first stage, a second stage, and a third stage (see FIG. 6). For this reason, in the spin transfer magnetization reversal, there is a time t ₀ when the magnetization reversal probability does not increase so much at the initial stage of the magnetization reversal. The time t ₀ is shown in FIG. 5 and (Equation 1). For example, in an MTJ element using a perpendicular magnetization film, when the diameter of the element is smaller than the single domain diameter, the time (period) t ₀ is approximately expressed by (Equation 4). In (Expression 4), the unit of “t ₀ ” is nsec.

In (Expression 4), “J _write ” indicates the current density of the write current, and “J _C0 ” is obtained when the pulse width T _wp is set such that (T _wp −t ₀ ) f ₀ = ln 2. The current density of the magnetization reversal current at 0 K (absolute temperature) is shown.

FIG. 11 shows the time dependence of the magnetization reversal probability similarly to FIG. 5, and shows the time dependence of the magnetization reversal probability of the MTJ element under the same conditions as FIG. Note that the result shown in FIG. 11 is calculated by micromagnetic simulation using the LLG equation. The horizontal axis in FIG. 11 indicates time, and the vertical axis in FIG. 11 indicates Log ₁₀ (1-P), as in FIG.

In FIG. 11, characteristic lines J1 and J2 indicate magnetization reversal probabilities in the case where write currents having current density J1 and current density J2 are used. The characteristic lines J1 and J2 correspond to the primary approximate line of the magnetization reversal model of the present embodiment shown in (Equation 1). The current density J1 is 3.8 MA / cm ² and the current density J2 is 4.0 MA / cm ² .

The characteristic line A is an approximate line of a magnetization reversal model by a conventional simple thermal activation process. A conventional magnetization reversal model by a thermal activation process is represented by (Equation 5).

  The time shown on the horizontal axis of FIG. 11 is the time (period) during which current is supplied to the MTJ element, and corresponds to the pulse width of the write current. “ΔT1” and “ΔT2” in FIG. 11 correspond to periods in which the pulse widths of the write currents having the current densities J1 and J2 are increased by about 7%, respectively.

  As shown in FIG. 11, in the write currents having current densities J1 and J2, it can be seen that when the pulse width is increased by about 7%, the probability that the magnetization is not reversed (1-P) is decreased by about one digit. If the pulse width of the write current is increased by about 14% to 15%, the probability that data cannot be written decreases by about two digits.

In the spin injection magnetization reversal model of (Equation 1) used in this embodiment, the write failure occurrence probability LOG ₁₀ (1-P) has a write current higher than that of the conventional spin injection magnetization reversal model shown in (Equation 5). It greatly depends on the pulse width.

Therefore, in the MRAM to which spin injection magnetization reversal is applied, it is effective to increase the pulse width of the write current in order to reduce the write failure occurrence probability Log ₁₀ (1-P).

In FIG. 12 and FIG. 13, the characteristic line indicated by the solid line corresponds to the magnetization reversal model of the present embodiment shown in Expression (1), where ΔE / kBT in (Expression 1) is “60”, and n is “2”. ", _{t 0} is" are respectively set to 7nsec ".

FIG. 12 shows the change of the magnetization reversal current (switching current) fluctuation σ (I _sw ) / I _sw with respect to the pulse width of the write current. In FIG. 12, the vertical axis corresponds to the fluctuation of the inversion threshold current, and the horizontal axis corresponds to the supply time of the inversion threshold current, that is, the pulse width _Twp of the write current. FIG. 13 shows a change in the switching current I _sw where the inversion probability is 0.5 with respect to the pulse width of the write current. In FIG. 13, the switching current I _sw is indicated by a current ratio I _sw / I _c0 .

12 and 13, the characteristic lines indicated by broken lines indicate the fluctuation σ (I _sw ) / I _sw and the current ratio I _sw / I _c0 of the magnetization reversal model shown in (Equation 5), respectively. .

As shown in FIG. 12, when a current is supplied to a certain MTJ element, the magnetization reversal model (Equation 1) of this embodiment has a fluctuation σ (I _sw ) / in comparison with the magnetization reversal model (Equation 5). It is shown that I _sw greatly depends on the current pulse width T _wp , and the fluctuation σ (I _sw ) / I _sw decreases as the pulse width T _wp increases.

Also in FIG. 13, the switching current I _sw supplied to a certain MTJ element depends on the pulse width T _{wp of the} current, and when the pulse width T _wp becomes longer, the rate of change becomes smaller.

Thus, also from the results shown in FIG. 12 and FIG. 13, by increasing the current pulse width T _wp , fluctuations in the write current to the MTJ element (memory layer) are reduced, and data write failures are reduced. I understand that well.

  There is a means for increasing the current value of the write current in order to reduce the probability of occurrence of a defect in which data cannot be normally written, but this has the following two drawbacks. First, the write current has an upper limit due to circuit restrictions such as the size of the selection transistor. Second, when the current value of the write current is increased, a write failure due to an excessive write current called back-hopping occurs. For these reasons, increasing the current value of the write current is not necessarily effective for reducing write defects.

  Therefore, it is preferable to increase the pulse width of the write current and write data to the MTJ element. However, using a write current having a long pulse width for all data writing means that the data writing time becomes long. Therefore, high-speed operation, which is one of the advantages of a magnetic memory, for example, MRAM, is impaired. Therefore, it is necessary to devise another method so that the time required for data processing does not become excessively long.

  In the magnetic memory according to the embodiment of the present invention, data stored (written) in the magnetoresistive effect element (MTJ element) 1 is output, and the output data is written back to the magnetoresistive effect element 1. In addition, a write current having a long pulse width is used. Data write-back (rewrite) is performed mainly when an error in data is corrected.

As shown in FIGS. 1 and 2, the magnetic memory according to the embodiment of the present invention includes an error detection and correction circuit 52 that detects and corrects an error in data output from the main memory 50. In addition, the magnetic memory of this embodiment includes a control circuit 51 having a function 53 for controlling the pulse widths of the write currents I _w1 and I _w2 .

In the magnetic memory according to the present embodiment, when data input from the outside is normally written to the MTJ element 1 in the main memory 50, a write current I _w1 having a certain pulse width T _wp1 is supplied to the MTJ element 1. For example, the pulse width T _wp1 corresponds to the dead time t ₀ or more shown in FIG. 5 and (Equation 1), and the sum of the coherent time t _coh and the amplification time t _amp shown in FIG. delay time t _id ) or more.

  In the magnetic memory of the present embodiment, an error detection / correction circuit (also referred to as a defect detection circuit) 52 performs error detection and correction on data stored in the MTJ element 1 at the time of data writing or data reading. To do. Then, the magnetic memory according to the present embodiment again writes the data corrected by the error detection / correction circuit 2 to the MTJ element 1 in the main memory 50.

  The control circuit 51 in the magnetic memory according to this embodiment determines whether data input from the outside is written or corrected data is written back.

When the corrected data is written back to the MTJ element 1, the control circuit 51 writes data corrected with _respect to the pulse width T _wp1 of the write current I _w1 based on the error detection and correction by the error detection and correction circuit 52. _Therefore , the operation of the write circuit 2 is controlled so as to increase the pulse width T _wp2 of the write current I _w2 for this purpose.

As described above, in the magnetic memory of this embodiment, the data input from the outside uses the write current I _w1 with the pulse width T _wp1 , and the data with the error corrected uses the pulse width T _wp2 ( A write current I _w2 of> T _wp1 ) is used.

As a result, the correction of data is performed, and when the corrected data is written back to the MTJ element 1, the write current I _w2 having a long pulse width T _wp2 is used, thereby reducing the probability that a write failure will occur. To do. For this reason, in the magnetic memory of this embodiment, the occurrence of defects in the data written to the MTJ element 1 is reduced.

  Then, by correcting an error in data stored in the MTJ element 1, a write failure, a read disturb, or a retention failure occurring in the magnetoresistive effect element 1 in the main memory 50 is corrected. That is, in the magnetic memory of this embodiment, data defects in the main memory 50 are reduced and malfunctions are reduced.

  There are two types of configurations for error correction described in this embodiment. The first configuration is a configuration using error correction technology (ECC). Here, the defect (or error) is an error of 1-bit data, which is often correctable by an error detection and correction technique. If the number of defects included in one block exceeds a certain number (for example, two or more), correction cannot be performed even using an error detection and correction technique. In this embodiment, the fact that a defect cannot be relieved by using an error detection and correction technique is called a malfunction.

  In the second configuration, the data written in the main memory is immediately read without using the ECC technology, and the read data is compared with the data from the outside (original data). ) Is detected. If there is a write failure in the read data, the data is replaced and the original data is written into the main memory.

  The magnetic memory according to the present embodiment increases the pulse width of the write current only when writing the error-corrected data back to the MTJ element 1. Therefore, the operation time of the magnetic memory, in particular, the write operation time does not become excessively long. Therefore, the high speed performance of the magnetic memory is not impaired.

  Therefore, in the magnetic memory according to the embodiment of the present invention, the operation reliability is improved and the operation characteristics are improved.

[Configuration example 1]
A configuration example of the magnetic memory according to the embodiment of the present invention will be described with reference to FIGS. 14 to 22. (1) Circuit
A configuration example of a circuit of the magnetic memory according to the embodiment of the present invention will be described with reference to FIGS. The magnetic memory of this configuration example is, for example, a magnetic random access memory (MRAM).

  As shown in FIG. 14, the MRAM of this configuration example includes a main memory 50. The main memory 50 has a function of writing data to a memory cell (MTJ element 1) in the main memory 50 and a function of reading data from a memory cell (MTJ element 1) in the main memory 50.

  FIG. 15 shows an example of an internal configuration of the main memory 50, and shows a circuit configuration near the memory cell array of the MRAM.

  The plurality of memory cells MC are arranged in an array in the memory cell array 20.

  FIG. 16 is a diagram showing an example of the structure of the memory cell MC provided in the memory cell array 20. The upper end of the MTJ element 1 is connected to the upper bit line 32 via the upper electrode 31. The lower end of the MTJ element 1 is connected to the source / drain diffusion layer 37a of the selection transistor Tr via the lower electrode 33, the lead wiring 34, and the plug 35. The source / drain diffusion layer 37 b of the selection transistor Tr is connected to the lower bit line 42 via the plug 41.

  A gate electrode 39 is formed on the semiconductor substrate (channel region) 36 between the source / drain diffusion layer 37a and the source / drain diffusion layer 37b via a gate insulating film 38. The gate electrode of the selection transistor Tr functions as the word line WL.

  Note that at least one of the lower electrode 33 and the extraction electrode 34 may be omitted. For example, when the lower electrode 33 is omitted, the MTJ element 1 is formed on the lead wiring 34. When the lead wiring 34 is omitted, the lower electrode 33 is formed on the plug 35. Further, when the lower electrode 33 and the extraction electrode 34 are omitted, the MTJ element 1 is formed on the plug 35.

  The word line WL extends in the row direction and is connected to the gate of the selection transistor Tr constituting the memory cell MC.

  One end of the word line WL is connected to the row control circuit 4. The row control circuit 4 performs a selection operation on the word line WL.

  The bit lines BL and bBL extend in the column direction. One end of the MTJ element 1 is connected to the bit line BL, and the bit line bBL is connected to one end of the current path of the selection transistor Tr. The two bit lines BL and bBL constitute one set of bit line pairs.

  Column control circuits 3A and 3B are connected to one end and the other end of the bit lines BL and bBL.

The write circuits 2A and 2B are connected to one end and the other end of the bit lines BL and bBL via the column control circuits 3A and 3B. The write circuits 2A and 2B each include a source circuit such as a current source or a voltage source for generating the write currents I _w1 and I _w2 and a sink circuit for absorbing the write current. The write circuits 2A and 2B are electrically isolated from the bit lines BL and bBL when the write operation is not executed.

The operations of the write circuits 2A and 2B are controlled by the control circuit 51 and a write pulse width control circuit 53 described later, and output write currents I _w1 and I _w2 shown in FIG. When writing data, the write circuits 2A and 2B supply write currents I _w1 and I _w2 to the MTJ element 1. Write currents I _w1 and I _w2 flow through the MTJ element 1.

The current values i _w of the write currents I _w1 and I _w2 may be the same between the two currents I _w1 and I _w2 or may be different from each other.

In FIG. 17, the write currents I _w1 and I _w2 have the same current value. The current values i _w of the write currents I _w1 and I _w2 are preferably equal to or greater than the maximum value i _th among the inversion thresholds of the plurality of MTJ elements included in the memory cell array 20. The write current I _w1 has a predetermined pulse width T _wp1 , and the write current I _w2 has a pulse width T _wp2 longer than the pulse width T _wp1 . For example, a value equal to or greater than time t ₀ is used as the pulse width T _{wp1 and} is set based on, for example, (Equation 4). The pulse width _{T wp2,} for example, than the pulse width _{T wp1,} is set to about 7% to 10% longer value.

As described above, the pulse widths T _wp1 and T _wp2 of the write currents I _w1 and I _w2 are defined by the full width at half maximum of the pulse-shaped write current.

The read circuit 5 is connected to one end of the bit lines BL and bBL via the column control circuit 3B. Readout circuit 5 includes, voltage or current source for generating a read current I _r, a sense amplifier for sensing and amplifying a read signal, and a latch circuit for temporarily holding data. The read circuit 5 is electrically isolated from the bit lines BL and bBL when the read operation is not executed.

The read circuit 5, a read operation, outputs the read current I _r. Figure 17 shows the waveform of the read current I _r is. For example, the maximum value of the current value i _r of the read current I _r is set to a value smaller than the inversion threshold value i _th . For example, the current value i _r of the read current I _r is constantly output during a period from the time when the pulse current rise ends to the time when the fall starts. For example, the pulse width T _rp of the read current I _r is defined by the full width at half maximum of the pulse current. For example, the pulse width T _rp may be shorter than the pulse width T _wp1 of the write current I _w1 and may be shorter than the dead time t ₀ . Thereby, in the MRAM of this configuration example, occurrence of read disturb may be reduced. However, not limited thereto, the read current current value _{i r} of _{I r} is sufficiently smaller than the inversion threshold _{i th,} the pulse width of the read current _I pulse width _{r T rp} is write currents _{I w1, I w2} It may be T _wp1 , T _wp2 or more.

Data reading is performed by passing a read current I _R in the MTJ element 1. When the resistance value in the parallel state is “R0” and the resistance value in the antiparallel state is “R1”, the value defined by “(R1−R0) / R0” is called a magnetoresistance ratio (MR ratio). The magnetoresistance ratio varies depending on the material constituting the MTJ element 1 and the process conditions, but can take a value of several tens to several hundreds.

  Information stored in the MTJ element 1 is read by detecting the amount of fluctuation of the read current (bit line potential) caused by the MR ratio.

  In the column control circuits 3A and 3B, a switch circuit for controlling the conduction state between the bit lines BL and bBL and the write circuits 2A and 2B, and a switch circuit for controlling the conduction state between the bit lines BL and bBL and the read circuit 5 are provided. Is provided.

  During the write operation, in the column control circuits 3A and 3B, the switch circuit connected to the memory cell MC to be written is turned on, and the other switch circuits are turned off. In addition, the row control circuit 4 turns on the selection transistor Tr in the selected memory cell MC. Then, a write current having a direction corresponding to the write data is supplied to the selected memory cell MC. When writing data, one of the write circuits 2A and 2B is on the source side, and the other write circuit 2B and 2A is on the sink side, depending on the direction of current flow.

  The MRAM of this configuration example includes an error detection / correction circuit 52. The error detection / correction circuit 52 has a function of detecting whether or not an error is included in the data output from the main memory 50 to the circuit 52 and a function of correcting an error included in the data.

  For example, the error detection and correction circuit 52 includes an encoding unit 61, an error detection unit 62, an error correction unit 63, and a decoding unit 64.

  The encoding unit 61 adds a code (redundant bit) for detecting and correcting a data error to the data DT1 input from the outside via the buffer memory 54. Hereinafter, the code added to the data by the encoding unit 61 is referred to as an error detection / correction code.

  The encoding unit 61 outputs the data nDT with the error detection and correction code added thereto to the main memory 50. The data nDT is handled as write data to be written to the selected cell in the main memory 50. Also. The encoding unit 61 outputs a control signal (first control signal) NWC to the write pulse width control circuit 53 when an error detection code is added to the input data DT1.

The control signal NWC is generated in the write pulse width control circuit 53 and the main memory 50 so as to generate and output a write current I _w1 having a pulse width T _wp1 when data nDT inputted from the outside is written in the main memory 50. This is a signal for controlling the operation of the write circuits 2A and 2B. Hereinafter, the control signal NWC is referred to as a normal write signal NWC.

  The error detection unit 62 checks whether or not the data rDT read from the main memory 50 includes an error, using the error detection and correction code of the data rDT output from the main memory 50. When the data rDT includes an error, the error detection unit 62 outputs data erd including the error to the error correction unit 63. On the other hand, when the data rDT does not include an error, the error detection unit 62 outputs the data rDT to the decoding unit 64.

  The error correction unit 63 corrects the error when the read data rDT includes an error. The error correction unit 63 outputs data (hereinafter referred to as correction data) cDT in which the error is corrected to the main memory 50 and the decoding unit 64. The correction data cDT output to the main memory 50 is written into a predetermined memory cell in the main memory 50. The correction data cDT is written, for example, in the same memory cell (MTJ element) that is stored before being corrected.

  The error correction unit 63 outputs a control signal (second control signal) RWC to the write pulse width control circuit 53 when the correction data is output to the main memory 50.

Control signal RWC, when writing back corrected data CDT in the main memory 50, a pulse width _{T wp2} of the current _{I w2} used to write correction data CDT, longer than the pulse width _{T wp1} of normal write current _{I w1} As described above, this is a signal for controlling the operation of the write pulse width control circuit 53 and the write circuits 2A and 2B in the main memory 50. As a result, when the data (corrected data cDT) once output from the main memory 50 is written again in the main memory 50 in the MRAM chip, the write current I _w2 having the long pulse width T _wp2 shown in FIG. Used for data writing. Hereinafter, the control signal RWC is referred to as a rewrite signal RWC.

  The decoding unit 64 decodes the data rDT and cDT output from the error detection unit 62 or the error correction unit 63 during the read operation. Then, the decoding unit 64 outputs the decoded data to the buffer memory 54.

  In the MRAM of this configuration example, the error detection / correction circuit 52 detects and corrects an error included in the data using, for example, an extended humming code as an error detection / correction technique. When the extended Hamming code is used, the error detection and correction code includes a Hamming code having a predetermined number of bits and a parity bit. However, other error detection and correction techniques such as the Reed-Solomon method may be applied to the error detection and correction circuit 52.

  Further, the MRAM of this configuration example includes a buffer memory 54, for example. The buffer memory 54 temporarily holds data DT1 input from the outside. The buffer memory 54 temporarily holds the data output from the main memory 50 via the error detection and correction circuit 52, and outputs the held data DT2 to the outside.

  The buffer memory 54 may be an MRAM, a DRAM (Dynamic RAM), or an SRAM (Static RAM). For example, when the buffer memory 54 is composed of an MRAM, it is desirable that the probability of writing failure occurring in the MRAM serving as the buffer memory 54 is lower than the probability of writing failure occurring in the MRAM serving as the main memory 50.

  Therefore, in the MRAM used for the buffer memory 54, it is preferable that the size (for example, channel length) of the selection transistor is larger than the size of the selection transistor Tr of the MRAM used in the main memory 50. As a result, the current driving capability of the selection transistor in the buffer memory 54 is increased, and a sufficiently large write current can be supplied to the MTJ element in the buffer memory 54. Therefore, write defects in the buffer memory 54 are reduced.

  Note that a memory cell having a 2Tr + 1MTJ configuration including one MTJ element and two selection transistors may be used for the MRAM serving as the buffer memory 54. In this case, since the two selection transistors are used for one MTJ element, the substantial size of the selection transistor in one memory cell is increased. Therefore, similarly to increasing the size of one select transistor, a sufficiently large write current can be supplied to the MTJ element in the buffer memory 54 even when a 2Tr + 1MTJ type memory cell is used. As a result, write defects in the buffer memory 54 can be reduced.

  The MRAM of this configuration example includes a control circuit 51 and a write pulse width control circuit 53. The control circuit 51 controls the operation of the entire MRAM (chip) based on the command signal CMD and the address signal ADR input from the outside. The command signal CMD indicates operations on the main memory 50 such as data writing, data reading, and data erasing. The address signal ADR indicates the address of the memory cell to be operated.

The write pulse width control circuit 53 has a predetermined pulse width T _wp1 as shown in FIG. 17 when the error detection / correction circuit 52 writes the external data nDT added with the error detection / correction code to the main memory 50. The operation of the main memory 50, particularly the operations of the write circuits 2A and 2B, is controlled so as to use the write current _Iw1 . Under the control of the write pulse width control circuit 53, the write circuits 2A and 2B in the main memory 50A output a write current I _w1 having a pulse width T _wp1 when data is externally written. Writing using the writing current I _w1 having the pulse width T _wp1 is referred to as normal writing.

The write pulse width control circuit 53 makes the pulse width longer than the pulse width T _wp1 of the write current I _w1 when writing the error-corrected data cDT in the main memory 50, and the write current having the long pulse width T _wp2 The operation of the main memory 50, particularly the operation of the write circuits 2A and 2B, is controlled so as to use _Iw2 . Under the control of the write pulse width control circuit 53, the write circuits 2A and 2B in the main memory 50A output a write current I _w2 having a pulse width T _wp2 when writing the corrected data. Writing using the writing current I _w2 having the pulse width T _wp2 is called rewriting or writing back.

The control of the pulse widths T _wp1 and T _wp2 is a period in which the write pulse width control circuit 53 activates the write circuits 2A and 2B, specifically, the write circuits 2A and 2B are electrically connected to the selected cell. It is executed by controlling the period.

The operation of the write pulse width control circuit 53 is controlled by the control circuit 51 and two control signals NWC and RWC. As described above, the normal write signal NWC is output from the encoding unit 61 in the error detection / correction circuit 52 when an error detection / correction code is added to the input data. The rewrite signal RWC is output from the error detection unit 62 or the error correction unit 63 in the error detection / correction circuit 52 when the error of the data rDT is corrected. When the normal write signal NWC is input, the write pulse width control circuit 53 outputs a control signal pwcs for outputting a write current I _w1 having a pulse width T _wp1 to the main memory 50. Write pulse width control circuit 53, when the rewriting signal RWC is input, outputs a control signal pwcs for outputting the write current _{I w2} of the pulse width _{T wp2} the main memory 50. Hereinafter, the control signal pwcs is referred to as a pulse width control signal pwcs. Pulse width control signal pwcs is, by showing that the use of one of the pulse width T _wp1 or T _wp2, to the pulse width of the write current may be controlled, by the presence or absence of the input of the pulse width control signal pwcs, write The pulse width of the current may be controlled.

  Note that the write pulse width control circuit 53 may be provided in the control circuit 51. Alternatively, the control circuit 51 may have the same function as the write pulse width control circuit 53 without providing the write pulse width control circuit 53, and two control signals NWC and RWC may be input to the control circuit 51. In addition to the configuration shown in FIG. 14, the MRAM of this configuration example may further include a command interface to which a command signal is input and an address buffer to which an address signal is input.

The MRAM according to the configuration example of the present embodiment uses a write current I _w1 having a pulse width T _wp1 when data input from the outside is normally written in the MTJ element 1. Further, the MRAM of this configuration example corrects an error in the data stored in the MTJ element 1 and increases the pulse width of the write current when the corrected data is written back to the MTJ element 1 and the pulse width T _wp1. A write current I _w2 having a longer pulse width T _wp2 is used.

As a result, the MRAM of this configuration example can reduce write defects even if the characteristics (for example, the inversion threshold value) vary among the plurality of MTJ elements in the memory cell array 20. Further, the MRAM of this configuration example has a long pulse width T _wp2 only when the data stored (written) in the MTJ element includes an error and the corrected data is written to the MTJ element 1 again. A write current _Iw2 is used. Therefore, the operation cycle of the MRAM does not become excessively long, and high speed performance is not impaired.

  Therefore, in the magnetic memory according to the embodiment of the present invention, the operation reliability is improved and the operation speed is improved.

(2) Operation
The operation of the magnetic memory according to the embodiment of the present invention will be described with reference to FIGS. Hereinafter, the operation of the magnetic memory according to the present embodiment will be described with reference to FIGS. 14 to 17 showing the configuration of the magnetic memory. In the operation of the magnetic memory according to the present embodiment, a case will be described in which an error in data is detected and corrected using an extended Hamming code. However, it goes without saying that other error detection and correction techniques (for example, Reed-Solomon method) can be applied to the magnetic memory of this embodiment.

(A) Operation example 1
The operation example 1 of the magnetic memory (MRAM) according to the configuration example of the present embodiment will be described with reference to FIG. Here, as an operation example 1 of the MRAM of this configuration example, writing of data used in the MRAM of this configuration example will be described.

  As shown in FIG. 18, at the time of data writing, a command signal CMD indicating writing, an address signal ADR, and data DT1 to be written are input from the outside (step ST1). The command signal CMD and the address signal ADR are input into the control circuit 51, for example. The data DT1 is input to the buffer memory 54, for example. The data DT1 is stored in the buffer memory 54 (step ST2B). For example, the data DT1 is preferably stored in the buffer memory 54 with a block length (for example, 64 bits) of data (information bits) in the extended Hamming code as one unit.

  The input data DT1 is stored in the buffer memory 54 and input to the error detection / correction circuit 52 via the buffer memory 54. The data DT1 is input to the encoding unit 61 in the error detection / correction circuit 52. For example, 8 redundant bits are added to the data DT1 as an error detection / correction code by the encoding unit 61. Data nDT to which redundant bits are added is output from the encoding unit 61 to the main memory 50.

  At this time, a control signal (normal write signal) NWC is output from the encoding unit 61 to the write pulse width control circuit 53.

The write pulse width control circuit 53 controls (adjusts) the pulse width of the write current for writing the data nDT based on the input normal write signal NWC. A control signal (pulse width control signal) pwcs for setting the pulse width of the write current to “T _wp1 ” is output from the write pulse width control circuit 53 to the main memory 50.

In the main memory 50, the word line indicated by the address signal ADR is activated by the row control circuit 4, and the bit line indicated by the address signal ADR is activated by the column control circuits 3A and 3B. The write circuit 2A, 2B in the main memory 50 is controlled by a control signal pwcs, for example, it outputs the write current _{I w1} having a predetermined pulse width _{T wp1} shown in Figure 17.

The write current _{I w1} is, the bit lines BL, bBL flow, is supplied to the selected cell indicated by the address signal ADR (MTJ element), data nDT is written (step ST2A). In normal writing, the pulse width T _wp1 of the write current I _w1 for writing the data nDT is set to, for example, the dead time t ₀ or more shown in (Equation 4).

Thus, when writing data nDT output from the coding unit 61 to the selected cell in the main memory 50, the pulse width T _wp1 of the write current I _w1, for example, the minimum time required for reversing the magnetization ( A pulse width corresponding to (period) is used.

After writing the data nDT write current I _w1 main memory 50 using, for verification operation performed on the written data, the written data is read from the main memory 50 to the error detecting and correcting circuit 52 (step ST3 ). Here, the data read for verification is referred to as verification data.

  The verify data rDT is input to the error detection unit 62 in the error detection / correction circuit 52. The error detection unit 62 checks whether or not the data rDT stored in the MTJ element 1 includes an error, using redundant bits (error detection / correction code) added to the verification data rDT (step ST4).

  If an error is detected in the verify data rDT, the error is corrected (step ST5). The verify data rDT including an error is output from the error detection unit 62 to the error correction unit 63. The error of the verify data rDT is corrected by the error correction unit 63 based on the redundant bits. If there is no error in the data written to the MTJ element 1, the data writing is terminated (step ST7).

  The error-corrected data (corrected data) cDT is output to the main memory 50 and written again to the MTJ element 1 in the memory cell array 20 (step ST6). The correction data cDT is normally overwritten at the same address as the address written before the verify operation. That is, the correction data cDT is written to the same MTJ element 1 before and after correction.

The writing of the corrected data (step ST6), the write current _{I w2} of long pulse width _{T wp2} than the pulse width _{T wp1} of the write current _{I w1} used for normal writing is used.

  In this operation example 1, when the correction data cDT is written to the MTJ element 1, a control signal (rewrite signal) RWC indicating rewrite is sent from the error correction unit 63 in the error detection and correction circuit 52 to the write pulse width control circuit 53. Is output.

When the rewrite signal RWC is input to the write pulse width control circuit 53, a pulse width control signal pwcs for increasing the pulse width of the write current is output from the write pulse width control circuit 53 to the main memory 50. By the pulse width control signal pwcs, as shown in FIG. 17, the write current I _w2 having the pulse width T _wp2 (> T _wp1 ) is output from the write circuit in the main memory 50, and the write current I _w2 is selected. Supplied directly to the cell.

  For example, in the loop of the write operation and the verify operation, the pulse width of the write current is controlled by the pulse width control signal pwcs so as to be 1.10 times the pulse width of the current used in the previous data write. The The increase rate for increasing the pulse width of the write current is not limited to 1.10 times, and may be in the range of about 1.07 times to 1.15 times, for example.

As described above, it is determined by the two control signals NWC and RWC output from the error detection and correction circuit 52 whether the data writing is normal writing or rewriting (writing back). Thus, it is determined whether the pulse width of the write current is set to a predetermined pulse width _Twp1 or longer than the pulse width _Twp1 .

  When data is written, if a read command is input to data for which processing is being executed during detection, correction, and rewriting of the write data error, the data The data stored in the buffer memory 54 corresponding to is read out to the outside (step ST2B).

  The correction data cDT written back in the main memory 50 (hereinafter referred to as rewrite data) is again subjected to the verify operation (step ST3). Therefore, the rewritten data is output again from the main memory 50, and it is checked whether there is an error in the data. If an error is detected in the rewritten data, the error is corrected, and the corrected data is rewritten and then verified again. If there is no error in the rewritten data, the data writing ends (step ST7).

  Note that when the verify operation is repeatedly executed and data rewrite is performed a plurality of times, it is preferable to increase the pulse width of the write current every time the number of rewrites is repeated for one data. In this case, the pulse width of the write current may be increased at the same magnification (for example, 1.1 times). However, the pulse width may be increased only during the first rewrite, and the pulse width of the write current used for the second and subsequent rewrites may be the same as the pulse width of the first write current.

  The loop for rewriting data may continue indefinitely until there is no data error. However, the data write loop is limited to a certain number of times, for example, 10 times, and if the data error is not eliminated even after 10 rewrite loops are performed, the MTJ element itself indicated by the selected address is not included. It is effective to determine that there is a defect and to change the correction data (write-back data) to be stored in another address of the main memory 50.

  In rewriting data, only the erroneous bit may be overwritten in one selected cell, or all bits included in one block may be overwritten in each corresponding selected cell. However, in order to suppress the power consumption of the magnetic memory, it is preferable to overwrite only the erroneous bits.

<Effect of Operation Example 1>
The effect of the operation example 1 of the magnetic memory (MRAM) of this embodiment will be described with reference to FIGS.

FIG. 19 shows a distribution of current values I _{c, mp} of the current supplied to the MTJ element. The current value I _{c, mp} indicates a current value at which the magnetization reversal probability of the storage layer of the MTJ element becomes 0.5 when data is written to the MTJ element using a write current having a certain pulse width.

In FIG. 19, a distribution C indicates a distribution of currents I _{c and mp to} be satisfied when data correction and rewriting are not executed. In this case, in order to reduce the occurrence probability of malfunction to a certain specification value or less, it is necessary to reduce the variation of the distribution C. A distribution D indicates a distribution when data correction and rewriting are executed. When the probability of malfunction occurrence is less than or equal to a certain specification value, the distribution D is corrected and rewritten, and therefore the variation may be larger than the distribution C.

FIG. 19 also shows the distribution of the write current _Iwr . In FIG. 19, the horizontal axis indicates the magnitudes of currents I _{c, mp} , and I _write , and the vertical axis indicates the existence probability.

As shown in FIG. 19, the distributions C and D of the currents I _{c and mp} secure predetermined margin regions MR and CR with respect to the distribution of the current I _wr . In the operation example 1 of the present embodiment, as shown in the distribution D of FIG. 19, the correction and rewriting of data is executed, so that the correction and rewriting of data indicated by the distribution C is not executed. There is an advantage that the tolerance of variation of the current I _{c, mp} is widened. That is, even if there is a large variation between bits (MTJ elements) in the memory cell array, the malfunction probability can be suppressed. In this embodiment, the malfunction is a defect that cannot be corrected by the error detection and correction technique. In the present embodiment, a defect that can be corrected by the error detection and correction technique is simply referred to as a defect, an error, or an error.

  In a magnetic memory, for example, an MRAM, since the magnetization reversal of a magnetic material is a stochastic phenomenon, a write failure, a read disturb, a retention failure, etc. occur. It is preferable that the total probability of malfunction caused by these is guaranteed to be 1000 FIT (Failures In Time) or less per chip. Therefore, here, the effect of this operation example (write operation) is described assuming 1000 FIT / chip. Note that 1000 FIT / chip is a specification for a general DRAM soft error.

Here, in a 1-Gbit MRAM, for example, an extended Hamming code is used as an error detection / correction code, an 8-bit error detection / correction code (redundant bit) is added to 64-bit data (information bits), and 72 bits are 1 Let it be a block. In this case, the total number of blocks included in the MRAM is 1.68 × 10 ⁷ . When data writing and data reading are repeated alternately for 10 years for each block, the total number of times of writing is 3.15 × 10 ¹⁵ times. The total number of readings is also 3.15 × 10 ¹⁵ times.

In order to suppress the probability of simultaneous occurrence of 2-bit defects in one block to 1000 FIT / chip in one data write, a write defect in one write to one bit (one MTJ element) Is preferably 2 × 10 ⁻¹⁰ or less. In addition, in order to suppress the probability of simultaneous occurrence of 2-bit defects in one block to 1000 FIT / chip in one data read, the probability of occurrence of read disturbance q in one read for one bit q (Read) is preferably 2 × 10 ⁻¹⁰ or less.

  Here, it is considered that the write failure becomes conspicuous in either “0” data write or “1” data write. Further, here, it is considered that the read disturb occurs only in either “0” data read or “1” data read.

Next, paying attention to an arbitrary block in the memory cell array, the probability of malfunction is considered.
The probability p ₁ (write) that a 1-bit write failure occurs in one block (72 bits) in one data write is represented by (Equation 6).

The probability p ₂₊ (write) in which a write failure occurs simultaneously in two blocks or more in one block and malfunctions is expressed by (Equation 7).

The probability p ₁ (read) that 1-bit read disturb occurs in one block in one data read is expressed by (Equation 8).

Further, the probability p ₂₊ (read) in which two or more bits are simultaneously generated in one block and a malfunction occurs is expressed by (Equation 9).

In data writing and data reading, the probability that a 1-bit write failure and a 1-bit read disturb occur in the same block and malfunctions is represented by (Equation 10).

The total probability of malfunctions can be expressed by (Equation 11) from the above probability of defects.

As described with reference to FIG. 17 and FIG. 18, data writing in the MRAM of this configuration example is performed by writing data from the outside into the MTJ element and then correcting the error included in the written data with the MTJ element. When the data is written again, the pulse width of the correction data write current is made longer than the pulse width of the external data write current. As a result, the probability p ₁ (write) of 1-bit write failure is sufficiently reduced.

For example, as described with reference to FIG. 11, when the pulse width is increased by 7% with respect to a pulse width of a certain write current, the probability of write failure p ₁ (write) is reduced to about 1/10 and the pulse width is reduced. When it becomes longer by about 14% to 15%, the probability of write failure p ₁ (write) decreases to about 1/100.

  Therefore, in the same block, a 1-bit write failure occurs due to writing, and a 1-bit read disturb occurs due to reading, so that the probability of malfunction can be reduced to 1/100.

In a general memory (for example, DRAM), the probability of occurrence of a defect is set to p ₁ (write) = p ₁ (read) in order to disperse the risk of malfunction during writing and reading.

However, as shown in (Equation 11), the probability of occurrence of a malfunction, the correlation to the sum of the first bit of the writing failure probability p _{1 (write)} and 1 occurrence of bit read disturb probability p _{1 (read)} Therefore, if the occurrence probability p ₁ (write) of 1-bit write failure is sufficiently small, even if the occurrence probability p ₁ (read) of 1-bit read disturb is slightly increased, the operation of the MRAM is large. There is no adverse effect.

As described above, in operation example 1 of the MRAM of the present configuration example, if the write back corrected data to the main memory (MTJ element 1), by lengthening the pulse width of the write current, the writing failure probability p ₁ ( (write) is made sufficiently small.

As described above, when the pulse width of the write current is made 7% longer than a certain pulse width, the write failure occurrence probability p ₁ (write) is reduced to 1/10. As a result, the read disturb occurrence probability p ₁ (read) can be increased up to 1.9 times. When the pulse width of the write current is 14% to 15% longer than a certain pulse width, the probability of write failure p ₁ (write) is reduced to 1/100. As a result, the read disturb occurrence probability p ₁ (read) can be increased to 1.99 times.

Further, by being able to read disturb occurrence probability _{p 1} a (read) to 1.9 times, the current value _{i r} of the read current _{I r} shown in FIG. 17, it is 1.02 times. Therefore, in the memory cell array 20 in the main memory 50, because even variations in the resistance of the MTJ element (MR ratio) is increased, it can supply a relatively large read current I _r to the MTJ element, S for reading A sufficiently large / N ratio can be secured. As described above, since a relatively large read current can be used when reading data in accordance with the write operation of the MRAM of this configuration example, accurate data can be obtained even if the resistance value (MR ratio) of the MTJ element is small. Can be executed, and the tolerance of variation of the MTJ element 1 in the memory cell array 20 with respect to the reading can be increased.

Further, the fact that the write failure occurrence probability p ₁ (write) can be reduced to, for example, 1/100, as shown in FIG. 19, the current I _{c, mp is} applied to a plurality of MTJ elements 1 of the memory cell array 20. It means that the tolerance of the variation of the spread is widened. This will be described with reference to FIGS.

20 and 21, a phenomenon in which inversion threshold varies between the MTJ elements, and a setting example of a typical write current density inversion threshold current density J _c is taken into consideration the phenomenon that variation between MTJ element, Show.

In the example shown in FIG. 20, when the variation between the elements of the current density J _c is 3% data, the pulse width is written by the write current of 20 nsec. In FIG. 20, the average of the write failure occurrence probability q (write) at the current density J _wr of the write current is set to 1 × 10 ⁻¹⁰ .

In FIG. 20, the vertical axis indicates the probability, and the horizontal axis indicates the current density. Further, in FIG. 20, a characteristic line f1 represents the normal distribution of the variation among elements of the current density J _c, the characteristic line PA represents the probability of occurrence of writing failure, the product of the probability PA characteristic line S1 is a normal distribution f1 Is shown. A line J _wr indicates the current density of the set write current.

FIG. 21 shows a case where the pulse width of the write current used in the setting example shown in FIG. 20 is increased by 14%. In Figure 21, a characteristic line f2 represents a normal distribution of variation among elements of the current density J _c, the characteristic line PB indicate the probability of occurrence of writing failure, characteristic line S2 represents the product of a normal distribution f2 probability PB ing. A line J _wr indicates the current density of the set write current.

In Figure 21, variation among elements of the current density _{J c} is 5%. As shown in FIG. 21, when the pulse width of the write current is increased by 14%, even inter-element variations in the current density J _c is increased up to about 5%, normal distribution f1, f2 and probability PA, PB With reference to product values S1 and S2, the average of the occurrence probability q (write) of defects shown in FIG. 21 is about 1 × 10 ⁻¹⁰ . This value is substantially the same as the example shown in FIG.

As described above, by reducing the probability of occurrence of write failure p ₁ (write) by the operation example 1 (data writing) of the MRAM of this configuration example, the tolerance of the inter-element variation of the current density J _c is 3 It corresponds to an increase from 5% to 5%.

  As described above, write data input from the outside is stored in the main memory 50 and also temporarily stored in the buffer memory 54. Therefore, when a command signal CMD for reading data is input during a cycle in which detection, correction, and data write-back of data are executed, the data is read from the buffer memory 54. Therefore, the operation of the memory is not slowed down by the process of writing back the correction data. Therefore, the high-speed operation of the magnetic memory, for example, the MRAM is not impaired.

As described above, the magnetic memory according to the present embodiment writes data from the outside to the MTJ element 1 using the write current having the pulse width _{Twp1 when} writing data. Then, the magnetic memory according to the present embodiment verifies whether or not the data written in the MTJ element 1 has been normally written. When the written data includes an error, the magnetic memory according to the present embodiment corrects the error and writes the corrected data to the MTJ element again. Corrected data using the write current _{I w2} of long pulse width _{T wp2} than the pulse width _{T wp1,} written in the MTJ element 1. As a result, the time for writing data is not excessively lengthened, and the probability of writing failure is reduced.

  In addition, since the occurrence of write failures in the memory cell array of the main memory is reduced, the occurrence of malfunctions due to write failures, read disturbs and retention failures is also reduced.

  Therefore, according to the magnetic memory according to the embodiment of the present invention, the reliability of the operation can be improved and the operation characteristics can be improved.

(B) Operation example 2
An operation example 2 of the magnetic memory (MRAM) according to the configuration example of this embodiment will be described with reference to FIG. Here, as operation example 2 of the MRAM of this configuration example, reading of data used in the MRAM of this configuration example will be described. In this operation example 2, the circuit configuration of the MRAM is the same as that of the operation example 1, and the common configuration and operation (steps) will be described as necessary.

  FIG. 22 is a flowchart showing the data read operation of the MRAM of this configuration example.

First, as shown in FIG. 22, data is written to a selected cell (MTJ element 1) in the main memory 50 in an operation cycle of the MRAM (step ST10). This data is, for example, normal writing, that is, data written using the write current I _w1 having the pulse width T _wp1 shown in FIG. However, rewriting, i.e., it may be data that has been written using a write current I _w2 of the pulse width T _wp2 shown in Figure 17.

  When reading data, a command signal CMD indicating a read command and an address signal ADR indicating a selected cell are input from the outside (step ST12). The command signal CMD and the address signal ADR are input into the control circuit 51, for example.

  Data is output from the main memory 50 based on the control of the control circuit 51. In this operation example, the data output from the main memory 50 by the read command is called read data rDT.

  The read data rDT is input to the error detection unit 62 in the error detection / correction circuit 52. The read data rDT including the error detection / correction signal (redundant bit) is inspected by the error detection unit 62 to determine whether or not it includes an error (step ST13).

  If no error is detected in the read data rDT, the read data rDT is output to the decoding unit 64 without correcting the data. The decryption unit 64 decrypts the input read data rDT. The decrypted data is temporarily stored in the buffer memory 54. Then, data DT2 is output from the buffer memory 54 to the outside of the chip (step ST14). As a result, when there is no error in the read data, the data reading ends.

  On the other hand, when an error is detected in the read data rDT, the error is corrected (step ST15). The read data rDT is output to the error correction unit 63, and errors in the read data rDT are corrected by the error correction unit 63 based on the added redundant bits.

  The corrected data is output to the decoding unit 64 and decoded. The decoded correction data cDT is output to the outside as output data DT2 via the buffer memory 54 (step ST16). The correction data cDT is temporarily stored in the buffer memory 54 at the same time as being output to the outside (step ST17). When a read command for the data is input while the correction data cDT is being rewritten, the data stored in the buffer memory 54 is output to the outside.

At the time of reading data in this operation example, the correction data cDT is output to the outside, and the correction data cDT is written back to the main memory 50 (step ST18).
If corrected data cDT is written back to main memory 50 writes, for example, as the write current I _w2 shown in Figure 17, the pulse width T _wp2 of the write current I _w2 used for rewriting, usually used for writing than the pulse width _{T wp1} of the current _{I w1,} it is lengthened. This write current _{I w2,} correction data cDT is rewritten in the MTJ element 1.

  The rewritten data cDT is read again from the main memory 50 (MTJ element 1) to the error detection unit 62, and it is checked whether or not there is an error (step ST19).

  When the correction data cDT written back does not contain an error, the data correction and the data rewriting at the time of reading the data are finished.

  When the rewritten data cDT includes an error again, the error of the data is corrected again (step ST20), and the corrected data is written again in the main memory 50. For the second rewriting, it is effective to make the current pulse width longer than the first rewriting. For example, each time the number of data correction and rewrite loops (ST18 to ST20) is repeated, the pulse width of the write current is increased by 1.1 times. However, a write current having the same pulse width may be used for the first rewrite and the second and subsequent rewrites.

  Data corrected during the rewrite loop (ST18 to ST20) is temporarily stored in, for example, the buffer memory 54 (step ST17). The stored data is rewritten at every rewrite loop.

  Then, when there is no error in the data to be written back, the data rewriting is completed.

  The rewriting loop (ST18 to ST20) may be continued until there is no data error, and the rewriting loop may be limited to a predetermined number of times (for example, 10 times). For example, if the error does not disappear even if rewriting is performed 10 times for the same address (MTJ element 1), changing the address to write to another address in the main memory 50 is possible in the memory cell array. It is effective to reduce the data defects.

<Effect of Operation Example 2>
Hereinafter, the effect of the operation example 2 of the magnetic memory (MRAM) of the present embodiment will be described. In addition, about the effect similar to the effect described in the operation example 1, description here is abbreviate | omitted.

  By applying the data read from the MRAM described in the second operation example to the MRAM, the write failure that has occurred during the normal write can be corrected during the data read.

  Further, in the data reading in the second operation example, the pulse width of the write current used for rewriting is made longer than the pulse width of the write current used in normal writing, which occurs when data is written back by rewriting. Write defects can be reduced.

  Furthermore, the data reading in the second operation example is effective for a retention failure that occurs when data is held due to thermal disturbance.

  That is, according to the data reading of the second operation example, a defective bit caused by a read disturb failure, a write failure, a retention failure, or the like can be corrected to a correct bit at an early stage. As a result, an error of 2 bits or more occurs in one block, and even if error detection and correction technology is used, it is possible to reduce the probability of malfunction that cannot correct data errors.

  Similarly to the above-described operation example 1, only when the corrected data is rewritten, the high-speed operation of the MRAM is not impaired by increasing the pulse width of the write current.

  Therefore, according to the magnetic memory according to the embodiment of the present invention, the reliability of the operation can be improved and the operation characteristics can be improved.

[Configuration example 2]
A configuration example 2 of the magnetic memory (for example, MRAM) according to the embodiment of the present invention will be described with reference to FIGS. In the second configuration example, the same configurations as those described in the basic example and the first configuration example are denoted by the same reference numerals, and detailed description thereof is omitted.

  Similar to the magnetic memory of Configuration Example 1 described above, the magnetic memory of Configuration Example 2 corrects the failure when a defect (error) is detected in the data (first data) once written in the main memory 50. The written data (second data) is converted into a main current using a write current (second write current) having a pulse width longer than the pulse width of the write current (first write current) used in the previous write. Write back to memory 50.

  However, the magnetic memory of Configuration Example 2 is different from the magnetic memory of Configuration Example 1 described above in that error detection and correction of written data is performed without using an error detection and correction code.

(1) Circuit
A circuit configuration of the magnetic memory (MRAM) of Configuration Example 2 will be described with reference to FIG.

  As shown in FIG. 23, the circuit configuration of the MRAM of this configuration example is that, for example, a comparison unit 69 is provided in an error detection / correction circuit (defect detection circuit) 52. And different.

  In the configuration example 2, the detection and correction of the error included in the written data is executed without using the error detection and correction code.

  Therefore, in the MRAM of this configuration example, data DT1 input from the outside in response to a command signal indicating writing (hereinafter referred to as a write command) passes through the buffer memory 54 without an error detection and correction code being added. And input to the main memory 50.

  In the second configuration example, the control circuit 51 controls the operation of the main memory 50 so that data without the error correction detection plus sign is written to a predetermined address in the main memory 50 by normal writing. .

  That is, the external data DT1 is written by flowing the write current Iw1 having the pulse width Twp1 through the MTJ element indicated by the address without being encoded.

  If the error detection / correction code is not added to the data, the data from the buffer memory 54 may be input to the main memory 50 via the error detection / correction circuit 52, or the main memory may be connected via another path. 50 may be input.

  In FIG. 23, the normal write signal NWC is output from the error detection / correction circuit 52. For example, the error detection / correction circuit 52 detects that external data has been input into the circuit 52 and outputs the normal write signal NWC to the write pulse width control circuit 53. However, the normal write signal NWC may be output from the control circuit 51 to the write pulse width control circuit 53 when a write command is input. Alternatively, the normal write signal NWC may be output from the buffer memory 54 to the write pulse width control circuit 53 in synchronization with the output of the data DT1 when the buffer memory 54 outputs the data DT1 to the main memory 50.

  After the external data DT1 is written into the main memory 50, the error detection / correction circuit 52 receives the external input data temporarily held in the buffer memory 54 and the main memory 50 corresponding to the input data. It is compared (verified) whether or not the data written in is identical. That is, the two data to be compared by the error detection / correction circuit 52 are data DT1 before being written to the main memory 50 and data wDT1 obtained by reading from the main memory data written to the main memory 50 by normal writing or rewriting. is there.

  For example, a comparison unit 69 is provided in the error detection / correction circuit 52, and the comparison unit 69 compares the external data DT1 held in the buffer memory 54 with the data wDT1 read from the main memory 50. The comparison unit 69 has a function of reading, for example, data held in the buffer memory 54 and data written in the main memory 50 in addition to a function of comparing input data and written data.

  As described above, the buffer memory 54 holds (stores) data with higher reliability than the main memory. Therefore, the MRAM in this configuration example regards the data held in the buffer memory 54 as data (data not including a defect) that matches the data input from the outside. In the configuration example 2, the data that does not include a defect means that the probability of occurrence of a defect (error) is sufficiently low as compared with the data written in the main memory 50 and the data is highly reliable. . Data that does not include a defect corresponds to the correction data of Configuration Example 1.

When the error detection and correction circuit 52 (comparator 69) determines that the data DT1 held in the buffer memory 54 and the data wDT1 written in the main memory 50 do not match, the control signal (rewrite signal) RWC is written. Output to the pulse width control circuit 53. Then, under the control of the control circuit 51 and the write pulse width control circuit 53, the data DT1 in the buffer memory 54 used for the detection of the write failure is the previous data as the data (second data) not including the failure. The MTJ element 1 in the main memory 50 is written using a write current having a pulse width T _wp2 longer than the pulse width T _wp1 of the write current of normal writing or rewriting. As described above, when there is a write failure in the data read from the main memory 50, the data held in the buffer memory 54 and the data read from the main memory 50 are replaced and the data is corrected (rewritten). .

  If the comparison unit 69 determines that the data DT1 held in the buffer memory 54 and the data written in the main memory 50 match, the control is performed assuming that the data written in the main memory 50 does not include a write failure. The circuit 51 ends the write operation corresponding to the input write command.

  In the MRAM of Configuration Example 2, since the error detection / correction code is not added to the data, the read operation is performed for the ECC technique to which the data RDT read from the main memory 50 is applied such as a decoding process. The data is transferred to the buffer memory 54 without processing. Then, the data RDT is held in the buffer memory 54 and output to the outside as data DT2.

  In the buffer memory 54, a write buffer 54A for a write operation and a read buffer 54B for a read operation may be provided. As a result, even during a period in which data rewriting is being executed, even if reading of the data is requested from the outside, data writing / reading can be executed efficiently by parallel processing, for example. In particular, in the present configuration example, the data held in the buffer memory 54 is used to detect a write failure, so the configuration of the buffer memory 54 having the two buffer areas 54A and 54B is effective.

In the MRAM of Configuration Example 2, in order to verify whether or not the data written in the main memory 50 includes a write failure (error), the buffer memory 54 completes the write operation after the external data is input. It is necessary to hold data from the outside corresponding to the data to be written to the main memory 50 until this time.
On the other hand, in the magnetic memory of the configuration example 1 (see FIG. 14), the magnetic memory of the configuration example 1 uses the error detection correction code added to the data, and the error of the data written in the main memory 50 ( Detect and correct (bad). For this reason, in the magnetic memory of Configuration Example 1, it is not necessary for the buffer memory 54 to hold external data corresponding to the data to be detected / corrected in order to be used for detecting / correcting data errors. .

  In the configuration example 2, there are an operation pattern in which only one normal write is executed for one write command, and an operation pattern in which one normal write and one or more rewrites are executed. In this configuration example, an operation cycle from when a write command is input to when one of the two operation patterns is executed until the writing is completed is referred to as a write event.

  In the configuration example 2, an error in data detected by comparing the data held in the buffer memory with the data held in the main memory is called a write failure.

  In the example shown in FIG. 23, the comparison unit 69 is provided in the error detection / correction circuit 52. However, the comparison unit 69 may be provided outside the error detection / correction circuit 52. Further, instead of newly providing the comparison unit 69, the error detection unit 62 and the error correction unit 63 shown in FIG. 14 have substantially the same functions as the comparison unit 69, respectively, and the buffer memory 54, the main memory 50, The substantially same operation as that of the comparison unit 69 may be executed.

  The magnetic memory (MRAM) of the configuration example 2 can execute detection and correction of a data write failure without using an error detection / correction code during one write event.

  That is, the MRAM according to the second configuration example has a time for adding (encoding) an error detection and correction code to data stored in the main memory, a time for decoding data including the error detection and correction code, or a data replacement. The time required for the ECC technology, such as the time required for Therefore, the MRAM of Configuration Example 2 can shorten one operation cycle as compared with the MRAM of Configuration Example 1.

Further, when the reliability of the memory is improved by using the ECC technology, the transfer rate of the data to which the error detection and correction code is added tends to be reduced.
On the other hand, in the MRAM of this configuration example, it is possible to detect and correct a writing failure (error) of data stored in the main memory 50 without adding an error detection and correction code. Therefore, the MRAM of this configuration example can output data having high reliability to the outside at a relatively fast transfer rate.

  Further, according to the MRAM of Configuration Example 2, there are three or more mismatches between the data held in the buffer memory 54 and the data written in the main memory 50, that is, there are three or more write failures. Even if it occurs, the data can be corrected.

  As described above, the magnetic memory of the configuration example 2 of the embodiment of the present invention can improve the operation reliability like the magnetic memory of the configuration example 1, and at a higher speed than the magnetic memory of the configuration example 1. Can work.

(2) Operation
A write operation of the magnetic memory (MRAM) according to Configuration Example 2 will be described with reference to FIG. FIG. 24 is a flowchart illustrating an example of a write operation of the MRAM according to Configuration Example 2. Here, the operation and configuration substantially the same as those of the MRAM of Configuration Example 1 will be described as necessary.

  As shown in FIG. 24, at the time of data writing, a command signal CMD, an address signal, and data DT1 indicating writing are input from the outside into the MRAM (step ST1).

  The data DT1 is stored in the buffer memory 54 until the write operation (write event) ends (step ST2B ').

The data DT1 stored in the buffer memory 54 is transferred from the buffer memory 54 to the main memory 50 under the control of the control circuit 51. As the data DT 1 is input to the main memory 50, the normal write signal NWC is input to the write pulse width control circuit 53. The data transferred to the main memory 50 is written into a predetermined area in the main memory 50 indicated by the address signal ADR by normal writing (step 2A ′). The write current I _w1 used for normal writing has a predetermined write pulse width T _wp1 (≧ t ₀ ).

  In the MRAM of this configuration example, when the external data DT1 is transferred to the main memory 50, no error detection and correction code is added to the data DT1. Therefore, in this configuration example, the data DT1 written to the main memory 50 in response to the input write command is data that does not include an error detection / correction code.

  After the data DT1 that does not include the error detection / correction code is written into the main memory 50 using normal writing, whether or not the written data DT1 includes a write failure (error) is verified by a verify operation. The

  In the MRAM of Configuration Example 2, since the data written in the main memory 50 does not include an error detection / correction code, this verify operation is held in the buffer memory 54 with the data written in the main memory 50 (MTJ element 1). This is done by comparing with the data being processed.

  The data wDT1 written in the main memory 50 is read into the error detection / correction circuit (defect detection circuit) 54 as verify data. At the same time, the data DT1 in the buffer memory 54 corresponding to the verify data is read into the error detection / correction circuit 54. The verify data wDT1 and the data DT1 are input into the comparison unit 69 (or the error detection unit 62).

  The comparison unit 69 compares the verify data with the data DT1 to verify whether the data written in the main memory 50 includes a write failure (step ST3 '). In the verification of the write failure, the data DT1 read from the buffer memory 50 is handled as data without error (data with high reliability).

  If the verify data wDT1 does not include a write failure, the writing of the input data corresponding to the write command ends (step ST7). In this case, the write event corresponding to the write command ends with only normal writing.

  When a write failure is detected in the verify data, data rewrite is executed (step ST6 '). In the MRAM of Configuration Example 2, data rewriting is executed as follows.

  Data DT1 from the buffer memory 54 used for the verify operation is transferred from the error detection / correction circuit 52 to the main memory 50 as data (second data) not including a defect (error). For example, the data DT1 is output again from the buffer memory 54 to the main memory 50. Note that data for rewriting may be output from the comparison unit 69 (or the error correction unit 63) to the main memory 50.

  Along with the retransfer of the data DT1, a rewrite signal RWC is output from the error detection / correction circuit 52 (comparison unit 69 or error correction unit 63) to the write pulse control circuit 53.

Thus, the data DT1 from the buffer memory as correction data, by using the write current _{I w2} having a long pulse width _{T wp2} than normal pulse width _{T wp1} of the write current _{I w1} writing, to a predetermined MTJ element, Rewritten.

The pulse width control signal is used so that the write pulse width T _wp2 of the write current I _w2 used for _rewriting is, for example, three times the pulse width of the current used for the previous write (for example, pulse width T _wp1 ). Controlled by pwcs. However, the increase rate X of the write pulse width _{T wp2} of rewriting is not limited to three times the normal writing of the write pulse width _{T wp1,} for example, within a range of about 5 times 1.07 times the pulse width _{T wp1} But you can.

As described above, also in the MRAM in the configuration example 2, as in the MRAM in the configuration example 1 described above, whether the data writing is normal writing or rewriting is determined by the two control signals NWC and RWC. The This controls whether the pulse width of the write current is set to a predetermined pulse width T _wp1 or a pulse width T _wp2 longer than the pulse width T _wp1 .

Data rewriting including defective writing due to rewriting may be limited to one time and data writing may be terminated (step ST7).
However, as shown in FIG. 24, the verify operation may be executed again on the data rewritten to the main memory 50 (rewritten data). In this case, the rewritten data is output from the main memory 50 to the error detection and correction circuit 52, and it is compared whether or not the rewritten data matches the data DT1 stored in the buffer memory 54, as described above. When a write failure is detected in the rewrite data, the write pulse width is further increased and the data in the buffer memory is rewritten. If no writing failure is detected in the rewritten data, the data writing is completed (step ST7).

  When a defect (error) is detected in the data written to the main memory 50 by normal writing, the write event corresponding to the input write command ends with one normal write and at least one rewrite.

  Also in this configuration example, when a read command is input to the data being processed during normal / rewrite and verification of the data, the data is stored in the buffer memory 54 corresponding to the data. Data is read out to the outside (step ST2X).

  In the MRAM of this configuration example, rewritten data may be written to the same address (MTJ element) in normal writing and rewriting, or may be written to different addresses. If the writing failure of the data written in the main memory 50 is not eliminated even after repeating the rewriting several times, the MTJ element itself is defective and the data is stored in another address in the main memory 50. It is preferable to change.

  Note that the read operation of the MRAM in Configuration Example 2 is executed based on a command signal indicating read input from the outside. The requested data DT2 is output to the outside from the MTJ element indicated by the address signal via the buffer memory 54 (read buffer 54B) without detecting and correcting errors in the data.

<Effect of Configuration Example 2>
The effects of Configuration Example 2 of the magnetic memory (MRAM) of this embodiment will be described with reference to FIGS.

  Here, a case where the number of rewrites during one write event is limited to one will be described. The magnetic memory (MRAM) of the configuration example 2 described here does not use the ECC technique, and even if rewriting is not executed twice or more in one writing event, the operation reliability and the operation speed are high. Can be realized.

In FIG. 25 to FIG. 30, “p _w1 ” indicates the probability of writing failure (writing failure occurrence probability) in the first writing of data (normal writing) in one writing event, and continues to the first writing. The probability of occurrence of write failure in the second data write (rewrite) is indicated by “p _w2 ”.
Here, the number of rewrites in one write event is limited to one. Therefore, the probability that a malfunction occurs in one write event (hereinafter referred to as a malfunction occurrence probability) is indicated by “p _w1 × p _w2 ”. It is not necessary to make the value of the probability p _w1 equal to the value of the probability p _w2 .

As will be described later, when the number of rewrites is limited to one in one write event, the write current I used for normal writing is used according to the specifications required for the magnetic memory (for example, MRAM). the pulse width _{T wp1} of _w1 reduced within an allowable range, by the pulse width _{T wp2} of the write current _{I w2} used for rewriting longer than the normal pulse width _{T wp1} of writing, the memory write operation (write event) The average time required for the process is shortened, and the performance of the memory is improved. In this case, the write failure occurrence probability p _w1 in normal writing is larger than the write failure occurrence probability p _w2 in rewriting.

In the following, it is assumed as a specification of 1 Gbit MRAM that a malfunction due to a write failure is suppressed to 1000 FIT / chip or less. Here, 1 FIT / chip represents that a malfunction occurs once in 1 billion hours in one LSI (memory). 1000 FIT / chip corresponds to the case where the occurrence probability of malfunction due to write failure in one write event is 8.7 × 10 ⁻²⁰ .

FIG. 25 is a graph showing the dependence of the write failure occurrence probability p _{w2 on} the write failure occurrence probability p _w1 when the malfunction occurrence probability p _w1 × p _w2 becomes 8.7 × 10 ⁻²⁰ . The horizontal axis of the graph of FIG. 25 corresponds to the write failure occurrence probability p _w1 of normal writing, and the vertical axis of the graph of FIG. 25 corresponds to the write failure occurrence probability p _w2 of rewriting.

As shown in FIG. 25, in order to satisfy the above-described malfunction occurrence probability, when the write failure occurrence probability p _w1 for normal writing increases, the write failure occurrence probability p _{w2 for} rewrite needs to be reduced.

As shown in FIG. 2, the current value of the write current I _w2 used for rewriting is preferably equal to the current value of the write current I _w1 used for normal writing. This is because, as described above, in consideration of circuit restrictions and suppression of back hopping, the probability of malfunction can be reduced by setting the same upper limit value for each of the write currents I _w1 and I _w2 . In the following, the current value of the write current I _w2 is, a case equal to the current value of the write current I _w1.

FIG. 26 is a graph showing changes in the write pulse widths T _wp1 and T _wp2 of the write currents I _w1 and I _w2 with respect to the write failure occurrence probability p _w1 when the MRAM of this configuration example satisfies 1000 FIT / chip or less. The horizontal axis of the graph in FIG. 26 corresponds to the write failure occurrence probability p _w1 , and the vertical axis of the graph in FIG. 26 corresponds to the write pulse widths T _wp1 and T _wp2 (unit: nsec).

In Figure 26, the characteristic line (solid line) E1 corresponding to the plot of the black indicates the pulse width _{T wp1} of the write current _{I w1} of normal writing. In Figure 26, characteristic line corresponding to the plot of the outline (broken line) E2 is a pulse width _{T wp2} of rewriting the write current _{I w2.}

In the example shown in FIG. 26, when each write pulse width T _wp1 , T _wp2 is set to ₃₀ nsec, each write failure occurrence probability p _w1 , p _w2 is set to 2.95 × 10 ^−10. The current densities J _w1 / Jc (mid, 30 ns) of the write currents I _w1 and I _w2 and J _w2 / Jc (mid, 30 ns) are set to a constant value of 1.28. The malfunction occurrence probability p _w1 × p _w2 is set to a constant value (8.7 × 10 ⁻²⁰ ) so as to satisfy the specification of 1000 Fit / chip or less.

  In the following, the characteristics of the MTJ element used in the simulation of FIG. 5 are assumed, and variations between elements in the memory cell array are not considered.

As shown in FIG. 26, in accordance with the pulse width T _wp1 of normal writing (characteristic line E1) decreases, writing failure probability p _w1 of normal writing is increased. Therefore, in order to suppress the occurrence of malfunction, it is necessary to increase the pulse width T _wp2 for _rewriting (characteristic line E2).

In the MRAM of Configuration Example 2, rewriting is executed only when a writing failure occurs during normal writing. Here, rewriting is executed only once in one writing event. Therefore, the average value of the write pulse width in one write event (hereinafter referred to as the average write pulse width T _{wp_ave} ) can be expressed by “T _wp1 + p _w1 × T _wp2 ”.

Based on the equation (T _wp1 + p _w1 × T _wp2 ) indicating the average write pulse width, the time generated by _rewriting is represented by the product of the write pulse width T _wp2 and the probability p _w1 , so the write pulse width T _wp2 is Even if it becomes longer, the influence of _rewriting on the average writing pulse width T _{wp_ave} is small.

In addition, the time for which the operation of the write circuit is occupied in one write operation (hereinafter referred to as the write circuit busy time _{Tw_busy} ) is greater than the write pulse width in consideration of the time required for wiring selection and wiring charging. Also gets longer. Therefore, the write circuit busy time T _{w_busy} is expressed by (T _wp1 + α) + p _w1 × (T _wp2 + α). “Α” is a delay time caused by wiring selection, wiring charging, or wiring delay. The delay time α is, for example, about 20 nsec.

FIG. 27 shows changes in the average write pulse width T _{w_ave} and the write circuit busy time T _{w_busy when} the _normal write _error probability p _w1 is used as a function. The vertical axis in FIG. 27 shows the average write pulse width T _{wp_ave} and the write circuit busy time _{Tw_busy} (unit: nsec), and the horizontal axis in FIG. 27 shows the write failure occurrence probability p _w1 in normal write. A characteristic line (broken line) F1 corresponding to a black circle represents the average write pulse width T _{wp_ave} . In FIG. 27, a characteristic line (solid line) F2 corresponding to a white circle indicates a change in the write circuit busy time _{Tw_busy} .

As shown in FIG. 27, each write failure occurrence probability p _w1 , p _w2 is set so that the malfunction occurrence probability p _w1 × p _w2 becomes a constant value (for example, 8.7 × 10 ⁻²⁰ ). If, even when a large writing failure probability _{p w1} of normal writing, the average write pulse width _{T W_ave} and writing circuit busy time _{T W_busy} is decreased.

As shown in FIGS. 26 and 27, even if the write failure occurrence probability p _w1 for normal writing increases, the write pulse width T _wp1 for normal write is shortened and the write failure occurrence probability p _w2 for rewrite is reduced. As a result, the average write pulse width _{Twp_ave} can be reduced.
As described above, since rewriting is executed only when a writing failure occurs in normal writing, the number of times of rewriting depends on the writing failure occurrence probability p _w1 . In consideration of a plurality of write events, even if the write pulse width T _wp2 is increased to reduce the write failure occurrence probability p _w2 , an increase in the _rewrite write pulse width T _wp2 is required for the MRAM write event. Since the influence on time is small, the average write pulse width _{Twp_ave} is small.

Therefore, within the scope of the reliability of the required operating, decrease the normal write pulse width T _wp1 of writing, by increasing the write pulse width T _wp2 of rewriting, the magnetic memory of the present configuration example, ECC techniques Even without using, the reliability of the memory is ensured and the performance (operation speed) of the memory is improved.

For example, when the pulse width T _wp1 of the write current I _w1 used for normal writing is set to 15 nsec, the write failure occurrence probability p _w1 in normal writing is 7 × 10 ⁻⁴ . In the example shown in FIGS. 25 to 27 under the condition that the malfunction occurrence probability p _w1 × p _w2 is set to 8.7 × 10 ⁻²⁰ , the pulse width T of the write current I _w2 used for rewriting is used. _wp2 is 45 nsec. In this case, the relationship between the write pulse width T _wp1 and the write pulse width T _wp2 is represented by “T _wp2 = X × T _wp1 = 3 × T _wp1 ”.

Therefore, for example, in FIG. 26 and FIG. 27, the write pulse width T _wp2 at the time of _rewriting is set to about three times the write pulse width T _wp1 of the normal write, so that the average write pulse width T _{wp_ave} is When the write pulse widths T _wp1 and T _wp2 are the same for normal writing and rewriting (here, 30 nsec), the average write pulse width is reduced by about 50%. Thus, in the MRAM of Configuration Example 2, the memory write operation is speeded up.

Further, the current value of the write current I _w2 used for rewriting is set to be the same as the current value of the write current I _w1 used for normal writing, for example. In this case, since the time required for the write operation (write event) is reduced due to the reduction of the average write pulse width T _{wp_ave} , the power consumption during the write operation of the memory is reduced by about ₅₀ %. Therefore, the MRAM of Configuration Example 2 can contribute to reduction of power consumption during the memory write operation.

As shown in FIG. 27, when the write pulse width T _wp2 is set to a value three times the write pulse width T _wp1 (in the case of p _w1 = 7 × 10 ⁻⁴ ), the write circuit busy time T _{w_busy} is Compared to the case where the write pulse width T _wp1 and the write pulse width T _wp2 are set to the same value (when x = 1), the number is reduced by about 30%. As a result, the parallelism of the write circuit used in the MRAM is reduced by about 30%. The degree of parallelism described in this configuration example refers to the number of operations that can be processed in parallel in a memory such as an MRAM, or the number of elements / circuits that are simultaneously driven during parallel processing.

  FIG. 28 is a diagram schematically showing the parallelism of the write circuits in the MRAM. Here, consider the case where the MRAM operates in accordance with the DRAM LPDDR2 standard (for example, f to 400 MHz).

In the case 1 MRAM shown in FIG. 28, the write pulse width T _wp1 for the first write is set to 30 nsec, and the write pulse width T _wp2 for writing back the data is set to ₃₀ nsec. Here, although first write pulse width T _wp1 and second write pulse width T _wp2 are set to the same value, for clarity of description, and the first write and normal writing, 2 The second writing is called rewriting.

In the case 2 MRAM (configuration example 2) shown in FIG. 28, the normal write pulse width T _wp1 is set to 15 nsec, and the rewrite write pulse width T _wp2 is set to ₄₅ nsec.

  In both the case 1 and case 2 MRAMs, the upper limit value of the write current is set to a constant value.

  For burst writing of the memory in the LPDDR2 standard, for example, it is necessary to write 16-bit data to the memory area every 1.25 nsec.

  In case 1 of FIG. 28, when the delay time α is set to 20 nsec as described above, one write circuit occupies until the write to a predetermined address is completed in one data write (normal write). The time spent is 50 nsec.

  For this reason, in the LPDDR2 standard, write data is input every 1.25 nsec, so that 40 pieces of data are sequentially input into the MRAM in a predetermined cycle for 50 nsec.

  Assuming that sequentially input data is written in a plurality of regions (for example, MAT) defined in the memory cell array by parallel processing, it is necessary to perform writing to 40 MATs in parallel. is there. That is, 40 write circuits are required for normal writing. Note that MAT is, for example, a memory area of about 1 Mbit.

  In addition, since rewriting is executed only when writing to each MAT is completed and a writing failure occurs in the written data, if one writing circuit is provided for rewriting. Good.

  As described above, in case 1 of FIG. 28, 41 write circuits are required to execute writing in parallel based on the LPDDR2 standard.

In Case 2 of Figure 28, since the write pulse width _{T wp1} of normal writing is set to 15 nsec, if the delay time α is 20 nsec, the normal write for one MAT, time one write circuit is occupied Is 35 nsec.

Therefore, in the MRAM of Case 2 (Configuration Example 2), based on the LPDDR2 standard, 28 pieces of data are sequentially input into the MRAM during 35 nsec. Therefore, in the case of case 2, when writing is performed in parallel, 28 write circuits are required. The write pulse T _wp2 (= 45 nsec) for rewriting in case 2 is longer than that in case 1, but the rewriting write circuit is also a single circuit in case 2 as in case 1. It is enough.

  As described above, the MRAM in case 2 of FIG. 28 may be provided with 29 write circuits in the chip (main memory).

As described above, the write pulse width _{T wp2} of rewriting, by setting three times the normal pulse width of the write of the write pulse _{T wp1,} it is standard (in this case, LPDDR2) in the MRAM operating at, MRAM The parallelism of the write circuit can be reduced by about 30%.

Therefore, as in the MRAM configuration example 2, in a range that satisfies the allowable value of the malfunction, by shortening the normal write pulse width T _wp1 of writing, a longer write pulse width T _wp2 of rewriting, writing MRAM The degree of parallelism (number of circuits) of the circuit can be reduced, which can contribute to the reduction of the circuit size and the chip size of the MRAM.

Within a tolerance of malfunction, shortening the normal write pulse width T _wp1 of writing, by increasing the write pulse width T _wp2 of rewriting, it is also possible to reduce the current value of the write current. Here, the characteristics of the MTJ element used in the simulation of FIG. 5 are assumed, and variations between elements in the memory cell array are not considered.

(I) When T _wp1 = T _wp2 = 30 nsec
When the current density of the write current is set to J _w1 / Jc (mid, 30 ns) = J _w2 / Jc (mid, 30 ns) = 1.28, the write failure occurrence probability p _w1 , p _w2 is expressed as p _w1 = p _w2 = 2.95 × 10 ⁻¹⁰ . In this case, the malfunction occurrence probability p _w1 × p _w2 is 8.7 × 10 ⁻²⁰ and satisfies the required specifications.

(Ii) When T _wp1 = 30 nsec and T _wp2 = 100 nsec
When the current density of the write current is set to J _w1 / Jc (mid, 30 ns) = J _w2 / Jc (mid, 100 ns) = 1.14, the write failure occurrence probability p _w1 and p _w2 is p _w1 = 2.9 × 10 ⁻⁴ and p _w2 = 3.0 × 10 ⁻¹⁶ . Even in this case, the malfunction occurrence probability p _w1 × p _w2 is 8.7 × 10 ⁻²⁰ and satisfies the required specifications.

  When the characteristic variation between the MTJ elements in the memory cell array is not taken into consideration, the MRAM having the set value (ii) has a write current current density (or current value) of 11 compared to the MRAM having the set value (i). % Reduction. When considering that the characteristics between MTJ elements in the memory cell array vary by about 6.9%, the MRAM with the set value of (ii) has the write current of the MRAM with the set value of (i). The current density is reduced by about 16%.

  Therefore, the magnetic memory of this configuration example can reduce the current density / current value of the write current, and can contribute to the reduction of the power consumption of the memory.

  In addition, since the magnetic memory of this configuration example does not use error detection and correction codes for data error detection and correction, the time required for encoding and decoding does not occur, the operation speed can be improved, and a high transfer rate is realized. it can.

29 and 30, the lower limit of the write pulse width T _wp1 of the write current I _w1 used for normal writing will be verified.

  When the MRAM using the above-mentioned LPDDR2 standard operates by burst writing, it is necessary to write 16-bit data every 1.25 nsec. That is, 12.8-bit data is written in 1 nsec.

The degree of parallelism of bits (MTJ elements) in normal writing is indicated by “(T _wp1 + α) × 12.8”. The degree of parallelism of the bits in rewriting is indicated by “p _w1 × (T _wp2 + α) × 12.8”.

FIG. 29 shows the parallelism of normal / rewritten MTJ elements and the total parallelism (called the total parallelism). FIG. 30 is an enlarged view of a part of FIG. The vertical axes in FIGS. 29 and 39 correspond to the degree of parallelism (unit: bit), and the horizontal axes in FIGS. 29 and 30 correspond to the write failure occurrence probability p _w1 in normal writing.

  In FIG. 29, the characteristic line G1 corresponds to the parallel degree of the MTJ element for normal writing, the characteristic line G2 corresponds to the parallel degree of the MTJ element for rewriting, and the characteristic line G3 is the sum of normal writing and rewriting. It corresponds to the degree of parallelism.

When the write pulse width _Twp1 is shortened, that is, when the write failure occurrence probability _pw1 is increased, the parallelism of the MTJ elements in normal writing decreases. However, since it is necessary to satisfy a value required for the occurrence probability of malfunction, the parallelism of MTJ elements in rewriting increases from a certain probability p _w1 .
As a result, the total parallelism shown by the characteristic line G3 in FIG. 29 also increases rapidly from the vicinity of the probability p _w1 that the rewrite parallelism increases.

FIG. 30 is an enlarged view of the vicinity of the minimum value of the total parallelism shown in FIG. As shown in FIG. 30, the total parallelism indicated by the characteristic line G3 has a minimum value in the vicinity of the write failure occurrence probability p _w1 = 0.015.
When the write failure occurrence probability p _w1 is greater than 0.02, the number of times rewrite is executed increases, so the parallelism of rewrite starts to increase, and as a result, the total parallelism also increases.

Therefore, it is preferable to set the pulse width T _wp1 of the write current I _w1 used for the normal write so that the write failure occurrence probability p _w1 for the normal write is 0.02 or less. When the write failure occurrence probability p _w1 = 0.02, the ratio T _wp2 / T _wp1 between the pulse width T _wp1 of the write current I _w1 for normal write and the pulse width T _wp2 of the write current I _w2 for _rewrite is 4. 1 or less.

  29 and 30 also verify the case where there is no variation in the characteristics of the MTJ element and the writing failure occurs uniformly over time. However, even in the verification considering the characteristic variation of the MTJ element, the degree of parallelism changes with substantially the same tendency.

In this configuration example, the case where the malfunction occurrence probability p _w1 × p _w2 is set to 8.7 × 10 ⁻²⁰ has been described, but in the case where the malfunction occurrence probability p _w1 × p _w2 is set to another constant value, In addition, substantially the same effect as that described in the present configuration example can be obtained.

  As described above, according to the magnetic memory according to the present embodiment, the operation reliability can be improved and the operation characteristics can be improved.

[Modification]
A modification of the configuration and operation of the magnetic memory described in Configuration Examples 1 and 2 will be described with reference to FIGS. In this modification, the same configurations as those described in the basic example and configuration examples 1 and 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In FIG. 14, normal data writing and data rewriting at the time of correction are performed based on the control signals NWC and RWC respectively output from the encoding unit 61 and the error correction unit 63 provided in the error detection and correction circuit 52. As described above, the pulse width of the write current is controlled.

  On the other hand, instead of using the control signal, a determination signal (flag) added to the data may be used to determine whether normal writing or rewriting (data writing back).

FIG. 31 shows the internal configuration of an MRAM according to a modification of the present embodiment.
A determination signal for determining whether normal writing or correction writing is added to the data nDT and cDT. For example, when an error detection / correction code using a normal Hamming code is used, 7 bits of redundant bits as an error detection / correction code are added to 64-bit data, and it is further determined whether normal writing or correction writing is performed. A 1-bit decision signal (hereinafter referred to as a decision bit) is added. In this case, 72-bit data is handled as one block. For example, when the determination bit is “0”, normal writing is indicated, and when the determination bit is “1”, correction writing is indicated.

  The encoding unit 61 sets the determination bit to “0” when data wDT is input or output. The error correction unit 63 sets the determination bit to “1” when data rDT is input or output.

  As shown in FIG. 31, the write pulse width control circuit 53 is disposed adjacent to the main memory 50. For example, data nDT and cDT are input to the write pulse width control circuit 53 directly or via the main memory 50. Only the determination bits included in the data nDT and cDT may be input to the write pulse width control circuit 53.

  The write pulse width control circuit 53 has a function of discriminating a determination bit included in one block of data. Depending on whether the determination bit is “1” or “0”, data writing is performed as normal writing or Determine correct write.

Thus, similar to the configuration shown in FIG. 14, the write pulse width control circuit 53 generates and outputs the write current I _w1 having the pulse width T _wp1 shown in FIG. The operation of the write circuit in the main memory 50 is controlled. Further, the write pulse width control circuit 53 generates and outputs a write current I _w2 having a pulse width T _wp2 longer than the pulse width T _wp1 shown in FIG. The operation of the write circuit is controlled.

  In this way, it is possible to determine whether normal writing or rewriting is performed based on the determination bit included in the data written to the MTJ element, and writing data to the MTJ element using a write current having a predetermined pulse width according to the determination result. Can do.

  As a result, it is not necessary to provide a new control signal to the MRAM chip, and accordingly, wiring for supplying the control signal is not required, so that the load on the entire control of the chip and the wiring layout in the chip is reduced.

One of the points of the MRAM according to the embodiment of the present invention is that a write current used for normal writing when data once read from the MTJ element 1 is written back to the MTJ element 1 in the operation cycle in the chip. Compared to I _w1 , the pulse width of the write current I _w2 used for rewriting is increased. As a result, the probability of occurrence of a write failure is reduced, and data errors in the main memory (memory cell array) are reduced.

  The operation of increasing the write current pulse width at the time of rewriting data can also be applied to the refresh operation (memory holding operation) for the main memory 50.

  FIG. 32 shows an internal configuration of an MRAM according to a modification of the present embodiment, and FIG. 33 shows a flowchart of an operation (refresh operation) of the MRAM according to the modification.

  For example, as shown in FIG. 32, the MRAM in which the refresh operation of this modification is used has a counter unit 59 that counts the number of times of reading.

As shown in FIG. 33, externally input data is written to the MTJ element in the main memory 50 (step ST21). At this time, the data wDT is written by normal writing, and a write current I _w1 having a pulse width T _wp1 shown in FIG. 17 is used for writing data.

  Thereafter, when a read command is input, the data stored in the main memory 50 is read (step ST22). Note that error detection and correction may be performed on the read data, or error detection and correction may not be performed.

  The counter unit 59 in the control circuit 51 counts the number of data read times (step ST23). The counter unit 59 may count the input of a command signal CMD indicating a read command, or may count the output of data from the main memory 50.

The control circuit 51 compares the value (hereinafter referred to as a count value) N _n counted by the counter unit 59 with a reference value N _rfl for executing the refresh operation (step ST24).

When the count value N _n is equal to or _smaller than the reference value N _rfl , the refresh operation is not executed, and the next operation (for example, data reading) or the operation ends. Even when the operation is finished, the counted counter value N _n is held in the counter unit 59 as the counter value N _n−1 thus far.

On the other hand, the count value _{N n} is greater than the reference value _{N rfl,} refresh operation is executed (step ST25). After the data stored in the main memory 50 is read once by the refresh operation, the data is written back into the main memory 50 again. Note that error detection and correction may be performed during the refresh operation.

During the refresh operation, the data read from the main memory 50 is written back into the main memory 50 using the write current I _w2 having a pulse width longer than that when writing data from the outside (step ST26). ). That is, during the refresh operation, as shown in FIG. 17, the write current I _w2 having a pulse width T _wp2 longer than the pulse width T _wp1 is used for data write back to the main memory 50.

  During the refresh operation, a control signal RFL indicating the refresh operation is input from the control circuit 51 to the write pulse width control circuit 53. Based on the control signal RFL, the write pulse width control circuit 53 controls the operation of the write circuits 2A and 2B so as to increase the pulse width of the write current.

After the refresh operation using the write current I _w2 of long pulse width T _wp2, for example, reading of data in the next operation cycle is executed. Of course, the operation following the refresh operation may be data writing.

  With the above operation, the refresh operation of the MRAM of this modification is completed.

As a result, it is possible to reduce the occurrence of defective data writing when data stored in the main memory 50 (MTJ element 1) is written back to the main memory 50 in the refresh operation. Further, only the data rewriting at the time of the refresh operation, the longer the pulse width T _wp2 of the write current I _w2 used therefor, by the pulse width of the write current is increased, the high-speed operation of the MRAM is impaired No.

  In this embodiment, a magnetic memory that combines the read operation of the magnetic memory of Configuration Example 1 and the write operation of the magnetic memory of Configuration Example 2 may be configured. FIG. 34 shows the circuit configuration of this magnetic memory.

  In this magnetic memory, the error detection / correction code is detected / corrected by comparing two data without using the error detection / correction code in the write operation, and the error detection / correction code is set in the read operation. The error detection / correction of data in the main memory 50 is executed.

  In the magnetic memory (for example, MRAM) shown in FIG. 34, the detection and correction (rewriting) of the write failure during the write operation is performed by using the data wDT1 written in the main memory 50 and the buffer memory as described in the configuration example 2. This is done by comparing the data stored in 54 with DT1.

In the magnetic memory shown in FIG. 34, during the read operation, as described in the operation example 2 of the configuration example 1, the error detection of the data written in the main memory 50 is performed using the error detection and correction code added to the data. And correction is performed.
The error detection / correction code is obtained by reading the data from the main memory 50, generating an error detection / correction code for the data, and writing a parity bit after a few milliseconds after the data is written. It is added to the data in the memory 50. The addition of the error detection / correction code may be executed in a standby state of the memory or in an operation cycle capable of parallel processing. For example, the encoding unit 61 encodes data written in the main memory 50. The encoded data is written back to the main memory 50. At this time, the encoding unit 61 outputs the rewrite signal RWC to the write pulse width control circuit 53, so that the encoded data is rewritten with the write pulse width set longer than that of the normal write, so that the main memory 50 may be written.

In the magnetic memory of FIG. 34, the write current I _w1 used for normal writing (data writing from the outside) when writing back the error-corrected data to the main memory 50 during the write operation and the read operation. using a write current having a pulse width longer Twp2 than the pulse width _{T wp1,} it is executed. As a result, data errors occurring in the main memory 50 are reduced.

  When the ECC technique is applied to the MRAM, an error detection and correction code is calculated and generated when data is written. In addition to data input from the outside, a parity bit as the error detection and correction code must be written in the main memory 50. As a result, it is difficult to increase the transfer rate when writing to the MRAM.

  For example, when the above-mentioned LPDDR2 standard is used for an MRAM, it becomes difficult for a memory using an error detection and correction code during a write operation to support a write mask instruction of this standard.

  The write mask instruction of the LPDDR2 standard causes a write operation to rewrite the remaining 16 bits without changing (rewriting) 48-bit data in one block (64 bits).

  In order for the MRAM using the error detection and correction code to correspond to such an operation, before rewriting the data, the 64-bit data is once read and decoded, and then the data is rewritten based on the write mask instruction. This is necessary. For this reason, the MRAM to which the ECC technology is applied always requires a read operation for a write operation called a write mask instruction. As a result, it is difficult to increase the transfer rate when writing data.

  The magnetic memory (for example, MRAM) shown in FIG. 34 does not use the error detection / correction code during the data write operation based on the write command as described in the configuration example 2, and is not affected by the memory standard. A high transfer rate can be realized, and high reliability in data writing can be ensured by comparing input data with written data.

  After that, the MRAM shown in FIG. 34 reduces the read disturb and the retention failure by using the added error detection and correction code during the data read operation as described in the operation example 2 of the configuration example 1. it can.

  Therefore, the MRAM shown in FIG. 34 can realize a magnetic memory with a high transfer rate and a high-speed operation, and reduce data defects (errors) such as write defects, read disturbs, and retention defects that occur in the magnetic memory. it can.

  As described above, also in the modification examples shown in FIGS. 31 to 34, the operation reliability can be improved and the operation characteristics can be improved as in the above-described configuration examples 1 and 2.

[Others]
In an embodiment of the present invention, as shown in FIG. 2 and FIG. 17, the write current I _w2 for the write current I _w1 and rewrite for normal writing is set to the same current value. However, the pulse width T _wp2 of the write current I _w2 used for writing back the read data once to the MTJ element is the pulse width T _wp1 of the write current I _w1 for newly writing data from the outside to the MTJ element. If longer, the magnitudes of the current values of the two currents I _w1 and I _w2 may be different from each other.

  The embodiments of the present invention have been described by taking as an example a magnetic memory (MRAM) in which a main memory is configured using a magnetoresistive element as a storage element. However, the present invention is not limited to this. For example, an element such as ReRAM (Resistive RAM) or PCRAM (Phase Change RAM) that stores a device whose resistance value reversibly changes by controlling the pulse width of the write current (write voltage) is stored. It goes without saying that other memories used for the element can obtain the same effects as those described in the embodiment of the present invention.

  The example of the present invention is not limited to the above-described embodiment, and can be embodied by modifying each component without departing from the gist thereof. Various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above-described embodiments, or constituent elements of different embodiments may be appropriately combined.

  50: main memory, 51: control circuit, 52: error detection and correction circuit, 53: write pulse width control circuit, 54: buffer memory, 20: memory cell array, 1: magnetoresistive effect element, 2, 2A, 2B: write circuit .

Claims (13)

Magnetoresistance having a first magnetic layer whose magnetization direction is invariable, a second magnetic layer whose magnetization direction is variable, and an intermediate layer provided between the first magnetic layer and the second magnetic layer An effect element;
Error detection that detects whether or not the first data written in the magnetoresistive element includes an error, and outputs the second data in which the error is corrected when the first data includes an error A correction circuit;
A write circuit for generating one of a first write current having a first pulse width and a second write current having a second pulse width longer than the first pulse width and passing the generated current through the magnetoresistive element When,
A control circuit for controlling the write circuit so that the second write current flows through the magnetoresistive element when writing the second data to the magnetoresistive element;
A magnetic memory comprising: When writing the first data to the magnetoresistive element,
2. The magnetic memory according to claim 1, wherein the control circuit controls the write circuit so that the first write current flows through the magnetoresistive element. 3.   The first pulse width is set to be equal to or greater than a total period of a period until the magnetization of the storage layer starts coherent precession and a period during which the coherent precession is amplified. The magnetic memory according to claim 2.   The magnetic memory according to claim 1, further comprising a buffer memory that temporarily stores third data corresponding to the first data.   The third data is read from the buffer memory when the reading of the first data is requested while the second data is being written to the magnetoresistive effect element. The magnetic memory according to claim 4. When the first data is written to the magnetoresistive effect element, the error detection and correction circuit outputs a first control signal to the control circuit;
When the second data is written to the magnetoresistive effect element, the error detection and correction circuit outputs a second control signal to the control circuit;
The control circuit includes:
Controlling the write circuit so that the first write current flows through the magnetoresistive element when the first control signal is input;
3. The magnetic memory according to claim 2, wherein when the second control signal is input, the write circuit is controlled so that the second write current flows through the magnetoresistive element. 4. . Including a first determination signal indicating that the first data is written using the first write current;
A second determination signal indicating that the second data is written using the second write current;
The control circuit includes:
Controlling the write circuit to cause the first write current to flow through the magnetoresistive element in accordance with the first determination signal;
The magnetic memory according to claim 2, wherein the write circuit is controlled so that the second write current flows through the magnetoresistive element in accordance with the second determination signal. The first data has an error detection and correction code,
The magnetic memory according to claim 1, wherein the error detection and correction circuit detects and corrects an error included in the first data using the error detection and correction code. . Magnetoresistance having a first magnetic layer whose magnetization direction is invariable, a second magnetic layer whose magnetization direction is variable, and an intermediate layer provided between the first magnetic layer and the second magnetic layer An effect element;
A defect detection circuit that detects whether or not the first data written in the magnetoresistive effect element includes a defect, and outputs second data that does not include the defect when the first data includes a defect. When,
A write circuit for generating one of a first write current having a first pulse width and a second write current having a second pulse width longer than the first pulse width and passing the generated current through the magnetoresistive element When,
A control circuit for controlling the write circuit so that the second write current flows through the magnetoresistive element when writing the second data to the magnetoresistive element;
A magnetic memory comprising: When writing the first data to the magnetoresistive element,
The magnetic memory according to claim 9, wherein the control circuit controls the write circuit so that the first write current flows through the magnetoresistive element. A buffer memory for temporarily storing external data corresponding to the first data;
The defect detection circuit detects a defect included in the first data by comparing the first data with data stored in the buffer memory. The magnetic memory described.   The magnetic memory according to claim 11, wherein when the first data includes a defect, data stored in the buffer memory is written to the magnetoresistive element as the second data. .   The magnetic memory according to claim 9, wherein a probability that the first data includes a defect is 0.02 or less.

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