WO2011034673A3 - Dispositif et procédé de mémoire - Google Patents

Dispositif et procédé de mémoire Download PDF

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Publication number
WO2011034673A3
WO2011034673A3 PCT/US2010/045573 US2010045573W WO2011034673A3 WO 2011034673 A3 WO2011034673 A3 WO 2011034673A3 US 2010045573 W US2010045573 W US 2010045573W WO 2011034673 A3 WO2011034673 A3 WO 2011034673A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
memory block
access
address decoder
access port
Prior art date
Application number
PCT/US2010/045573
Other languages
English (en)
Other versions
WO2011034673A2 (fr
Inventor
Evandro Jose Pitaro Borracini
Marcelo Del Fiore De Araujo
Jefferson Bastreghi
Ross Sinclair Scouller
Original Assignee
Freescale Semiconductor Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc. filed Critical Freescale Semiconductor Inc.
Priority to CN201080041997.5A priority Critical patent/CN102648456B/zh
Priority to EP10817624.9A priority patent/EP2480976A4/fr
Publication of WO2011034673A2 publication Critical patent/WO2011034673A2/fr
Publication of WO2011034673A3 publication Critical patent/WO2011034673A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7201—Logical to physical mapping or translation of blocks or pages

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Read Only Memory (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

L'invention porte sur un dispositif qui présente un module de mémoire (16) qui comporte un premier bloc de mémoire (22), un second bloc de mémoire (23), un emplacement programmable de mémorisation et un dispositif de commande de mémoire (26). Le premier bloc de mémoire (22) de la mémoire non volatile comporte une pluralité d'emplacements de mots et un décodeur d'adresse (201) couplé à un premier port d'accès du dispositif de commande de mémoire (26). Le décodeur d'adresse (201) est destiné à sélectionner l'un parmi une pluralité d'emplacements de mots pour un accès en réponse à la réception d'informations d'adresse par l'intermédiaire du premier port d'accès. Le second bloc de mémoire (23) comporte une pluralité d'emplacements de mots et un décodeur d'adresse (201) couplé à un second port d'accès du dispositif de commande de mémoire (26). Le décodeur d'adresse (201) est destiné à sélectionner l'un parmi une pluralité d'emplacements de mots pour un accès en réponse à la réception d'informations d'adresse par l'intermédiaire du second port d'accès. Le dispositif de commande de mémoire (26) comporte une entrée couplée à l'emplacement programmable (25) de mémorisation et destinée à accéder, en réponse aux informations de configuration programmables ayant une première valeur, à une première partie du premier bloc de mémoire (22) et à une première partie du second bloc de mémoire (23) en tant que mémoire entrelacée, à une seconde partie du premier bloc de mémoire (22) en tant que mémoire non entrelacée, et à une seconde partie du second bloc de mémoire (23) en tant que mémoire non entrelacée.
PCT/US2010/045573 2009-09-21 2010-08-16 Dispositif et procédé de mémoire WO2011034673A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201080041997.5A CN102648456B (zh) 2009-09-21 2010-08-16 存储器装置及方法
EP10817624.9A EP2480976A4 (fr) 2009-09-21 2010-08-16 Dispositif et procédé de mémoire

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/563,259 US8327092B2 (en) 2009-09-21 2009-09-21 Memory device configurable as interleaved or non-interleaved memory
US12/563,259 2009-09-21

Publications (2)

Publication Number Publication Date
WO2011034673A2 WO2011034673A2 (fr) 2011-03-24
WO2011034673A3 true WO2011034673A3 (fr) 2011-06-16

Family

ID=43757596

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2010/045573 WO2011034673A2 (fr) 2009-09-21 2010-08-16 Dispositif et procédé de mémoire

Country Status (4)

Country Link
US (1) US8327092B2 (fr)
EP (1) EP2480976A4 (fr)
CN (1) CN102648456B (fr)
WO (1) WO2011034673A2 (fr)

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JP2012230621A (ja) * 2011-04-27 2012-11-22 Sony Corp メモリ装置、メモリ制御装置、メモリ制御方法
US9396106B2 (en) * 2011-05-12 2016-07-19 Avago Technologies General Ip (Singapore) Pte. Ltd. Advanced management of a non-volatile memory
GB2493340A (en) * 2011-07-28 2013-02-06 St Microelectronics Res & Dev Address mapping of boot transactions between dies in a system in package
US9256531B2 (en) * 2012-06-19 2016-02-09 Samsung Electronics Co., Ltd. Memory system and SoC including linear addresss remapping logic
US9740485B2 (en) * 2012-10-26 2017-08-22 Micron Technology, Inc. Apparatuses and methods for memory operations having variable latencies
US9754648B2 (en) * 2012-10-26 2017-09-05 Micron Technology, Inc. Apparatuses and methods for memory operations having variable latencies
US9245496B2 (en) * 2012-12-21 2016-01-26 Qualcomm Incorporated Multi-mode memory access techniques for performing graphics processing unit-based memory transfer operations
US9734097B2 (en) * 2013-03-15 2017-08-15 Micron Technology, Inc. Apparatuses and methods for variable latency memory operations
TWI494849B (zh) * 2013-05-06 2015-08-01 Phison Electronics Corp 韌體碼載入方法、記憶體控制器與記憶體儲存裝置
US9563565B2 (en) 2013-08-14 2017-02-07 Micron Technology, Inc. Apparatuses and methods for providing data from a buffer
US9727493B2 (en) 2013-08-14 2017-08-08 Micron Technology, Inc. Apparatuses and methods for providing data to a configurable storage area
US9208083B2 (en) 2013-12-04 2015-12-08 Avago Technologies General Ip (Singapore) Pte. Ltd. System and method to interleave memory
US10365835B2 (en) 2014-05-28 2019-07-30 Micron Technology, Inc. Apparatuses and methods for performing write count threshold wear leveling operations
KR102355573B1 (ko) * 2014-10-29 2022-01-27 삼성전자주식회사 선형 리맵퍼 및 액세스 윈도우를 포함하는 메모리 시스템 및 시스템 온 칩
KR102269899B1 (ko) * 2015-01-12 2021-06-28 삼성전자주식회사 메모리 장치 및 이를 포함하는 메모리 시스템
CN107451493A (zh) * 2016-05-30 2017-12-08 珠海市微半导体有限公司 Risc架构保密电路及其方法
CN106294546B (zh) * 2016-07-22 2019-04-16 北京英诺威尔科技股份有限公司 一种内存存储设备端口状态数据的方法
US10642497B2 (en) * 2016-08-31 2020-05-05 International Business Machines Corporation System, method and computer program product for instantiating blocks of a solid-state disk to include different flash characteristics
CN106873909B (zh) * 2017-01-22 2020-06-30 建荣集成电路科技(珠海)有限公司 一种存储访问方法及其系统、存储设备
TWI639917B (zh) 2017-04-25 2018-11-01 慧榮科技股份有限公司 資料儲存裝置及映射表重建方法
US10936199B2 (en) * 2018-07-17 2021-03-02 Silicon Motion, Inc. Flash controllers, methods, and corresponding storage devices capable of rapidly/fast generating or updating contents of valid page count table
TWI719779B (zh) * 2019-12-26 2021-02-21 新唐科技股份有限公司 一次性可編程記憶體裝置及其容錯方法
CN113110878A (zh) * 2020-01-09 2021-07-13 瑞昱半导体股份有限公司 存储器装置及其操作方法

Citations (3)

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Publication number Priority date Publication date Assignee Title
US20010033524A1 (en) * 2000-01-31 2001-10-25 Stmicroelectronics S.R.L. Circuit for managing the transfer of data streams from a plurality of sources within a system
EP1191445A2 (fr) * 2000-09-20 2002-03-27 Broadcom Corporation Commande de mémoire à configuration programmable
US20040156361A1 (en) * 2003-02-07 2004-08-12 Fujitsu Limited Memory interleaving in a high-speed switching environment

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US5226134A (en) * 1990-10-01 1993-07-06 International Business Machines Corp. Data processing system including a memory controller for direct or interleave memory accessing
US5630098A (en) * 1991-08-30 1997-05-13 Ncr Corporation System and method for interleaving memory addresses between memory banks based on the capacity of the memory banks
US6049855A (en) * 1997-07-02 2000-04-11 Micron Electronics, Inc. Segmented memory system employing different interleaving scheme for each different memory segment
US6938133B2 (en) * 2001-09-28 2005-08-30 Hewlett-Packard Development Company, L.P. Memory latency and bandwidth optimizations
US7793059B2 (en) * 2006-01-18 2010-09-07 Apple Inc. Interleaving policies for flash memory
ES2498096T3 (es) * 2006-03-31 2014-09-24 Mosaid Technologies Incorporated Esquema de control de sistema de memoria Flash

Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
US20010033524A1 (en) * 2000-01-31 2001-10-25 Stmicroelectronics S.R.L. Circuit for managing the transfer of data streams from a plurality of sources within a system
EP1191445A2 (fr) * 2000-09-20 2002-03-27 Broadcom Corporation Commande de mémoire à configuration programmable
US20040156361A1 (en) * 2003-02-07 2004-08-12 Fujitsu Limited Memory interleaving in a high-speed switching environment

Non-Patent Citations (1)

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Title
See also references of EP2480976A4 *

Also Published As

Publication number Publication date
EP2480976A4 (fr) 2013-08-07
US8327092B2 (en) 2012-12-04
CN102648456B (zh) 2015-04-01
US20110072190A1 (en) 2011-03-24
EP2480976A2 (fr) 2012-08-01
CN102648456A (zh) 2012-08-22
WO2011034673A2 (fr) 2011-03-24

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