WO2011033695A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

Info

Publication number
WO2011033695A1
WO2011033695A1 PCT/JP2010/002650 JP2010002650W WO2011033695A1 WO 2011033695 A1 WO2011033695 A1 WO 2011033695A1 JP 2010002650 W JP2010002650 W JP 2010002650W WO 2011033695 A1 WO2011033695 A1 WO 2011033695A1
Authority
WO
WIPO (PCT)
Prior art keywords
epitaxial layer
semiconductor device
gate electrode
region
manufacturing
Prior art date
Application number
PCT/JP2010/002650
Other languages
French (fr)
Japanese (ja)
Inventor
香川和宏
米田健司
Original Assignee
パナソニック株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Publication of WO2011033695A1 publication Critical patent/WO2011033695A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Definitions

  • the present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a P-channel transistor having a SiGe epitaxial film in a source / drain region and a manufacturing method thereof.
  • the width of the gate electrode is about to be 40 nm or less.
  • a distortion technique for increasing driving force by applying stress to a channel formation region of a transistor (a region where a channel is formed in a substrate) of a transistor has already been put into practical use in response to the increase in speed.
  • the band structure of the channel formation region changes.
  • the effective mass of carriers in the channel formation region changes, causing a change in band occupancy, and the channel portion mobility changes.
  • NMOS n-channel MOS
  • PMOS p-channel MOS
  • Non-Patent Document 1 A method of forming a silicon germanium film having a constant by epitaxial growth has been proposed.
  • a compressive stress caused by a lattice constant difference can be applied from the side to the channel formation region below the gate electrode.
  • the compressive stress applied to the channel formation region increases as the concentration of germanium contained in silicon germanium increases.
  • the inventors of the present application examined the reason why the channel portion mobility is not improved as compared with the expectation and the reason why the leakage current increases. This will be described below.
  • FIG. 6 shows a structure in which a gate electrode 12 with a sidewall 13 is formed on a semiconductor substrate 10 and a silicon germanium (SiGe) film 11 is buried in an S / D region on the side of the gate electrode 12 by epitaxial growth. Show.
  • Non-patent Document 2 When a SiGe crystal is epitaxially grown on a Si substrate (semiconductor substrate 10), a crystal defect 14 accompanying an increase in strain energy occurs (Non-patent Document 2).
  • the SiGe epitaxial film thickness that can be grown without the occurrence of such crystal defects is called the critical film thickness.
  • the critical film thickness decreases as the Ge concentration increases.
  • FIG. 7 shows the relationship between film thickness and lattice relaxation for a SiGe layer having a Ge concentration of about 30 atom%. Since the lattice relaxation becomes large when crystal defects occur, the lattice relaxation suddenly increases when the film thickness exceeds about 80 nm, and it can be understood that the critical film thickness is about 80 nm.
  • the portion that becomes the S / D region of the P channel has a depth that includes at least the side of the channel formation region by etching.
  • a recess is formed, and a SiGe epitaxial layer is formed in the recess.
  • the SiGe epitaxial layer is formed on the substrate so as to have a certain height. As a result, when the recess portion and the portion on the substrate are combined, the thickness of the SiGe epitaxial layer to be grown may be 80 nm or more.
  • interface impurities such as O (oxygen) that cannot be removed by cleaning before epitaxial growth, H 2 bake during epitaxial growth, or the like.
  • interface impurities cause a stacking fault 14 in the SiGe epitaxial layer (see FIG. 6). Since the stacking fault 14 here penetrates the SiGe crystal layer, it also penetrates the S / D junction interface formed in the SiGe crystal, causing junction leakage.
  • the inventors of the present application have conceived that a SiGe epitaxial layer having no stacking fault or the like is formed in a portion sandwiching the channel formation region from both sides to ensure the application of stress. Furthermore, the inventors conceived of suppressing the leakage current by positioning the S / D junction interface in a portion free from crystal defects.
  • a semiconductor device includes a source region and a drain region formed on a surface portion of a semiconductor substrate, and a gate electrode formed on a channel formation region sandwiched between these via a gate insulating film.
  • the source region and the drain region are formed in the third epitaxial layer, and each junction depth is Is shallower than the depth of the third epitaxial layer.
  • the channel formation region is compressed by the epitaxial layer formed in the recesses on both sides of the gate electrode, particularly the third epitaxial layer made of silicon germanium (SiGe) and sandwiching the channel formation region. Stress can be applied.
  • the third epitaxial layer generation of stacking faults and lattice relaxation is suppressed for the reason described later. Therefore, a compressive stress can be reliably applied to the channel formation region, and the channel portion mobility can be improved. Further, since the junction depth of the source region and the drain region is shallower than the depth of the third epitaxial layer, the S / D junction interface can be made free of crystal defects that cause a leakage current. As a result, leakage current can be reduced.
  • crystal defects such as stacking faults are likely to occur due to interface impurities such as O on the bottom surface of the recess (interface between the semiconductor substrate and the first epitaxial layer).
  • interface impurities such as O on the bottom surface of the recess (interface between the semiconductor substrate and the first epitaxial layer).
  • the crystal defects are absorbed in the second epitaxial layer so that no crystal defects exist on the upper surface of the second epitaxial layer. can do. Therefore, generation of crystal defects can be suppressed for the third epitaxial layer formed on the second epitaxial layer.
  • the thickness of the third epitaxial layer which is the main part sandwiching the channel formation region, can be suppressed, and the critical film thickness can be reduced. Therefore, the occurrence of lattice relaxation in the third epitaxial layer is suppressed.
  • the source region and the drain region are preferably formed by introducing a P-type impurity, and the P-type impurity is preferably not introduced into the first epitaxial layer and the second epitaxial layer.
  • the third epitaxial layer preferably includes a layer having a P-type impurity concentration of 1 ⁇ 10 18 / cm 3 or more.
  • the junction depth of the source region and the drain region can be surely made smaller than the depth of the third epitaxial layer.
  • the third epitaxial layer from the interface between the second epitaxial layer and the third epitaxial layer, in a range up to the junction depth of the source region or the drain region, a P-type impurity concentration 0 / cm 3 from 1 ⁇ 10 18 / It is preferable to have a P-type impurity profile that varies to cm 3 .
  • the S / D junction interface of the source region or the drain region is a surface having an impurity concentration of about 1 ⁇ 10 18 / cm 3 for forming these regions. Therefore, the source region and the drain region can be reliably arranged in the third epitaxial layer by setting the position where the concentration is to be shallower than the lower surface of the third epitaxial layer.
  • the first epitaxial layer contains 25 atom% or more of germanium.
  • the third epitaxial layer preferably contains 30 atom% or more of germanium.
  • An epitaxial layer made of silicon germanium should have such a germanium concentration.
  • the third epitaxial layer should have such a concentration in order to apply compressive stress to the channel formation region.
  • the third epitaxial layer is preferably thicker than the first epitaxial layer, and the first epitaxial layer is preferably thicker than the second epitaxial layer.
  • the second epitaxial layer made of silicon only needs to have a film thickness that can absorb stacking faults and the like in the first epitaxial layer.
  • the film thicknesses of the first, second, and third epitaxial layers are preferably in the relationship as described above.
  • the first epitaxial layer preferably has a thickness of 10 nm or more. Thereby, it can be set as the silicon germanium layer which covers the bottom face of a recess.
  • the second epitaxial layer preferably has a film thickness of 5 nm or more and 20 nm or less.
  • a stacking fault or the like of the first epitaxial layer can be absorbed, and the second epitaxial layer having no crystal defect on the upper surface can be obtained. Thereby, it can function as a base for forming a defect-free third epitaxial layer.
  • the third epitaxial layer preferably has a film thickness equal to or less than the critical film thickness.
  • the third epitaxial layer can be realized as a silicon germanium layer without stacking faults, and compressive stress can be effectively applied to the channel forming region.
  • the third epitaxial layer is preferably formed so as to rise above the upper surface of the semiconductor substrate.
  • the substrate digging after the third epitaxial layer is formed can be prevented.
  • an N-channel transistor is further provided in addition to the P-channel transistor, and the N-channel transistor does not include a region made of silicon germanium.
  • CMOS complementary MOS
  • PMOS P-channel transistor
  • a manufacturing method of a semiconductor device includes a step (a) of forming a gate electrode on a semiconductor substrate via a gate insulating film in a manufacturing method of a semiconductor device including a P-channel transistor, and a gate A step (b) of forming a recess in the semiconductor substrate on each side of the electrode, a step (c) of forming a first epitaxial layer made of silicon germanium in the recess, and a first step made of silicon on the first epitaxial layer.
  • the semiconductor substrate of the present disclosure described above can be manufactured. That is, a compressive stress can be applied to the channel formation region by the third epitaxial layer made of SiGe in which stacking faults are suppressed, so that the channel portion mobility can be improved, and defects at the S / D junction interface are suppressed. Therefore, a semiconductor substrate in which leakage current is suppressed can be manufactured.
  • the interface between the second epitaxial layer and the third epitaxial layer is formed. It is preferable to obtain a P-type impurity profile in which the P-type impurity concentration varies from 0 / cm 3 to 1 ⁇ 10 18 / cm 3 in the range up to the junction depth of the source region or the drain region.
  • the first and second epitaxial layers do not contain P-type impurities, and a semiconductor device having a source region and a drain region in which P-type impurities are introduced into the third epitaxial layer can be obtained.
  • the third epitaxial layer preferably contains 30% or more germanium and has a film thickness equal to or less than the critical film thickness.
  • an extension region is formed by a step of forming an offset sidewall covering the side wall of the gate electrode and ion implantation using the gate electrode and the offset sidewall as a mask.
  • the method further includes a step and a step of covering the side wall of the offset sidewall and forming a sidewall having the same height as the gate electrode.
  • P-channel transistor further comprising offset sidewalls, sidewalls, extension regions, and the like.
  • an N-channel transistor is formed in addition to the P-channel transistor, and the N-channel transistor does not have a silicon germanium region.
  • MOS metal-insulator-semiconductor
  • stacking faults and the like in the first epitaxial layer made of silicon germanium are absorbed by the second epitaxial layer made of silicon and do not reach the third epitaxial layer.
  • the source region and the drain region are formed to be shallower than the depth of the third epitaxial layer so that there is no defect at the S / D junction interface.
  • compressive stress is effectively applied to the channel formation region to improve channel portion mobility, and leakage current due to defects at the S / D junction interface can be reduced.
  • FIG. 1 is a diagram illustrating a cross-section of the main part of an exemplary semiconductor device according to the first embodiment of the present disclosure.
  • 2 (a) to 2 (f) are diagrams for explaining a manufacturing process of the semiconductor device of FIG.
  • FIG. 3 is a diagram illustrating a cross-section of the main part of an exemplary semiconductor device according to the second embodiment of the present disclosure.
  • 4 (a) to 4 (e) are diagrams for explaining a manufacturing process of the semiconductor device of FIG. 5 (a) to 5 (d) are diagrams for explaining the manufacturing process of the semiconductor device of FIG. 3 following FIG. 4 (e).
  • FIG. 6 is a diagram illustrating an example of stacking faults in the silicon germanium layer embedded in the semiconductor substrate on the side of the gate electrode.
  • FIG. 7 is a diagram showing the film thickness dependence of lattice relaxation for a silicon germanium layer containing 30 atom% germanium.
  • FIG. 1 is a diagram schematically illustrating a cross-sectional structure of a PMOS transistor included in the exemplary semiconductor device 120 according to the first embodiment.
  • the semiconductor device 120 is formed using an N-type semiconductor substrate 100.
  • a gate electrode 102 made of polysilicon is formed on the semiconductor substrate 100 with a gate insulating film 101 made of SiO 2 interposed therebetween.
  • a metal silicide layer 121 is formed on the gate electrode 102.
  • An offset sidewall 104 made of SiO 2 or the like is formed so as to cover the side wall of the gate electrode 102.
  • extension regions 105 are formed in the semiconductor substrate 100 on both sides of the gate electrode 102.
  • a first sidewall 106 having an L-shaped cross section and made of SiO 2 is formed so as to cover the sidewall of the offset sidewall 104 and the extension region 105, and the first sidewall 106 is A second sidewall 107 made of SiN is formed.
  • the semiconductor substrate 100 is provided with a recess by etching or the like, and three epitaxial layers are laminated on the recess.
  • a first epitaxial layer 111 having a thickness of at least 10 nm is formed so as to cover the bottom surface of the recess.
  • This is made of silicon germanium (SiGe) having a germanium concentration of 25 atom% or more, and is not doped with a P-type impurity such as B.
  • a second epitaxial layer 112 having a thickness of 5 nm or more and 20 nm or less is formed. This is made of silicon not containing germanium, and is not doped with P-type impurities such as B.
  • a third epitaxial layer 113 having a thickness of about 50 nm is formed. This is made of silicon germanium having a germanium concentration of 30 atom% or more.
  • a P-type impurity such as B is doped to form S / D (source / drain) regions 122 sandwiching a channel formation region below the gate electrode 102 (on both sides of the gate electrode 102).
  • a source region is formed in one of the third epitaxial layers 113, and a drain region is formed in the other).
  • the interface between the second epitaxial layer 112 and the third epitaxial layer 113 contains no P-type impurities.
  • the concentration of the P-type impurity gradually increases from the interface toward the shallow side of the third epitaxial layer 113, and at the uppermost portion, for example, the concentration is about 1 ⁇ 10 23 / cm 3 .
  • a position where the impurity concentration is about 1 ⁇ 10 18 / cm 3 is defined as an S / D junction interface.
  • the S / D junction interface is above the interface between the second epitaxial layer 112 and the third epitaxial layer 113 and is located in the third epitaxial layer 113.
  • a metal silicide layer 121 is formed on the S / D region 122 and the gate electrode 102.
  • the compressive stress can be applied to the channel formation region by the epitaxial layer made of SiGe embedded in the recesses on both sides of the gate electrode 102, particularly the third epitaxial layer 113.
  • the generation of stacking faults and lattice relaxation is suppressed for the third epitaxial layer 113 for reasons described later. From this, it is possible to reliably apply a compressive stress to the channel formation region and improve the channel portion mobility.
  • the junction depth of the S / D region 122 (the depth of the S / D junction interface) is shallower than the depth of the third epitaxial layer 113, the S / D junction interface has a stacking fault that causes a leakage current. It is located in the area where there is no etc. Therefore, the leakage current is reduced.
  • FIG. 1 illustrates a profile of a P-type impurity introduced to configure the S / D region 122 in accordance with the structure of the semiconductor device 120.
  • the P-type impurity concentration is 0 at the interface depth D1 between the second epitaxial layer 112 and the third epitaxial layer 113.
  • the depth D2 of the S / D junction interface at which the P-type impurity concentration is about 1 ⁇ 10 18 / cm 3 is at a position shallower than D1.
  • the P-type impurity concentration further increases from the depth D2 toward the top of the third epitaxial layer 113.
  • the first epitaxial layer 111 is likely to have crystal defects such as stacking faults due to interface impurities (for example, oxygen) on the bottom surface of the recess (interface between the semiconductor substrate 100 and the first epitaxial layer 111).
  • the crystal defects can be absorbed by forming the second epitaxial layer 112 made of silicon on the first epitaxial layer 111. That is, even if there is a crystal defect in the first epitaxial layer 111, the upper surface of the second epitaxial layer 112 having a certain thickness is a surface having no defect. Therefore, the third epitaxial layer 113 formed on the second epitaxial layer 112 can avoid the influence of crystal defects in the first epitaxial layer 111.
  • the thickness of the third epitaxial layer 113 which is the main part sandwiching the channel formation region, can be suppressed, and the critical film thickness can be reduced. As a result, the occurrence of lattice relaxation in the third epitaxial layer is suppressed.
  • the critical film thickness is about 80 nm, and the third epitaxial layer 113 is thinner than this.
  • FIGS. 2A to 2F are cross-sectional views schematically showing the process.
  • a gate insulating film 101 made of, for example, SiO 2 is formed on the semiconductor substrate 100.
  • a polysilicon film and an SiO 2 film are sequentially stacked thereon, a mask (not shown) is formed, and the gate electrode 102 and the SiO 2 film 103 thereon are formed by etching.
  • an SiO 2 film is further formed to cover the semiconductor substrate 100, the side surface of the gate electrode 102 and the SiO 2 film 103, and etched back to form an offset sidewall 104 on the side wall of the gate electrode 102.
  • ion implantation is performed using the gate electrode 102, the offset sidewall 104, etc. as a mask, and extension regions 105 are formed near the surface of the semiconductor substrate 100 on both sides of the gate electrode 102.
  • the gate insulating film 101 may be formed of a high dielectric material such as HfSiO instead of SiO 2 . Further, the gate electrode 102 may have a laminated structure of a metal such as TiN and polysilicon instead of the single layer structure made of polysilicon.
  • a SiO 2 film is formed so as to cover the gate electrode 102 via the offset sidewall 104 and the SiO 2 film 103, and further a silicon nitride film is formed so as to cover the SiO 2 film.
  • dry etching is performed to form a first sidewall 106 having an L-shaped cross section covering the sidewall of the gate electrode 102 and the extension region 105, and a second sidewall 107 covering the top.
  • the epitaxial cover film 108 is formed so as to cover the semiconductor substrate 100, the second sidewall 107, the SiO 2 film 103, and the like.
  • Epitaxial cover film 108, the film density than the SiO 2 film 103 on the gate electrode 102 is low, to form a SiO 2 film can be formed, for example, by a low temperature of 400 ° C. or less.
  • FIG. 2D the process of FIG. 2D is performed.
  • a resist 109 having a gate electrode 102 and regions on both sides thereof is formed on the epitaxial cover film 108.
  • the epitaxial cover film 108 in the opening is removed using the resist 109 as a mask. As a result, the portion of the semiconductor substrate 100 in which the epitaxial layer made of SiGe is embedded is exposed.
  • the process of FIG. 2E is performed.
  • the epitaxial cover film 108 is used as a mask, and either or both of dry etching and wet etching are used to provide the semiconductor substrate 100 with a recess 110 having a depth of 60 nm or more, for example.
  • FIG. 2 (f) the process of FIG. 2 (f) is performed.
  • three epitaxial layers are sequentially formed in the recess 110.
  • a first epitaxial layer 111 made of SiGe containing germanium of 25 atom% or more is formed so as to cover the bottom of the recess. This is formed at a film thickness of 10 nm or more by epitaxial growth in a hydrogen atmosphere at 650 ° C. or lower. At this time, doping of P-type impurities such as B is not performed.
  • the first epitaxial layer 111 made of silicon germanium having a germanium concentration of 25 atom% can be formed.
  • a second epitaxial layer 112 made of silicon and not containing germanium is formed on the first epitaxial layer 111 continuously.
  • This film is formed to a thickness necessary for absorbing crystal defects generated in the first epitaxial layer 111 and preventing the crystal defects from appearing on the upper surface.
  • the film thickness is 5 nm or more and 20 nm or less.
  • Epitaxial growth is used for film formation, and P-type impurities such as B are not doped.
  • the temperature is 650 ° C.
  • a third epitaxial layer 113 made of SiGe containing germanium of 30 atm% or more is formed on the second epitaxial layer 112 further continuously. This is formed at least on both sides of the channel formation region below the gate electrode 102.
  • the occurrence of lattice relaxation is avoided by setting the critical film thickness or less.
  • the temperature is 650 ° C.
  • the hydrogen atmosphere (10 Torr (1.33 ⁇ 10 3 Pa)
  • the third epitaxial layer 113 is doped with a P-type impurity such as B.
  • the concentration profile of P-type impurities such as B is 0 immediately above the second epitaxial layer 112 and 1 ⁇ 10 18 / cm at the S / D junction interface depth set in the third epitaxial layer 113. 3 so that the concentration profile is about 1 ⁇ 10 23 / cm 3 at the top of the third epitaxial layer 113.
  • the S / D junction interface depth is set in a region having a depth of 30 nm to 50 nm from the upper surface of the semiconductor substrate 100.
  • Such a concentration profile can be realized by adjusting the flow rate of B 2 H 6 when the third epitaxial layer 113 is epitaxially grown.
  • B 2 H 6 is further used as a material gas.
  • the B 2 H 6 flow rate is set to 0, and the B 2 H 6 flow rate is increased as the film formation proceeds.
  • the flow rate of B 2 H 6 is adjusted to 100 sccm, and thereafter 160 sccm.
  • the third epitaxial layer 113 may be formed on the semiconductor substrate 100 so as to rise to a height of, for example, about 20 nm to 30 nm. In a later process, the buried epitaxial layer may be scraped, and the substrate may be dug next to the sidewall. Therefore, it is conceivable that the third epitaxial layer 113 is formed so as to rise above the semiconductor substrate 100 in advance so that the substrate is not dug even if the epitaxial layer is shaved.
  • the epitaxial cover film 108 and the SiO 2 film 103 on the gate electrode 102 are removed. Further, after forming a metal film (for example, NiPt having a thickness of 10 nm), a metal silicide layer 121 is formed on the gate electrode 102 and the S / D region 122 as shown in FIG.
  • a metal film for example, NiPt having a thickness of 10 nm
  • the exemplary semiconductor device 120 of this embodiment is manufactured. Its features and the like are as already described.
  • the germanium concentration of the first epitaxial layer 111 is 25 atom%
  • the germanium concentration of the third epitaxial layer 113 is 30 atom%.
  • the germanium concentration, the film thickness, and the like may be set in accordance with the size of the PMOS transistor to be formed, required performance, and the like. At this time, it is necessary that the thickness of the third epitaxial layer does not exceed the critical thickness.
  • FIG. 3 is a diagram illustrating an exemplary semiconductor device 130 according to the second embodiment.
  • the semiconductor device 130 is formed using the semiconductor substrate 100.
  • the surface of the semiconductor substrate 100 is partitioned by a shallow trench 114, and a PMOS transistor and a CMOS transistor are formed to constitute a CMOS transistor.
  • the PMOS transistor has the same structure as that described in the first embodiment. That is, three epitaxial layers are embedded in the semiconductor substrate 100 on both sides of the gate electrode 102 that is formed through the gate insulating film 101 and includes the offset sidewall 104, the first sidewall 106, and the second sidewall 107. In this structure, the S / D region 122 is provided in the third epitaxial layer 113.
  • the NMOS transistor does not include an epitaxial layer and has a structure having an S / D region 115 formed by doping the semiconductor substrate 100 with impurities.
  • the gate electrode 102, the sidewall, and the like have the same configuration as that of the PMOS transistor.
  • the S / D region 115 is formed by doping the semiconductor substrate 100 with an impurity without using an NMOS transistor having an epitaxial layer made of SiGe.
  • the gate electrode 102 is made of, for example, polysilicon, and is formed on the semiconductor substrate 100 via the gate insulating film 101 made of, for example, an SiO 2 film.
  • the gate insulating film 101 may be formed of a high dielectric such as HfSiO.
  • the gate electrode 102 may have a stacked structure of a metal such as TiN and polysilicon.
  • FIGS. 4A to 4E and FIGS. 5A to 5D are cross-sectional views schematically showing the process.
  • a shallow trench 114 is formed on the semiconductor substrate 100 by a conventional technique as an element isolation region that partitions a surface portion.
  • a gate electrode 102 is formed through a gate insulating film 101 in a region (hereinafter referred to as a PMOS region and an NMOS region) where a PMOS transistor and an NMOS transistor are formed in the semiconductor substrate 100, and an SiO 2 film is formed thereon.
  • 103 is formed.
  • an offset sidewall 104 that covers the side surface of the gate electrode 102 is formed.
  • extension regions 105 are formed in the semiconductor substrate 100 on both sides of the gate electrode 102 by ion implantation using the gate electrode 102, the offset sidewall 104, and the like as a mask. These are the same steps as described with reference to FIG. 2A in the first embodiment.
  • the process of FIG. 4B is performed.
  • the first sidewall 106 made of, for example, a SiO 2 film and having an L-shaped cross section is formed so as to cover the sidewall of the gate electrode 102 via the offset sidewall 104.
  • a second sidewall 107 made of a silicon nitride film is formed thereon. This is the same process as described in the first embodiment with reference to FIG.
  • an epitaxial cover film 108 is formed so as to cover the semiconductor substrate 100, the second sidewall 107, the SiO 2 film 103, and the like in both the PMOS region and the NMOS region.
  • This film density than the SiO 2 film 103 on the gate electrode 102 is low, to form a SiO 2 film can be formed, for example, by a low temperature of 400 ° C. or less.
  • a resist 131 is formed in which the sidewalls in the PMOS region, the gate electrode 102, and the regions where the S / D regions 122 on both sides are formed are opened. Further, using the resist 131 as a mask, the epitaxial cover film 108 at the opening is removed, and the PMOS region is exposed.
  • a recess 110 is formed in the semiconductor substrate 100 on both sides of the gate electrode 102 in the PMOS region using the epitaxial cover film 108 as a mask.
  • the epitaxial cover film 108 is used, and the depth is 60 nm.
  • Layer 113 is formed sequentially.
  • the first epitaxial layer 111 and the second epitaxial layer 112 are not doped with a P-type impurity such as B.
  • the third epitaxial layer 113 is doped with a P-type impurity such as B to form an S / D region 122.
  • the impurity concentration is 0 immediately above the second epitaxial layer 112, 1 ⁇ 10 18 / cm 3 at the S / D junction interface depth set in the third epitaxial layer 113, and 1 at the top of the third epitaxial layer 113.
  • the concentration profile is set to about ⁇ 10 23 / cm 3 .
  • the compressive stress is applied to the channel formation region below the gate electrode 102, and the third epitaxial layer 113 including the S / D region 122 having the S / D junction interface depth in the portion having no crystal defect, can do.
  • a resist 131 is formed so as to cover the PMOS region and open in the regions where the sidewalls in the NMOS region, the gate electrode 102, and the S / D regions 115 on both sides thereof are formed.
  • the portion of the epitaxial cover film 108 exposed in the opening of the resist 131 is removed, and ion implantation and annealing are performed using each sidewall, the gate electrode 102, and the like as a mask.
  • the S / D region 115 is formed outside the extension region 125 in the semiconductor substrate 100 in the NMOS region.
  • the annealing condition is, for example, spike annealing at 1025 ° C.
  • the process of FIG. 5B is performed.
  • the resist 132 is removed, and the SiO 2 film 103 on the epitaxial cover film 108 and the gate electrode 102 is further removed.
  • the metal film 116 is formed so as to cover the third epitaxial layer 113 in which the S / D region 122 is formed, the gate electrode 102 and the semiconductor substrate 100 in which the S / D region 115 is formed.
  • This is, for example, a 10 nm thick NiPt film.
  • FIG. 5D the process of FIG. 5D is performed.
  • heat treatment is performed to form the metal silicide layer 121 on the gate electrode 102, the S / D region 122, and the S / D region 115.
  • the semiconductor device 130 having the CMOS transistor is manufactured. Its features and the like are as already described.
  • MOS transistors have been described as examples. However, the present invention is not limited to MOS transistors, and can be applied to MIS transistors.
  • the technology of the present disclosure is a PMOS transistor that uses a silicon germanium layer as a source / drain region, can improve channel portion mobility and reduce leakage current, and can achieve a fine MIS transistor with a gate width of, for example, 40 nm or less. It is also useful as a semiconductor device having the same and a manufacturing method thereof.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Disclosed is a semiconductor device (120) provided with a P-channel transistor that includes source and drain regions (122), which are formed on surface portions of a semiconductor substrate (100), and a gate electrode (102), which is formed on a channel-forming region sandwiched between the source and drain regions by having a gate insulating film (101) between the channel-forming region and the gate electrode. On both the sides of the gate electrode (102), recesses are formed in the semiconductor substrate (100), and the recesses are respectively provided with: first epitaxial layers (111) composed of SiGe; second epitaxial layers (112), which are formed on the first epitaxial layers and are composed of Si; and third epitaxial layers (113), which are formed on the second epitaxial layers, are composed of SiGe, and sandwich the channel forming region. The source and the drain regions (122) are formed in the third epitaxial layers (113), respectively, and the junction depth in each region is less than the depth of the third epitaxial layer (133).

Description

半導体装置とその製造方法Semiconductor device and manufacturing method thereof
　本開示は、半導体装置及びその製造方法に関し、特に、ＳｉＧｅエピタキシャル膜をソース・ドレイン領域に備えたＰチャネル型トランジスタを有する半導体装置及びその製造方法に関するものである。 The present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a P-channel transistor having a SiGe epitaxial film in a source / drain region and a manufacturing method thereof.
　近年の半導体装置における大容量化は著しい。ＭＯＳ（Metal Oxide Semiconductor ）トランジスタの微細化も進展し、ゲート電極の幅が４０ｎｍ以下になろうとしている。また、高速化に対応して、トランジスタのチャネル形成領域（基板におけるチャネルが形成される領域）にストレスを印加することにより駆動力を上げる歪技術も既に実用化されている。 The recent increase in capacity of semiconductor devices is remarkable. With the progress of miniaturization of MOS (Metal-Oxide-Semiconductor) transistors, the width of the gate electrode is about to be 40 nm or less. In addition, a distortion technique for increasing driving force by applying stress to a channel formation region of a transistor (a region where a channel is formed in a substrate) of a transistor has already been put into practical use in response to the increase in speed.
　歪技術によると、トランジスタのチャネル形成領域に歪を導入することにより、チャネル形成領域のバンド構造が変化する。その結果、チャネル形成領域におけるキャリアの有効質量が変化してバンド占有率の変化等が起こり、チャネル部移動度が変化する。 According to the strain technology, by introducing strain into the channel formation region of the transistor, the band structure of the channel formation region changes. As a result, the effective mass of carriers in the channel formation region changes, causing a change in band occupancy, and the channel portion mobility changes.
　チャネル形成領域に歪を入れるには、チャネル形成領域に応力（ストレス）を印加する必要がある。印加するべき応力の方向は、ＮＭＯＳ（n-channel ＭＯＳ）とＰＭＯＳ（p-channel ＭＯＳ）とでは異なる。具体的に、チャネル方向に一軸で応力を印加する場合、ＮＭＯＳでは引張り応力、ＰＭＯＳでは圧縮応力を印加する必要があることが知られている。 To apply strain to the channel formation region, it is necessary to apply stress to the channel formation region. The direction of the stress to be applied differs between NMOS (n-channel MOS) and PMOS (p-channel MOS). Specifically, it is known that when uniaxial stress is applied in the channel direction, it is necessary to apply tensile stress in NMOS and compressive stress in PMOS.
　このうち、ＰＭＯＳトランジスタにおけるキャリアの移動度を劇的に上げる歪技術として、基板におけるチャネル形成領域（ゲート電極下方）の両側のソースドレイン（Ｓ／Ｄ）領域に埋め込むように、シリコンよりも大きい格子定数を持つシリコンゲルマニウム膜をエピタキシャル成長により成膜する方法が提案されている（非特許文献１）。 Among these, as a distortion technique for dramatically increasing the carrier mobility in the PMOS transistor, a lattice larger than silicon so as to be embedded in the source / drain (S / D) regions on both sides of the channel formation region (below the gate electrode) in the substrate. A method of forming a silicon germanium film having a constant by epitaxial growth has been proposed (Non-Patent Document 1).
　この方法によると、ゲート電極下方のチャネル形成領域に対し、側方から、格子定数差に起因する圧縮応力を印加することができる。チャネル形成領域に印加される圧縮応力は、シリコンゲルマニウムに含まれるゲルマニウム濃度が高いほど大きくなる。 According to this method, a compressive stress caused by a lattice constant difference can be applied from the side to the channel formation region below the gate electrode. The compressive stress applied to the channel formation region increases as the concentration of germanium contained in silicon germanium increases.
　しかしながら、以上に説明した構造のＭＯＳトランジスタにおいて、予想されたほどにはチャネル部移動度が上がらず、トランジスタの駆動力も上がらない例が見られる。更に、リーク電流が増加する傾向もある。そこで、これらの点の解決が課題となる。 However, in the MOS transistor having the structure described above, there is an example in which the channel mobility does not increase as expected and the driving power of the transistor does not increase. Furthermore, there is a tendency that the leakage current increases. Therefore, the solution of these points becomes a problem.
　以上に鑑み、ＳｉＧｅエピタキシャル層を用いてチャネル形成領域に圧縮応力を印加する構成のトランジスタにおいて、チャネル部移動度の向上をより確実にすること、リーク電流を抑制することができる半導体装置及びその製造方法を提供することについて以下に説明する。 In view of the above, in a transistor having a structure in which compressive stress is applied to a channel formation region using a SiGe epitaxial layer, a semiconductor device capable of further improving channel portion mobility and suppressing leakage current and its manufacture Providing a method is described below.
　本願発明者らは、前記のように予想に比べてチャネル部移動度が向上しない理由及びリーク電流が増加する理由について検討した。これを以下に説明する。 The inventors of the present application examined the reason why the channel portion mobility is not improved as compared with the expectation and the reason why the leakage current increases. This will be described below.
　図６に、半導体基板１０上にサイドウォール１３を伴うゲート電極１２が形成され、ゲート電極１２側方のＳ／Ｄ領域の部分にはエピタキシャル成長によるシリコンゲルマニウム（ＳｉＧｅ）膜１１が埋め込まれた構造を示す。 FIG. 6 shows a structure in which a gate electrode 12 with a sidewall 13 is formed on a semiconductor substrate 10 and a silicon germanium (SiGe) film 11 is buried in an S / D region on the side of the gate electrode 12 by epitaxial growth. Show.
　Ｓｉ基板（半導体基板１０）上にＳｉＧｅ結晶をエピタキシャル成長させるとき、歪エネルギーの増大に伴う結晶欠陥１４が発生する（非特許文献２）。このような結晶欠陥の発生無しに成長できるＳｉＧｅエピタキシャル膜厚は臨界膜厚と呼ばれる。臨界膜厚は、Ｇｅ濃度が高いほど薄くなる。具体例として、Ｇｅ濃度が３０atom％程度のＳｉＧｅ層について、図７に膜厚と格子緩和（relaxation）の関係を示す。格子緩和は結晶欠陥が生じると大きくなるので、膜厚が８０ｎｍ程度を越えると急に格子緩和が大きくなることから、臨界膜厚が８０ｎｍ程度であると分かる。 When a SiGe crystal is epitaxially grown on a Si substrate (semiconductor substrate 10), a crystal defect 14 accompanying an increase in strain energy occurs (Non-patent Document 2). The SiGe epitaxial film thickness that can be grown without the occurrence of such crystal defects is called the critical film thickness. The critical film thickness decreases as the Ge concentration increases. As a specific example, FIG. 7 shows the relationship between film thickness and lattice relaxation for a SiGe layer having a Ge concentration of about 30 atom%. Since the lattice relaxation becomes large when crystal defects occur, the lattice relaxation suddenly increases when the film thickness exceeds about 80 nm, and it can be understood that the critical film thickness is about 80 nm.
　また、Ｓｉ上に形成したＳｉＧｅ結晶による圧縮応力を有効にチャネル形成領域へ印加するためには、ＰチャネルのＳ／Ｄ領域となる部分に、エッチングにより少なくともチャネル形成領域側方を含む深さのリセスを形成し、該リセスにＳｉＧｅエピタキシャル層を形成する。また、後工程によるサイドウォール横の基板掘れ等を防ぐために、ＳｉＧｅエピタキシャル層を基板上にある程度の高さを有するように形成する。この結果、リセス部と基板上の部分とを合わせると、成長させるＳｉＧｅエピタキシャル層の膜厚は、８０ｎｍ以上になる可能性がある。 Further, in order to effectively apply the compressive stress due to the SiGe crystal formed on Si to the channel formation region, the portion that becomes the S / D region of the P channel has a depth that includes at least the side of the channel formation region by etching. A recess is formed, and a SiGe epitaxial layer is formed in the recess. Further, in order to prevent a substrate digging beside the side wall in the subsequent process, the SiGe epitaxial layer is formed on the substrate so as to have a certain height. As a result, when the recess portion and the portion on the substrate are combined, the thickness of the SiGe epitaxial layer to be grown may be 80 nm or more.
　前記の通り、Ｇｅ濃度が３０atom％以上で且つ膜厚が８０ｎｍになると、ＳｉＧｅ層に結晶欠陥が発生して応力が緩和する。この結果、チャネル形成領域に有効に圧縮応力を印加できなくなるという問題が発生する。 As described above, when the Ge concentration is 30 atom% or more and the film thickness is 80 nm, crystal defects are generated in the SiGe layer and the stress is relaxed. As a result, there arises a problem that compressive stress cannot be effectively applied to the channel formation region.
　また、リセス底面のＳｉＧｅとＳｉとの界面には、エピタキシャル成長前の洗浄、エピタキシャル成長中のＨ２　ベーク等では除去しきれないＯ（酸素）等の界面不純物がある。このような界面不純物は、ＳｉＧｅエピタキシャル層に積層欠陥１４を発生させる原因となる（図６を参照）。ここでの積層欠陥１４はＳｉＧｅ結晶層中を貫くので、ＳｉＧｅ結晶中に形成されるＳ／Ｄ接合界面についても貫き、接合リークの原因になる。 Further, at the interface between SiGe and Si on the bottom surface of the recess, there are interface impurities such as O (oxygen) that cannot be removed by cleaning before epitaxial growth, H 2 bake during epitaxial growth, or the like. Such interface impurities cause a stacking fault 14 in the SiGe epitaxial layer (see FIG. 6). Since the stacking fault 14 here penetrates the SiGe crystal layer, it also penetrates the S / D junction interface formed in the SiGe crystal, causing junction leakage.
　以上の検討結果から、本願発明者らは、チャネル形成領域を両側から挟む部分に積層欠陥等の無いＳｉＧｅエピタキシャル層を形成して応力の印加を確実にすることを着想した。更に、Ｓ／Ｄ接合界面を結晶欠陥の無い部分に位置させることにより、リーク電流を抑制することを着想した。 From the above examination results, the inventors of the present application have conceived that a SiGe epitaxial layer having no stacking fault or the like is formed in a portion sandwiching the channel formation region from both sides to ensure the application of stress. Furthermore, the inventors conceived of suppressing the leakage current by positioning the S / D junction interface in a portion free from crystal defects.
　具体的に、本開示に係る半導体装置は、半導体基板の表面部に形成されたソース領域及びドレイン領域と、これらに挟まれたチャネル形成領域上にゲート絶縁膜を介して形成されたゲート電極とを含むＰチャネル型トランジスタを備え、ゲート電極の両側それぞれにおいて半導体基板にリセスが形成され、リセスに、シリコンゲルマニウムからなる第１エピタキシャル層と、その上に形成され且つシリコンからなる第２エピタキシャル層と、その上に形成され且つシリコンゲルマニウムからなり、チャネル形成領域を挟む第３エピタキシャル層とを備え、ソース領域及びドレイン領域は、第３エピタキシャル層中に形成され、且つ、それぞれの接合深さがいずれも第３エピタキシャル層の深さよりも浅い。 Specifically, a semiconductor device according to the present disclosure includes a source region and a drain region formed on a surface portion of a semiconductor substrate, and a gate electrode formed on a channel formation region sandwiched between these via a gate insulating film. A recess formed in the semiconductor substrate on each side of the gate electrode, and a recess formed in the first epitaxial layer made of silicon germanium, and a second epitaxial layer made of silicon and formed thereon And a third epitaxial layer made of silicon germanium and sandwiching the channel formation region. The source region and the drain region are formed in the third epitaxial layer, and each junction depth is Is shallower than the depth of the third epitaxial layer.
　このような半導体装置によると、ゲート電極両側のリセスに形成されたエピタキシャル層、特に、シリコンゲルマニウム（ＳｉＧｅ）からなり且つチャネル形成領域を挟んでいる第３エピタキシャル層により、チャネル形成領域に対して圧縮応力を印加することができる。 According to such a semiconductor device, the channel formation region is compressed by the epitaxial layer formed in the recesses on both sides of the gate electrode, particularly the third epitaxial layer made of silicon germanium (SiGe) and sandwiching the channel formation region. Stress can be applied.
　この際、第３エピタキシャル層については、後述の理由により、積層欠陥及び格子緩和の発生が抑制されている。よって、チャネル形成領域に対して確実に圧縮応力を印加することができ、チャネル部移動度を向上することができる。また、ソース領域及びドレイン領域の接合深さが第３エピタキシャル層の深さよりも浅いことから、Ｓ／Ｄ接合界面には、リーク電流の原因となる結晶欠陥が無いようにすることができる。この結果、リーク電流を低減することができる。 At this time, with respect to the third epitaxial layer, generation of stacking faults and lattice relaxation is suppressed for the reason described later. Therefore, a compressive stress can be reliably applied to the channel formation region, and the channel portion mobility can be improved. Further, since the junction depth of the source region and the drain region is shallower than the depth of the third epitaxial layer, the S / D junction interface can be made free of crystal defects that cause a leakage current. As a result, leakage current can be reduced.
　第３エピタキシャル層において積層欠陥及び格子緩和の発生が抑制されている理由は、次の通りである。 The reason why the generation of stacking faults and lattice relaxation is suppressed in the third epitaxial layer is as follows.
　まず、第１エピタキシャル層には、例えばリセスの底面（半導体基板と第１エピタキシャル層との界面）におけるＯ等の界面不純物に起因して、積層欠陥等の結晶欠陥が生じやすい。しかしながら、第１エピタキシャル層上にシリコンからなる第２エピタキシャル層を形成することにより、第２エピタキシャル層中において前記の結晶欠陥を吸収し、第２エピタキシャル層の上面には結晶欠陥が存在しないようにすることができる。よって、第２エピタキシャル層上に形成される第３エピタキシャル層については、結晶欠陥の発生を抑制することができる。 First, in the first epitaxial layer, crystal defects such as stacking faults are likely to occur due to interface impurities such as O on the bottom surface of the recess (interface between the semiconductor substrate and the first epitaxial layer). However, by forming the second epitaxial layer made of silicon on the first epitaxial layer, the crystal defects are absorbed in the second epitaxial layer so that no crystal defects exist on the upper surface of the second epitaxial layer. can do. Therefore, generation of crystal defects can be suppressed for the third epitaxial layer formed on the second epitaxial layer.
　また、リセス内に３層のエピタキシャル層を設けることにより、チャネル形成領域を挟む主要な部分である第３エピタキシャル層の厚さを抑制し、臨界膜厚以下にすることができる。よって、第３エピタキシャル層における格子緩和の発生は抑制されている。 Also, by providing three epitaxial layers in the recess, the thickness of the third epitaxial layer, which is the main part sandwiching the channel formation region, can be suppressed, and the critical film thickness can be reduced. Therefore, the occurrence of lattice relaxation in the third epitaxial layer is suppressed.
　尚、ソース領域及びドレイン領域は、Ｐ型不純物が導入されることにより形成され、第１エピタキシャル層及び第２エピタキシャル層には、前記Ｐ型不純物が導入されていないことが好ましい。また、第３エピタキシャル層には、少なくともＰ型不純物濃度１×１０１８／ｃｍ３　以上である層が含まれていることが好ましい。 The source region and the drain region are preferably formed by introducing a P-type impurity, and the P-type impurity is preferably not introduced into the first epitaxial layer and the second epitaxial layer. The third epitaxial layer preferably includes a layer having a P-type impurity concentration of 1 × 10 18 / cm 3 or more.
　このようにすると、ソース領域及びドレイン領域の接合深さを確実に第３エピタキシャル層の深さよりも浅くすることができる。 In this way, the junction depth of the source region and the drain region can be surely made smaller than the depth of the third epitaxial layer.
　また、第３エピタキシャル層は、第２エピタキシャル層と第３エピタキシャル層との界面から、ソース領域又はドレイン領域の接合深さまでの範囲において、Ｐ型不純物濃度が０／ｃｍ３　から１×１０１８／ｃｍ３　にまで変化するＰ型不純物プロファイルを有することが好ましい。 The third epitaxial layer from the interface between the second epitaxial layer and the third epitaxial layer, in a range up to the junction depth of the source region or the drain region, a P-type impurity concentration 0 / cm 3 from 1 × 10 18 / It is preferable to have a P-type impurity profile that varies to cm 3 .
　ソース領域又はドレイン領域のＳ／Ｄ接合界面は、これらの領域を形成するための不純物濃度が１×１０１８／ｃｍ３　程度である面となる。そこで、該濃度となる位置を、第３エピタキシャル層の下面よりも浅い位置とすることにより、ソース領域及びドレイン領域を確実に第３エピタキシャル層内に配置することができる。 The S / D junction interface of the source region or the drain region is a surface having an impurity concentration of about 1 × 10 18 / cm 3 for forming these regions. Therefore, the source region and the drain region can be reliably arranged in the third epitaxial layer by setting the position where the concentration is to be shallower than the lower surface of the third epitaxial layer.
　また、第１エピタキシャル層は、２５atom％以上のゲルマニウムを含むことが好ましい。また、第３エピタキシャル層は、３０atom％以上のゲルマニウムを含むことが好ましい。 Moreover, it is preferable that the first epitaxial layer contains 25 atom% or more of germanium. The third epitaxial layer preferably contains 30 atom% or more of germanium.
　シリコンゲルマニウムからなるエピタキシャル層については、このようなゲルマニウム濃度とするのがよい。特に第３エピタキシャル層についてはチャネル形成領域に対する圧縮応力印加のために、このような濃度にするのがよい。 An epitaxial layer made of silicon germanium should have such a germanium concentration. In particular, the third epitaxial layer should have such a concentration in order to apply compressive stress to the channel formation region.
　また、第３エピタキシャル層は、第１エピタキシャル層よりも厚く、第１エピタキシャル層は、第２エピタキシャル層よりも厚いことが好ましい。 The third epitaxial layer is preferably thicker than the first epitaxial layer, and the first epitaxial layer is preferably thicker than the second epitaxial layer.
　チャネル形成領域に応力を印加するのは主に第３エピタキシャル層であるから、この層を厚くする必要がある。また、シリコンからなる第２エピタキシャル層については、第１エピタキシャル層における積層欠陥等を吸収することができるだけの膜厚が有れば良い。これらのことから、第１、第２及び第３のエピタキシャル層の膜厚について、前記のような関係になっているのがよい。 Since it is mainly the third epitaxial layer that applies stress to the channel formation region, it is necessary to increase the thickness of this layer. Further, the second epitaxial layer made of silicon only needs to have a film thickness that can absorb stacking faults and the like in the first epitaxial layer. For these reasons, the film thicknesses of the first, second, and third epitaxial layers are preferably in the relationship as described above.
　また、第１エピタキシャル層は、１０ｎｍ以上の膜厚を有することが好ましい。これにより、リセスの底面を覆うシリコンゲルマニウム層とすることができる。 The first epitaxial layer preferably has a thickness of 10 nm or more. Thereby, it can be set as the silicon germanium layer which covers the bottom face of a recess.
　また、第２エピタキシャル層は、５ｎｍ以上で且つ２０ｎｍ以下の膜厚を有することが好ましい。 The second epitaxial layer preferably has a film thickness of 5 nm or more and 20 nm or less.
　このような膜厚であれば、第１エピタキシャル層の積層欠陥等を吸収し、上面には結晶欠陥のない第２エピタキシャル層とすることができる。これにより、欠陥のない第３エピタキシャル層を形成するための下地として機能することができる。 With such a film thickness, a stacking fault or the like of the first epitaxial layer can be absorbed, and the second epitaxial layer having no crystal defect on the upper surface can be obtained. Thereby, it can function as a base for forming a defect-free third epitaxial layer.
　また、第３エピタキシャル層は、臨界膜厚以下の膜厚を有することが好ましい。 Further, the third epitaxial layer preferably has a film thickness equal to or less than the critical film thickness.
　これにより、第３エピタキシャル層を積層欠陥等のないシリコンゲルマニウム層として実現し、チャネル形成領域に効果的に圧縮応力を印加することができる。 Thereby, the third epitaxial layer can be realized as a silicon germanium layer without stacking faults, and compressive stress can be effectively applied to the channel forming region.
　第３エピタキシャル層は、半導体基板上面よりも上にも盛上がって形成されていることが好ましい。 The third epitaxial layer is preferably formed so as to rise above the upper surface of the semiconductor substrate.
　これにより、第３エピタキシャル層を形成した後の基板掘れを防ぐことができる。 Thereby, the substrate digging after the third epitaxial layer is formed can be prevented.
　また、Ｐチャネル型トランジスタに加えてＮチャネル型トランジスタを更に備え、Ｎチャネル型トランジスタは、シリコンゲルマニウムからなる領域を備えないことが好ましい。 Further, it is preferable that an N-channel transistor is further provided in addition to the P-channel transistor, and the N-channel transistor does not include a region made of silicon germanium.
　つまり、以上に説明した構成のＰチャネル型トランジスタ（ＰＭＯＳ）と共にＮチャネル型トランジスタ（ＮＭＯＳ）を備えるＣＭＯＳ（complementary ＭＯＳ）であることが好ましい。また、ＮＭＯＳについては、チャネル形成領域に圧縮応力を印加してもチャネル部移動度は向上せず、むしろ低下する。そこで、ＮＭＯＳについては、シリコンゲルマニウムからなる領域を設けない方が良い。 That is, a CMOS (complementary MOS) including an N-channel transistor (NMOS) together with a P-channel transistor (PMOS) having the configuration described above is preferable. In addition, for NMOS, even if compressive stress is applied to the channel formation region, the channel portion mobility does not improve, but rather decreases. Therefore, for NMOS, it is better not to provide a region made of silicon germanium.
　次に、本開示に係る半導体装置の製造方法は、Ｐチャネル型トランジスタを備える半導体装置の製造方法において、半導体基板上に、ゲート絶縁膜を介してゲート電極を形成する工程（ａ）と、ゲート電極の両側それぞれにおいて、半導体基板にリセスを形成する工程（ｂ）と、リセス内にシリコンゲルマニウムからなる第１エピタキシャル層を形成する工程（ｃ）と、第１エピタキシャル層上に、シリコンからなる第２エピタキシャル層を形成する工程（ｄ）と、第２エピタキシャル層上に、ゲート電極下方のチャネル形成領域を挟むように、シリコンゲルマニウムからなる第３エピタキシャル層を形成する工程（ｅ）とを備え、Ｐ型不純物の導入量を調整しながら工程（ｅ）を行なうことにより、第３エピタキシャル層中に、接合深さが第３エピタキシャル層の深さよりも浅いソース領域及びドレイン領域を形成する。 Next, a manufacturing method of a semiconductor device according to the present disclosure includes a step (a) of forming a gate electrode on a semiconductor substrate via a gate insulating film in a manufacturing method of a semiconductor device including a P-channel transistor, and a gate A step (b) of forming a recess in the semiconductor substrate on each side of the electrode, a step (c) of forming a first epitaxial layer made of silicon germanium in the recess, and a first step made of silicon on the first epitaxial layer. A step (d) of forming two epitaxial layers, and a step (e) of forming a third epitaxial layer made of silicon germanium on the second epitaxial layer so as to sandwich a channel formation region below the gate electrode, By performing step (e) while adjusting the amount of P-type impurity introduced, the junction depth is increased in the third epitaxial layer. Forming a shallow source region and a drain region than the depth of the third epitaxial layer.
　このようにすると、既に説明した本開示の半導体基板を製造することができる。つまり、積層欠陥等の抑制されたＳｉＧｅからなる第３エピタキシャル層によりチャネル形成領域に圧縮応力を印加し、チャネル部移動度を向上することができ、且つ、Ｓ／Ｄ接合界面の欠陥が抑制されていることからリーク電流の抑制された半導体基板を製造することができる。 In this way, the semiconductor substrate of the present disclosure described above can be manufactured. That is, a compressive stress can be applied to the channel formation region by the third epitaxial layer made of SiGe in which stacking faults are suppressed, so that the channel portion mobility can be improved, and defects at the S / D junction interface are suppressed. Therefore, a semiconductor substrate in which leakage current is suppressed can be manufactured.
　尚、工程（ｃ）及び工程（ｄ）は、Ｐ型不純物を含ませることなくエピタキシャル成長により行なうことが好ましい。 In addition, it is preferable to perform a process (c) and a process (d) by epitaxial growth, without including a P-type impurity.
　また、工程（ｅ）において、第３エピタキシャル層の成長に合わせてＰ型不純物の導入量を増加しながら第３エピタキシャル層を形成することにより、第２エピタキシャル層と第３エピタキシャル層との界面から、ソース領域又はドレイン領域の接合深さまでの範囲において、Ｐ型不純物濃度が０／ｃｍ３　から１×１０１８／ｃｍ３　にまで変化するＰ型不純物プロファイルを得ることが好ましい。 Further, in the step (e), by forming the third epitaxial layer while increasing the introduction amount of the P-type impurity in accordance with the growth of the third epitaxial layer, the interface between the second epitaxial layer and the third epitaxial layer is formed. It is preferable to obtain a P-type impurity profile in which the P-type impurity concentration varies from 0 / cm 3 to 1 × 10 18 / cm 3 in the range up to the junction depth of the source region or the drain region.
　このようにすると、第１及び第２エピタキシャル層についてはＰ型不純物を含まず、また、第３エピタキシャル層内にＰ型不純物が導入されたソース領域及びドレイン領域を有する半導体装置とすることができる。 In this case, the first and second epitaxial layers do not contain P-type impurities, and a semiconductor device having a source region and a drain region in which P-type impurities are introduced into the third epitaxial layer can be obtained. .
　また、第３エピタキシャル層は、３０％以上のゲルマニウムを含み且つ臨界膜厚以下の膜厚を有することが好ましい。 The third epitaxial layer preferably contains 30% or more germanium and has a film thickness equal to or less than the critical film thickness.
　これにより、Ｇｅ濃度が比較的高く且つ格子緩和がないことから、チャネル形成領域に確実に圧縮応力を印加できる第３のエピタキシャル層とすることができる。 Thereby, since the Ge concentration is relatively high and there is no lattice relaxation, a third epitaxial layer that can reliably apply compressive stress to the channel formation region can be obtained.
　また、工程（ｅ）の後に、第３エピタキシャル層上に金属膜を形成すると共に熱処理を行なって金属シリサイドを形成する工程を更に備えることが好ましい。 Moreover, it is preferable to further include a step of forming a metal silicide on the third epitaxial layer and performing a heat treatment after the step (e) to form a metal silicide.
　このようにすると、金属シリサイド層を有する半導体装置を製造することができる。 In this way, a semiconductor device having a metal silicide layer can be manufactured.
　また、工程（ａ）の後、工程（ｂ）の前に、ゲート電極の側壁を覆うオフセットサイドウォールを形成する工程と、ゲート電極及びオフセットサイドウォールをマスクとするイオン注入によりエクステンション領域を形成する工程と、オフセットサイドウォールの側壁を覆い且つゲート電極と同じ高さのサイドウォールを形成する工程とを更に備えることが好ましい。 Further, after step (a) and before step (b), an extension region is formed by a step of forming an offset sidewall covering the side wall of the gate electrode and ion implantation using the gate electrode and the offset sidewall as a mask. Preferably, the method further includes a step and a step of covering the side wall of the offset sidewall and forming a sidewall having the same height as the gate electrode.
　オフセットサイドウォール、サイドウォール、エクステンション領域等を更に備えるＰチャネル型トランジスタを形成するために、このようにしてもよい。 This may be done in order to form a P-channel transistor further comprising offset sidewalls, sidewalls, extension regions, and the like.
　また、Ｐチャネル型トランジスタに加えてＮチャネル型トランジスタを形成し、Ｎチャネル型トランジスタは、シリコンゲルマニウム領域を備えない構成であることが好ましい。 Further, it is preferable that an N-channel transistor is formed in addition to the P-channel transistor, and the N-channel transistor does not have a silicon germanium region.
　これにより、チャネル形成領域に圧縮応力を印加しないＮチャネル型トランジスタを更に備えるＰＭＯＳを実現することができる。 Thereby, it is possible to realize a PMOS that further includes an N-channel transistor that does not apply compressive stress to the channel formation region.
　尚、以上ではＭＯＳトランジスタとして説明しているが、ＭＩＳ（metal-insulator-semiconductor ）トランジスタに適用することも可能である。 In addition, although it demonstrated as a MOS transistor above, it is also possible to apply to a MIS (metal-insulator-semiconductor) transistor.
　本開示の半導体装置によると、シリコンゲルマニウムからなる第１エピタキシャル層における積層欠陥等をシリコンからなる第２エピタキシャル層により吸収し、第３エピタキシャル層には及ばないようにしている。更に、ソース領域及びドレイン領域について、第３エピタキシャル層の深さよりも浅く形成し、Ｓ／Ｄ接合界面には欠陥がないようになっている。これにより、チャネル形成領域に効果的に圧縮応力を印加してチャネル部移動度を向上すると共に、Ｓ／Ｄ接合界面における欠陥に起因するリーク電流を低減することができる。 According to the semiconductor device of the present disclosure, stacking faults and the like in the first epitaxial layer made of silicon germanium are absorbed by the second epitaxial layer made of silicon and do not reach the third epitaxial layer. Furthermore, the source region and the drain region are formed to be shallower than the depth of the third epitaxial layer so that there is no defect at the S / D junction interface. As a result, compressive stress is effectively applied to the channel formation region to improve channel portion mobility, and leakage current due to defects at the S / D junction interface can be reduced.
図１は、本開示の第１の実施形態における例示的半導体装置の要部断面を説明する図である。FIG. 1 is a diagram illustrating a cross-section of the main part of an exemplary semiconductor device according to the first embodiment of the present disclosure. 図２（ａ）～（ｆ）は、図１の半導体装置の製造工程を説明する図である。2 (a) to 2 (f) are diagrams for explaining a manufacturing process of the semiconductor device of FIG. 図３は、本開示の第２の実施形態における例示的半導体装置の要部断面を説明する図である。FIG. 3 is a diagram illustrating a cross-section of the main part of an exemplary semiconductor device according to the second embodiment of the present disclosure. 図４（ａ）～（ｅ）は、図３の半導体装置の製造工程を説明する図である。4 (a) to 4 (e) are diagrams for explaining a manufacturing process of the semiconductor device of FIG. 図５（ａ）～（ｄ）は、図４（ｅ）に続いて、図３の半導体装置の製造工程を説明する図である。5 (a) to 5 (d) are diagrams for explaining the manufacturing process of the semiconductor device of FIG. 3 following FIG. 4 (e). 図６は、ゲート電極の側方において半導体基板に埋め込まれたシリコンゲルマニウム層について、積層欠陥の例を示す図である。FIG. 6 is a diagram illustrating an example of stacking faults in the silicon germanium layer embedded in the semiconductor substrate on the side of the gate electrode. 図７は、３０atom％のゲルマニウムを含むシリコンゲルマニウム層について、格子緩和の膜厚依存性を示す図である。FIG. 7 is a diagram showing the film thickness dependence of lattice relaxation for a silicon germanium layer containing 30 atom% germanium.
　以下、本開示の実施形態について、図面を参照しながら説明する。尚、各構成要素の材料及び寸法、各種処理の条件等はいずれも例示するものであり、記載内容には限定されない。 Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be noted that the materials and dimensions of each component, the conditions for various treatments, etc. are only examples, and are not limited to the description.
　　（第１の実施形態）
　図１は、第１の実施形態における例示的半導体装置１２０が備えるＰＭＯＳトランジスタの断面構造を模式的に示す図である。 (First embodiment)
FIG. 1 is a diagram schematically illustrating a cross-sectional structure of a PMOS transistor included in the exemplary semiconductor device 120 according to the first embodiment.
　図１に示す通り、半導体装置１２０は、Ｎ型の半導体基板１００を用いて形成されている。半導体基板１００上に、ＳｉＯ２　からなるゲート絶縁膜１０１を介し、ポリシリコンからなるゲート電極１０２が形成されている。ゲート電極１０２上には、金属シリサイド層１２１が形成されている。 As shown in FIG. 1, the semiconductor device 120 is formed using an N-type semiconductor substrate 100. A gate electrode 102 made of polysilicon is formed on the semiconductor substrate 100 with a gate insulating film 101 made of SiO 2 interposed therebetween. A metal silicide layer 121 is formed on the gate electrode 102.
　ゲート電極１０２の側壁を覆うように、ＳｉＯ２　等からなるオフセットサイドウォール１０４が形成されている。また、ゲート電極１０２の両側において、半導体基板１００にエクステンション領域１０５が形成されている。更に、オフセットサイドウォール１０４の側壁及びエクステンション領域１０５上を覆うように、Ｌ字型の断面を有し且つＳｉＯ２　からなる第１のサイドウォール１０６が形成されると共に、第１のサイドウォール１０６を覆い且つＳｉＮからなる第２のサイドウォール１０７が形成されている。 An offset sidewall 104 made of SiO 2 or the like is formed so as to cover the side wall of the gate electrode 102. In addition, extension regions 105 are formed in the semiconductor substrate 100 on both sides of the gate electrode 102. Further, a first sidewall 106 having an L-shaped cross section and made of SiO 2 is formed so as to cover the sidewall of the offset sidewall 104 and the extension region 105, and the first sidewall 106 is A second sidewall 107 made of SiN is formed.
　また、ゲート電極１０２の両側において、半導体基板１００にはエッチング等によりリセスが設けられ、該リセスに３層のエピタキシャル層が積層されている。 Further, on both sides of the gate electrode 102, the semiconductor substrate 100 is provided with a recess by etching or the like, and three epitaxial layers are laminated on the recess.
　より詳しくは、まず、リセスの底面を覆うように、膜厚が少なくとも１０ｎｍの第１エピタキシャル層１１１が形成されている。これは、ゲルマニウム濃度が２５atom％以上のシリコンゲルマニウム（ＳｉＧｅ）からなり、Ｂ等のＰ型不純物はドープされていない。 More specifically, first, a first epitaxial layer 111 having a thickness of at least 10 nm is formed so as to cover the bottom surface of the recess. This is made of silicon germanium (SiGe) having a germanium concentration of 25 atom% or more, and is not doped with a P-type impurity such as B.
　第１エピタキシャル層１１１上には、膜厚が５ｎｍ以上で且つ２０ｎｍ以下の第２エピタキシャル層１１２が形成されている。これは、ゲルマニウムを含まないシリコンからなり、Ｂ等のＰ型不純物はドープされていない。 On the first epitaxial layer 111, a second epitaxial layer 112 having a thickness of 5 nm or more and 20 nm or less is formed. This is made of silicon not containing germanium, and is not doped with P-type impurities such as B.
　第２エピタキシャル層１１２上には、膜厚が５０ｎｍ程度の第３エピタキシャル層１１３が形成されている。これは、ゲルマニウム濃度が３０atom％以上のシリコンゲルマニウムからなる。 On the second epitaxial layer 112, a third epitaxial layer 113 having a thickness of about 50 nm is formed. This is made of silicon germanium having a germanium concentration of 30 atom% or more.
　第３エピタキシャル層１１３中には、Ｂ等のＰ型不純物がドープされ、ゲート電極１０２下方のチャネル形成領域を挟むＳ／Ｄ（ソース／ドレイン）領域１２２が形成されている（ゲート電極１０２両側の第３エピタキシャル層１１３のうち一方にソース領域、他方にドレイン領域が形成されている）。ここで、第２エピタキシャル層１１２と第３エピタキシャル層１１３との界面には、Ｐ型不純物は含まれていない。該界面から第３エピタキシャル層１１３の浅い側に向かってＰ型不純物の濃度が次第に増加し、最上部では、例えば、１×１０２３／ｃｍ３　程度の濃度となっている。 In the third epitaxial layer 113, a P-type impurity such as B is doped to form S / D (source / drain) regions 122 sandwiching a channel formation region below the gate electrode 102 (on both sides of the gate electrode 102). A source region is formed in one of the third epitaxial layers 113, and a drain region is formed in the other). Here, the interface between the second epitaxial layer 112 and the third epitaxial layer 113 contains no P-type impurities. The concentration of the P-type impurity gradually increases from the interface toward the shallow side of the third epitaxial layer 113, and at the uppermost portion, for example, the concentration is about 1 × 10 23 / cm 3 .
　また、一般に不純物濃度が１×１０１８／ｃｍ３　程度の位置をＳ／Ｄ接合界面とする。この結果、本実施形態の構成において、Ｓ／Ｄ接合界面は、第２エピタキシャル層１１２と第３エピタキシャル層１１３との界面よりも上であり、第３エピタキシャル層１１３内に位置している。但し、他の濃度の位置を界面と考えることも可能である。 In general, a position where the impurity concentration is about 1 × 10 18 / cm 3 is defined as an S / D junction interface. As a result, in the configuration of the present embodiment, the S / D junction interface is above the interface between the second epitaxial layer 112 and the third epitaxial layer 113 and is located in the third epitaxial layer 113. However, it is also possible to consider other density positions as the interface.
　尚、Ｓ／Ｄ領域１２２上及びゲート電極１０２上には、金属シリサイド層１２１が形成されている。 A metal silicide layer 121 is formed on the S / D region 122 and the gate electrode 102.
　以上の構成によると、ゲート電極１０２の両側のリセスに埋め込んだＳｉＧｅからなるエピタキシャル層、特に、第３エピタキシャル層１１３により、チャネル形成領域に対して圧縮応力を印加することができる。ここで、後述の理由により、第３エピタキシャル層１１３については積層欠陥及び格子緩和の発生が抑制されている。このことから、チャネル形成領域に対して確実に圧縮応力を印加し、チャネル部移動度を向上することができる。また、Ｓ／Ｄ領域１２２の接合深さ（Ｓ／Ｄ接合界面の深さ）が第３エピタキシャル層１１３の深さよりも浅いことから、Ｓ／Ｄ接合界面は、リーク電流の原因になる積層欠陥等の無い領域に位置している。よって、リーク電流が低減されている。 According to the above configuration, the compressive stress can be applied to the channel formation region by the epitaxial layer made of SiGe embedded in the recesses on both sides of the gate electrode 102, particularly the third epitaxial layer 113. Here, the generation of stacking faults and lattice relaxation is suppressed for the third epitaxial layer 113 for reasons described later. From this, it is possible to reliably apply a compressive stress to the channel formation region and improve the channel portion mobility. Further, since the junction depth of the S / D region 122 (the depth of the S / D junction interface) is shallower than the depth of the third epitaxial layer 113, the S / D junction interface has a stacking fault that causes a leakage current. It is located in the area where there is no etc. Therefore, the leakage current is reduced.
　図１には、半導体装置１２０の構造に合わせて、Ｓ／Ｄ領域１２２を構成するために導入されたＰ型不純物のプロファイルを例示している。図中に示す通り、第２エピタキシャル層１１２と第３エピタキシャル層１１３との界面の深さＤ１においてＰ型不純物濃度は０である。また、Ｐ型不純物濃度が１×１０１８／ｃｍ３　程度となるＳ／Ｄ接合界面の深さＤ２は、Ｄ１よりも浅い位置にある。深さＤ２から、第３エピタキシャル層１１３の最上部に向けて、Ｐ型不純物濃度は更に上昇する。 FIG. 1 illustrates a profile of a P-type impurity introduced to configure the S / D region 122 in accordance with the structure of the semiconductor device 120. As shown in the drawing, the P-type impurity concentration is 0 at the interface depth D1 between the second epitaxial layer 112 and the third epitaxial layer 113. Further, the depth D2 of the S / D junction interface at which the P-type impurity concentration is about 1 × 10 18 / cm 3 is at a position shallower than D1. The P-type impurity concentration further increases from the depth D2 toward the top of the third epitaxial layer 113.
　次に、第３エピタキシャル層１１３において積層欠陥及び格子緩和の発生が抑制されている理由を説明する。 Next, the reason why the generation of stacking faults and lattice relaxation in the third epitaxial layer 113 is suppressed will be described.
　まず、第１エピタキシャル層１１１には、リセスの底面（半導体基板１００と第１エピタキシャル層１１１との界面）の界面不純物（例えば酸素）等に起因して、積層欠陥等の結晶欠陥が生じやすい。しかしながら、第１エピタキシャル層１１１上に、シリコンからなる第２エピタキシャル層１１２を形成することにより、前記の結晶欠陥を吸収することができる。つまり、第１エピタキシャル層１１１に結晶欠陥があったとしても、一定の厚さを有する第２エピタキシャル層１１２の上面においては、欠陥のない面となっている。よって、第２エピタキシャル層１１２上に形成される第３エピタキシャル層１１３については、第１エピタキシャル層１１１における結晶欠陥の影響を避けることができる。 First, the first epitaxial layer 111 is likely to have crystal defects such as stacking faults due to interface impurities (for example, oxygen) on the bottom surface of the recess (interface between the semiconductor substrate 100 and the first epitaxial layer 111). However, the crystal defects can be absorbed by forming the second epitaxial layer 112 made of silicon on the first epitaxial layer 111. That is, even if there is a crystal defect in the first epitaxial layer 111, the upper surface of the second epitaxial layer 112 having a certain thickness is a surface having no defect. Therefore, the third epitaxial layer 113 formed on the second epitaxial layer 112 can avoid the influence of crystal defects in the first epitaxial layer 111.
　また、リセス内に３層のエピタキシャル層を設けることにより、チャネル形成領域を挟む主要な部分である第３エピタキシャル層１１３の厚さを抑制し、臨界膜厚以下にすることができる。この結果、第３エピタキシャル層における格子緩和の発生は抑制されている。尚、この例では、ゲルマニウム濃度が３０atom％であるから臨界膜厚は８０ｎｍ程度であり、これよりも薄い第３エピタキシャル層１１３としている。 Also, by providing three epitaxial layers in the recess, the thickness of the third epitaxial layer 113, which is the main part sandwiching the channel formation region, can be suppressed, and the critical film thickness can be reduced. As a result, the occurrence of lattice relaxation in the third epitaxial layer is suppressed. In this example, since the germanium concentration is 30 atom%, the critical film thickness is about 80 nm, and the third epitaxial layer 113 is thinner than this.
　次に、半導体装置１２０の製造方法について、その工程を模式的に示す断面図である図２（ａ）～（ｆ）を参照して説明する。 Next, a method for manufacturing the semiconductor device 120 will be described with reference to FIGS. 2A to 2F which are cross-sectional views schematically showing the process.
　まず、図２（ａ）の工程を行なう。ここでは、半導体基板１００上に、例えばＳｉＯ２　からなるゲート絶縁膜１０１を形成する。その上にポリシリコン膜及びＳｉＯ２　膜を順に積層した後、マスク（図示せず）形成してエッチングによりゲート電極１０２とその上のＳｉＯ２　膜１０３とする。 First, the process of FIG. Here, a gate insulating film 101 made of, for example, SiO 2 is formed on the semiconductor substrate 100. A polysilicon film and an SiO 2 film are sequentially stacked thereon, a mask (not shown) is formed, and the gate electrode 102 and the SiO 2 film 103 thereon are formed by etching.
　次に、ＳｉＯ２　膜を更に形成して半導体基板１００上、ゲート電極１０２側面及びＳｉＯ２　膜１０３上を覆い、エッチバックして、ゲート電極１０２の側壁にオフセットサイドウォール１０４を形成する。 Next, an SiO 2 film is further formed to cover the semiconductor substrate 100, the side surface of the gate electrode 102 and the SiO 2 film 103, and etched back to form an offset sidewall 104 on the side wall of the gate electrode 102.
　次に、ゲート電極１０２、オフセットサイドウォール１０４等をマスクとするイオン注入を行ない、ゲート電極１０２両側において半導体基板１００表面付近にエクステンション領域１０５を形成する。 Next, ion implantation is performed using the gate electrode 102, the offset sidewall 104, etc. as a mask, and extension regions 105 are formed near the surface of the semiconductor substrate 100 on both sides of the gate electrode 102.
　尚、ゲート絶縁膜１０１は、ＳｉＯ２　に代えて、ＨｆＳｉＯ等の高誘電体によって形成しても良い。また、ゲート電極１０２は、ポリシリコンからなる単層構造に代えて、ＴｉＮ等のメタルとポリシリコンの積層構造としても良い。 The gate insulating film 101 may be formed of a high dielectric material such as HfSiO instead of SiO 2 . Further, the gate electrode 102 may have a laminated structure of a metal such as TiN and polysilicon instead of the single layer structure made of polysilicon.
　続いて、図２（ｂ）の工程を行なう。まず、オフセットサイドウォール１０４、ＳｉＯ２　膜１０３を介してゲート電極１０２を覆うようにＳｉＯ２　膜を形成し、更に該ＳｉＯ２　膜を覆うようにシリコン窒化膜を形成する。次に、ドライエッチングを行ない、ゲート電極１０２の側壁及びエクステンション領域１０５上を覆うＬ字型の断面を有する第１のサイドウォール１０６と、その上を覆う第２のサイドウォール１０７とを形成する。 Subsequently, the process of FIG. 2B is performed. First, a SiO 2 film is formed so as to cover the gate electrode 102 via the offset sidewall 104 and the SiO 2 film 103, and further a silicon nitride film is formed so as to cover the SiO 2 film. Next, dry etching is performed to form a first sidewall 106 having an L-shaped cross section covering the sidewall of the gate electrode 102 and the extension region 105, and a second sidewall 107 covering the top.
　続いて、図２（ｃ）の工程を行なう。ここでは、半導体基板１００、第２のサイドウォール１０７、ＳｉＯ２　膜１０３等を覆うように、エピタキシャルカバー膜１０８を形成する。エピタキシャルカバー膜１０８は、ゲート電極１０２上のＳｉＯ２　膜１０３よりも膜密度が低く、例えば４００℃以下の低温にて成膜できるＳｉＯ２　膜として形成する。 Subsequently, the process of FIG. Here, the epitaxial cover film 108 is formed so as to cover the semiconductor substrate 100, the second sidewall 107, the SiO 2 film 103, and the like. Epitaxial cover film 108, the film density than the SiO 2 film 103 on the gate electrode 102 is low, to form a SiO 2 film can be formed, for example, by a low temperature of 400 ° C. or less.
　続いて、図２（ｄ）の工程を行なう。ここでは、エピタキシャルカバー膜１０８上に、ゲート電極１０２及びその両側の領域が開口されたレジスト１０９を形成する。次に、レジスト１０９をマスクとして、前記開口部分のエピタキシャルカバー膜１０８を除去する。これにより、ＳｉＧｅからなるエピタキシャル層を埋め込む部分の半導体基板１００が露出される。 Subsequently, the process of FIG. 2D is performed. Here, a resist 109 having a gate electrode 102 and regions on both sides thereof is formed on the epitaxial cover film 108. Next, the epitaxial cover film 108 in the opening is removed using the resist 109 as a mask. As a result, the portion of the semiconductor substrate 100 in which the epitaxial layer made of SiGe is embedded is exposed.
　続いて、図２（ｅ）の工程を行なう。ここでは、レジスト１０９を除去した後、エピタキシャルカバー膜１０８をマスクとして、ドライエッチング及びウェットエッチングのいずれか一方又は両方を用い、半導体基板１００に例えば深さ６０ｎｍ以上のリセス１１０を設ける。 Subsequently, the process of FIG. 2E is performed. Here, after removing the resist 109, the epitaxial cover film 108 is used as a mask, and either or both of dry etching and wet etching are used to provide the semiconductor substrate 100 with a recess 110 having a depth of 60 nm or more, for example.
　続いて、図２（ｆ）の工程を行なう。ここでは、リセス１１０内に、３層のエピタキシャル層を順次形成する。 Subsequently, the process of FIG. 2 (f) is performed. Here, three epitaxial layers are sequentially formed in the recess 110.
　まず、リセスの底部を覆うように、２５atom％以上のゲルマニウムを含むＳｉＧｅからなる第１エピタキシャル層１１１を形成する。これは、６５０℃以下で且つ水素雰囲気において、エピタキシャル成長によって１０ｎｍ以上の膜厚に成膜する。この際、Ｂ等のＰ型不純物のドープは行なわない。 First, a first epitaxial layer 111 made of SiGe containing germanium of 25 atom% or more is formed so as to cover the bottom of the recess. This is formed at a film thickness of 10 nm or more by epitaxial growth in a hydrogen atmosphere at 650 ° C. or lower. At this time, doping of P-type impurities such as B is not performed.
　より具体的な成膜の条件として、例えば、温度６５０℃、水素雰囲気（１０Torr（１．３３×１０３　Ｐａ））、ガス流量ＤＣＳ／ＧｅＨ４　／ＨＣｌ／Ｈ２　＝２０／１６／３５／１００００sccm（sccmは、０℃で且つ一気圧におけるｍｌ／分を表す）とする。尚、水素はキャリアガスである。これにより、ゲルマニウム濃度が２５atom％のシリコンゲルマニウムからなる第１エピタキシャル層１１１を成膜することができる。 More specific film forming conditions include, for example, a temperature of 650 ° C., a hydrogen atmosphere (10 Torr (1.33 × 10 3 Pa)), a gas flow rate DCS / GeH 4 / HCl / H 2 = 20/16/35/10000 sccm. (Sccm represents ml / min at 0 ° C. and 1 atm). Hydrogen is a carrier gas. Thereby, the first epitaxial layer 111 made of silicon germanium having a germanium concentration of 25 atom% can be formed.
　次に、第１エピタキシャル層１１１上に、連続して、シリコンからなりゲルマニウムを含まない第２エピタキシャル層１１２を形成する。これは、第１エピタキシャル層１１１に生じた結晶欠陥を吸収し、上面には結晶欠陥が現れないようにするために必要な程度の膜厚に形成する。本実施形態の例としては、膜厚５ｎｍ以上で且つ２０ｎｍ以下とする。成膜にはエピタキシャル成長を用い、Ｂ等のＰ型不純物のドープは行なわない。成膜条件の一例を挙げると、温度６５０℃、水素雰囲気（１０Torr（１．３３×１０３　Ｐａ））、ガス流量ＳｉＨ４　／ＨＣｌ／Ｈ２　＝３０／３５／１００００sccmである。 Next, a second epitaxial layer 112 made of silicon and not containing germanium is formed on the first epitaxial layer 111 continuously. This film is formed to a thickness necessary for absorbing crystal defects generated in the first epitaxial layer 111 and preventing the crystal defects from appearing on the upper surface. As an example of this embodiment, the film thickness is 5 nm or more and 20 nm or less. Epitaxial growth is used for film formation, and P-type impurities such as B are not doped. As an example of film formation conditions, the temperature is 650 ° C., the hydrogen atmosphere (10 Torr (1.33 × 10 3 Pa)), and the gas flow rate is SiH 4 / HCl / H 2 = 30/35/10000 sccm.
　この後、更に連続して、第２エピタキシャル層１１２上に、３０ａｔｍ％以上のゲルマニウムを含むＳｉＧｅからなる第３エピタキシャル層１１３を形成する。これは、少なくともゲート電極１０２下方のチャネル形成領域の両側に形成する。また、臨界膜厚以下とすることにより、格子緩和の発生を避ける。成膜条件の一例を挙げると、温度６５０℃、水素雰囲気（１０Torr（１．３３×１０３　Ｐａ））、ガス流量ＤＣＳ／ＧｅＨ４　／ＨＣｌ／Ｈ２　＝３０／２４／６０／１００００sccmである。 Thereafter, a third epitaxial layer 113 made of SiGe containing germanium of 30 atm% or more is formed on the second epitaxial layer 112 further continuously. This is formed at least on both sides of the channel formation region below the gate electrode 102. In addition, the occurrence of lattice relaxation is avoided by setting the critical film thickness or less. As an example of the film forming conditions, the temperature is 650 ° C., the hydrogen atmosphere (10 Torr (1.33 × 10 3 Pa)), and the gas flow rate is DCS / GeH 4 / HCl / H 2 = 30/24/60/10000 sccm.
　第３エピタキシャル層１１３については、Ｂ等のＰ型不純物をドープする。Ｂ等のＰ型不純物の濃度プロファイルについては、第２エピタキシャル層１１２の直上においては濃度０であり、第３エピタキシャル層１１３内に設定されるＳ／Ｄ接合界面深さにおいて１×１０１８／ｃｍ３　となり、第３エピタキシャル層１１３の最上部において１×１０２３／ｃｍ３　程度となるような濃度プロファイルとする。ここで、Ｓ／Ｄ接合界面深さは、半導体基板１００の上面から深さ３０ｎｍ～５０ｎｍの領域に設定する。 The third epitaxial layer 113 is doped with a P-type impurity such as B. The concentration profile of P-type impurities such as B is 0 immediately above the second epitaxial layer 112 and 1 × 10 18 / cm at the S / D junction interface depth set in the third epitaxial layer 113. 3 so that the concentration profile is about 1 × 10 23 / cm 3 at the top of the third epitaxial layer 113. Here, the S / D junction interface depth is set in a region having a depth of 30 nm to 50 nm from the upper surface of the semiconductor substrate 100.
　このような濃度プロファイルは、第３エピタキシャル層１１３をエピタキシャル成長する際に、Ｂ２Ｈ６の流量を調整することにより実現できる。具体例として、前記の成膜の条件により第３エピタキシャル層１１３を形成する際、材料ガスとしてＢ２Ｈ６を更に用いる。成膜開始時にはＢ２Ｈ６流量を０として、成膜の進行と共にＢ２Ｈ６流量を増やして行く。設定したＳ／Ｄ接合界面深さにまで成膜が進行した時点でＢ２Ｈ６流量が１００sccmとなるように調整し、その後は１６０sccmとする。 Such a concentration profile can be realized by adjusting the flow rate of B 2 H 6 when the third epitaxial layer 113 is epitaxially grown. As a specific example, when forming the third epitaxial layer 113 under the above-described film formation conditions, B 2 H 6 is further used as a material gas. At the start of film formation, the B 2 H 6 flow rate is set to 0, and the B 2 H 6 flow rate is increased as the film formation proceeds. When the film formation proceeds to the set S / D junction interface depth, the flow rate of B 2 H 6 is adjusted to 100 sccm, and thereafter 160 sccm.
　このようにして、ゲート電極１０２の両側において半導体基板１００に設けたリセス１１０に対し、３層のエピタキシャル層が形成される。 In this way, three epitaxial layers are formed on the recesses 110 provided on the semiconductor substrate 100 on both sides of the gate electrode 102.
　尚、第３エピタキシャル層１１３は、半導体基板１００上に例えば２０ｎｍ～３０ｎｍ程度の高さに盛上がるように形成しても良い。後の工程において、埋め込まれているエピタキシャル層が削られ、サイドウォール横の基板掘れが生じる可能性がある。そこで、第３のエピタキシャル層１１３を予め半導体基板１００よりも上にも盛上がって形成しておくことにより、エピタキシャル層が削られたとしても基板掘れが生じないようにすることが考えられる。 Note that the third epitaxial layer 113 may be formed on the semiconductor substrate 100 so as to rise to a height of, for example, about 20 nm to 30 nm. In a later process, the buried epitaxial layer may be scraped, and the substrate may be dug next to the sidewall. Therefore, it is conceivable that the third epitaxial layer 113 is formed so as to rise above the semiconductor substrate 100 in advance so that the substrate is not dug even if the epitaxial layer is shaved.
　この後、エピタキシャルカバー膜１０８と、ゲート電極１０２上のＳｉＯ２　膜１０３を除去する。更に、金属膜（例えば、膜厚１０ｎｍのＮｉＰｔ）を形成した後に熱処理を行なうことにより、図１に示すように、ゲート電極１０２上及びＳ／Ｄ領域１２２上に金属シリサイド層１２１を形成する。 Thereafter, the epitaxial cover film 108 and the SiO 2 film 103 on the gate electrode 102 are removed. Further, after forming a metal film (for example, NiPt having a thickness of 10 nm), a metal silicide layer 121 is formed on the gate electrode 102 and the S / D region 122 as shown in FIG.
　以上のようにして、本実施形態の例示的半導体装置１２０が製造される。その特徴等については、既に説明した通りである。 As described above, the exemplary semiconductor device 120 of this embodiment is manufactured. Its features and the like are as already described.
　尚、以上では、第１エピタキシャル層１１１のゲルマニウム濃度が２５atom％、第３エピタキシャル層１１３のゲルマニウム濃度が３０atom％としている。しかしながら、これには限らない。ゲルマニウム濃度を高くするほど大きな圧縮応力を発生させることが可能になるが、臨界膜厚は小さくなり、格子緩和を避けるためには薄くする必要がある。よって、形成するＰＭＯＳトランジスタの寸法、必要な性能等に合わせてゲルマニウム濃度、膜厚等を設定すればよい。この際、第３エピタキシャル層の膜厚が臨界膜厚を越えないようにすることが必要である。 In the above, the germanium concentration of the first epitaxial layer 111 is 25 atom%, and the germanium concentration of the third epitaxial layer 113 is 30 atom%. However, this is not restrictive. A higher compressive stress can be generated as the germanium concentration is increased, but the critical film thickness is reduced, and it is necessary to reduce the thickness in order to avoid lattice relaxation. Therefore, the germanium concentration, the film thickness, and the like may be set in accordance with the size of the PMOS transistor to be formed, required performance, and the like. At this time, it is necessary that the thickness of the third epitaxial layer does not exceed the critical thickness.
　　（第２の実施形態）
　図３は、第２の実施形態における例示的半導体装置１３０を説明する図である。 (Second Embodiment)
FIG. 3 is a diagram illustrating an exemplary semiconductor device 130 according to the second embodiment.
　半導体装置１３０は、半導体基板１００を用いて形成されている。半導体基板１００の表面はシャロートレンチ１１４によって区画され、ＰＭＯＳトランジスタ及びＣＭＯＳトランジスタが形成されてＣＭＯＳトランジスタを構成している。 The semiconductor device 130 is formed using the semiconductor substrate 100. The surface of the semiconductor substrate 100 is partitioned by a shallow trench 114, and a PMOS transistor and a CMOS transistor are formed to constitute a CMOS transistor.
　ここで、ＰＭＯＳトランジスタについては、第１の実施形態において説明したのと同様の構造を有する。つまり、ゲート絶縁膜１０１を介して形成され、オフセットサイドウォール１０４、第１のサイドウォール１０６及び第２のサイドウォール１０７を備えるゲート電極１０２の両側において、半導体基板１００に３層のエピタキシャル層が埋め込まれ、そのうちの第３エピタキシャル層１１３内にＳ／Ｄ領域１２２が設けられた構造である。 Here, the PMOS transistor has the same structure as that described in the first embodiment. That is, three epitaxial layers are embedded in the semiconductor substrate 100 on both sides of the gate electrode 102 that is formed through the gate insulating film 101 and includes the offset sidewall 104, the first sidewall 106, and the second sidewall 107. In this structure, the S / D region 122 is provided in the third epitaxial layer 113.
　これにより、ＰＭＯＳトランジスタにおいて、第１の実施形態にて説明したのと同様の特徴が実現する。つまり、チャネル形成領域には第３エピタキシャル層１１３によって圧縮応力が印加され、チャネル部移動度が向上している。このとき、シリコンからなる第２エピタキシャル層１１２によって、第１エピタキシャル層１１１における結晶欠陥等が吸収され、第３エピタキシャル層１１３については積層欠陥及び格子緩和の発生が抑制されている。このことから、圧縮応力の印加を確実に行なうことができる。更に、Ｓ／Ｄ接合界面は結晶欠陥のない部分に位置していることから、結晶欠陥に起因するリーク電流を避けることができ、リーク電流が低減されている。 This realizes the same characteristics as those described in the first embodiment in the PMOS transistor. That is, compressive stress is applied to the channel formation region by the third epitaxial layer 113, and the channel portion mobility is improved. At this time, crystal defects and the like in the first epitaxial layer 111 are absorbed by the second epitaxial layer 112 made of silicon, and the generation of stacking faults and lattice relaxation is suppressed in the third epitaxial layer 113. From this, it is possible to reliably apply the compressive stress. Furthermore, since the S / D junction interface is located in a portion having no crystal defect, a leak current due to the crystal defect can be avoided, and the leak current is reduced.
　これに対し、ＮＭＯＳトランジスタはエピタキシャル層を備えず、半導体基板１００に不純物をドープすることにより形成されたＳ／Ｄ領域１１５を有する構造である。ゲート電極１０２、サイドウォール等については、ＰＭＯＳトランジスタと同様の構成となっている。 On the other hand, the NMOS transistor does not include an epitaxial layer and has a structure having an S / D region 115 formed by doping the semiconductor substrate 100 with impurities. The gate electrode 102, the sidewall, and the like have the same configuration as that of the PMOS transistor.
　ＮＭＯＳトランジスタの場合、チャネル形成領域に圧縮応力を印加することはチャネル部移動度の向上に貢献せず、むしろ低下させる。そこで、ＮＭＯＳトランジスタについてはＳｉＧｅからなるエピタキシャル層を埋め込む構造とはせず、半導体基板１００に不純物をドープすることによってＳ／Ｄ領域１１５を形成するのが良い。 In the case of an NMOS transistor, applying compressive stress to the channel formation region does not contribute to the improvement of channel portion mobility, but rather decreases it. Therefore, it is preferable that the S / D region 115 is formed by doping the semiconductor substrate 100 with an impurity without using an NMOS transistor having an epitaxial layer made of SiGe.
　尚、ＰＭＯＳトランジスタ、ＮＭＯＳトランジスタのいずれにおいても、ゲート電極１０２は例えばポリシリコンからなり、半導体基板１００上に例えばＳｉＯ２　膜からなるゲート絶縁膜１０１を介して形成されている。但し、本実施形態においても、ゲート絶縁膜１０１は、ＨｆＳｉＯ等の高誘電体によって形成しても良い。また、ゲート電極１０２は、ＴｉＮ等のメタルとポリシリコンの積層構造としても良い。 In both the PMOS transistor and the NMOS transistor, the gate electrode 102 is made of, for example, polysilicon, and is formed on the semiconductor substrate 100 via the gate insulating film 101 made of, for example, an SiO 2 film. However, also in this embodiment, the gate insulating film 101 may be formed of a high dielectric such as HfSiO. The gate electrode 102 may have a stacked structure of a metal such as TiN and polysilicon.
　次に、半導体装置１３０の製造方法について、その工程を模式的に示す断面図である図４（ａ）～（ｅ）と図５（ａ）～（ｄ）とを参照して説明する。 Next, a method for manufacturing the semiconductor device 130 will be described with reference to FIGS. 4A to 4E and FIGS. 5A to 5D, which are cross-sectional views schematically showing the process.
　図４（ａ）に示す工程から説明する。まず、半導体基板１００に対し、表面部を区画する素子分離領域として、従来技術によりシャロートレンチ１１４を形成する。その後、半導体基板１００におけるＰＭＯＳトランジスタ及びＮＭＯＳトランジスタを形成する領域（以下、ＰＭＯＳ領域、ＮＭＯＳ領域と呼ぶ）に、それぞれ、ゲート絶縁膜１０１を介してゲート電極１０２を形成し、その上にＳｉＯ２　膜１０３を形成する。また、ゲート電極１０２の側面を覆うオフセットサイドウォール１０４を形成する。この後、ゲート電極１０２、オフセットサイドウォール１０４等をマスクとするイオン注入により、ゲート電極１０２両側における半導体基板１００にエクステンション領域１０５を形成する。これらは、第１の実施形態において図２（ａ）を参照して説明したのと同様の工程である。 The process shown in FIG. 4A will be described. First, a shallow trench 114 is formed on the semiconductor substrate 100 by a conventional technique as an element isolation region that partitions a surface portion. Thereafter, a gate electrode 102 is formed through a gate insulating film 101 in a region (hereinafter referred to as a PMOS region and an NMOS region) where a PMOS transistor and an NMOS transistor are formed in the semiconductor substrate 100, and an SiO 2 film is formed thereon. 103 is formed. In addition, an offset sidewall 104 that covers the side surface of the gate electrode 102 is formed. Thereafter, extension regions 105 are formed in the semiconductor substrate 100 on both sides of the gate electrode 102 by ion implantation using the gate electrode 102, the offset sidewall 104, and the like as a mask. These are the same steps as described with reference to FIG. 2A in the first embodiment.
　続いて、図４（ｂ）の工程を行なう。ここでは、ＰＭＯＳ領域及びＮＭＯＳ領域に両方において、オフセットサイドウォール１０４を介してゲート電極１０２の側壁を覆うように、例えばＳｉＯ２　膜からなりＬ字型の断面を有する第１のサイドウォール１０６を形成すると共に、更にその上に、シリコン窒化膜からなる第２のサイドウォール１０７とを形成する。これは、第１の実施形態において図２（ｂ）を参照して説明したのど同様の工程である。 Subsequently, the process of FIG. 4B is performed. Here, in both the PMOS region and the NMOS region, the first sidewall 106 made of, for example, a SiO 2 film and having an L-shaped cross section is formed so as to cover the sidewall of the gate electrode 102 via the offset sidewall 104. At the same time, a second sidewall 107 made of a silicon nitride film is formed thereon. This is the same process as described in the first embodiment with reference to FIG.
　続いて、図４（ｃ）の工程を行なう。まず、ＰＭＯＳ領域及びＮＭＯＳ領域の両方において、半導体基板１００、第２のサイドウォール１０７、ＳｉＯ２　膜１０３等を覆うように、エピタキシャルカバー膜１０８を形成する。これは、ゲート電極１０２上のＳｉＯ２　膜１０３よりも膜密度が低く、例えば４００℃以下の低温にて成膜できるＳｉＯ２　膜として形成する。 Then, the process of FIG.4 (c) is performed. First, an epitaxial cover film 108 is formed so as to cover the semiconductor substrate 100, the second sidewall 107, the SiO 2 film 103, and the like in both the PMOS region and the NMOS region. This film density than the SiO 2 film 103 on the gate electrode 102 is low, to form a SiO 2 film can be formed, for example, by a low temperature of 400 ° C. or less.
　次に、エピタキシャルカバー膜１０８上に、ＰＭＯＳ領域における各サイドウォール、ゲート電極１０２及びその両側のＳ／Ｄ領域１２２が形成される領域上が開口されたレジスト１３１を形成する。更に、レジスト１３１をマスクとして、開口部分のエピタキシャルカバー膜１０８を除去し、ＰＭＯＳ領域を露出させる。 Next, on the epitaxial cover film 108, a resist 131 is formed in which the sidewalls in the PMOS region, the gate electrode 102, and the regions where the S / D regions 122 on both sides are formed are opened. Further, using the resist 131 as a mask, the epitaxial cover film 108 at the opening is removed, and the PMOS region is exposed.
　続いて、図４（ｄ）の工程を行なう。レジスト１３１を除去した後、エピタキシャルカバー膜１０８をマスクとして、ＰＭＯＳ領域におけるゲート電極１０２の両側の半導体基板１００にリセス１１０を形成する。これは、例えば、ドライエッチング及びウェットエッチングのいずれか一方又は両方を用い、深さ６０ｎｍに形成する。 Subsequently, the process of FIG. 4D is performed. After removing the resist 131, a recess 110 is formed in the semiconductor substrate 100 on both sides of the gate electrode 102 in the PMOS region using the epitaxial cover film 108 as a mask. For example, one or both of dry etching and wet etching is used, and the depth is 60 nm.
　続いて、図４（ｅ）の工程を行なう。ここでは、ＰＭＯＳ領域に形成したリセス１１０に、２５atom％以上のゲルマニウムを含むＳｉＧｅからなる第１エピタキシャル層１１１、シリコンからなる第２エピタキシャル層１１２、３０atom％以上のゲルマニウムを含むＳｉＧｅからなる第３エピタキシャル層１１３を順次形成する。ここで、第１エピタキシャル層１１１及び第２エピタキシャル層１１２にはＢ等のＰ型不純物のドープを行なわない。また、第３エピタキシャル層１１３にはＢ等のＰ型不純物をドープし、Ｓ／Ｄ領域１２２を形成する。この際、第２エピタキシャル層１１２直上では不純物濃度０、第３エピタキシャル層１１３内に設定されるＳ／Ｄ接合界面深さにおいて１×１０１８／ｃｍ３　、第３エピタキシャル層１１３の最上部において１×１０２３／ｃｍ３　程度となるような濃度プロファイルとする。 Then, the process of FIG.4 (e) is performed. Here, in the recess 110 formed in the PMOS region, a first epitaxial layer 111 made of SiGe containing 25 atomic percent or more of germanium, a second epitaxial layer 112 made of silicon, and a third epitaxial layer made of SiGe containing 30 atomic percent or more of germanium. Layer 113 is formed sequentially. Here, the first epitaxial layer 111 and the second epitaxial layer 112 are not doped with a P-type impurity such as B. The third epitaxial layer 113 is doped with a P-type impurity such as B to form an S / D region 122. At this time, the impurity concentration is 0 immediately above the second epitaxial layer 112, 1 × 10 18 / cm 3 at the S / D junction interface depth set in the third epitaxial layer 113, and 1 at the top of the third epitaxial layer 113. The concentration profile is set to about × 10 23 / cm 3 .
　このようにして、ゲート電極１０２下方のチャネル形成領域に圧縮応力を印加すると共に、結晶欠陥の無い部分にＳ／Ｄ接合界面深さを有するＳ／Ｄ領域１２２を備えた第３エピタキシャル層１１３とすることができる。 In this way, the compressive stress is applied to the channel formation region below the gate electrode 102, and the third epitaxial layer 113 including the S / D region 122 having the S / D junction interface depth in the portion having no crystal defect, can do.
　より詳しくは、第１の実施形態において図２（ｆ）を参照して説明したのと同様である。 More specifically, this is the same as that described with reference to FIG. 2F in the first embodiment.
　続いて、図５（ａ）の工程を行なう。まず、ＰＭＯＳ領域上を覆い、ＮＭＯＳ領域における各サイドウォール、ゲート電極１０２及びその両側のＳ／Ｄ領域１１５が形成される領域上が開口されたレジスト１３１を形成する。次に、レジスト１３１の開口部に露出した部分のエピタキシャルカバー膜１０８を除去し、各サイドウォール、ゲート電極１０２等をマスクとするイオン注入及びアニールを行なう。これにより、ＮＭＯＳ領域において、半導体基板１００におけるエクステンション領域１２５の外側に、Ｓ／Ｄ領域１１５が形成される。尚、前記アニールの条件は、例えば、１０２５℃のスパイクアニールである。 Subsequently, the process of FIG. 5A is performed. First, a resist 131 is formed so as to cover the PMOS region and open in the regions where the sidewalls in the NMOS region, the gate electrode 102, and the S / D regions 115 on both sides thereof are formed. Next, the portion of the epitaxial cover film 108 exposed in the opening of the resist 131 is removed, and ion implantation and annealing are performed using each sidewall, the gate electrode 102, and the like as a mask. As a result, the S / D region 115 is formed outside the extension region 125 in the semiconductor substrate 100 in the NMOS region. The annealing condition is, for example, spike annealing at 1025 ° C.
　続いて、図５（ｂ）の工程を行なう。ここでは、レジスト１３２を除去し、更に、エピタキシャルカバー膜１０８及びゲート電極１０２上のＳｉＯ２　膜１０３を除去する。 Subsequently, the process of FIG. 5B is performed. Here, the resist 132 is removed, and the SiO 2 film 103 on the epitaxial cover film 108 and the gate electrode 102 is further removed.
　続いて、図５（ｃ）の工程を行なう。ここでは、Ｓ／Ｄ領域１２２の形成された第３エピタキシャル層１１３上、ゲート電極１０２上及びＳ／Ｄ領域１１５の形成された半導体基板１００上を覆うように、金属膜１１６を形成する。これは、例えば、膜厚１０ｎｍのＮｉＰｔ膜である。 Subsequently, the process of FIG. 5C is performed. Here, the metal film 116 is formed so as to cover the third epitaxial layer 113 in which the S / D region 122 is formed, the gate electrode 102 and the semiconductor substrate 100 in which the S / D region 115 is formed. This is, for example, a 10 nm thick NiPt film.
　続いて、図５（ｄ）の工程を行なう。ここでは、熱処理を行ない、ゲート電極１０２上、Ｓ／Ｄ領域１２２上及びＳ／Ｄ領域１１５上に金属シリサイド層１２１を形成する。 Subsequently, the process of FIG. 5D is performed. Here, heat treatment is performed to form the metal silicide layer 121 on the gate electrode 102, the S / D region 122, and the S / D region 115.
　以上のようにして、ＣＭＯＳトランジスタを有する半導体装置１３０が製造される。その特徴等については、既に説明した通りである。 As described above, the semiconductor device 130 having the CMOS transistor is manufactured. Its features and the like are as already described.
　尚、以上ではいずれもＭＯＳトランジスタを例として説明した。しかしながら、ＭＯＳトランジスタには限らず、ＭＩＳトランジスタに適用することも可能である。 In the above description, MOS transistors have been described as examples. However, the present invention is not limited to MOS transistors, and can be applied to MIS transistors.
　本開示の技術は、シリコンゲルマニウム層をソース／ドレイン領域として利用するＰＭＯＳトランジスタにおいて、チャネル部移動度を向上し且つリーク電流を低減することができ、ゲート幅が例えば４０ｎｍ以下の微細なＭＩＳトランジスタを有する半導体装置及びその製造方法としても有用である。 The technology of the present disclosure is a PMOS transistor that uses a silicon germanium layer as a source / drain region, can improve channel portion mobility and reduce leakage current, and can achieve a fine MIS transistor with a gate width of, for example, 40 nm or less. It is also useful as a semiconductor device having the same and a manufacturing method thereof.
１００　　　半導体基板
１０１　　　ゲート絶縁膜
１０２　　　ゲート電極
１０３　　　ＳｉＯ２　膜
１０４　　　オフセットサイドウォール
１０５　　　エクステンション領域
１０６　　　第１のサイドウォール
１０７　　　第２のサイドウォール
１０８　　　エピタキシャルカバー膜
１０９　　　レジスト
１１０　　　リセス
１１１　　　第１エピタキシャル層
１１２　　　第２エピタキシャル層
１１３　　　第３エピタキシャル層
１１４　　　シャロートレンチ
１１５　　　Ｓ／Ｄ領域
１１６　　　金属膜
１２０　　　半導体装置
１２１　　　金属シリサイド層
１２２　　　Ｓ／Ｄ領域
１２５　　　エクステンション領域
１３０　　　半導体装置
１３１　　　レジスト
１３２　　　レジスト 100 Semiconductor substrate 101 Gate insulating film 102 Gate electrode 103 SiO 2 film 104 Offset sidewall 105 Extension region 106 First sidewall 107 Second sidewall 108 Epitaxial cover film 109 Resist 110 Recess 111 First epitaxial layer 112 Second epitaxial Layer 113 Third epitaxial layer 114 Shallow trench 115 S / D region 116 Metal film 120 Semiconductor device 121 Metal silicide layer 122 S / D region 125 Extension region 130 Semiconductor device 131 Resist 132 Resist

Claims (18)

  1. 　半導体基板の表面部に形成されたソース領域及びドレイン領域と、これらに挟まれたチャネル形成領域上にゲート絶縁膜を介して形成されたゲート電極とを含むＰチャネル型トランジスタを備え、
    　前記ゲート電極の両側それぞれにおいて前記半導体基板にリセスが形成され、
    　前記リセスに、シリコンゲルマニウムからなる第１エピタキシャル層と、その上に形成され且つシリコンからなる第２エピタキシャル層と、その上に形成され且つシリコンゲルマニウムからなり、前記チャネル形成領域を挟む第３エピタキシャル層とを備え、
    　前記ソース領域及び前記ドレイン領域は、前記第３エピタキシャル層中に形成され、且つ、それぞれの接合深さがいずれも前記第３エピタキシャル層の深さよりも浅いことを特徴とする半導体装置。     A p-channel transistor including a source region and a drain region formed on the surface portion of the semiconductor substrate, and a gate electrode formed on the channel formation region sandwiched between the gate electrode and the gate electrode;
    A recess is formed in the semiconductor substrate on each side of the gate electrode,
    The recess includes a first epitaxial layer made of silicon germanium, a second epitaxial layer formed thereon and made of silicon, and a third epitaxial layer formed thereon and made of silicon germanium and sandwiching the channel formation region And
    The semiconductor device is characterized in that the source region and the drain region are formed in the third epitaxial layer, and each junction depth is shallower than the depth of the third epitaxial layer.
  2. 　請求項１の半導体装置において、
    　前記ソース領域及びドレイン領域は、Ｐ型不純物が導入されることにより形成され、
    　前記第１エピタキシャル層及び前記第２エピタキシャル層には、前記Ｐ型不純物が導入されていないことを特徴とする半導体装置。     The semiconductor device according to claim 1.
    The source region and the drain region are formed by introducing a P-type impurity,
    The semiconductor device, wherein the P-type impurity is not introduced into the first epitaxial layer and the second epitaxial layer.
  3. 　請求項１の半導体装置において、
    　前記第３エピタキシャル層は、前記第２エピタキシャル層と前記第３エピタキシャル層との界面から、前記ソース領域又は前記ドレイン領域の接合深さまでの範囲において、Ｐ型不純物濃度が０／ｃｍ３　から１×１０１８／ｃｍ３　にまで変化するＰ型不純物プロファイルを有することを特徴とする半導体装置。     The semiconductor device according to claim 1.
    The third epitaxial layer has a P-type impurity concentration of 0 / cm 3 to 1 × in the range from the interface between the second epitaxial layer and the third epitaxial layer to the junction depth of the source region or the drain region. A semiconductor device having a P-type impurity profile that changes to 10 18 / cm 3 .
  4. 　請求項１の半導体装置において、
    　前記第１エピタキシャル層は、２５atom％以上のゲルマニウムを含むことを特徴とする半導体装置。     The semiconductor device according to claim 1.
    The semiconductor device according to claim 1, wherein the first epitaxial layer contains germanium of 25 atom% or more.
  5. 　請求項１の半導体装置において、
    　前記第３エピタキシャル層は、３０atom％以上のゲルマニウムを含むことを特徴とする半導体装置。     The semiconductor device according to claim 1.
    The semiconductor device, wherein the third epitaxial layer contains germanium of 30 atom% or more.
  6. 　請求項１の半導体装置において、
    　前記第３エピタキシャル層は、前記第１エピタキシャル層よりも厚く、
    　前記第１エピタキシャル層は、前記第２エピタキシャル層よりも厚いことを特徴とする半導体装置。     The semiconductor device according to claim 1.
    The third epitaxial layer is thicker than the first epitaxial layer,
    The semiconductor device according to claim 1, wherein the first epitaxial layer is thicker than the second epitaxial layer.
  7. 　請求項１の半導体装置において、
    　前記第１エピタキシャル層は、１０ｎｍ以上の膜厚を有することを特徴とする半導体装置。     The semiconductor device according to claim 1.
    The semiconductor device according to claim 1, wherein the first epitaxial layer has a thickness of 10 nm or more.
  8. 　請求項１の半導体装置において、
    　前記第２エピタキシャル層は、５ｎｍ以上で且つ２０ｎｍ以下の膜厚を有することを特徴とする半導体装置。     The semiconductor device according to claim 1.
    The second epitaxial layer has a film thickness of 5 nm or more and 20 nm or less.
  9. 　請求項１の半導体装置において、
    　前記第３エピタキシャル層は、臨界膜厚以下の膜厚を有することを特徴とする半導体装置。     The semiconductor device according to claim 1.
    The semiconductor device, wherein the third epitaxial layer has a film thickness equal to or less than a critical film thickness.
  10. 　請求項１の半導体装置において、
    　前記第３エピタキシャル層は、前記半導体基板上面よりも上にも盛上がって形成されていることを特徴とする半導体装置。     The semiconductor device according to claim 1.
    The third epitaxial layer is formed so as to rise above the upper surface of the semiconductor substrate.
  11. 　請求項１の半導体装置において、
    　前記Ｐチャネル型トランジスタに加えてＮチャネル型トランジスタを更に備え、
    　前記Ｎチャネル型トランジスタは、シリコンゲルマニウムからなる領域を備えない構成であることを特徴とする半導体装置。     The semiconductor device according to claim 1.
    In addition to the P-channel transistor, an N-channel transistor is further provided.
    The semiconductor device according to claim 1, wherein the N-channel transistor does not include a region made of silicon germanium.
  12. 　Ｐチャネル型トランジスタを備える半導体装置の製造方法において、
    　半導体基板上に、ゲート絶縁膜を介してゲート電極を形成する工程（ａ）と、
    　前記ゲート電極の両側それぞれにおいて、前記半導体基板にリセスを形成する工程（ｂ）と、
    　前記リセス内にシリコンゲルマニウムからなる第１エピタキシャル層を形成する工程（ｃ）と、
    　前記第１エピタキシャル層上に、シリコンからなる第２エピタキシャル層を形成する工程（ｄ）と、
    　前記第２エピタキシャル層上に、前記ゲート電極下方のチャネル形成領域を挟むように、シリコンゲルマニウムからなる第３エピタキシャル層を形成する工程（ｅ）とを備え、
    　Ｐ型不純物の導入量を調整しながら前記工程（ｅ）を行なうことにより、前記第３エピタキシャル層中に、接合深さが前記第３エピタキシャル層の深さよりも浅いソース領域及びドレイン領域を形成することを特徴とする半導体装置の製造方法。     In a method for manufacturing a semiconductor device including a P-channel transistor,
    Forming a gate electrode on the semiconductor substrate via a gate insulating film;
    Forming a recess in the semiconductor substrate on each side of the gate electrode (b);
    Forming a first epitaxial layer made of silicon germanium in the recess (c);
    Forming a second epitaxial layer made of silicon on the first epitaxial layer (d);
    A step (e) of forming a third epitaxial layer made of silicon germanium on the second epitaxial layer so as to sandwich a channel formation region below the gate electrode;
    By performing the step (e) while adjusting the introduction amount of the P-type impurity, a source region and a drain region having a junction depth shallower than the depth of the third epitaxial layer are formed in the third epitaxial layer. A method for manufacturing a semiconductor device.
  13. 　請求項１２の半導体装置の製造方法において、
    　前記工程（ｃ）及び前記工程（ｄ）は、Ｐ型不純物を含ませることなくエピタキシャル成長により行なうことを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device of Claim 12,
    The method of manufacturing a semiconductor device, wherein the step (c) and the step (d) are performed by epitaxial growth without including a P-type impurity.
  14. 　請求項１２の半導体装置の製造方法おいて、
    　前記工程（ｅ）において、第３エピタキシャル層の成長に合わせてＰ型不純物の導入量を増加しながら前記第３エピタキシャル層を形成することにより、前記第２エピタキシャル層と前記第３エピタキシャル層との界面から、前記ソース領域又は前記ドレイン領域の接合深さまでの範囲において、Ｐ型不純物濃度が０／ｃｍ３　から１×１０１８／ｃｍ３　にまで変化するＰ型不純物プロファイルを得ることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device of Claim 12,
    In the step (e), by forming the third epitaxial layer while increasing the amount of introduction of P-type impurities in accordance with the growth of the third epitaxial layer, the second epitaxial layer and the third epitaxial layer are formed. A P-type impurity profile having a P-type impurity concentration varying from 0 / cm 3 to 1 × 10 18 / cm 3 in a range from the interface to the junction depth of the source region or the drain region is obtained. A method for manufacturing a semiconductor device.
  15. 　請求項１２の半導体装置の製造方法において、
    　前記第３エピタキシャル層は、３０％以上のゲルマニウムを含み且つ臨界膜厚以下の膜厚を有することを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device of Claim 12,
    The third epitaxial layer contains 30% or more of germanium and has a film thickness equal to or less than a critical film thickness.
  16. 　請求項１２の半導体装置の製造方法において、
    　前記工程（ｅ）の後に、前記第３エピタキシャル層上に金属膜を形成すると共に熱処理を行なって金属シリサイドを形成する工程を更に備えることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device of Claim 12,
    A method of manufacturing a semiconductor device, further comprising a step of forming a metal silicide on the third epitaxial layer and performing a heat treatment after the step (e) to form a metal silicide.
  17. 　請求項１２の半導体装置の製造方法において、
    　前記工程（ａ）の後、前記工程（ｂ）の前に、
    　前記ゲート電極の側壁を覆うオフセットサイドウォールを形成する工程と、
    　前記ゲート電極及び前記オフセットサイドウォールをマスクとするイオン注入によりエクステンション領域を形成する工程と、
    　前記オフセットサイドウォールの側壁を覆い且つ前記ゲート電極と同じ高さのサイドウォールを形成する工程とを更に備えることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device of Claim 12,
    After the step (a) and before the step (b),
    Forming an offset sidewall covering the sidewall of the gate electrode;
    Forming an extension region by ion implantation using the gate electrode and the offset sidewall as a mask;
    And a step of covering the side wall of the offset side wall and forming a side wall having the same height as the gate electrode.
  18. 　請求項１２の半導体装置の製造方法において、
    　前記Ｐチャネル型トランジスタに加えてＮチャネル型トランジスタを形成し、
    　前記Ｎチャネル型トランジスタは、シリコンゲルマニウム領域を備えない構成であることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device of Claim 12,
    Forming an N-channel transistor in addition to the P-channel transistor;
    The method of manufacturing a semiconductor device, wherein the N-channel transistor has a structure not including a silicon germanium region.
PCT/JP2010/002650 2009-09-15 2010-04-12 Semiconductor device and method for manufacturing same WO2011033695A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009-212846 2009-09-15
JP2009212846A JP2011066042A (en) 2009-09-15 2009-09-15 Semiconductor device and method of manufacturing the same

Publications (1)

Publication Number Publication Date
WO2011033695A1 true WO2011033695A1 (en) 2011-03-24

Family

ID=43758314

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2010/002650 WO2011033695A1 (en) 2009-09-15 2010-04-12 Semiconductor device and method for manufacturing same

Country Status (2)

Country Link
JP (1) JP2011066042A (en)
WO (1) WO2011033695A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9577097B2 (en) 2014-12-08 2017-02-21 Samsung Electronics Co., Ltd. Semiconductor device having stressor and method of forming the same
EP3120388A4 (en) * 2014-03-21 2017-11-29 Intel Corporation Techniques for integration of ge-rich p-mos source/drain contacts

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8299535B2 (en) * 2010-06-25 2012-10-30 International Business Machines Corporation Delta monolayer dopants epitaxy for embedded source/drain silicide
CN103187299B (en) * 2011-12-31 2015-08-05 中芯国际集成电路制造(上海)有限公司 The formation method of transistor
KR102065973B1 (en) * 2013-07-12 2020-01-15 삼성전자 주식회사 Semiconductor device and fabricating method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000299462A (en) * 1999-04-15 2000-10-24 Toshiba Corp Semiconductor device and its manufacture
JP2007214362A (en) * 2006-02-09 2007-08-23 Sony Corp Method of manufacturing semiconductor device
JP2008177319A (en) * 2007-01-18 2008-07-31 Sony Corp Semiconductor device manufacturing method and semiconductor device
JP2008192989A (en) * 2007-02-07 2008-08-21 Fujitsu Ltd Semiconductor device and manufacturing method therefor
JP2009043916A (en) * 2007-08-08 2009-02-26 Toshiba Corp Semiconductor device and manufacturing method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000299462A (en) * 1999-04-15 2000-10-24 Toshiba Corp Semiconductor device and its manufacture
JP2007214362A (en) * 2006-02-09 2007-08-23 Sony Corp Method of manufacturing semiconductor device
JP2008177319A (en) * 2007-01-18 2008-07-31 Sony Corp Semiconductor device manufacturing method and semiconductor device
JP2008192989A (en) * 2007-02-07 2008-08-21 Fujitsu Ltd Semiconductor device and manufacturing method therefor
JP2009043916A (en) * 2007-08-08 2009-02-26 Toshiba Corp Semiconductor device and manufacturing method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3120388A4 (en) * 2014-03-21 2017-11-29 Intel Corporation Techniques for integration of ge-rich p-mos source/drain contacts
US9859424B2 (en) 2014-03-21 2018-01-02 Intel Corporation Techniques for integration of Ge-rich p-MOS source/drain contacts
US10147817B2 (en) 2014-03-21 2018-12-04 Intel Corporation Techniques for integration of Ge-rich p-MOS source/drain
US10541334B2 (en) 2014-03-21 2020-01-21 Intel Corporation Techniques for integration of Ge-rich p-MOS source/drain
US9577097B2 (en) 2014-12-08 2017-02-21 Samsung Electronics Co., Ltd. Semiconductor device having stressor and method of forming the same

Also Published As

Publication number Publication date
JP2011066042A (en) 2011-03-31

Similar Documents

Publication Publication Date Title
US6882025B2 (en) Strained-channel transistor and methods of manufacture
US7642607B2 (en) MOS devices with reduced recess on substrate surface
US7928474B2 (en) Forming embedded dielectric layers adjacent to sidewalls of shallow trench isolation regions
US7981750B2 (en) Methods of fabrication of channel-stressed semiconductor devices
US9711413B2 (en) High performance CMOS device design
US7138310B2 (en) Semiconductor devices having strained dual channel layers
US8404546B2 (en) Source/drain carbon implant and RTA anneal, pre-SiGe deposition
US8518813B2 (en) Semiconductor device and method of manufacturing semiconductor device
US20080179636A1 (en) N-fets with tensilely strained semiconductor channels, and method for fabricating same using buried pseudomorphic layers
US20070267703A1 (en) Strained channel transistor and method of fabrication thereof
US20070200170A1 (en) Semiconductor device and method of manufacturing the same
US20080054347A1 (en) Composite stressors in MOS devices
JP2006253317A (en) SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND p-CHANNEL MOS TRANSISTOR
US20090085123A1 (en) Semiconductor device and method for fabricating the same
US20120256265A1 (en) Semiconductor device and manufacturing method thereof
JP4992710B2 (en) MOS transistor and manufacturing method thereof
US20120256266A1 (en) Semiconductor device
JP2009182297A (en) Semiconductor device and method of manufacturing the same
WO2013139064A1 (en) Semiconductor structure and manufacturing method therefor
US20160027702A1 (en) MOS Devices with Modulated Performance and Methods for Forming the Same
WO2011033695A1 (en) Semiconductor device and method for manufacturing same
US8441045B2 (en) Semiconductor device and method for manufacturing the same
WO2013139063A1 (en) Semiconductor structure and manufacturing method therefor
US20240071818A1 (en) Semiconductor device and method of fabricating the same
JP2010010382A (en) Semiconductor device and its method for manufacturing

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10816812

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10816812

Country of ref document: EP

Kind code of ref document: A1