JP2007214362A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which can form a recess broadened toward a channel formation region by avoiding formation of the too deep recess, and can suppress abnormal epitaxial growth of an SiGe film upon its epitaxial growth or degradation of the element isolation characteristic of a transistor. <P>SOLUTION: A gate electrode 21a is formed on the surface of a semiconductor substrate (10a) with a gate insulating film 20a disposed therebetween, a recess A is formed at each of both sides of the gate electrode 21a in the semiconductor substrate (10a), an anisotropic mask 25 is formed on the inner wall surface of the recess A at a bottom surface rather than its side wall surface with a high selectivity, the substrate is etched with the bottom surface of being protected by the mask 25 to extend the recess A toward the gate electrode 21a, the mask 25 is removed, and then a conductor is buried in the recess A to form a pair of source/drain regions at the both sides of the gate electrode 21a. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a recess is formed in a source / drain region of a field effect transistor and a SiGe film is embedded.

  MISFET (metal-insulating film-semiconductor field effect transistor), which is a basic element of a semiconductor device, has been increasingly miniaturized as the semiconductor device has been miniaturized and highly integrated.

  However, as miniaturization progresses, it is difficult to improve the performance of the MISFET by conventional scaling alone. For example, as described in Patent Document 1, the gate length direction (direction perpendicular to the extending direction of the gate electrode) Attention has been focused on a technique for improving the MISFET capability by applying a stress using a stress film that generates a tensile or compressive stress to the capability of MISFET since the 90 nm generation.

  In the above, after the formation of the source / drain regions, an N-channel MISFET (hereinafter also referred to as NTr) and a P-channel MISFET (hereinafter also referred to as PTr) form an insulating film having different film stresses. The PTr is given a compressive stress to improve its capacity.

  For example, as described in Non-Patent Document 1, a method is known in which a recess is formed in a region to be a source / drain region of PTr, and a SiGe film is formed by epitaxial growth as a stress film for applying compressive stress.

FIG. 11 is a cross-sectional view of the semiconductor device formed as described above.
For example, an STI (shallow trench isolation) type element isolation insulating film 111 is formed so as to separate active regions in the n-type semiconductor region 110a and the p-type semiconductor region 110b of the semiconductor substrate.
A P-channel MISFET (PTr) is formed in the n-type semiconductor region 110a, and an N-channel MISFET (NTr) is formed in the p-type semiconductor region 110b.

First, PTr will be described.
A gate insulating film 120a is formed on the active region of the n-type semiconductor region 110a, a gate electrode 121a is formed thereon, a cap insulating film 122a is formed thereon, and both sides of the gate electrode 121a are formed. Sidewall insulating films 123a are formed.
Further, a recess A is formed in a region to be a source / drain region on the surface of the n-type semiconductor region 110a on both sides of the gate electrode 121a, and a SiGe film 126 is embedded in the recess A to form a pair of source / drain regions. Is formed.

Next, NTr will be described.
A gate insulating film 120b is formed on the active region of the p-type semiconductor region 110b, a gate electrode 121b is formed thereon, a cap insulating film 122b is formed thereon, and both sides of the gate electrode 121b are formed. Sidewall insulating films 123b are formed.
Further, a pair of source / drain regions 130 are formed in the p-type semiconductor region 110b on both sides of the gate electrode 121b.

A method for manufacturing the semiconductor device will be described.
First, as shown in FIG. 12A, an STI-type element isolation insulating film 111 is formed so as to partition an active region in an n-type semiconductor region 110a and a p-type semiconductor region 110b of a semiconductor substrate.
The n-type semiconductor region 110a becomes the PTr formation region Ra, and the p-type semiconductor region 110b becomes the NTr formation region Rb.
Next, for example, in the above-described PTr formation region Ra and NTr formation region Rb, a gate insulating film (120a, 120b) and a gate electrode (121a, 121b) are formed on the n-type semiconductor region 110a and the p-type semiconductor region 110b in the active region. ) And cap insulating films (122a, 122b).

  Next, as shown in FIG. 12B, a silicon oxide film 123 is deposited in the PTr formation region Ra and the NTr formation region Rb.

  Next, as shown in FIG. 13A, for example, the PTr formation region Ra is opened and a resist film 124 is patterned on the NTr formation region Rb, and the silicon oxide film 123 is etched on the entire surface in the PTr formation region Ra. Back sidewall insulating film 123a is formed.

  Next, as shown in FIG. 13B, for example, in the PTr formation region Ra, wet etching is performed on the surface of the n-type semiconductor region 110a in the active region using the sidewall insulating film 123a and the cap insulating film 122a as a mask. , A recess A is formed in a region to be a source / drain region of PTr.

  Next, after removing the resist film 124 and further removing the natural oxide film on the surface of the recess A, SiGe is selectively applied to the surface of the recess A where silicon is exposed as shown in FIG. The SiGe film 126 is formed by epitaxial growth.

  Next, as shown in FIG. 14B, for example, the NTr formation region Rb is opened and a resist film 127 is patterned in the PTr formation region Ra, and the silicon oxide film 123 is etched back on the entire surface in the NTr formation region Rb. Thus, a sidewall insulating film 123b is formed.

Next, as shown in FIG. 15, in the NTr formation region Rb, n-type conductive impurities are ion-implanted using the sidewall insulating film 123b and the cap insulating film 122b as masks to form source / drain regions 130.
Thus, the semiconductor device shown in FIG. 11 is formed.

The PTr formed in this way has a source / drain portion formed of a SiGe film, which causes distortion of compressive stress and improves the PTr current driving capability.
Also in NTr, the use of SiC for the source / drain portions causes distortion opposite to the above and improves the current driving capability.

Here, the stress application to the channel formation region by the SiGe film is more effective as the SiGe layer is closer to the channel formation region and the volume of the SiGe film is larger. For this reason, when forming the recess, it is important to form the recess as wide as possible on the channel formation region side.
However, since the recess formation isotropically proceeds by wet etching, the recess becomes deeper as the etching time is extended to extend the recess to the channel formation region, and the film thickness of the finally formed SiGe film becomes larger. It will become thicker.

However, the SiGe film growth process has a problem that abnormal growth is likely to occur as the thickness of the SiGe film is increased. Abnormal growth may occur with a film thickness of, for example, about several tens of nm depending on conditions.
In the formation of the recess, if the lower direction of the substrate is also etched and scraped, the element isolation characteristics of the transistor are deteriorated.
For this reason, when forming the recess, it is important that the recess is formed so as not to be as deep as possible and to be spread toward the channel formation region.
JP-A-2005-57301 P. Bai et al, “A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect, Low-k ILD and 0.57 μm2 SRAM Cell”, International Electron Devices Meeting, pp 657-660, 2004.

  The present invention has been made in view of the above problems, and provides a method for manufacturing a semiconductor device capable of forming a recess by forming it in a channel forming region side so as not to be as deep as possible when forming the recess. Objective.

  In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate electrode on a surface of a semiconductor substrate via a gate insulating film, and recessing the semiconductor substrate at both sides of the gate electrode. Forming the mask, anisotropically forming a mask with higher selectivity on the bottom surface than the side surface of the recess on the inner wall surface of the recess, and performing etching while protecting the bottom surface of the recess with the mask, A step of extending the recess toward the gate electrode, a step of removing the mask, and a step of burying a conductor in the recess to form a pair of source / drain regions on both sides of the gate electrode.

In the semiconductor device manufacturing method of the present invention, a gate electrode is formed on the surface of a semiconductor substrate via a gate insulating film, and a recess is formed in the semiconductor substrate on both sides of the gate electrode.
Next, on the inner wall surface of the recess, a mask is anisotropically formed with higher selectivity on the bottom surface than on the side surface of the recess.
Next, etching is performed while protecting the bottom surface of the recess with a mask, and the recess is extended to the gate electrode side.
Next, the mask is removed, and a conductor is buried in the recess to form a pair of source / drain regions on both sides of the gate electrode.

  According to the method for manufacturing a semiconductor device of the present invention, when forming a recess, the recess can be formed by extending it toward the channel forming region side so as not to be as deep as possible. Deterioration of separation characteristics can be suppressed.

  Embodiments of a method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1 is a cross-sectional view of a semiconductor device according to the present embodiment.
For example, an STI (shallow trench isolation) type element isolation insulating film 11 is formed so as to separate active regions in the n-type semiconductor region 10a and the p-type semiconductor region 10b of the semiconductor substrate.
A P-channel MISFET (PTr) is formed in the n-type semiconductor region 10a, and an N-channel MISFET (NTr) is formed in the p-type semiconductor region 10b.

First, PTr will be described.
For example, the gate insulating film 20a is formed on the active region of the n-type semiconductor region 10a, the gate electrode 21a is formed on the upper layer, and the cap insulating film 22a is formed on the upper layer.
Side wall insulating films 23a are formed on both sides of the gate electrode 21a.

For example, the sidewall insulating film 23a is a silicon oxide film (TEOS film) by a low pressure CVD (chemical vapor deposition) method using TEOS (tetra-ethyl-ortho-silicate) as a source gas or an NSG (non-doped) by a plasma CVD method. It is formed of a silicon oxide film (NSG film) which is silicate glass. Alternatively, for example, it may be formed of a silicon nitride film (low temperature SiN film) formed by a low temperature CVD method at a film forming temperature of 650 ° C. or less, or may be formed of a stacked body of a silicon oxide film and a silicon nitride film. .
Further, the gate insulating film 20a is formed of, for example, silicon oxide, or may be formed of a metal oxide film containing hafnium or aluminum.
The gate electrode 21a is made of, for example, polysilicon, or may be an electrode containing a metal material.
The cap insulating film 22a is formed of silicon nitride or the like, and the element isolation insulating film 11 is formed of an NSG film or the like.

Further, a recess A is formed in a region to be a source / drain region on the surface of the n-type semiconductor region 10a on both sides of the gate electrode 21a, and a SiGe film 26 is embedded in the recess A to form a pair of source / drain regions. Is formed.
An extension region (not shown) is formed in the surface layer portion of the n-type semiconductor region 10a on the channel formation region side of the SiGe film 26.
The PTr is configured as described above.

  In the PTr described above, the SiGe film 26 is a stress film that applies compressive stress to the channel formation region of the PTr, and is a PTr with improved current driving capability and improved capability.

Next, NTr will be described.
A gate insulating film 20b is formed on the active region of the p-type semiconductor region 10b, a gate electrode 21b is formed thereon, and a cap insulating film 22b is formed thereon.
Further, sidewall insulating films 23b are formed on both sides of the gate electrode 21b.
The gate insulating film 20b, the gate electrode 21b, the cap insulating film 22b, and the sidewall insulating film 23b are each formed of the same material as the corresponding member of PTr, for example.

Further, a pair of source / drain regions 30 are formed in the p-type semiconductor region 10b on both sides of the gate electrode 21b.
An extension region (not shown) is formed in the surface layer portion of the p-type semiconductor region 10b on the channel forming region side of the source / drain region 30.
NTr is configured as described above.

Further, a stress film 31 made of, for example, silicon nitride and applying a tensile stress to the NTr is formed so as to cover the NTr.
Since the above-described stress film 31 is formed, the current driving capability is enhanced and the NTr has improved capability.

Next, a method for manufacturing the semiconductor device will be described.
First, as shown in FIG. 2A, for example, an STI type element isolation insulating film 11 made of an NSG film is formed so as to partition an active region in an n type semiconductor region 10a and a p type semiconductor region 10b of a semiconductor substrate. Form.
The n-type semiconductor region 10a becomes the PTr formation region Ra, and the p-type semiconductor region 10b becomes the NTr formation region Rb.

  Next, for example, in the above-described PTr formation region Ra and NTr formation region Rb, gate insulating films (20a, 20b) are formed on the n-type semiconductor region 10a and the p-type semiconductor region 10b in the active region by, eg, thermal oxidation. Form.

  Next, for example, in the PTr formation region Ra and the NTr formation region Rb, a conductive film such as polysilicon is deposited on the gate insulating films (20a, 20b) by a CVD method, and the film formation temperature is 650 ° C. or lower. Silicon nitride or the like is deposited by a CVD method and etched into a gate electrode pattern to form a gate electrode (21a, 21b) made of polysilicon or the like and a cap insulating film (22a, 22b) made of a low-temperature SiN film or the like. . The cap insulating films (22a, 22b) serve as a mask when etching the conductive film to be the gate electrode, and are also referred to as a hard mask.

Next, for example, in the PTr formation region Ra, p-type conductive impurities are ion-implanted into the surface layer portion in the active region of the n-type semiconductor region 10a using the gate electrode 21a and the cap insulating film 22a as a mask, thereby not shown. An extension region is formed.
Further, for example, in the NTr formation region Rb, an n-type conductive impurity is ion-implanted into the surface layer portion in the active region of the p-type semiconductor region 10b using the gate electrode 21b and the cap insulating film 22b as a mask, thereby extending an extension (not shown). Form a region.

  Next, as shown in FIG. 2B, for example, a silicon oxide film (TEOS film) 23 is deposited in the PTr formation region Ra and the NTr formation region Rb by a low pressure CVD method using TEOS as a source gas.

Next, as shown in FIG. 3A, for example, the PTr formation region Ra is opened and a resist film 24 is patterned in the NTr formation region Rb. In the PTr formation region Ra, for example, the TEOS film 23 is formed on the entire surface. Etchback is performed to form a sidewall insulating film 23a which is a TEOS film.
The sidewall insulating film 23a may be formed of an NSG film, a silicon nitride film, or the like as described above, or may be formed as a stacked body of materials selected from a TEOS film, an NSG film, a silicon nitride film, or the like. Also good.

  Next, as shown in FIG. 3B, for example, in the PTr formation region Ra, the surface of the n-type semiconductor region 10a in the active region is etched using the sidewall insulating film 23a and the cap insulating film 22a as a mask. A recess A is formed in a region to be a source / drain region of PTr.

The recess etching is performed so as to remove about 50 nm under the following conditions, for example.
・ Processing pressure: 20 mTorr
・ Processing temperature: 60 ℃
・ Source power: 500W, bias power: 50W
CF ₄ / O ₂ flow rate: 40/10 sccm

Next, as shown in FIG. 4A, for example, a mask 25 is anisotropically formed on the bottom surface of the recess A with higher selectivity.
Here, ashing oxidation is performed only on the bottom surface of the recess by anisotropic ashing using O ₂ ion species as a seed to form a silicon oxide film. The ashing oxidation used here is desirably performed by a ashing apparatus having a holo cathode type structure. Since the discharge impedance is small in the holocathode structure, a large current flows. That is, the plasma density is very high, and a large amount of O ₂ ions are incident on the substrate surface. Since the main reactive species is ions, it has high straightness, and the side wall of the recess is not oxidized so much, but only the bottom is actively oxidized.

The conditions for anisotropic ashing for forming the mask are as follows.
・ O ₂ flow rate: 100 sccm
・ RF power: 200W
・ Pressure: 0.1 Torr
・ Processing time: 2-3 minutes

Although the parallel plate type RIE apparatus can oxidize mainly O ₂ ions, the holocathode type treatment is more effective because the ion density is small.

  Alternatively, in the step of forming the mask 25, the mask 25 may be formed by anisotropically forming a silicon nitride film or a silicon carbide film on the bottom surface of the recess A by a highly directional sputtering method or the like.

Next, as shown in FIG. 4B, for example, etching is performed while protecting the bottom surface of the recess A with a mask 25, and the recess A is expanded to the gate electrode 21a side.
Here, for example, the etching is performed so that the end of the recess A on the gate electrode 21a side is as close as possible to the channel formation region side so as not to reach directly below the gate electrode 21a.
Since the mask 25 exists at the bottom of the recess A, etching in the downward direction of the substrate is suppressed, and etching in the lateral direction is promoted.

As etching for extending the recess A to the gate electrode 21a side, isotropic etching is performed under the following conditions.
・ Processing pressure: 20 mTorr
・ Processing temperature: 60 ℃
・ Source power: 500W, bias power: 50W
CF ₄ / O ₂ flow rate: 40/10 sccm

  Next, as shown in FIG. 5A, the resist film 24 is removed by, for example, an ashing process.

Next, a SiGe film is selectively epitaxially grown in the recess A portion. Since the surface of the SiGe film growth region needs to be Si, as a pretreatment for the SiGe film growth, as shown in FIG. Further, the mask 25 existing on the bottom surface of the recess A and the natural oxide film and the damaged layer existing on the side wall of the recess A are removed.
In general, a wet etching process equivalent to a thermal oxide film of 1 to 3 nm is performed by a DHF process, but the following dry cleaning technique is used to remove the recess oxide film with a higher selectivity.

  In the etching process for removing the mask 25, for example, as a first process, the surface of the mask 25 exposed on the inner wall surface of the recess A is first treated with an etching gas containing ammonia and hydrogen fluoride. Next, as the second treatment, the product formed in the first treatment is decomposed and evaporated.

The first process will be described.
For example, the inner wall surface of the recess A is chemically etched in a mixed gas atmosphere composed of NH ₃ , HF, and Ar.
Specifically, after transferring the wafer to the chemical etching chamber of the etching apparatus and placing the wafer on the wafer stage, the following gas atmosphere is created, the mask 25 and the natural oxide film are chemically reacted, and the inside of the recess A A complex layer containing Si is formed on the wall surface.

The conditions for the first process are as follows.
-Chamber pressure: 10-30 mTorr, for example 20 mTorr
・ HF flow rate: 10-50 sccm, 40 mTorr
· NH ₃ flow rate: 10~50sccm, 40mTorr
Ar flow rate: 50-100 sccm, 80 mTorr
-Substrate temperature: 20-40 ° C, for example 35 ° C

The chemical reaction in the above mixed gas atmosphere is explained as follows.
When HF / NH ₃ / Ar is supplied in the vapor phase to the chemical etching chamber, the gas is Langmuir adsorbed on the surface of the exposed natural oxide film (silicon oxide). At the same time, the chemical reaction shown by the following chemical formulas (1) and (2) proceeds.

[Chemical 1]
SiO ₂ + 4HF → SiF ₄ + 2H ₂ O (1)
SiF ₄ + 2NH ₃ + 2HF → (NH ₄ ) ₂ SiF ₆ (2)

That is, once SiF ₄ and H ₂ O are generated by HF, the (NH ₄ ) ₂ SiF ₆ complex is formed on the surface of the natural oxide film made of silicon oxide by a chemical reaction between NH ₃ , HF and SiF ₄ . A layer is to be formed.
This reaction is governed by gas adsorption at the molecular number layer level by Langmuir adsorption, and self-stops when the coverage of adsorbed gas molecules is saturated.

Next, the second process will be described.
The wafer on which the (NH ₄ ) ₂ SiF ₆ complex layer was formed was immediately transferred to the heating chamber and placed on the heating stage, and then the heater heating was started, and (NH ₄ ) ₂ SiF ₆ Is decomposed into SiF ₄ or the like and evaporated.

The conditions for the second process are as follows.
-Chamber pressure: 500-700 mTorr, for example 675 mTorr
-Temperature: 100-200 ° C, for example 175 ° C

This reaction is illustrated by the following chemical formula (3). When the substrate temperature is heated to the above temperature, the (NH ₄ ) ₂ SiF ₆ complex layer 27c formed on the inner wall surface of the recess A decomposes and evaporates into SiF ₄ , NH ₃ , HF, etc. The gas is exhausted by a dry pump.

[Chemical 2]
(NH ₄ ) ₂ SiF ₆ → SiF ₄ + 2NH ₃ + 2HF (3)

In the chemical etching described above, the etching selectivity between the thermal oxide film (natural oxide film) and the TEOS film is reversed from that in the case of etching using a conventional DHF chemical solution.
In the case of the DHF chemical solution, the etching amount of the TEOS film is about 5 to 7 when the etching amount of the thermal oxide film is 1, whereas the chemical etching reaction by the gas reaction of the present embodiment is performed. The etching amount of the TEOS film is about 0.5 to 1.0 when the etching amount of the thermal oxide film is 1.
The same applies to the NSG film. In the case of a DHF chemical solution, the etching rate is about seven times that of the thermal oxide film, but the above chemical etching has an etching rate equivalent to that of the thermal oxide film.
The same applies to the low-temperature SiN film, and the above-described chemical etching can achieve an etching rate equivalent to that of the thermal oxide film.

Further, the mask 25 and the natural oxide film may be removed by DHF treatment.
Alternatively, when the mask 25 is formed of a material other than silicon oxide, the mask may be removed under etching conditions other than those described above, and the natural oxide film may be removed by etching as described above.

  Next, as shown in FIG. 6A, a SiGe film is selectively epitaxially grown on the surface of the recess A from which silicon is exposed to form, for example, a SiGe film 26 doped with boron.

The conditions for forming the SiGe film 26 are as follows.
・ Processing temperature: 700 ℃
・ Processing pressure: 10 Torr
DCS / GeH ₄ / HCl = 50/100/20 sccm

The SiGe film 26 becomes a source / drain region as it is, and a PTr is formed.
The SiGe film 26 is a stress film that applies a compressive stress to the channel formation region of the PTr, and the current driving capability is enhanced to improve the PTr capability.

  Next, as shown in FIG. 6B, for example, the NTr formation region Rb is opened and a resist film 27 is patterned in the PTr formation region. In the NTr formation region Rb, for example, the TEOS film 23 is etched on the entire surface. Then, a sidewall insulating film 23b which is a TEOS film is formed.

  Next, as shown in FIG. 7A, for example, in the NTr formation region Rb, an n-type conductive impurity is used as an active region of the p-type semiconductor region 10b using the sidewall insulating film 23b and the cap insulating film 22b as a mask. Source / drain regions 30 are formed by implanting ions into the surface layer portion in FIG. Thereby, NTr is formed.

Next, for example, in the NTr formation region Rb, the nitride film is deposited by covering the NTr by the CVD method, and the stress film 31 is formed. The configuration shown in FIG. 1 can be obtained as described above.
The stress film 31 is a stress film for applying a tensile stress to the channel formation region of the NTr, and the current drive capability is enhanced to improve the NTr capability.
Alternatively, similar to PTr, a recess is formed also in NTr, a SiC film is selectively epitaxially grown as a source / drain in the recess, and a tensile stress is applied to the channel formation region by the SiC film to improve transistor characteristics. be able to.

The conditions for forming the SiC film are as follows, for example.
・ Processing temperature: 700 ℃
・ Processing pressure: 10 Torr
SiH ₄ / SiH ₃ CH ₃ / HCl / AsH ₃ = 30/50/20/10 sccm

  According to the method of manufacturing a semiconductor device according to the above-described embodiment, in order to increase the PTr driving capability, the recess is formed in the method of forming the recess in the source / drain region and forming the SiGe film as the stress film. In addition, it can be formed so as not to be as deep as possible and spread toward the channel formation region side, so that abnormal growth during epitaxial growth of the SiGe film and deterioration of element isolation characteristics of the transistor can be suppressed.

Second Embodiment FIG. 8 is a sectional view of a semiconductor device according to this embodiment.
Although substantially the same as the semiconductor device of the first embodiment, the SiGe film 26 embedded in the recess A as the source / drain of the PTr is formed by a laminated body of a non-doped SiGe film 28 and a boron-doped SiGe film 29. Is different.

A method for manufacturing the semiconductor device of the present embodiment will be described.
First, the steps up to the step of removing the mask 25, the natural oxide film, and the damaged layer on the inner wall surface of the recess A shown in FIG. 9A are performed in the same manner as in the first embodiment.
Next, as shown in FIG. 9B, the SiGe film is selectively epitaxially grown on the surface of the recess A where the silicon is exposed, and the non-doped SiGe film is formed so as to embed a part of the recess A. 28 is formed.
Next, as shown in FIG. 10A, a boron-doped non-doped SiGe film 29 is formed so as to embed the recess A in the upper layer of the non-doped SiGe film 28.

  In the subsequent steps, as in the first embodiment, as shown in FIG. 10B, sidewall insulating films 23b are formed in the NTr formation region Rb, source / drain regions 30 are formed, and NTr and To do.

  According to the method of manufacturing a semiconductor device according to the above-described embodiment, in order to increase the PTr driving capability, the recess is formed in the method of forming the recess in the source / drain region and forming the SiGe film as the stress film. In addition, it can be formed so as not to be as deep as possible and spread toward the channel formation region side, so that abnormal growth during epitaxial growth of the SiGe film and deterioration of element isolation characteristics of the transistor can be suppressed.

The present invention is not limited to the above description.
For example, although the SiGe film is embedded as the source / drain of the PTr in the embodiment, it is also possible to embed other conductive stress films. For example, when applied to NTr, an SiC film may be formed. it can.
In addition, various modifications can be made without departing from the scope of the present invention.

  The method of manufacturing a semiconductor device according to the present invention can be formed so as not to become as deep as possible when forming a recess, and can be formed to be widened toward the channel formation region side, and abnormal growth during the epitaxial growth of a SiGe film or deterioration of element isolation characteristics of a transistor can be achieved. Can be suppressed.

FIG. 1 is a sectional view of a semiconductor device according to the first embodiment of the present invention. 2A and 2B are cross-sectional views showing the manufacturing process of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 3A and FIG. 3B are cross-sectional views illustrating manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 4A and FIG. 4B are cross-sectional views illustrating manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 5A and FIG. 5B are cross-sectional views illustrating manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6A and FIG. 6B are cross-sectional views showing manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 7A and FIG. 7B are cross-sectional views illustrating manufacturing steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 8 is a sectional view of a semiconductor device according to the second embodiment of the present invention. FIG. 9A and FIG. 9B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 10A and FIG. 10B are cross-sectional views showing the manufacturing process of the semiconductor device manufacturing method according to the second embodiment of the present invention. FIG. 11 is a cross-sectional view of a conventional semiconductor device. 12 (a) and 12 (b) are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to a conventional example. FIG. 13A and FIG. 13B are cross-sectional views showing the manufacturing process of the manufacturing method of the semiconductor device according to the conventional example. 14 (a) and 14 (b) are cross-sectional views showing the manufacturing process of the semiconductor device manufacturing method according to the conventional example. FIG. 15 is a schematic diagram for explaining the problems of the conventional example.

Explanation of symbols

10a ... n-type semiconductor region, 10b ... p-type semiconductor region, 11 ... element isolation insulating film, 20a, 20b ... gate insulating film, 21a, 21b ... gate electrode, 22a, 22b ... cap insulating film, 23a, 23b ... side wall Insulating film 24 ... resist film 25 ... mask 26 ... SiGe film 27 ... resist film 28 ... non-doped SiGe film 29 ... boron-doped SiGe film 30 ... source / drain region 31 ... stress film 110a ... n-type semiconductor region, 110b ... p-type semiconductor region, 111 ... element isolation insulating film, 120a, 120b ... gate insulating film, 121a, 121b ... gate electrode, 122a, 122b ... cap insulating film, 123a, 123b ... side wall insulating film 124 ... resist film 126 ... SiGe film 127 ... resist film 130 ... source Rain area, A ... recess

Claims (11)

Forming a gate electrode on the surface of the semiconductor substrate via a gate insulating film;
Forming a recess in the semiconductor substrate at both sides of the gate electrode;
Forming an anisotropically anisotropic mask on the inner wall surface of the recess with a higher selectivity on the bottom surface than the side surface of the recess;
Etching while protecting the bottom surface of the recess with the mask, and extending the recess to the gate electrode side;
Removing the mask;
And a step of burying a conductor in the recess to form a pair of source / drain regions on both sides of the gate electrode. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the mask, a silicon oxide film is anisotropically formed on the bottom surface of the recess as the mask. The method for manufacturing a semiconductor device according to claim 2, wherein in the step of forming the mask, the mask is formed by performing plasma oxidation with O ₂ ion species. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the conductive layer, a SiGe film is formed on the inner wall surface of the recess by epitaxial growth. The step of removing the mask includes a first process for treating the surface of the mask with an etching gas containing ammonia and hydrogen fluoride, and a second process for decomposing and evaporating the product formed in the first process. A method for manufacturing a semiconductor device according to claim 2. The method for manufacturing a semiconductor device according to claim 5, wherein the product formed in the first process in the etching process and decomposed and evaporated in the second process is a (NH ₄ ) ₂ SiF ₆ complex. The method for manufacturing a semiconductor device according to claim 5, wherein the second treatment is a heat treatment in which a temperature of 900 to 1100 ° C. is applied. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of removing the mask, the mask is removed by wet etching. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of removing the mask, a natural oxide film formed on the inner wall surface of the recess is removed simultaneously. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the mask, a silicon nitride film or a silicon carbide film is anisotropically formed on the bottom surface of the recess as the mask. And a step of forming a sidewall insulating film made of a silicon oxide film and / or a silicon nitride film on both sides of the gate electrode between the step of forming the gate electrode and the step of forming the recess. Item 14. A method for manufacturing a semiconductor device according to Item 1.

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