WO2011019378A1 - Dispositif à transistor mos à grille en tranchée isolée et son procédé de fabrication - Google Patents

Dispositif à transistor mos à grille en tranchée isolée et son procédé de fabrication Download PDF

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Publication number
WO2011019378A1
WO2011019378A1 PCT/US2010/002198 US2010002198W WO2011019378A1 WO 2011019378 A1 WO2011019378 A1 WO 2011019378A1 US 2010002198 W US2010002198 W US 2010002198W WO 2011019378 A1 WO2011019378 A1 WO 2011019378A1
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WIPO (PCT)
Prior art keywords
trench
gate
semiconductor device
region
polysilicon
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PCT/US2010/002198
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English (en)
Inventor
John Chen
Il Kwan Lee
Hong Chang
Wenjun Li
Anup Bhalla
Hamza Yilmaz
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Alpha And Omega Semiconductor Incorporated
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Priority claimed from US12/583,191 external-priority patent/US8193580B2/en
Priority claimed from US12/583,192 external-priority patent/US8236651B2/en
Application filed by Alpha And Omega Semiconductor Incorporated filed Critical Alpha And Omega Semiconductor Incorporated
Publication of WO2011019378A1 publication Critical patent/WO2011019378A1/fr

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66719—With a step of forming an insulating sidewall spacer
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
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    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate

Definitions

  • MOSFETs Shielded gate trench Metal Oxide Semiconductor Field Effect Transistors
  • existing fabrication techniques for shielded gate MOSFETs are typically complex and expensive, usually requiring 6 or more masks to be applied during processing.
  • FIG. IA is a diagram illustrating a top view of an embodiment of a shielded gate MOSFET structure.
  • FIG. IB is a flowchart illustrating an embodiment of a process for fabricating a shielded gate MOSFET such as 100.
  • FIG. 2 is a diagram illustrating an example of a first mask used in an embodiment of a device fabrication process.
  • FIG. 3 is a diagram illustrating an example of a second mask used in an embodiment of a device fabrication process.
  • FIG. 4 is a diagram illustrating an example of a third mask used in an embodiment of a device fabrication process.
  • FIG. 5 is a diagram illustrating an example of a fourth mask used in an embodiment of a device fabrication process.
  • FIGS. 6AA'-32AA' are cross sectional diagrams illustrating the AA' region of structure 100 during the fabrication process.
  • FIGS. 6BB'-32BB' are cross sectional diagrams illustrating the BB' region of structure 100 during the fabrication process.
  • FIGS. 6CC-32CC are cross sectional diagrams illustrating the CC region of structure 100 during the fabrication process.
  • FIGS. 6LL'-32LL' are cross sectional diagrams illustrating the LL' region of structure 100 during the fabrication process.
  • FIG. 33AA' is a cross sectional diagram illustrating the AA' cross section of an example device.
  • FIG. 33BB' is a cross sectional diagram illustrating the BB' cross section of an example device.
  • FIG. 33CC is a cross sectional diagram illustrating the CC cross section of an example device.
  • FIG. 33DD' is a cross sectional diagram illustrating the DD' cross section of an example device.
  • FIG. 34 is a cross sectional diagram illustrating the AA' cross section of another embodiment of a device.
  • FIG. 35 is a cross sectional diagram illustrating the AA' cross section of yet another embodiment of a device.
  • the invention can be implemented in numerous ways, including as a process; an apparatus; a system; a composition of matter; a computer program product embodied on a computer readable storage medium; and/or a processor, such as a processor configured to execute instructions stored on and/or provided by a memory coupled to the processor.
  • these implementations, or any other form that the invention may take, may be referred to as techniques.
  • the order of the steps of disclosed processes may be altered within the scope of the invention.
  • a component such as a processor or a memory described as being configured to perform a task may be implemented as a general component that is temporarily configured to perform the task at a given time or a specific component that is manufactured to perform the task.
  • the term 'processor' refers to one or more devices, circuits, and/or processing cores configured to process data, such as computer program instructions.
  • Embodiments of shielded gate MOSFET devices and fabrication process are disclosed.
  • the fabrication process employs a self aligned contact scheme and requires only four masks.
  • the resulting shielded gate MOSFET devices are less expensive to produce and have improved device characteristics, such as higher breakdown voltage.
  • FIG. IA is a diagram illustrating a top view of an embodiment of a shielded gate MOSFET structure.
  • structure 100 is built on a semiconductor substrate 102.
  • Active regions of the structure include active gate trenches such as 104, in which gates are formed.
  • the active regions further include source/body contact openings such as 106, in which contacts are formed to electrically connect source regions and body regions to the source metal 116.
  • the active regions also include source polysilicon (poly) pickup contacts such as 108.
  • poly source electrode is disposed in the source pickup trench 118 and is electrically connected through source pickup contact opening 108 to source metal 116, which in turn is electrically connected to the source and body regions of the device.
  • the active regions are surrounded by trenches such as 110, which serve several purposes, including as termination trenches that separate high potential areas (such as the drain) from low potential areas (such as the source), and as gate runners configured to form electrical connections with the gate electrodes in active gate trenches.
  • termination/gate runner trenches 1 10 are mostly covered by source metal 116, which, as will be shown in the cross sectional views below, is insulated from the gate electrodes in trenches 104 and 110 by a dielectric layer.
  • Termination/gate runner trenches 110 further include portions that form gate runner extension trenches 120.
  • the gate runner extension trenches extend into gate metal area 1 14 and serve as gate pickup trenches where gate pickup contact openings 112 are disposed for electrically connecting gate runner to gate metal 114.
  • the gate runner extension trenches 120 further interconnect the gate runners in different areas such as 116-1 and 116-2. In the example shown, the gate runner/termination trenches 110 and source poly pickup trenches 118 are wider than the active gate trenches 104.
  • FIG. IB is a flowchart illustrating an embodiment of a process for fabricating a shielded gate MOSFET such as 100.
  • Process 150 involves four masks.
  • a number of trenches are formed using a first mask.
  • a first set of polysilicon regions also referred to as source poly, shield poly, or poly 1 are formed in the plurality of trenches.
  • one or more inter-polysilicon dielectric regions and one or more termination protection regions are formed using a second mask.
  • polysilicon is disposed in some of the trenches to form a second set of polysilicon regions, also referred to as gate poly or poly 2.
  • a first electrical contact opening is made to a gate poly, and a second electrical contact opening is made to a source poly.
  • a metal layer is disposed.
  • a source metal region and a gate metal region are formed using a fourth mask.
  • Fabrication process 150 is discussed in greater detail below in connection with
  • FIGS. 2-5 which illustrate the top views of four masks used in the processes
  • FIGS. 6AA'-32AA', 6BB'-32BB', 6CC-32CC, and 6LL ⁇ 32LL' which respectively illustrate cross sectional views along AA', BB', CC, and LL' of FIG. IA.
  • AA' extends across active gate trenches and source/body contacts in an active region, as well as a termination/gate runner trench that terminates the active region and surrounds the active area.
  • BB' extends along a set of source/body contacts, and intersects a source poly pickup contact trench that lies between the source/body contacts.
  • CC extends along a set of active gate trenches, and intersects a source poly pickup contact trench that lies between the set of active gate trenches.
  • LL' extends through a termination region, and intersects a gate pick up trench (which, in this case, is an extension of the termination/gate runner trench) as well as a gate pickup contact.
  • the cross sectional diagrams of the device are illustrated in FIGS. 32AA', 32BB', 32CC, and 32LL' and are discussed in greater detail in connection with these figures. [0025] In the following discussion, an N type device is described for purposes of illustration. P type devices may be fabricated using a similar process. In FIGS.
  • an N type substrate 602 i.e., an N + silicon wafer with an N " epi layer grown on it
  • Epi doping concentration is approximately 3El 6 - IE 17 dopants/cm 3 , with thickness of 2 - 4 um, and substrate resistivity of 0.5 - 3 mohm*cm.
  • a silicon oxide layer 604 is formed on the substrate by deposition or thermal oxidation.
  • a nitride layer 606 is disposed on top of the silicon oxide layer.
  • the thickness of the silicon oxide layer is approximately 5OO-15OOA, and the thickness of the nitride layer is approximately 1500A.
  • FIG. 2 is a diagram illustrating the top view of an example of a first mask, also referred to as the trench mask.
  • Trench mask 200 is used to pattern the PR layer.
  • the PR areas corresponding to the shaded areas of the mask are not exposed, and the PR areas corresponding to the un-shaded areas of the mask are exposed.
  • positive PR is used, thus the unexposed areas are kept and the exposed areas are removed.
  • Negative PR may also be used, and the mask would be modified accordingly.
  • the trench mask defines active gate trenches 204, source poly pickup trenches such as 208, and gate runner/termination trenches such as 210.
  • different types of trenches have different width: the active gate trenches are the narrowest, the source poly pickup trenches are medium width, and the gate runner/termination trenches are the widest.
  • the widths of the active gate trenches, the source poly pickup trenches, and the gate runner/termination trenches are approximately 0.6um, l.Oum, and 2.0um, respectively.
  • Low grade masks such as masks with critical dimension of 0.35 um can be used to fabricate the device therefore reduce the cost of masks required.
  • the residual PR layer forms termination trench opening 702 and active gate trench openings 704.
  • the residual PR layer forms source poly pickup contact opening 706.
  • the residual PR layer forms gate pickup contact opening 708.
  • HM hard mask
  • FIGS. 8AA', 8BB', and 8LL' trench openings are formed in exposed areas.
  • FIG. 8CC all the nitride layer and silicon oxide layer are removed along the CC cross section.
  • a trench etch follows.
  • the trench openings are etched deeper.
  • the target depth of the trenches is approximately 0.3um ⁇ 0.5um.
  • FIG. 9CC a silicon layer is removed along the CC cross section.
  • a thin layer of oxide is deposited or grown thermally in the trench openings, lining both the trench bottom and the trench walls.
  • the oxide layer is approximately 200A thick in some embodiments.
  • an additional layer of nitride is deposited and etched back along the horizontal surface. In some embodiments, the thickness of the nitride layer is approximately 2200A.
  • Nitride spacers 1000, 1002, 1004 are formed along the trench walls after blanket etch back, as shown in FIGS. 10AA', lOBB', and 10LL'. The CC cross section is unchanged since the liner oxide and the nitride are etched off.
  • any exposed liner oxide layer in the bottom of the trench opening is removed and a blanket silicon etch step is performed to further deepen the trenches in FIGS. 1 IAA', 1 IBB', 1 ICC, and 1 ILL'.
  • the resulting trench depth is on the order of
  • the nitride spacers allow for a self-aligned etching step that does not require additional alignment steps such as an additional alignment mask, thus achieving trench slope etch.
  • a wider trench opening results in a deeper trench than a narrower trench opening due to the nature of Si etch loading factor.
  • the resulting gate runner trench 1102 is deeper than active gate trench 1104, as shown in FIG. 1 IAA'.
  • the depth of the trenches may range from a few hundred angstroms to a few microns.
  • Round hole (R/H) etch ranging from 25 ⁇ A ⁇ 5O ⁇ A is performed to make the corners of the trenches smoother to prevent high electric fields due to sharp corner.
  • one or more oxide layers are deposited or thermally grown.
  • a sacrificial oxide layer of approximately 5O ⁇ A is optionally grown and removed to improve the silicon surface.
  • a layer of gate oxide of approximately 25 ⁇ A is grown, followed by a layer of high temperature thermal oxide (HTO) of
  • Polysilicon is disposed, as shown in FIGS. 13AA-13LL ⁇
  • the thickness of the poly is approximately 12000A, which is greater than half the width of the widest trench.
  • This layer of poly is sometimes referred to as source poly, shield poly, or poly 1.
  • the remaining poly has a thickness of approximately 6000A.
  • High density plasma (HDP) oxide is then deposited and densified.
  • the densification takes place at a temperature of approximately 1150 0 C and lasts for approximately 30 seconds.
  • the oxide on the trench sidewalls has a substantially uniform thickness (labeled as tl in FIGS. 15AA'-15LL') throughout the device.
  • tl is approximately ranging from 2000A ⁇ 4000A to completely fill only the narrow trenches (such as active gate trencher and source contact trenches), but partially fill the wider trenches such as gate runner trench 1502 and gate pickup trench 1504.
  • the wider trenches are not completely filled, allowing a gate electrode to be disposed in the space not completely filled by the HDP oxide in such wider trenches in a later step.
  • the thickness of the oxide layer tl is greater than half the width of the trench, and thus the oxide linings merge and completely fill the trench.
  • Oxide chemical mechanical polish (CMP) is performed. As shown in FIGS.
  • the CMP process is used to polish the oxide until the top surface of the oxide is even with the nitride surface, which serves as an etch stop.
  • FIGS. 17AA'- 17LL' show that another layer of oxide is added.
  • the thickness of the oxide layer is approximately IOOOA ⁇ 2000A in some embodiments.
  • the thickness of this oxide controls the degree of undercut of wet etching under the second mask.
  • This oxide film also protects the nitride in all the non-active area of the device. The protected nitride allows maskless blanket etching of the Si later.
  • a layer of photo resist is then spun on the surface of the structure and a second mask is applied.
  • FIG. 3 is a diagram illustrating the top view of an example of a second mask. The outline of the previous mask, the trench mask, is shown in dashed lines.
  • the outline of the second mask also referred to as the poly cover mask, is shown in solid lines.
  • the poly cover mask is used to facilitate the formation of the inter-polysilicon oxide region and the termination protection region.
  • PR in area 302 (shaded area) of the poly cover mask is not exposed and kept, thus covering the areas underneath and protecting the areas from oxide wet etching.
  • PR in areas such 304 (un-shaded areas) of the mask is exposed and removed. Areas not covered by PR are etched.
  • the active MOSFET cells are formed within openings such as 304. As will be described in greater detail below, the edges of the openings are placed close to termination trenches such as 306 and 308 to facilitate asymmetric etching of these trenches.
  • FIGS. 18AA', 18BB', 18CC, and 18LL' show the pattern of the PR cover after the exposed portions have been removed.
  • the PR cover in the AA' cross sectional area extends into termination region at 1802, fills termination trench at 1804, and extends over into the active area at 1806.
  • a portion of the oxide under the PR will be removed by etching.
  • Mask overlap and wet etch undercut together determine the final profile.
  • the oxide undercut depth ranges from 0.6um ⁇ 1.5um.
  • the PR cover shields source poly pickup trench 1806 from being etched.
  • the PR cover shields a portion of the nitride in the desired contact location.
  • the gate pick up contact trench and its adjacent areas are covered by PR.
  • Some oxide in areas unmasked by PR is removed, such that the remaining oxide is held at desired height. Some oxide near the edges of the PR is also removed.
  • FIG. 19AA' a portion of oxide in gate runner trench 1902, located underneath the PR and close to the PR edge is removed.
  • the amount of oxide that is etched can be controlled by adjusting the position of edge 1904 of PR layer. Extending edge 1904 closer to the active region would result in less oxide being etched, and extending the edge further away from the active region would have the opposite effect.
  • the amount of oxide etched away can vary in different embodiments. In the example shown, enough oxide is etched away such that the remaining oxide lining the trench wall in the vertical direction is approximately uniform in thickness.
  • IPD inter- poly dielectric
  • the PR is then removed, and a layer of gate oxide is disposed or thermally grown.
  • the added oxide layer is approximately 45 ⁇ A thick in some embodiments.
  • trench walls such as 2002, 2004, 2006, and 2008 are lined with oxide.
  • Termination trench 2010 has asymmetric sidewalls, where sidewall 2008 has a thicker oxide layer than sidewall 2002.
  • FIGS 21 AA'-21LL' approximately 8000A ⁇ 12000A of poly is disposed in various trenches.
  • the disposed poly is etched back, forming gate poly such as 2102, 2104, 2106, and 2108.
  • the poly surface is approximately 500-lOO ⁇ A below nitride spacer bottom reference level.
  • a layer of metal such as titanium or cobalt is deposited and annealed. Where the metal is in contact with the poly, a polycide layer is formed. The titanium or cobalt metal over the oxide or nitride does not form suicide and is removed.
  • polycide is formed at 2110, 2112, 2114, 2116, and 2118 on top of gate poly electrodes.
  • FIG. 22AA' exposed nitride spacers in the runner gate trench and the active gate trenches are removed through a wet etch process.
  • FIG. 22BB' the exposed nitride layer is removed, as well as a portion of the nitride layer underneath oxide 2202.
  • Nitride spacers 2204 and 2206 are protected from the etching process by the oxide layer.
  • FIG. 22LL' nitride layer 2208 are protected by oxide layer 2212.
  • FIGS. 23AA'-23LL ⁇ body implant takes place.
  • the device is bombarded with dopant ions with an angle.
  • the implant forms body regions such as 2304.
  • Boron ions with a dosage level of approximately 1.8el3 at 60KEV-180 KeV are used to form an N-channel device.
  • Other types of ions can be used.
  • Phosphorous ions can be used for P-channel devices.
  • source implant takes place with a zero tilt angle.
  • the device is again bombarded with dopant ions.
  • Arsenic ions with a dosage level of 4el5 at 40KeV- 80KeV are used.
  • Source regions such as 2402 are formed within body regions such as 2304.
  • the oxide-nitrite-oxide barrier blocks implant ions and prevents source and body regions from being formed, thus improving device behavior in its off or blocking state.
  • oxide ranging from 5000A ⁇ 8OO ⁇ A is deposited through to fill trench openings and block source and gate poly regions.
  • a chemical vapor deposition (CVD) process is used to deposit Low
  • LTO Temperature Oxide
  • BPSG Boron Phosphorus Silicate Glass
  • the oxide is etched back through a dry etch process where the oxide is etched down and stopped by endpoint etch on the active cell silicon surface.
  • the silicon etch depth is range from 0.6um ⁇ 0.9um depending on device
  • Exposed silicon areas are etched, while areas protected by oxide and/or nitride are not etched. Since the etching process does not require an additional mask, it is referred to as a self-aligned contact process.
  • FIG. 4 is a diagram illustrating an example of a third mask.
  • the third mask is also referred to as a poly pickup mask or contact mask.
  • features that are masked include gate poly pickup contacts such as 402, and source poly pickup contacts such as 404.
  • contact patterns are formed by removing exposed PR.
  • FIG. 29AA'-29LL' contact etch is performed. PR is then removed. Body contact implant is performed.
  • P-type material for example BF 2 ions at a dosage level of 1. OeI 5 at 40KeV
  • the implantation process is followed by contact implant activation.
  • the contact implant activation process is a Rapid Thermal Process (RTP) at approximately 1000 0 C for 30 seconds.
  • RTP Rapid Thermal Process
  • Active Thermal Drive can be used to activate the contact implant.
  • source polys such as 2904 and 2906 are unaffected by the implantation since the source polys are already heavily doped with source type dopants.
  • barrier metal such as Ti and TiN are deposited, followed by RTP to form Ti suicide near the contact region.
  • the thicknesses of Ti and TiN used in some embodiments are 300A and lOOOA, respectively.
  • W is then deposited. In some embodiments 4000A ⁇ 6OO ⁇ A of W is deposited. The deposited W is etched back up to the oxide surface to form individual W plugs such as 3002, 3004, 3006, and 3008.
  • FIG. 5 is a diagram illustrating an example of a fourth mask, also referred to as a metal mask. Shaded regions 502 and 504 correspond to the source metal and the gate metal, respectively. The un-shaded portion corresponds to metal portion that is etched away to separate the source metal region and the gate metal region.
  • a metal layer is deposited.
  • a metal layer is deposited.
  • AlCu is used to form a metal layer that is approximately 3um ⁇ 6um thick. PR is then disposed and exposed using the metal mask. Metal in exposed regions such as 3102 and 3104 is etched away.
  • FIGS. 32AA'-32LL' illustrate cross sectional views of the final device.
  • FIG. 33AA' is a cross sectional diagram illustrating the AA' cross section of an example device.
  • Device 3300 includes an asymmetric trench 3306, and active gate trenches 3302 and 3304.
  • Asymmetric trench 3306 serves as a termination trench separating a high potential area (i.e. the drain) from a low potential area (i.e., the source).
  • sidewall 3308 is in close proximity to the termination region and sidewall 3310 is in close proximity to the active region.
  • the oxide layer 3338 lining between sidewall 3308 and top gate poly 3316 is thicker than the oxide layer 3328 lining between sidewall 3310 and top gate poly 3316.
  • trench 3306 also serves the additional purpose of a gate runner trench that surrounds the active area and interconnects with active gate trenches.
  • the asymmetric trench and the active gate trenches each include a top poly electrode (e.g., poly 3316, 3312, or 3314), also referred to as the gate poly since it function as the gate, or poly 2 since it is formed from the second poly deposition process during fabrication.
  • Each top poly electrode further includes a polycide layer 3340 disposed on top surface of gate electrode to improve the conductivity along the gate.
  • Each trench further includes a bottom poly electrode (e.g., poly 3318, 3320, and 3322), also referred to as the source poly since it is connected to the source, or poly 1 since it is formed from the first poly deposition process during fabrication, or shield poly since it shields the gate poly from high voltages.
  • the gate poly is separated from the source poly by inter-poly dielectric regions formed by oxide.
  • the oxide layer e.g., oxide layer in region 3324
  • oxide layer 3326 the oxide layer surrounding the source/shield poly and lining the sidewalls of the bottom portion of the trench.
  • oxide layer 3328 is substantially the same thickness as the active gate oxide 3324 as they are formed in the same process.
  • active area source metal 3334 is insulated from gate electrodes 3312, 3314 and 3316 by a dielectric layer such as oxide 3309.
  • Source metal layer 3334 electrically connects to source regions 3332 and body regions 3348 through a conductor 3330 such as Tungsten plug that fills the source body contact openings and extends from source metal penetrating through the source regions into the body regions.
  • Body contact implant regions 3346 improve the Ohmic contact between the body regions and the conductor 3330.
  • oxide 3338 extends along nitride spacer 3336 to substantially the same top surface of nitride layer 3342.
  • Nitride layer 3342 and nitride spacer 3336 seal the oxide layer 3344 deposited on the top surface of epi layer in termination area. The bottom of oxide layer 3344 or the top surface of epi layer in termination area is substantially aligned with the top surface of oxide layer 3309 in the active area.
  • nitride spacer 3336 serves as a reference to align the top surface of source regions 3332.
  • the top surfaces of top poly gate electrodes 3321, 3314 and 3316 are recessed from this reference mark and lie below the top surface of the source regions 3332.
  • Gate metal 3335 disposed on top of nitride layer 3342 is separated from source metal and electrically connects to gate electrode in another location as shown in Fig. 33LL'.
  • FIG. 33BB' is a cross sectional diagram illustrating the BB' cross section of an example device.
  • source pickup trench 3352 has a source polysilicon electrode 3354 that is electrically connected to the source metal 3356 via a metal conductor such as a tungsten plug filling a contact hole 3358 within the trench 3352.
  • the contact hole has a width narrower than the polysilicon electrode and extends vertically from the source polysilicon electrode to source metal layer 3356 deposited on top surface.
  • the top surface of the source poly electrode is positioned below the bottom of body region 3350 (body junction).
  • the source pickup trench 3352 may be wider and deeper than the active gate trenches 3302 and 3304 as shown in Fig. 33AA'.
  • the source pickup trenches may be narrower and shallower than the active gate trenches.
  • FIG. 33CC is a cross sectional diagram illustrating the CC cross section of an example device.
  • source poly 3360 is connected to source metal layer 3356 via tungsten plug 3362, which fills a contact hole opened within the source poly pickup trench and extends from the source polysilicon electrode to source metal layer 3356.
  • the source poly 3360 further extends into a space below the active gate electrodes 3364 along the active gate trenches therefore forming a shield electrode (source/shield poly) to shield the gate electrodes from the drain region 3366 disposed on the semiconductor substrate, which usually connects to high voltage.
  • FIG. 33LL' is a cross sectional diagram illustrating the LL" cross section of an example device. Unlike the asymmetric trench 3306 in Fig. 33AA', gate pickup trench 3370 in Fig. 33LL' (which is an extension trench of gate runner trench 3306) exhibits a
  • source/shield poly 3372 and gate poly 3374 are embedded in gate pickup trench 3370.
  • the thicknesses of oxide layers 3373 disposed between the gate poly 3374 and the sidewalls of the upper portion of the trench is substantially uniform and is substantially thicker than the oxide layers (e.g. oxide layer 3378) surrounding the source/shield poly and lining the both sidewalls of the bottom portion of the trench.
  • the top surface of the gate poly is recessed from the top surface of epi substrate 3366 and has a polycide layer 3375 for improving gate conductivity along the gate trench.
  • a tungsten plug filling a contact hole 3376 opened within the gate pickup trench extends from the top of gate poly to the gate metal layer 3378 deposited on top surface of nitride layer 3384, and electrically connects the gate poly electrode 3374 with gate metal 3378.
  • Nitride spacer 3382 in proximity to the top portion of the gate pickup trench sidewall extends to the top surface of nitride layer 3384.
  • Nitride layer 3384 and nitride spacer 3382 seal the oxide layer 3386 deposited on the top surface of epi substrate in termination area.
  • the top surface of gate electrode 3374 lies below the bottom of nitride spacer 3382.
  • Gate pickup trench 3370 is wider than the active gate trench.
  • the above embodiment provides a MOSFET device with a gate runner trench having an asymmetric structure in some sections (such as AA') and a substantially symmetric structure in other sections (such as LL').
  • alternative embodiments may be produced following the same process.
  • the second mask as shown in Fig. 18AA' extends over into the active area at 1806 to such a distance that the PR completely protects the oxides lining both sidewalls of trench 1804 from etch in the following wet etch process, in a way similar to that shown in Figs. 18LL' and 19LL', the resulting device structure following the process as previously described is a device 3400 shown in FIG.
  • gate contact opening 3376 may be formed directly above the termination/gate runner trench 3402 in AA' cross section by rearrange the gate contact location in the third mask, so that the termination/gate runner trench 3402 also functions as the gate pickup trench.
  • the first mask and the fourth mask are modified such that the distance between the termination/gate runner trench 3402 and the active gate trench 3302 next to termination area is increased to have enough space to separate gate metal 3406 from source metal 3408.
  • gate contact hole may be disposed on top of asymmetric termination/gate runner trench to directly pick up gate contact to the gate metal.
  • the termination/gate runner trench therefore, also serves as gate pickup trench.
  • device 3500 has a similar structure as device 3300 in Fig. 33AA', except a gate contact hole 3376 is disposed on top of asymmetric
  • termination/gate runner trench 3506, and the gate and source metals are separated in an appropriate location to facilitate the gate contact.
  • the above examples mostly illustrate N-type devices.
  • the techniques described are also applicable to P-type devices, in which polarities of various dopants are reversed.

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
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Abstract

La présente invention concerne un dispositif semi-conducteur comprenant la formation d’une pluralité de tranchées, comprenant l’application d’un premier masque, la formation d’une première région de silicium polycristallin dans au moins certaines de la pluralité de tranchées, la formation d’une région diélectrique d’inter-polysilicium et d'une région de protection de terminaison, comprenant l’application d’un second masque, la formation d’une seconde région de silicium polycristallin dans au moins certains de la pluralité de tranchées, la formation d’un premier contact électrique vers la première région de silicium polycristallin et la formation d’un second contact électrique vers la seconde région de silicium polycristallin, comprenant l’application d’un troisième masque, la réalisation d’une couche métallique, et la formation d’une région métallique de source et d’une région métallique de grille, comprenant l’application d’un quatrième masque.
PCT/US2010/002198 2009-08-14 2010-08-09 Dispositif à transistor mos à grille en tranchée isolée et son procédé de fabrication WO2011019378A1 (fr)

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US12/583,191 US8193580B2 (en) 2009-08-14 2009-08-14 Shielded gate trench MOSFET device and fabrication
US12/583,192 2009-08-14
US12/583,192 US8236651B2 (en) 2009-08-14 2009-08-14 Shielded gate trench MOSFET device and fabrication
US12/583,191 2009-08-14

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US8816431B2 (en) * 2012-03-09 2014-08-26 Fairchild Semiconductor Corporation Shielded gate MOSFET device with a funnel-shaped trench
CN105428241B (zh) * 2015-12-25 2018-04-17 上海华虹宏力半导体制造有限公司 具有屏蔽栅的沟槽栅功率器件的制造方法
WO2024060262A1 (fr) * 2022-09-23 2024-03-28 华为数字能源技术有限公司 Dispositif à semi-conducteur, procédé de fabrication, circuit de conversion de puissance et véhicule
CN117393501B (zh) * 2023-12-07 2024-03-19 合肥晶合集成电路股份有限公司 一种半导体结构及其制造方法

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CN104134696A (zh) 2014-11-05
CN101997033B (zh) 2014-09-10
TWI492380B (zh) 2015-07-11
CN101997033A (zh) 2011-03-30
CN104134696B (zh) 2017-12-05

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