WO2010149182A1

WO2010149182A1 - Apparatus and method for combining electrical or electronic components; apparatus and method for providing a combination information; apparatus and method for determining a sequence of combinations and computer program

Info

Publication number: WO2010149182A1
Application number: PCT/EP2009/004489
Authority: WO
Inventors: Jochen Rivoir
Original assignee: Verigy (Singapore) Pte. Ltd.
Priority date: 2009-06-22
Filing date: 2009-06-22
Publication date: 2010-12-29
Also published as: TW201108625A

Abstract

An apparatus for combining electrical or electronic components based on a digital input signal which can take a plurality of values out of a range of values, so as to generate an analog quantity corresponding to the digital input signal comprises a combination generator and a component combiner. The combination generator is adapted to supply, in dependence on the input signal, a control signal describing a sequence of combinations of electrical or electronic components. For a given value of the digital input signal, at least two different combinations of electrical or electronic components associated with the given value are available. At least one of the combinations includes at least two electrical or electronic components having different nominal values. The combination generator is configured to provide the control signal such that, in response to the given value, the control signal describes, in the course of time, a plurality of different combinations of electrical or electronic components. The component combiner comprises a plurality of electrical or electronic components, at least two of which electrical or electronic components comprise different nominal values. The component combiner is adapted to select, in dependence on the control signal, the different sets of the electrical or electronic components to be combined from the plurality of electrical or electronic components.

Description

Apparatus and Method for Combining Electrical or Electronic Components, Apparatus and Method for Providing a Combination Information, Apparatus and Method for Determining a Sequence of Combinations and Computer Program

Background of the Invention

Embodiments according to the invention relate to an apparatus and a method for combining electrical or electronic components. Further embodiments according to the invention relate to an apparatus and a method for providing a combination information signal. Embodiments according to the invention relate to a method for determining a sequence of combinations of electrical or electronic components. Embodiments according to the invention relate to a digital-to- analog converter. Further embodiments according to the invention relate to a computer program.

Some embodiments according to the invention are related to a dynamic matching of unequal elements.

Converting a digital quantity (or digital value) into an analog quantity has always been a challenging task. Several alternatives are known for creating an analog quantity by summing up a programmable subset of elements with nominal but inaccurate values:

• Current steering digital-to-analog converters. In current steering digital-to-analog converters, switches select a subset of currents that flow into a summation node;

• Switched capacitor digital-to-analog converters. In switched capacitor digital-to-analog converters, switches select a subset of capacitors that share their charge in a charge sharing node;

• Programmable capacitor. In a programmable capacitor, switches select a subset of capacitors that are combined in a parallel manner.

Several conventional concepts for creating an analog quantity by summing up a programmable subset of elements are known. In a conventional apparatus, a binary scaling is used. For example, normalized element values of 1,2,4,...,2¹^^"1 are used. In such an embodiment using a binary scaling of element values, 2^N different sums can be formed: 0, 1, 2, 3, ..., 2^s'1. However, element mismatches affect the quality of the sum.

Another conventional apparatus uses a dynamic element matching of equal elements. In such a conventional embodiment, all N elements have equal normalized value "1". Thus, (N+l) different sums can be formed: 0, 1, 2, 3, ...,N.

In a conventional apparatus, dynamic element matching (DEM) reduces the effect of element mismatch by cycling through all elements, and thus using each element equally often. On average, the mismatches cancel out.

Fig. 16 shows an example of five elements and a value of 3. Different element combinations are described to obtain the value of 3.

Fig. 17 shows an example of four elements and a value of 2. Two different combinations are shown to obtain the value of 2, each of the combinations using two out of the four elements.

Digital-to-analog converters (DACs) are widely used in communications and other applications with ever increasing linearity and signal-to-noise ratio (SNR) requirements. Most lower bandwidth digital-to-analog converters use oversampling. A single-bit delta-sigma digital-to-analog converter is inherently linear because it performs a pulse-density interpolation between just two points. However, the large quantization between just two points introduces significant noise. Multi-bit delta-sigma digital-to-analog converters use a subset of N nominally equal elements to choose from N+l different quantization levels, which reduces quantization noise, but assumes perfectly equal elements.

Dynamic element matching (DEM) , which is for example described in the publication "Understanding Delta-Sigma Data Converters" by R. Schreier and G. C. Temes, John Wiley and Sons, 2005, refers to a series of techniques that reduce the average effect of mismatch. For example, data weighted average (DWA) rotates element usage such that, on average, all elements are used equally often, thus contributing their mismatch error equally often. Because, by definition, the sum of all element mismatch errors is zero (which is an idealizing assumption) , the average mismatch error is zero as well. For example, to generate level 3 with 8 equal elements, first elements {1,2,3} are used, then {4,5,6}, then {7,8,1}, which exploits redundant representations of the desired level. With N equal elements, the 2^N possible combinations result in only N+l different quantization levels, leaving significant redundancy. This is the common approach for multi-bit ΔΣ digital-to-analog converters (DACs) (cf. the article "Understanding Delta-Sigma Data Converters") . The other extreme is binary element scaling, where all 2^N possible element combinations map to 2^N unique quantization levels, leading to the smallest possible quantization noise, but leave no redundancy to reduce the effect of mismatch. For details, see the publication "Analog Test Signal Generation Using Periodic ΣΔ Encoded Data Streams" by B. Dufort and G. W. Roberts, Kluver Academic Publishers, 2000.

Some conventional multi-bit Δ-Σ digital-to-analog converters sum up subsets of N nominally equal elements and apply dynamic element matching (DEM) techniques to eliminate the average effect of element mismatch. All known DEM techniques require equal elements and thus limit the number of quantization steps to N+l, where N is practically limited by the ability to layout elements symmetrically. US 2007/0024481 Al describes a method and system for digital- to-analog conversion using multi-purpose current summation.

US 2007/00224482 Al describes a digital-to-analog conversion using a summation of multiple digital-to-analog converters (DACs) .

In view of the above discussion, there is a need for a concept which brings along an improved tradeoff between an impact of an element mismatch and a dynamic range when converting a digital quantity into an analog quantity.

Summary of the Invention

Embodiments according to the invention create an apparatus for combining electrical or electronic components based on a digital input signal which can take a plurality of values out of a range of values, so as to generate an analog quantity corresponding to the digital input signal.

Another embodiment according to the invention creates an apparatus for providing a combination information signal describing a sequence of combinations of electrical or electronic components, so as to describe combinations of elements for generating an analog quantity corresponding to the digital input signal.

Embodiments according to the invention comprise an apparatus for determining a pre-computed sequence of combinations of electrical or electronic components for a given digital input value.

Some embodiments according to the invention create methods implementing the functionality described herein.

Some embodiments according to the invention create computer programs for performing the methods described herein. Brief Description of the Figures

Embodiments according to the invention will subsequently be described taking reference to the enclosed figures in which:

Fig. 1 shows a block schematic diagram of an apparatus for combining electrical or electronic components based on a digital input signal, according to an embodiment of the invention;

Fig. 2 shows a schematic representation of a summation of unequal elements;

Figs. 3a, 3b, 3c show graphical representations of different combinations of elements for obtaining nominal sum values of 8, of 10 and of 15, respectively, using elements having nominal element values 1, 2, 3, 4, 5, 6, 7, and 8;

Fig. 4 shows a graphical representation of a number of combinations of twelve linearly scaled elements for the 79 reachable quantization levels (0, 1,..., 78);

Fig. 5 shows a flowchart of a method for combining electrical or electronic components, according to an embodiment of the invention;

Fig. 6a shows a graphical representation of element combinations in a sequence of element combinations for obtaining a nominal sum value of 15, using elements having nominal element values of 1, 2, 3, 4, 5, 6, 7, and 8;

Fig. 6b shows a graphical representation of element combinations in a sequence of element combinations for obtaining a nominal sum value of 16, using elements having nominal element values of 1, 2, 3, 4, 5, 6, 7, and 8;

Fig. 7 shows a flowchart of a method for providing a combination information signal, according to an embodiment of the invention;

Fig. 8a shows a graphical representation of lists of combinations of different sequences of combinations for different nominal sum values;

Fig. 8b shows a graphical representation of a sequence of combinations to be output, which are generated in response to a sequence of desired output values;

Fig. 8c shows a graphical representation of a sequence of combinations to be output, which are generated in response to a sequence of desired output values;

Fig. 9 shows a block schematic diagram of an apparatus for combining electrical or electronic components, according to an embodiment of the invention;

Fig. 10 shows a flowchart of a method for determining a sequence of combinations of electrical or electronic components for a sequence of digital input samples, according to an embodiment of the invention;

Fig. 11 shows a flowchart of a method for selecting an element combination, according to an embodiment of the invention;

Fig. 12 shows a graphical representation of an element usage variation of all reachable quantization levels for N=12;

Fig. 13 shows a graphical representation of a resolution R in bits for linear element scaling with L_maχ =64 compared to equal elements and binary scaling;

Fig. 14 shows a block diagram of a Δ∑-DAC with unequal elements, where blocks inside the dashed rectangle can be implemented in software (SW) ; Fig. 15 shows a graphical representation of a comparison of element scaling and selection methods for an over-sampled multi-bit DAC with 16 elements;

Fig. 16 shows a graphical representation of conventional element combinations for an example of 5 elements and a nominal sum value of 3; and

Fig. 17 shows a graphical representation of combinations of elements for an example with 4 elements and a nominal sum value of 2.

Detailed Description of the Embodiments

Embodiments according to the invention will subsequently be described taking reference to the figures.

Fig. 1 shows a block schematic diagram of an apparatus for combining electrical or electronic components. The apparatus shown in Fig. 1 is designated in its entirety with 100. The apparatus 100 is configured to receive a digital input signal (or digital input quantity) 110 which can take a plurality of values out of a range of values. The apparatus 100 is configured to generate an analog quantity 120 based on the digital input signal 110, such that the analog quantity 120 corresponds to the digital input signal 110. The apparatus 100 comprises a combination generator 130 which is adapted to receive the digital input signal 110 and supply, in dependence on the digital input signal 110, a control signal 132 describing a sequence of combinations of electrical or electronic components. The apparatus 100 is configured such that for a given value of the digital input signal 110, at least two different combinations of electrical or electronic components associated with the given value are available. At least one of the combinations includes at least two electrical or electronic components having different nominal values. The combination generator 130 is configured to provide the control signal such that in response to the given value, the control signal describes, in the course of the time, a plurality of different combinations of electrical or electronic components.

The apparatus 100 also comprises a component combiner 140 comprising a plurality of electrical or electronic components 142a, 142b, 142c, at least two of which electrical or electronic components 142a, 142b, 142c comprise different nominal values. The component combiner 140 is adapted to select, in dependence on the control signal 132, different sets of the electrical or electronic components 142a, 142b, 142c to be combined from the plurality of electrical or electronic components, to obtain the analog quantity on the basis of the selected set of electrical or electronic components .

The apparatus 100 is based on the finding that a large dynamic range of the analog quantity 120 can be obtained by selecting combinations of electrical or electronic elements having different nominal values. For example, in comparison to an apparatus comprising electrical or electronic components with equal nominal values, the dynamic range of the analog quantity 120 can be significantly improved for a given number of electrical or electronic components by using elements having different nominal values. However, the apparatus 100 is also based on the finding that an impact of element tolerances on the generation of the analog quantity 120 can be reduced by using more than one combination in response to a given value. Thus, a single given value of the digital input signal 110 results in different combinations of electrical or electronic components 142a to 142c in the course of time. Accordingly, the generation of the analog quantity 120 on the basis of a first combination associated with the given value is affected by the element tolerances of electrical or electronic components included in the first combination. Similarly, the generation of the analog quantity 120 on the basis of a second combination of the electrical or electronic components 142a to 142c, associated with the given value of the digital input signal, is affected by the tolerances of the electrical or the electronic components included in the second combination. Assuming that, at least partially, different electrical or electronic components are included in the different combinations, the tolerances tend to average out.

Accordingly, by using different combinations of unequal elements in response to a given value of the digital input signal 110, a large dynamic range of the analog quantity 120 can be obtained while keeping the impact of element tolerances of the electrical or electronic components 142a to 142c small.

Some embodiments described herein are based on the idea to create an analog quantity as a summation of N elements, where not all elements are equal. To generate a given sum value, go through a list of element combinations, each generating the nominal sum value, such that - by the end of the sequence - each element is used equally often.

Combination of Elements

Fig. 2 shows a schematic representation of a summation of unequal elements. The circuit shown in Fig. 2 is designated in its entirety with 200. The circuit 200 comprises a plurality of current sources 210a, 210b, and 210c. The current sources 210a, 210b, and 210c are switchably connected to a summation element in the form of a summation node 220 via corresponding switches 212a, 212b, and 212c, as shown in Fig. 2. The summation node 220 is configured to provide a sum signal 230, which is designated with q.

The current sources 210a, 210b, 210c comprise different nominal values, i.e. are configured to provide currents of different normalized magnitudes ei, e₂, ..., e_N. The current sources 210a - 210c are connectable to the summation node 220 in dependence on control signals Ci, C₂,..., C_n. For example, the control signals Ci,C₂,...,c_n may be used to open or close the switches 212a, 212b, 212c. The output signal 230 provided by the summation node 220 comprises a signal value, which is determined by the sum of the currents provided by those of the current sources 210a, 210b, 210c, which are coupled to the summation node 220 in response to the control signals Cχ_r C₂,..., C_n.

Accordingly, the circuit 200 may take the function of the component combiner 140. The control signals Ci,C₂,...,c_n may take over the function of the control signal 132. The analog quantity 120 may be represented by the sum signal 230. The current sources 210a, 210b, 210c may be considered as the electrical or electronic components 142a to 142c.

Fig. 3a shows a graphical representation of different combinations of elements for obtaining a nominal sum value of 8 using elements having nominal element values of 1, 2, 3, 4, 5, 6, 7, and 8. As can be seen, there are 6 combinations of elements which can be used to obtain the nominal sum value of 8. The combinations are designated with "combination 11 value β" to "combination 61 v_alue β" r and can also be designated by their combination indices (comb 19, comb 13, comb 65, comb 34, comb 20, comb 128) . The combinations "combination 11 value s" to "combination 61 _value β" can be used as entries of a sequence of combinations associated to the nominal value of 8. For example, a sequence of combinations associated to the nominal value of 8 may comprise, for example in a cyclically repetitive manner, the following sequence of combinations: "comb 11 value a! comb 2|_vai_ue β; comb 3|_vaiue β; comb 41 _vaiue 8/ comb5 lvalue 8'" comb 61 value 8'' comb 11 value 8'" comb 4 I value β! comb 5lvaiue8''" (or a different sequence of combinations).

Fig. 3b shows a graphical representation of different combinations of elements which can be used to obtain a nominal sum value of 10 using elements having nominal element values of 1, 2, 3, 4, 5, 6, 7, and 8.

Fig. 3c shows a graphical representation of different combinations of elements for obtaining a nominal sum value of 15 using elements having nominal element values of 1, 2, 3, 4, 5, 6, 7, and 8.

Fig. 4 shows a graphical representation of a number of combinations of 12 linearly scaled elements for the 79 reachable quantization levels (0, 1, ..., 78) . A larger number of different combinations of elements is available for medium quantization levels (within a range between 20 and 60), when compared to lower quantization levels (within a range between 0 and 20), and upper quantization levels (within a range between 60 and 78) .

Sequence Generation Using Element Selection for Quantization Level

In the following, the concept of dynamic element matching using an element selection per quantization level will be described taking reference to Figs. 5 to 9. Firstly, a method for combining electrical or electronic components based on a digital input information will be described taking reference to Fig. 5. Fig. 5 shows a flow chart of such a method, which is designated in its entirety with 600. The method 600 comprises, as a preparatory measure, a pre-computation 610 of sequences S(q) for different quantization levels. The method 600 also comprises a provision 620 of an output sequence of element combinations on the basis of a digital input signal (or digital input information) and on the basis of the pre- computed sequences S(q). Furthermore, the method 600 comprises applying 630 the selected combination of elements. The steps of providing 620 an output sequence of element combinations and of applying 630 provided combinations of elements can be repeated, if desired.

The pre-computation 610 of sequences S(q), the provision 620 of an actual sequence of element combinations and the step 630 can be performed in different apparatus and/or at different times. In the following, the pre-computation of sequences for different quantization levels will be discussed in detail. The pre-computation of sequences S(q) for different quantization levels comprises determining 612 reachable quantization levels q. For example, if a plurality of elements is available having linearly increasing (normalized) nominal values between 1 and N, nominal sum values or quantization levels q between 0 and N (N + l)/2 are reachable. However, if another set of elements is available, different nominal sum values may be available. The available nominal sum values can be computed, for example, by considering all possible combinations of the elements. In a step 614, element combinations c associated to the different reachable quantization levels q are determined to obtain sets A(q) of combinations associated to different quantization levels. For example, if there are elements having nominal element values of 1, 2, 3, 4, 5, 6, 7, and 8, there are 6 combinations associated to the nominal sum value q=8, as can be seen from Fig. 3a. There are 8 combinations associated to the nominal sum value q=10, as can be seen in Fig. 3b, and there are also 8 combinations associated to the nominal sum value q=15, as can be seen in Fig. 3c. Accordingly, the set A(q=8) comprises the combinations shown in Fig. 3a, the set A(q=10) comprises the combination shown in Fig. 3b and the set A(q=15) comprises the combination shown in Fig. 3c.

The pre-computation of the sequences also comprises a step 616 of pre-computing the sequences S(q) of element combinations c(q) e A(q), such that the elements included in a specific sequence S(q) are used at least approximately equally often in the course of said sequences S(q). The step 616 can be executed for some of the quantization levels q, or even for each of the quantization levels q. Accordingly, sequences S(q) are pre-computed for some of the quantization levels, or even for each of the quantization levels.

In general, it is desired to provide a sequence of element combinations associated with a nominal sum value q, wherein the combinations associated with the nominal sum value q are used in the sequence. It is therefore determined how often the different combinations associated with the nominal sum value q should be used in the sequence associated with the nominal sum value q, to obtain a balanced element usage (wherein all the elements included in the sequence are used equally often or at least approximately equally often) .

Examples of combinations obtained using the algorithm described herein are shown in Figs. 6a and 6b. Fig. 6a shows a graphical representation of 8 different combinations of elements 1 - 8 that lead to a sum value equal to 15. After using the combination "COMB 1" once, combination "COMB 2" once, combination "COMB 3" twice,..., combination "COMB 8" twice, all elements have been used five times.

Accordingly, when the target sum value is 15, for example, the sequence of combinations [comb 1, comb 2, comb 3, comb 4, comb 5, comb 6, comb 7, comb 8, comb 3, comb 5, comb 7, comb 8], cancels out (or at least reduces) element mismatch.

A further example is described making reference to Fig. 6b. Fig. 6b shows a graphical representation of element combinations yielding a nominal sum value of 16. The value 16 is generated using 5 different combinations (designated with COMB 1 through COMB 5 in Fig. 6b) of element values (1, 2, 3, 4, 5, 6, 7, 8), such that all elements are used equally often (four times) . Regarding the example shown in Fig. 6b, it should be noted that not all of the element combinations yielding the nominal sum value of 16 are used. For example, the element combination comprising the elements having nominal sum values of 2, 3, 4, and 7 is not included in the list of combinations shown in Fig. 6b.

Provision of an Output Sequence of Element Combinations

In the following, the provision of an output sequence of element combinations on the basis of a digital input signal and on the basis of the pre-computed sequences S(q) will be described. It will be described how a sequence of the different input samples can be transformed into an information describing a sequence of corresponding element combinations. The provision 620 of an output sequence comprises receiving 622 the next desired output value q_neχ_t represented by the digital input signal. The provision 620 of an output sequence also comprises selecting 624 one or more combinations of the elements from the one of the sequences S(q_neχt) corresponding to the received desired output value q_neχt- The currently selected one or more combinations of elements follow, in the cyclic sequence S(q_neχ_t) of combinations corresponding to the received desired output value, previously selected combinations of elements, previously selected in response to a previously received desired output value which is identical to the presently received desired output value (or which at least corresponds to the same reachable quantization level) . Thus, if a specific combination of the sequence S(q_next) has been selected in response to a previous occurrence of the value q_nex_tf a subsequent combination (subsequent to the specific combination) within the sequence S (q_neχ_t) is output for the present occurrence of the value q_neχ_t- Accordingly, for subsequent occurrences of the desired value q_neχ_t/ subsequent element combinations of the sequence S(q_neχt) are output. For one occurrence of the desired output value q_neχtf one or more combinations (in general: a predetermined number of combinations) of the sequence S(q_next) may be output. However, the combinations of the sequence S(q_next) may be applied cyclically in that the first combination of the sequence S (q_next) is output after the last combination of the sequence S (q_neχt) has been output.

Furthermore, between two subsequent occurrences of the desired output value q_next? other desired output values q_other may occur. Accordingly, element combinations from other sequences S(q_other) may be output in between two subsequent element combinations of the sequence S(q_neχt)-

Once a combination of elements is selected from a respective sequence of combinations, the selected combination of elements is applied in a step 630. For example, an element combination may be physically formed in response to the selection of a combination from a sequence of combinations.

In the following, further details regarding the provision of the output sequence of element combinations on the basis of the digital input signal and on the basis of the pre-computed sequences S(q) will be described taking reference to Figs. 7, 8a, 8b, 8c, and 9.

Fig. 7 shows a flow chart of a method 1000 for the provision of an output sequence of element combinations. The method 1000 may take the place of the step 620 of the method 600. The method 1000 optionally comprises quantizing 1010 an input value to obtain the next desired output value. The method 1000 further comprises receiving 1020 the next desired output value q_neχ_t represented by the digital input signal. The method 1000 also comprises determining 1030 which sequence S (q_neχt) is associated with the desired output value q_next« Thus, one of the sequences S(q) provided in the step 610 may be selected. Further, a current position within the selected sequence S(q_neχt) associated with the desired output value q_neχt is determined in a step 1040. For example, a pointer may be used (or evaluated) to designate the current position within the sequence S(q_next)- In a step 1050, one or more combinations of elements may be selected from the sequence S(q_next) starting from the current position within the sequence S(q_next)- A combination of the sequence S(q_next) may be selected, which follows (within the sequence S(q_next)) a previously selected combination. A cyclic wrapping from the end of the sequence S(qneχt) to the beginning of the sequence S(q_next) may be considered when selecting the one or more combinations of elements. If a last element of the sequence S(q_next) has been previously selected, then a first element of the sequence S(q_next) will be subsequently selected. The current positions within the different sequences of S(q) may be maintained independently. In response to the selection 1050 of the one or more combinations of elements from the sequence S(q_next), an information is provided in step 1060 describing the one or more selected combinations of elements. The information describing one or more selected combinations of elements may for example be applied in order to determine physical combinations of elements. Furthermore, the information about the current position within the present sequence S(q_next) may be updated in a step 1070.

In the following, the generation of an output sequence of element combinations will be described taking reference to an example shown in Figs. 8a, 8b, and 8c.

Fig. 8a shows a graphical representation of different sequences of element combinations which are associated with different nominal sum values. Fig. 8a describes different sequences of combinations for the case that elements having element values of 1, 2, 3, 4, 5, 6, 7, and 8 are available. For example, the sequences of combinations which have been shown in Figs. 3a, 3b, 3c, 6a and 6b.

Thus, a first list 1210 may describe, for example, only a single combination of elements associated with the nominal sum value of 1. A list 1212 describes a sequence of combinations for a nominal sum value of 8. A list 1214 describes a sequence of element combinations for a nominal sum value of 10. A further list 1216 describes a single element combination for a nominal sum value of 16. Naturally, lists may be available for other nominal sum values which, for the sake of simplicity, are not shown here. Furthermore, for each of the lists 1210 to 1216, a pointer may be available pointing at a current position within the respective lists. A pointer for a current position within the list 1212 is designated with 1212a and a pointer for a current position within the list 1214 is designated with 1214a.

Fig. 8b shows a graphical representation of a sequence of output element combinations, which sequence of output element combinations is generated in response to a sequence of desired output values. It is assumed here that in the course of time, a sequence of values 1, 8, 10, 8, 10, 10 is to be output. The sample values to be output are designated with 1232a to 1232f. For example in response to the sample value 1232a, a combination associated with a nominal sum value of 1 is output (1242a) . Further in response to the sample value 1232b, a first element combination associated with the nominal sum value of 8 is output (1242b) . In response to the sample value 1232c, a first element combination from the sequence S(q=10) of element combinations associated with the nominal sum value of 10 is output (1242c) . In response to the sample value 1232d, a second combination from the sequence S(q=8) of combinations associated with the nominal sum value 8 is output (1242d) . In response to the sample value 1232e, a second element combination of the element combinations associated to the nominal sum value 10 is output (1242e) . In response to the sample value 1232f, a third element combination from the sequence of element combinations associated with the nominal sum value of 10 is output (1242f) .

It can be seen that the subsequent element combinations from the list (or sequence) 1212 of element combinations associated with the nominal sum value of 8 are output in response to subsequent occurrences of the sample value 8 (1232b, 1232d) . It can also be seen that subsequent element combinations from the list (or sequence) 1214 are output for subsequent occurrences of the sample value of 10 (1232c, 1232e, 1232f ) .

As mentioned above, the lists 1210 to 1216 (or sequences S(q) 1210 to 1216) are chosen such that an element usage variation is kept sufficiently small (as discussed above) .

Referring now to Fig. 8c, a case is described in which a plurality of element combinations are output for each input sample value (desired output value) . Again, it is assumed that a sequence of sample values 1262a to 1262f, are to be output. As can be seen, for each of the sample values 1262a to 1262f, a plurality of element combinations are output, wherein the output element combinations are determined by the lists of combinations 1210 to 1216. Whenever an end of one of the lists is reached, a cyclic return is executed to the beginning of the list. A current position within each of the lists is tracked.

Apparatus

In the following, an apparatus will be described for implementing the concept of providing an output sequence of element combinations, which has been explained with reference to Figs. 6 (steps 620, 630) and also with reference to Figs. 7, 8a, 8b, and 8c.

Fig. 9 shows a block schematic diagram of an apparatus 1300 for combining electrical or electronic components, according to an embodiment of the invention. The apparatus 1300 comprises a combination generator 1310 and a component combiner 1320. The combination generator is configured to receive a digital input signal 1312 which can take a plurality of values out of a range of values. The combination generator is further configured to provide a control signal 1314 to the component combiner 1320. The control signal 1314 describes which components out of a plurality of electrical or electronic components are to be combined. The component combiner 1320 is configured to form, in dependence on the control signal 1314, a combination of electrical or electronic components, to obtain an analog output quantity 1322. The combination generator 1310 may be equivalent to the combination generator 130, and the component combiner 1320 may be equivalent to the component combiner 140.

In the following, details of the combination generator 1310 will be described. Generally, the combination generator 1310 is configured to provide an output sequence of element combinations (represented by the control signal 1314) on the basis of the digital input signal 1312, and on the basis of pre-computed sequences S(q). Thus, the combination generator 1310 may be configured to perform the functionality of the step 620 as described with reference to Fig. 6. Alternatively, the combination generator may perform the functionality of the method 1000 described with reference to Fig. 7. The component combiner may, therefore, be configured to provide, for example, a sequence of combinations to be output (represented by the control signal 1314), as described with reference to Figs. 8b and 8c.

The combination generator 1310 may for example comprise, as a key component, a combination selector 1340. Generally speaking, the combination selector may be configured to select from a plurality of sequences, a current element combination to be currently output. For example, if the sequences of element combinations illustrated in Figs. 3a-3c, or Figs. 6a and 6b are available, the combination selector 1340 may be configured to select which element combination out of this plurality of sequences of element combinations is to be output. For this purpose, it is decided by the combination selector 1340 which sequence of element combinations is to be evaluated. It is further decided, which element combination out of the chosen sequence of element combinations is to be output.

For this purpose, the combination selector 1340 comprises a plurality of list evaluators 1342a, 1342b, 1342c. For example, each of the list evaluators 1342a, 1342b, and 1342c may be associated with a corresponding "available" nominal sum value. The list evaluators 1342a, 1342b, 1342c may be structurally identical (except that they are configured in accordance with different sequences of element combinations) . Thus, the structure of the first list evaluator 1342a will be described as a representative example. List evaluator 1342a comprises a memory 1350. The memory 1350 comprises a representation of the sequence of elements, which is associated to the given nominal sum value. The sequence of element combinations may be described in the form of a pre-computed list (which may be obtained in accordance with step 610 of the method 600, and/or which may fulfill a quality condition with respect to a variance of the frequencies of use of the included elements, as descried in detail below with reference to equation (11) . The list evaluator further comprises a counter 1352, which is coupled with the memory 1350 to address a memory position of the memory (i.e. an entry of the list stored in the memory 1350 which describes a combination of elements stored in the memory 1350) . Accordingly, the counter may be coupled to the memory 1350 such that an increase in the count value of the counter 1352 results in a stepping through the list of element combinations stored in the memory 1350. In addition, the memory 1350 may be configured to provide a restart signal to the counter 1352, such that the counter is reset to address the beginning of the list whenever an end of the list is reached. Accordingly, the counter 1352 may cooperate with the memory, such that the entries of the list stored in the memory 1350 are cyclically provided at an output 1350a of the memory 1350 in response to a clocking of the counter 1352. Further, the counter 1352 may be configured to receive a count signal which may either serve as a clock signal for clocking the counter 1352, or which may serve to enable/disable the counting of the counter. Accordingly, the list evaluator 1342a can only proceed with the evaluation of the list stored in its memory when the corresponding counter 1352 is enabled to count, or clocked to count. The combination selector 1340 further comprises a demultiplexer 1360. The demultiplexer 1360 is configured to receive a select signal 1362 and to select a respective counter of one of the list evaluators 1342a, 1342b, 1342c, for example by selectively forwarding a count enable signal to the counter of only one of the list evaluators, or by selectively forwarding a counter clock signal to only one of the list evaluators 1342, 1342b, 1342c.

The combination selector 1340 further comprises an output multiplexer 1370 which is configured to selectively forward a representation of an element combination provided by one of the list evaluators 1342a to 1342c to an output of the combination generator 1310 to provide a description of a current combination of elements. The output multiplexer 1370 is configured to receive the select signal 1362. Accordingly, the control signal 1314 describes the combination of elements obtained using the currently selected list evaluator.

The select signal 1362 describes the analog quantity to be output. For this purpose, the select signal 1362 is based on the digital input signal 1312. In some embodiments, the select signal 1362 may even be identical to the digital input signal 1312. However, optionally, a quantizer 1318 may be present to derive the select signal 1362 from the digital input signal 1312. The quantizer 1318 may be configured to quantize the value described by the digital input signal 1312, to obtain the select signal 1362. For example, the quantizer 1318 may be configured to quantize the digital input signal to "sum values with solution" to obtain the select signal 1362. For example, the quantizer 1318 may round the digital input signal 1312 to an integer, and to look up the closest "sum value with solution" .

For example, the quantizer 1318 may be configured to map the value of the digital input signal 1312 to a nominal sum value associated with one of the sequences of combinations stored in the memory of one of the list evaluators 1342a to 1342c. Thus, the quantization is performed such that the select signal 1362 selects one of the list evaluators 1342a to 1342c which comprises a representation of the "most appropriate" sequence of combinations (sequence of combinations whose nominal value fits best to the value of the digital input signal 1312) .

The element combiner 1320 comprises a plurality of electrical or electronic components 1392a to 1392c, which are switchably coupled to a summation node 1394. For example, switches 1396a to 1396c are circuited between the electrical or electronic components 1392a to 1392c and the summation node 1394. The switches 1396a to 1396c are controlled in accordance with the control signal 1314. Accordingly, a combination of electrical or electronic components 1392a to 1392 can be obtained. A combination of electrical or electronic components 1392a to 1392c is controlled by the combination generator 1310. Accordingly, the combination of electrical or electronic components is chosen in accordance with an entry of a selected list evaluator 1342a to 1342c, and in dependence on the presently selected entry of the respective list (sequence of element combinations) .

Globally Optimized Element Selection

In the following, a concept for a globally optimized element selection will be described which can applied, for example, in the combination generator 130. In some embodiments according to the invention, it is therefore no longer necessary to determine pre-computed sequences S (q) of element combinations for different quantization levels. Rather, an element combination associated with the present sample of a digital input signal is determined using an element usage history taking into consideration element usage for different values of the digital input signal (different values being associated with different nominal sum values) .

Fig. 10 shows a flowchart of a method 1400 for a globally optimized element selection, according to an embodiment of the invention. For the execution of the method 1400, it is assumed that different reachable quantization levels q have been determined (as has been described with reference to step 612 of the method 600). It is further assumed that sets A(q) of combinations associated to different quantization levels have been obtained (for example as described with reference to steps 614 of the method 600) .

The method 1400 comprises, in a step 1410, initializing an accumulated element usage. The element usage is described by a vector u. For example, the element usage u is initialized to 0 for all the elements upon initialization of the method 1400. The method 1400 further comprises obtaining 1420 the desired output value q(i). The method 1400 comprises selecting 1430 an element combination c(i) associated to the current desired output value q(i) from a set A(q(i)) of possible element combinations associated with the desired output value q(i), such that a standard deviation σ of a current accumulated element usage u[i], which summarizes a previous accumulated element usage u[i-l] and an element usage c[q(i)] by the selected element combination c(i), is minimized. For example, the current element combination c(i) may be chosen such that a standard deviation is minimized by the current element combination, for example, when compared to an accumulated element usage which summarizes the previous accumulated element usage and the element usage of other possible element combinations γ ≠ c[q(i) ] (with Y e A(q(i) ) .

Thus, one of the possible element combinations which are associated to the current desired output value q(i) is selected. The selection (out of the possible element combinations associated with the desired output value q(i)) is performed to minimize an imbalance of an accumulated element usage. Thus, that one of the possible element combinations (associated with the desired output value q(i)) is chosen which results in a minimum overall element usage variation. For this purpose, the previous usage of the different elements is taken into consideration.

Details regarding a selection of the element combination will be described with reference to Fig. 11.

The method 1400 further comprises, as an optional feature, applying 1440 a selected element combination to obtain an output quantity.

In addition, the method 1400 optionally comprises selecting 1450 further element combinations associated to the current desired output value and applying the selected further element combinations to obtain the output quantity. Step 1450 may for example be executed if it is desired to output more than one element combination per desired value q(i). The method 1400 further comprises updating 1460 the accumulated element usage, to obtain u[i] .

Further, the method 1400 comprises setting 1470 i to designate the next desired output value (or the next sample thereof) .

The method 1400 may further loop back to step 1420 to obtain a next desired output value u[i], wherein i is incremented with respect to a previous execution of the set 1420. Thus, a next element combination is selected, wherein the updated accumulated element usage is applied.

To summarize the method 1400, the element combination c(i) is chosen taking a previous element usage into consideration, to keep an accumulated element usage as balanced as possible (or at least sufficiently balanced). In other words, when selecting an element combination in response to a desired output value, it is attempted to act towards an equally frequent usage of all the elements (accumulated over time) . For example, if the elements 1, 3, and 4 have been used less frequently in the past, it is attempted to find an element combination associated with the desired output value q(i) which uses one or more of the elements 1, 3 and 4. Generally, several different element combinations are normally associated with a given desired output value q(i) • From these different element combinations, an element combination may for example be chosen which mainly uses elements which have been used less frequently in the past, when compared to other elements. As a criterion to select the "best" element combination, a standard deviation σ may be taken into consideration, as will be explained in the following.

Fig. 11 shows a flowchart of a method 1500 for selecting an element combination. The method 1500 may for example be used to take over the functionality of the step 1430. The method 1500 comprises a step 1510 of computing standard deviations σ-j(i) for a plurality of element combinations γ from the set A(qi) of possible element combinations associated with the desired output value q(i). A standard deviation σ-_j(i) corresponding to a j^th possible element combination is calculated by forming a standard deviation of an expected element usage u[i-l] + Yj(q[i]) summarizing a previous accumulated element usage u[i-l] and an element usage Yj(q[i]) of the j^th possible element combination.

Thus, it is determined which element combinations γ are associated with the desired output value. Naturally, for these elements combinations γ, an element usage is known. Accordingly, an expected accumulated element usage is determined for each of the different possible element combinations γ (or at least for some of the different possible element combinations γ) . For this purpose, a previous accumulated element usage is taken into consideration. Accordingly, different expected element usage information is available for different element combinations γ. Thus, it can be checked for which of the element combinations γ the expected (accumulated) element usage is most balanced, or at least sufficiently balanced. For example, it can be determined for which of the element combinations γ the expected element usage information takes a minimum value (or a value which is below a predetermined threshold) .

Nevertheless, it is naturally not necessary to compute the expected element usage for each of the possible element combinations Y. Rather, it is sufficient to continue until an element combination is identified which results in a sufficiently small element usage variation.

Accordingly, the method 1500 comprises the step 1520 of identifying and element combination γ_j resulting in a sufficiently small (e.g. smaller than a threshold value) standard deviation (of the expected element usage) . Alternatively, the step 1520 may comprise identifying an element combination γ_j minimizing the standard deviation. The identified element combination γj may then serve as the selected element combination c[i] .

Further embodiments and aspects

In the following, some embodiments and aspects according to the invention will be described, along with some advantages.

In general, it can be said that the embodiments described herein are related to creating an analog quantity by summing a programmable subset of elements with nominal but inaccurate values.

Embodiments according to the invention can be used in current steering digital-to-analog converters, wherein a switch is used to select a subset of currents that flow in a summation node. Further embodiments according to the invention can be used in switched capacitor digital-to-analog converters, wherein switches select a subset of capacitors that share their charge in a charge sharing node. Further embodiments according to the invention can be used for implementing a programmable capacitor, wherein switches select a subset of capacitors that are combined in a parallel manner.

Embodiments according to the invention reduce the impact of element mismatch, while improving the dynamic range, compared to the dynamic element matching DEM, which assumes equal element values .

Some embodiments according to the invention are based on the observation that a binary element scaling leads to a small quantization error (many possible sum values) . Furthermore, embodiments according to the invention are based on the observation that equal elements provide enough redundancy to eliminate mismatch, but can generate much less different sum values . It has been found that redundant sum representations occur when less than 2^N different sum values can be formed with all 2^N combinations of N elements. In other words it has been found that a so-called "soft" scaling provides still enough redundancy while increasing the number of possible sum values.

Accordingly, some embodiments according to the invention are based on the idea of using "soft" element scaling, for example, linear element scaling 1, 2, 3, 4, ..., N. Thus, normalized nominal sum values of the elements to be combined may form a linear series between 1 and N.

Embodiments according to the invention are based on the idea of using redundant representations to average out the effect of element mismatch. In some embodiments, redundancy comes from the fact that there are 2^N combinations to sum N elements, while there are only N • (N+l) /2+1 different sum values, namely

0, 1, 2, 3, ..., N • (N+l) /2. In some embodiments it is desired to find all combinations (or at least a plurality of combinations) that lead to a given sum value.

In some embodiments, each combination is used a (different) (e.g. pre-determined) integer number of times, such that all elements are used (almost) equally often. In some embodiments, only those sum values are used, where the element usage is equal (or equal enough) . In the following an example will be described. For example, there are 8 different combinations of elements 1 - 8 that leads to a sum value of 15. For details, reference is made to Fig. 6a. After using COMB 1 once, COMB 2 once, COMB 3 twice, ... COMB 8 twice, all elements have been used 5 times. When the target sum value is 15, e.g. the sequence of combinations [COMB 1, COMB 2, COMB 3, COMB4, COMB 5, COMB 6, COMB 7, COMB 8, COMB 3, COMB 5, COMB 7, COMB 8] cancels out element mismatch.

Continuing the example for elements 1 - 8, equal element usage can be obtained for 18 different sum values, namely {0,9,11 ~25,27,36}. For 21 different sum values it is possible to obtain an element usage variation below 10%, where a 1Ox reduced impact of element mismatch can be expected.

Compared to equal elements, the number of sum values with ideal suppression of element mismatch is doubled. This corresponds to one bit added dynamic range, which is a significant improvement.

Method

In the following, a method for a creation of sequences of combinations will be briefly described. The method may comprise the following steps:

• Pick N element values, not all equal.

• Determine sums for all 2^N element combinations and group combinations by equal sum.

• For each reached sum value: Find integer uses of each combination (leading to given sum) , such that all elements are used (almost) equally often. This is a linear Diophantine equation, which can be solved using the extended Euclidean algorithm.

• Discard those sum values, where there is no solution.

• For each sum value with a solution, create a sequence of combinations that follows the above solution, i.e. uses the combinations for the target sum the found integer times .

It should be noted that the method can be used, for example, to identify a sequence of combinations for the application in the apparatus 1300 according to Fig. 13. Naturally, the method can be applied for different sum values.

Variations to the Scheme

In the following, some possible variations will be described, which can be applied in any of the embodiments described herein. For example, different element scaling can be used. As mentioned above, linear element scaling can be used, such that the nominal element values form a linear series. However, in some embodiments, a double linear scaling of the form: 1,1,2,2,3,3,4,4,... can be used. In other words, nominal values of the elements may be chosen to form a double linear series.

Alternatively, a Fibonacci scaling of the form: 1,2,3,5,8,13,... can be used. In other words, nominal element values may be chosen to form a Fibonacci series.

Some or all of the functionalities described herein can be implemented in hardware or in software. Naturally, a combined hardware/software implementation can also be applied. In some embodiments, everything may be pre-computed.

The functionalities of the system can be distributed in different ways. For example, the sequence of element combinations may be pre-computed, for example, using a computer. The pre-computed sequence of elements combinations may be stored in a memory of a computer or on a data carrier of the computer. Subsequently, the sequence of the element combinations may be transferred to a memory of an analog signal generator, such that the pre-computed sequence of element combinations is stored in the memory of the analog value generator. Subsequently, the analog value generator may eventually form element combinations on the basis of the pre- computed description of element combinations stored in its memory. Thus, a whole sequence of element combinations may be pre-computed (for example on a computer), well before the different element combinations are actually formed by the analog signal generator.

The advantage of such a concept is the fact that the pre- computation of the element combinations which is a comparatively complex task in some cases, can be performed in a high performance computer and does not need to be done in real time. Accordingly, the hardware of the analog signal generator can be made very simple, as the analog signal generator merely forms combinations in dependence on a predetermined information describing the combinations.

In another embodiment, an analog quantity generator may be a real time circuit, which is configured to receive, in real time, a digital input signal and to form, in real time, a sequence of combinations of elements corresponding to the digital input signal. Depending on the required speed, the analog signal generator may be configured to perform the determination of the appropriate combination of elements in hardware (as shown in Fig. 9) or in a software-supported way.

In view of the above discussion, it should be noted that embodiments according to the invention are not limited to a complete system for providing an analog quantity in dependence on a digital input signal. Rather, the ideas according to the invention are also realized by an apparatus or a method for providing a combination information signal describing a sequence of combinations of electrical or electronic component (without physically forming the distant combinations by combining elements) .

Computer Implementation

Naturally, the method described herein can also be performed in a computer-implemented manner.

Depending on certain implementation requirements, embodiments of the invention can be implemented in hardware or in software. The implementation can be performed using a digital storage medium, for example a floppy disk, a DVD, a CD, a ROM, a PROM, an EPROM, an EEPROM or a FLASH memory, having electronically readable control signals stored thereon, which cooperate (or are capable of cooperating) with a programmable computer system such that the respective method is performed.

Some embodiments according to the invention comprise a data carrier having electronically readable control signals, which are capable of cooperating with a programmable computer system, such that one of the methods described herein is performed.

Generally, embodiments of the present invention can be implemented as a computer program product with a program code, the program code being operative for performing one of the methods when the computer program product runs on a computer. The program code may for example be stored on a machine readable carrier.

Other embodiments comprise the computer program for performing one of the methods described herein, stored on a machine readable carrier.

In other words, an embodiment of the inventive method is, therefore, a computer program having a program code for performing one of the methods described herein, when the computer program runs on a computer.

A further embodiment of the inventive methods is, therefore, a data carrier (or a digital storage medium) comprising the computer program for performing one of the methods described herein .

A further embodiment of the inventive method is, therefore, a data stream or a sequence of signals representing the computer program for performing one of the methods described herein. The data stream or the sequence of signals may for example be configured to be transferred via a data communication connection, for example via the Internet.

A further embodiment comprises a processing means, for example a computer, or a programmable logic device, configured to or adapted to perform one of the methods described herein. Al A further embodiment comprises a computer having installed thereon the computer program for performing one of the methods described herein.

In some embodiments, a programmable logic device (for example a field programmable gate array) may be used to perform some or all of the functionalities of the methods described herein. In some embodiments, a field programmable gate array may cooperate with a microprocessor in order to perform one of the methods described herein.

Summary of Important Aspects of Some Embodiments

In the following, the concept of a digital-to-analog converter using dynamic mismatch correction of unequal elements will be explained using a mathematical formulation.

This description introduces dynamic element matching methods for unequal elements, for example a linear scaling (1,2,3,...,N) and applies them in a novel architecture of over-sampled digital-to-analog converters (DAC). The increased number of quantization steps add up to three effective bits, where quantization levels with enough redundant representations can use all elements equally often, and thus eliminate the average effect of element mismatch. Compared to equal elements, an increased complexity and an increased sensitivity of element mismatch may occur. However, in some embodiments, the increased number of quantization steps (which results in an increased resolution or a reduced signal-to-noise ratio) may over-compensate the disadvantages.

Accordingly, a concept for digital-to-analog conversion is created using a dynamic element matching. The concept may for example be applied in arbitrary wave form generators.

The idea pursued in this description is using a moderate element scaling, for example, linear element scaling, that increases the number of quantization levels and thus reduces quantization noise, compared to equal elements, but preserves enough redundancy for mismatch reduction.

In the following, two novel dynamic element matching methods for unequal elements will be described in the section entitled "Dynamic Matching of Unequal Elements". In the section "Over- Sampled Digital-to-Analog Converter with Unequal Elements", a novel oversampled Digital-to-Analog converter architecture will be introduced which is based on the proposed methods. Under the section entitled "Verification", simulation results will be presented and discussed. Some conclusions will be provided in the section entitled "Discussion".

Dynamic Matching of Unequal Elements

A. Element Summation in Current Steering Digital-to-Analog Converter

The quantized output q of a current steering digital-to analog converter is the weighted sum of N current elements with values e_n € R, each weighted with a corresponding binary control signal, C_n e{0,l}, see Fig. 2.

g = ∑c_ne_n (1)

This can also be written as

q=f (O=C -e (2)

with element combinations c' = (ci, ..., c_N) e { 0, 1 }^N and element values e= (βi, ...e_N) ' e R^N.

B. Quantization

Calculating the weighted sum (2) for all possible 2^N element combinations identifies the set R of all reachable quantization levels R = { q : q=f (e) ; c e { 0 , l } ^N } . ( 3 )

Quantization of input value x finds the closest quantization level q in a suitable subset Q cr R of reachable quantization levels that will be defined later.

q = arg min | x-ξ | =g (x,β) (4) ς e ^Q

C. Element Combinations for a Given Quantization Level

The proposed dynamic element matching method exploits the fact that at least some quantization levels q e R can be reached with multiple element combinations expressed as sets A(q) . The number of element combinations in A(q) will be termed C(q).

A(q) = {e' :f (c)=q; c € {0,l}^N},q € R (5)

Fig. 6b shows an example where 5 of the 2⁸ = 256 combinations of 8 unequal elements (1,2,3,4,5,6,7,8) sum up to q = 16. In other words, the value 16 is generated using 5 different combinations (Combl through Comb5) of element values (1,2,3,4,5,6,7,8) such that all elements are used equally often (4 times) .

For linear scaling, β' = (1, 2,...N) , R contains all integers from 0 to ∑^n&N² /2for 2^N combinations of N elements, which leaves significant redundancy.

Fig. 4 shows the number of combinations C(q) of 12 linearly scaled elements for the 79 reachable quantization levels (0,1, ...,78) .

D. Globally Optimized Element Selection

In the following, a concept for an element selection (or for a selection of combinations of elements) will be described. This conceptually simple, but computationally demanding element selection method keeps track of the accumulated element usage u[i] € N^N up to the current sample i.

u[i] = u[i-l] + e(q[i]), U[O]=O (6)

The element combination c[i] = c(q[i]) for quantization level q[i] is selected from A(q[i]) such that the standard deviation σ(u[i] ) across all N accumulated element usages in u[i] is minimized.

c[i]= arg min σ (u[i-l] +γ(q[i] ) ) (7) γ e A(q[i])

The required dynamic minimum-search makes this method difficult to implement in hardware (HW) . Nevertheless, if sufficient computational power is available in hardware, a hardware implementation is naturally also possible. However, for arbitrary waveform generators with pre-computed sample sequences (or pre-computed sequences of combinations of elements) , this algorithm can be readily implemented in software (SW) .

Details regarding the possible realization of this algorithm have been described with reference to Figs. 10 and 11. Naturally, the embodiment described with reference to Figs. 10 and 11 should be considered as examples only.

E. Element Selection per Quantization Level

In the following, another element selection method will be described that can be implemented in hardware (but naturally also in software) .

The idea is, for a given quantization level q, to create a sequence S(q) of element combinations Oj/ (q) in A(q), each combination included hi(q) times in the sequence such that all elements are used equally often, k times, and as few times as possible in order to shorten the time over which mismatch errors average out. It will be convenient to concatenate the combinations in A(q) row-wise C(q) x N binary matrix A(q) , where A_i:j(q)=l indicates that element combination Ci' for quantization level q includes element e-j . The occurrences hi(q) can now be computed from the following system of linear Diophantine equations using the extended Euclidean algorithm (which is, for example, described in the book "Abstract Algebra" of D. S. Dummit and R.M. Foote, John Wiley and Sons, 2003) in case a solution exists for any k, l<k≤k_max.

h(q)A(q)=k«l, h(q) e N^^(q), (8)

Where 1 = (1,1,...,1). The sequence length is

In Fig. 6b, h ( 16) = (1, 2, 2, 1, 3) and k=4 is a solution for combinations A(16) = (Ci' ;...; C5' ) • A possible sequence, where combinations A(16) = (ci' ;...; C₅' ) occur h (16) = (1, 2, 2, 1, 3) times is S (16) = (C₁' ,c₂' ,c₃' ,c₄' ,c₅' ,c₂' ,c₃' ,c₅' ,c₅' ) .

If an exact solution does not exist, combination occurrences h can be chosen to minimize the element usage variation within the constraint of a maximum sequence length L_max for any k,l≤k<k_max.

h(q) = argmin min ||η • A(q) - k • if

H€N^C(*> Y^C(9)π <L ^l≤k≤k™ ⁽¹⁰⁾

The resulting element usage variation is

V(q)=σ (h(q)«A(q) ) , (11)

where σ(a) is the standard deviation across vector a. Fig. 12 shows an element usage variation of all reachable quantization levels for N=12. Fig. 12 shows that for 12 linearly scaled elements and L_max = 64, 25 of 79 reachable quantization levels allow equal element usage and 43 have an element usage variation not exceeding 0.02. The smallest level without element usage variation equals at least the largest single element.

In some embodiments, the element usage variation may be defined as the square of the standard deviation σ(a) .

Quantization levels q with low enough element usage variation V(q)≤V_max and short enough sequence length L(q)≤L_max are extracted into set

Q= {q:q € R, V(q) < V_max, L(q) < L_max } . (12)

The number of extracted quantization levels |Q| in Q is a measure for the average resolution expressed in bits, and

Fig. 13 compares the resolution R in bits as a function of the number of elements N between equal elements, wherein R = Iog2 (N+l) , linear scaling for various maximum element usage variations, V_max, according to (13) , and binary scaling, where |Q|=2^N and thus R = N. As an example, Fig. 13 shows a resolution R in bits for linear element scaling with L_max =64, compared to equal elements and binary scaling.

As expected, linear scaling achieves a higher resolution than equal elements, but less than the steeper binary scaling. A higher allowed element usage variation increases the resolution, but will also reduce the effectiveness of element mismatch reduction.

This element selection method can be implemented in hardware, when the sequences S(q) are stored in a memory with dedicated pointers per quantization level (for example the memories 1350 of the sequence evaluators 1342a, wherein the counters 1352 act as pointers) . The large number of element combinations practically limits this to about 16 elements.

Over-Sampled Digital-to-Analog Converter with Unequal Elements

Fig. 14 shows a block diagram of a ΔΣ digital-to-analog converter with element correction of unequal elements. Blocks inside the dashed rectangle can be implemented in software (but can alternatively also be implemented in hardware) .

The digital-to-analog converter shown in Fig. 14 is designated in its entirety with 1800. The digital-to-analog converter 1800 comprises an input for a digital input signal 1810. Furthermore, the digital-to-analog converter 1800 is configured to provide an analog output quantity 1820. The digital-to-analog converter 1800 comprises a combination provider 1830, which is configured to provide a control signal 1832 describing combinations of elements. Furthermore, the digital-to-analog converter comprises an element combiner or component combiner 1840 which is configured to provide the analog output quantity 1820 by combining elements (or signals, for example currents provided by the elements) having actual values e, , ...e_N .

The combination generator 1830 comprises a feedback loop to act as a ΔΣ digital-to-analog converter. An input summing device (or input difference forming device) 1850 is configured to receive the input signal 1810 and to subtract therefrom a feedback signal, to provide a loop-filter input signal 1854. Furthermore, the combination generator 1830 comprises a loop- filter 1860 (for example an integrator) , which is configured to provide a filtered quantity x. Further, the combination generator 1830 comprises a quantizer 1870 which quantizer is configured to receive the filtered quantity x and to provide a quantized quantity q, based on the filtered quantity x. The quantizer 1817 is for example configured to evaluate a quantization function g(x, β) . The quantization function g may for example describe a mapping between the filtered input quantity x and the quantized quantity q, wherein the filtered quantity x may be mapped to a closest available sum value (taking into consideration the nominal values of the elements e) . The combination generator 1830 further comprises an element selector 1880 which element selector 1880 is configured to select a combination c of elements in response to the quantized quantity q. The element selector 1818 may, for example, be configured to perform the functionality of the step 620 of the method 600, or the functionality of the steps 1020, 1030, 1040, 1050, 1060, 1070 of the method 1000. In an example, the element selector 1880 may be configured to perform the functionality of the block 1340 of the apparatus 1300. In another embodiment, the element selector 1880 may be configured to perform the functionality of the steps 1410, 1420, 1430, 1460, 1470 of the method of 1400, and/or of the steps 1510, 1520 of the method 1500 according to Fig. 15. The combination provider 1830 may further comprise an element sum estimator 1890, which may be configured to receive an information describing the selected combination c of elements and to provide the information 1852 to describe an estimated sum of elements. The element sum estimator 1890 may be configured to consider estimated actual element values (rather than nominal element values) in the feedback loop. Accordingly, a particularly accurate feedback signal 1852 can be obtained, taking the deviation between nominal and actual element values into account.

In the following, further details regarding the digital-to- analog converter 1800 will be described. In some embodiments, the loop filter output x is quantized to q, for example, by using equation (4), based on the ideal element values β, e.g. β = {1, 2, 3, ... ,N} . Selected element combinations c for q can either be optimized globally or selected per quantization level, as is described in the sections entitled "Globally Optimized Element Selection" or "Element Selection per Quantization Level", respectively. In either case, the actual current output ^=C^{1 •} e is the sum of the selected actual current element 6, which may deviate slightly from e (the vector of nominal element values) . Since the actual current output q is not available, the ΔΣ-loop is closed with an estimated output q = c' • e, which is based on the known element combination c and the estimated element values S from calibration. When no estimate is available, the loop can be closed directly behind the quantizer output q. Compared to the publication "Analog Test Signal Generation Using Periodic ΣΔ- Encoded Data Streams" of B. Dufort, G. W. Roberts (Kluwer Academic Publishers, 2000) , where a binary-coded digital-to- analog converter is stimulated with over-sampled values, closed loop dynamic element matching of estimated unequal elements demands are rigorous distinction between quantization, element selection and element summation, such as shown in Fig. 14.

Verification

To verify the proposed dynamic element correction methods for unequal elements, the digital-to-analog converter architecture of Fig. 14 was simulated in "MATLAB" with 16 linearly scaled elements, and compared to results with the same number of equal or binary scaled elements. The comparison is based on the effective number of bits (ENOB) of a generated 10 kHz sine wave and its sensitivity to element estimation accuracy α in units of bits, where the individual estimation errors §i - ei of elements i= 1...N are uniformly distributed in [-0.5, +0.5] •2^"α. The over-sampled digital-to-analog converter uses a 20 Msa/s, fifth order ΔΣ-modulator with an over-sampling ratio of 32, i.e. the first 30 harmonics of the generated 10 kHz sine wave are visible in the modulator pass-band on 312 kHz and thus contribute to a reduced ENOB. Differences between ideal element values e, actual element values 6, an estimated element values e are the only source of performance degradation . Fig. 15 compares the sensitivity of ENOB to the element estimation accuracy α for four element scaling and correction methods. Fig. 15 shows a comparison of element scaling and selection methods for an over-sampled multi-bit digital-to- analog converter with 16 elements. Linear element scaling with globally optimized element selection is best when element values are known with 14 to 20 bit of accuracy.

"Linear (Global)" and "Linear (Per Level)" refer to linear element scaling with globally optimized element selection introduced in the section entitled "Globally Optimized Element Selection" and element selection per quantization level as introduced in the section entitled "Element Selection Per Quantization Level", respectively, parameterized with L_max = 32 and V_max = 0.01.

This is compared to a most commonly used multi-bit ΔΣ digital- to-analog converter architecture with data weighted averaging (DWA) of equal elements (R. Schreier, G. C. Temes, "Understanding delta-sigma data converters") , labeled "Equal", and to quantization with a binary coded digital-to-analog converter (B. Dufort, G. W. Roberts, "Analog Signal Generation Using Periodic ΣΔ encoded data streams") labeled "Binary".

Discussion

In the following, simulation results will be discussed. Binary scaling achieves the best peak ENOB performance, 23.9 bits owing to the largest number of quantization levels, 2^N. However, the lack of redundancy makes this method extremely sensitive to finite element estimation accuracy.

Equal elements, on the other extreme, reach only N+l quantization levels and thus achieve a peak ENOB of just 17,3 bits. Yet, DWA makes this architecture extremely insensitive to element estimation accuracy, as the element usage never varies by more than one count across all elements, independent of the sequence of quantization levels.

Linear scaling behaves somewhere in between. With « N²/2 quantization levels, its peak ENOB performance of 20,8 bits is a compromise between equal elements and binary element scaling. Redundant element combinations of quantization levels can be exploited to make linear scaling less sensitive to element estimation errors than binary scaling. However, it is far more sensitive than DWA of equal elements. Linear scaling with globally optimized element selection outperforms "binary" and "equal" by up to three effective bits, when element values are known with 14-20 bits of accuracy, which is a practically interesting range, when element values are measured during calibration. For a 16-bit accurate element calibration, linear element scaling adds 2.5 effective bits. Element selection quantization is more sensitive to element estimation errors, since element usage is balanced over longer periods of time.

Other element scalings, in other maximum element usage variations V_max, did not improve the above results.

Conclusion

The present description has introduced dynamic element correction methods for unequal elements. These methods can be applied to a novel multi-bit Δ∑-digital-to-analog converter architecture, for globally optimized element selection providing significant performance improvements for arbitrarily wave form generators with measured element values and pre- computed samples. Element selection per quantization level has been proposed for cases where a hardware implemented is required. Nevertheless, all the methods can be implemented in built-in hardware and in software. Naturally, combined implementations are possible.

Claims

Claims :

1. Apparatus (100; 1300) for combining electrical or electronic components (142a to 142c; 1392a to 1392c) based on a digital input signal (110; 1312) which can take a plurality of values out of a range of values, so as to generate an analog quantity (120; 1322) corresponding to the digital input signal, the apparatus comprising:

a combination generator (130; 1310) adapted to supply, in dependence on the input signal, a control signal (132; 1314) describing a sequence of combinations of electrical or electronic components,

wherein for a given value of the digital input signal, at least two different combinations of electrical or electronic components associated with the given value are available, at least one of the combinations including at least two electrical or electronic components having different nominal values, and

wherein the combination generator is configured to provide the control signal such that in response to the given value, the control signal describes, in the course of time, a plurality of different combinations of electrical or electronic components; and

a component combiner (140; 1320) comprising a plurality of electrical or electronic components (142a to 142c; 1392a tO 1392c) , at least two of which electrical or electronic components comprise different nominal values,

wherein the component combiner is adapted to select, in dependence on the control signal, different sets of the electrical or electronic components to be combined from the plurality of electrical or electronic components.

2. The apparatus (100; 1300) according to claim 1, wherein the combination generator is configured to provide the control signal (132; 1370) such that the electrical or electronic components are used approximately equally often in the course of time.

3. The apparatus (100; 1300) according to one of claims 1 to 2, wherein the combination generator (130; 1310) comprises a list (1210; 1212; 1214; 1216) representing a sequence (S (q) ) of different combinations of electrical or electronic components associated with the given value (q) , and

wherein the combination generator is configured to cyclically select a predetermined number of one or more combinations from the list for each occurrence of the given value in the digital input signal (110; 1312) and to supply the control signal (132; 1314) to describe the one or more selected combinations.

4. The apparatus (100; 1300) according to claim 3, wherein a number of entries of the list (1212, 1214) is larger than the predetermined number of combinations selected for each occurrence of the given value, and

wherein the combination generator (130; 1310) is configured such that the control signal (132; 1314) describes a cyclic sequence of combinations of electrical or electronic components (142a to 142c; 1392a to 1392c) over subsequent occurrences of the given value.

5. The apparatus (100; 1300) according to one of claims 3 to 4, wherein the different combinations of electrical or electronic components (142a to 142c; 1392a to 1392c) represented by the list (1212; 1214) are chosen such that a component usage variation (V (q) ) describing a standard deviation of frequencies of usage of different components is smaller than 0.02.

6. The apparatus (100; 1300) according to one of claims 3 to

5, wherein the combinations of electrical or electronic components represented by the list (1212; 1214) are chosen such that over a complete pass through the list, the components included in the combinations represented by the list are used equally often.

7. The apparatus (100; 1300) according to one of claims 1 to

6, wherein the combination generator (130; 1310) comprises a plurality of lists (1210, 1212, 1214, 1216) associated with different given values,

each of the lists (1210, 1212, 1214, 1216) representing a respective sequence of combinations associated with a corresponding given value, and

wherein the combination generator is configured to provide the control signal (132; 1314) to describe, in response to respective samples of the digital input signal (110; 1312), one or more of the combinations of the lists corresponding to the values of the respective samples .

8. The apparatus (100; 1300) according to claim 7, wherein the combination generator (130; 1310) is configured to provide the combinations of the lists (1210, 1212, 1214, 1216) in a cyclic manner, to provide cyclically subsequent combinations of a given list for subsequent occurrences of a sample value associated with the given list, and

wherein the combination generator (130; 1310) is configured to independently track current positions within the lists, and to select, in response to a current sample of the digital input signal, one of the combinations from the list associated with the value of the current sample, taking the current position within the list associated with the value of the current sample into account.

9. The apparatus (100; 1300) according to one of claims 1 to 11, wherein the combination generator (130; 1310) is configured to select a sequence out of a plurality of different sequences of component combinations in dependence on the given value, and to supply the control signals such that the control signal describes one or more component combinations of the selected sequence.

10. The apparatus (100; 1300) according to claim 1 or 2, wherein the combination generator is configured to determine a sequence of combinations of electrical or electronic components for a sequence of digital input samples describing the digital input signal, such that the sequence of combinations comprises one or more combinations of electrical or electronic components for each of the digital input samples,

wherein different sets (A(q)) of combinations are associated with different values (q) of the digital input samples, and

wherein the combination generator is configured to choose a combination of electrical or electronic components for a respective digital input sample from a set (A(qi)) of combinations associated with a value (q(i) of the respective digital input sample, to act towards a balanced time-accumulated usage of electrical or electronic components.

11. The apparatus (100; 1300) according to claim 10, wherein the combination generator is configured to track an accumulated frequency of usage (u[i-l] ) of electrical or electronic components over time, or to track an imbalance of an accumulated frequency of usage of the electrical or electronic components over time, and wherein the combination generator is configured to choose a combination (c[i]) of electrical or electronic components for the respective digital input sample (i) from the set (A(q(i)) of combinations associated with the value (q(i)) of the digital input sample, to minimize an imbalance of the accumulated frequency of usage (u[i]) taking into account the chosen combination, or

to act towards a minimization of an imbalance of the accumulated frequency of usage taking into account the chosen combination.

12. The apparatus (100; 1300) according to claim 11, wherein the combination generator is configured to choose a combinations of electrical or electronic components for the respective digital input sample from the set of combinations (A(q(i)) associated with the value (q(i)) of the digital input sample, to minimize a variance of the accumulated frequency of usage (u[i]) taking the chosen combination into account.

13. The apparatus (100; 1300) according to claim 10, wherein the combination generator is configured to choose, on the basis of the set of combinations (A(q(i)) associated with the value (q(i)) of the digital input sample, a combination of elements resulting in an imbalance value (σ) which is smaller than or equal to a predetermined threshold value.

14. The apparatus (100; 1300) according to one of claims 1 to 13, wherein the combination generator (130; 1310) is configured to provide the control signal (132; 1314) describing which sets of electrical or electronic components are to be combined, such that a sum of nominal component values of electrical or electronic components to be combined remains constant for different combinations of the components associated with the given value .

15. The apparatus (100; 1300) according to one of claims 1 to

14, wherein the component combiner (140; 1320) is adapted to combine the subset of components described by the control signal, so as to obtain a combination of the electrical or electronic components, such that the combination of electrical or electronic components comprises a nominal sum value corresponding to a summation of the nominal values of the combined components of the subset.

16. The apparatus (100; 1300) according to one of claims 1 to

15, wherein the nominal values of at least two of the electrical or electronic components comprised by at least one of the combinations differ by a difference value, which difference value amounts to at least 20% of the smallest one of the nominal values of the electrical or electronic components to be combined.

17. The apparatus (100; 1300) according to one of claims 1 to

16, wherein nominal values of the electrical or electronic components (142a to 142c; 1392a to 1392c) are chosen such that the number of possible nominal sum values of combinations of the components exceeds the number of the electrical or electronic components at least by 2.

18. The apparatus (100; 1300) according to one of claims 1 to

17, wherein the nominal values of the electrical or electronic components (142a to 142c; 1392a to 1392c) describe a linear series, or wherein the nominal values of the electrical or electronic components (142a to 142c; 1392a to 1392c) describe a double linear series, or wherein the nominal values of the electrical or electronic components (142a to 142c; 1392a to 1392c) describe a Fibonacci-series.

19. A method for combining electrical or electronic components based on a digital input information, which can take a plurality of values out of a range of values, so as to generate an analog quantity corresponding to the digital input information, the method comprising:

forming a sequence of combinations of the electrical or electronic components, at least two of which electrical or electronic components comprise different nominal values, in dependence on the digital input information,

wherein, in response to a given value of the digital input information, at least two different combinations of electrical or electronic components are formed in the course of time, at least one of the different combinations comprising at least two electrical or electronic components having different nominal values.

20. An apparatus (130; 1310) for providing a combination information signal (132; 1314) describing a sequence of combinations of electrical or electronic components based on a digital input signal (110; 1312) which can take a plurality of values out of a range of values, so as to describe combinations of elements for generating an analog quantity corresponding to the digital input signal, the apparatus comprising:

a combination generator adapted to supply, in dependence on the digital input signal (110; 1312), the combination information signal (132; 1314),

wherein, for a given value of the digital input signal (110; 1312), at least two different combinations of the electrical or electronic components associated with the given value are available, at least one of the combinations including at least two electrical or electronic components having different nominal values, and wherein the combination generator is configured to provide the combination information signal such that, in response to the given value, the combination information signal describes, in the course of time, a plurality of different combinations of electrical or electronic components .

21. A method for providing a combination information signal describing a sequence of combinations of electrical or electronic components based on a digital input signal which can take a plurality of values out of a range of values, so as to describe combinations of elements for generating an analog quantity corresponding to the digital input signal, the method comprising:

supplying, in dependence on the digital input signal, the combination information signal,

wherein, for a given value of the digital input signal, at least two different combinations of the electrical or electronic components associated with the given value are available, at least one of the combinations including at least two electrical or electronic components having different nominal values, and

wherein the combination information signal is provided such that in response to the given value, the combination information signal describes, in the course of time, a plurality of different combinations of electrical or electronic components.

22. An apparatus for determining a sequence (S (q) ) of combinations of electrical or electronic components for a given digital input value (q) , the apparatus comprising:

a combination determinator configured to determine a plurality (A(q)) of different combinations of electrical or electronic components, the determined combinations having nominal sum values of the included components associated with the digital input value (q) ; and

a sequence provider configured to provide the sequence (S (q) ) of combinations on the basis of the determined combinations, (A(q)) wherein the sequence provider is configured to choose a frequency of occurrence (h(q)) of the different determined combinations within the sequence (S (q) ) of combinations to act towards a balanced usage of the electrical or electronic components in the sequence of combinations.

23. The apparatus according to claim 22, wherein the apparatus is configured to solve a linear Diophantine equation of the form

h(q) A(q) = k • 1

to determine the frequency of occurrence of the different determined combinations,

wherein h(q) is a vector describing the frequency of the occurrence of the different combinations,

wherein A(q) is a matrix describing which elements are included in the different determined combinations, and

wherein k is an integer number.

24. A method for determining a sequence (S (q) ) of combinations of electrical or electronic components for a given digital input value (q) , the method comprising:

determining (614) a plurality of different combinations (A(q)) of electrical or electronic components, the determined combinations having nominal sum values of the included components associated with the given digital input value (q) ; and

providing (616) the sequence (S (q) ) of combinations on the basis of the determined combinations, wherein a frequency of occurrence (h(q)) of the different determined combinations within the sequence of combinations is chosen to act towards a balanced usage of the electrical or electronic components in the sequence of combinations.

25. A computer program for performing a method according to claim 19, claim 21 or 24, when the computer program runs on a computer.