WO2010147049A1

WO2010147049A1 - Data signal-line driving circuit, liquid-crystal display device, and driving method of liquid-crystal display device

Info

Publication number: WO2010147049A1
Application number: PCT/JP2010/059870
Authority: WO
Inventors: 淳森脇
Original assignee: シャープ株式会社
Priority date: 2009-06-16
Filing date: 2010-06-10
Publication date: 2010-12-23
Also published as: JP2011002513A; TW201106332A; JP5073712B2

Abstract

A data signal-line driver (30) that outputs, to source lines (22) of a liquid-crystal panel (20), data signals that are in accordance with gradation data, as adjacent outputs with opposite polarities; wherein the data signal-line driver (30) is provided with a polarity-switching control circuit (44) that reverses the polarities of adjacent outputs of polarity-reversal switching circuits (33, 41), based on a control signal (Ctrl_REV); an output short-circuiting control circuit (45) that short-circuits adjacent outputs of short-circuit switching circuits (40), based on a control signal (Ctrl_CS); and an assessing circuit (43) that successively obtains gradation data, and selectively outputs the control signal (Ctrl_REV) and the control signal (Ctrl_CS), based on a display pattern, consisting of penetrating-states and non-penetrating-states at adjacent outputs, of the majority of the one-line's worth of gradation data that was obtained the last time, and a display pattern of the majority of the one-line's worth of gradation data that was obtained currently. In such a way, current consumption is reduced, and heating due to this current consumption is reduced, when displaying a peculiar image upon source-block reversal driving.

Description

Data signal line driving circuit, liquid crystal display device, and liquid crystal display device driving method

The present invention relates to a data signal line driving circuit, a liquid crystal display device, and a driving method of the liquid crystal display device, and in particular, dot inversion driving for changing the polarity for each data signal line and scanning signal line, In the source block inversion driving, in which the scanning interval is divided and the interlaced scanning is performed in the interval, the data signal line driving circuit recognizes the image pattern separately from the control of the liquid crystal display device, and independently performs the polarity inversion. The present invention relates to a technique for performing control and charge share control.

Conventionally, active matrix liquid crystal panels have been widely used. An active matrix type liquid crystal panel crosses a plurality of data signal lines (hereinafter referred to as “data lines”) and the plurality of data lines on one of the two transparent substrates sandwiching the liquid crystal layer. A plurality of scanning signal lines are formed, and pixel electrodes formed corresponding to each intersection are arranged in a matrix (matrix). Each pixel electrode is connected to a data line passing through a corresponding intersection through a TFT (Thin Film Transistor) as a switching element, and a gate terminal of the TFT is connected to a scanning signal line passing through the intersection. Has been. On the other transparent substrate, a common electrode common to a plurality of pixel electrodes is formed as a common electrode.

The liquid crystal display device including the liquid crystal panel having such a configuration includes a gate driver and a source driver as a drive circuit for displaying an image on the liquid crystal panel. The gate driver is also called a scanning signal line driving circuit, and is a driving circuit that applies a scanning signal for sequentially selecting a plurality of scanning signal lines to the plurality of scanning signal lines. The source driver is also called a data signal line drive circuit or a video signal line drive circuit, and is a drive circuit that applies a data signal for writing data to each pixel formation portion in the liquid crystal panel to a plurality of data lines.

The common voltage Vcom is applied to the common electrode facing the pixel electrode. A data signal is applied from the source driver to the pixel electrode selected by the gate driver. An image is displayed on the liquid crystal panel by changing the transmittance of the liquid crystal layer according to the voltage applied between each pixel electrode and the common electrode. At this time, the liquid crystal panel is AC driven in order to prevent deterioration of the liquid crystal material constituting the liquid crystal layer. That is, the source driver outputs a data signal so that the positive and negative polarities of the voltage applied between each pixel electrode and the common electrode are inverted, for example, every frame.

However, in general, in an active matrix liquid crystal panel, characteristics of switching elements such as TFTs provided for each pixel vary, and therefore, a data signal output from a source driver (applied voltage based on the potential of the common electrode). The transmittance of the liquid crystal layer is not completely symmetric with respect to the positive and negative data signals even if the positive and negative signs of) are symmetric. For this reason, in the driving method (frame inversion driving method) in which the positive / negative polarity of the voltage applied to the liquid crystal layer is inverted every frame, flickering occurs in the display on the liquid crystal panel.

As a countermeasure against such flickering, there is known a driving method in which the positive / negative polarity of the applied voltage is inverted for each horizontal scanning signal line and the positive / negative polarity is inverted for each frame. Also known is a driving method (dot inversion driving method) that inverts the positive / negative polarity of the voltage applied to the liquid crystal layer forming the pixel for each scanning signal line and for each data line, and for each frame. ing.

FIG. 20 shows the output waveform of the source driver when the liquid crystal panel is driven by the dot inversion driving method. As shown in FIG. 20, the source driver has a positive data signal Vpdata having a voltage higher than the common voltage Vcom applied to the common electrode and a negative data having a voltage lower than the common voltage Vcom for each scanning signal line. The output with the signal Vndata is repeated.

However, the source driver is provided with a number of output buffers, and each of the output buffers is connected to each data line and drives the load of each data line and each liquid crystal cell. For this reason, when the source driver outputs the positive data signal Vpdata, a charging current from the high potential voltage VDD flows to the load. On the other hand, when the source driver outputs the negative data signal Vndata, a discharge current to the low potential voltage VSS flows. Since the charging current and the discharging current pass through the internal resistance in the output buffer provided in the source driver, the amount of heat generation increases.

¡Heat generation from inside the source driver mainly occurs from the output buffer. Therefore, in order to reduce the heat generation amount of the source driver, the heat generation from the output buffer section, particularly the heat generation from the output section of the output buffer must be minimized. However, as shown in FIG. 20, when the potential of the data signal swings between the positive data signal Vpdata and the negative data signal Vndata, the heat generated by the internal resistance in the output buffer increases according to the width of the swing. Moreover, since the number of times of charging / discharging increases, power consumption also increases.

Therefore, as one method for preventing the increase in power consumption, a driving method using interlaced scanning (interlace driving method) has been proposed (for example, see Patent Document 1). In the interlace scanning described in Patent Document 1, all odd-numbered (or even-numbered) scanning signal lines are scanned first, and then the remaining even-numbered (or odd-numbered) scanning signal lines are scanned.

Fig. 21 shows the output waveform of the source driver when interlaced scanning is performed. In interlaced scanning, rows of pixels with the same polarity are sequentially scanned, so that polarity inversion is performed at the timing when switching from odd-numbered line scanning to even-numbered line scanning is performed. FIG. 22 shows the output waveform of the source driver when the output state shown in FIG. 21 is rearranged in order of 1, 2, 3,... According to FIG.

FIG. 22 shows the output waveform of the source driver at the time when one frame of scanning, that is, scanning of both odd and even lines, is completed when interlaced scanning is performed. The output waveform of the source driver is the same as the output waveform of the source driver in the dot inversion driving method shown in FIG.

Thus, in interlaced scanning, polarity inversion driving for each scanning signal line is possible and the number of polarity inversions can be suppressed. Therefore, the number of times of charging / discharging is reduced, and an increase in power consumption can be suppressed.

However, as in Patent Document 1, when interlaced scanning is performed over the entire screen of the liquid crystal panel, flickering is caused. Therefore, the display unit is divided into a plurality of areas in the column direction, and driving for performing interlaced scanning scanning for each area is performed. A method has been proposed (see, for example, Patent Document 2).

FIG. 23 shows a scanning order when the driving described in Patent Document 2 is performed. A display portion having 8 lines of pixel electrodes is divided into a section 1 and a section 2. Then, interlaced scanning is performed in order from odd two lines to even two lines for each section. In this scanning, data signals having different polarities are given during each selection period of the area 1 and the area 2, and flickering can be suppressed. This driving method is called a source block inversion driving method.

Further, as a method for reducing power consumption associated with charging / discharging of liquid crystal in the dot inversion driving, there is a method described in Patent Document 3 called charge sharing. In this method, in the blanking period, the digital / analog converting means and the output terminal are disconnected by a disconnect switch, and the output terminals are short-circuited by a short-circuit switch. Thereby, when inverting the drive signal applied to the same output terminal, it is possible to eliminate power consumption during a period from when the output terminals are short-circuited to the same potential.

The above power consumption occurs in the period from when the output terminals are short-circuited to the same potential until the inversion, but the potential of the output terminals that have become the same potential due to the short-circuit between the output terminals is the driving during inversion. Since it is close to the potential of the signal, power consumption when the drive signal is inverted can be reduced.

However, it is a source block inversion driving method that is originally a driving method that consumes less current and generates less heat. However, when a special image pattern called a killer pattern is displayed, current consumption increases and a problem of heat generation occurs. I understand that.

FIG. 24 shows a pattern called a killer pattern of the source block inversion driving method, where (a) shows the pattern, (b) shows an odd line pattern, and (c) shows an even line pattern. Show.

As shown in FIG. 24A, the killer pattern is a pattern in which black and white are alternately displayed for every two pixels in the scanning signal line direction, and black and white are alternately displayed for each data line. is there. When this killer pattern is interlaced, the odd lines are displayed as shown in FIG. 24B, and the even lines are displayed as shown in FIG. For this reason, the source driver outputs a black driving voltage and a white driving voltage each time the driving voltage of one scanning signal line is output.

Here, in the case of a normally white display type, the white driving voltage is equal to the voltage of the common electrode of the liquid crystal panel so that no voltage is applied to the liquid crystal pixels. The black driving voltage is a voltage for applying a voltage to the liquid crystal pixels, and a positive voltage (positive polarity) and a negative voltage (negative polarity) may be applied to the common electrode. For example, the white driving voltage is 6V, while the black driving voltage is 0V and + 12V. Therefore, when the output of the source driver alternately outputs black and white, the output voltage changes for each scanning signal line, so that current consumption increases and heat generation becomes a problem.

In the source block inversion driving method, since the interlace scanning is performed in the block, the polarity does not change every scanning, so it is common not to perform charge sharing. However, here, in order to reduce power consumption, source block inversion driving Let us consider a case where charge sharing between outputs is performed as shown in Patent Document 3 when a killer pattern is displayed. For example, as shown in FIG. 24B, line 1 of output 1 is black with positive polarity, and line 1 of output 2 is white with negative polarity. This potential state is shown in FIGS.

25A shows a change in the potential of output 1 and FIG. 25B shows a change in the potential of output 2 when charge sharing is performed between output 1 and output 2. FIG. In source block inversion drive, charge sharing is performed between line 1 and line 3, so when output 1 and output 2 are short-circuited, the voltage of output 1 and the voltage of output 2 are intermediate between + black and -white. The voltage is “a”. Then, after opening the short circuit, output 1 outputs a + white voltage and output 2 outputs a -black voltage in order to display on line 3.

As a result, since the output 2 becomes a black voltage to be output on the line 3 after the potential changes in the opposite direction, the output 2 is compared with the case where the charge sharing is not performed when the black voltage is output. It is necessary to pass a large amount of current. The same is true when scanning from line 3 to line 5; output 1 outputs + black because the output 1 and output 2 are short-circuited, resulting in a voltage of “b” that is an intermediate voltage between + white and −black. When doing so, more current is required. Therefore, when a killer pattern is displayed by performing source block inversion driving, charge sharing between outputs is not effective in reducing power consumption.

Therefore, for example, Patent Document 4 describes a technique for performing charge sharing by determining a representative gradation of an image. In the technique described in Patent Document 4, charge sharing is not performed for each data in the dot inversion driving every two lines in the vertical direction, but (1) charge sharing is performed every time the polarity of the data voltage is changed. Charge sharing is performed when there is no change and when the displayed gradation and the gradation to be displayed change from white to black (when the representative gradation changes from the white gradation to the black gradation).

In the technique described in Patent Document 4, normally, the dot inversion drive is performed for each line in the horizontal direction. However, when the weak pattern is detected, the weak pattern is also obtained by performing the dot inversion for every two lines in the horizontal direction. The display trouble in is prevented from occurring.

Japanese Patent Publication “Japanese Patent Laid-Open No. 8-32074 (published on Dec. 3, 1996)” Japanese Patent Publication “Japanese Patent Laid-Open No. 11-352938 (published December 24, 1999)” Japanese Patent Publication “Japanese Patent Laid-Open No. 9-212137 (published on August 15, 1997)” Japanese Patent Publication “JP 2009-9088 (published Jan. 15, 2009)”

However, the technique described in Patent Document 4 has a problem that current consumption increases when charge sharing is applied in displaying a specific pattern as shown in FIG. A valid charge share cannot be applied to the pattern.

27A shows the potential change of output 1 and FIG. 27B shows the potential change of output 2 when charge sharing is performed between output 1 and output 2 in the pattern shown in FIG. . When charge sharing is performed between the output 1 and the output 2, as shown in FIGS. 27A and 27B, the points a and b become the charge sharing voltage. Therefore, in particular, in the output 2 shown in FIG. 27 (b), a phenomenon occurs in which the current consumption increases.

For this reason, in Patent Document 4, charge sharing is performed only when the color changes from white to black, and it corresponds to the case where the color changes from black to white, or from black and white to black and white, and from black and white to black and white. I can't. Further, in Patent Document 4, although a weak pattern is detected, as described above, the countermeasure is not to perform charge sharing, and thus the current consumption is not sufficiently reduced.

The present invention has been made in view of the above-described conventional problems, and its purpose is to reduce current consumption even when displaying a special image called a killer pattern in source block inversion driving. Another object of the present invention is to provide a data signal line driving circuit, a liquid crystal display device, and a driving method for the liquid crystal display device, which can reduce heat generation due to this.

In order to solve the above problems, a data signal line driving circuit of the present invention includes a plurality of pixel electrodes arranged in a matrix, a plurality of scanning signal lines for supplying scanning signals to the pixel electrodes in the same row, and For the liquid crystal display unit having a plurality of data signal lines for supplying data signals to the pixel electrodes in the same column, each data signal line of the liquid crystal display unit is created according to the gradation data. A data signal line drive circuit for outputting data signals with opposite polarities at adjacent outputs, polarity inversion means for inverting the polarity of the adjacent outputs, and short-circuit means for short-circuiting between the adjacent outputs, The first control means for inverting the polarity of the adjacent output to the polarity inverting means based on the first control signal, and the adjacent output to the short-circuit means based on the second control signal. And a second control means for outputting the first control signal to the first control means and a determination means for outputting the second control signal to the second control means. The odd-numbered or even-numbered scanning signal lines are scanned in order after the liquid crystal display section is divided into a plurality of sections in the column direction, and then the even-numbered or odd-numbered scanning signal lines are scanned in order. The determination means sequentially acquires the gradation data, and the display at the adjacent output in the previously acquired gradation data for one row is transmitted. The display pattern of the majority of the display pattern consisting of the transparent state that becomes non-transparent and the non-transparent state that becomes non-transparent, and the transmissive state and non-transparent state of the adjacent output in the gradation data for one row acquired this time From Based on the majority of the display pattern of the display pattern that is characterized by selectively outputting the first control signal and the second control signal.

According to the above configuration, the determination means includes the majority display pattern in one line corresponding to the scanning signal line previously scanned by the interlaced scanning and the majority in one line corresponding to the scanning signal line currently scanned. Based on the display pattern, whether or not it is effective to invert polarity between adjacent outputs and perform charge sharing between adjacent outputs, and charge sharing between adjacent outputs without performing the above polarity inversion It is possible to determine whether or not it is effective. That is, the determination means can recognize the pattern of the image to be displayed and make the above determination.

When it is determined that it is effective to invert the polarity with adjacent outputs and perform charge sharing between adjacent outputs, the first control means outputs both the first control signal and the second control signal. The polarity inversion means inverts the polarity of adjacent outputs, and the second control means causes the short-circuit means to short-circuit between adjacent outputs.

In addition, when it is judged that it is effective to perform charge sharing between adjacent outputs without performing polarity reversal, the second control means outputs a short circuit between adjacent outputs by outputting the second control signal. To do.

Therefore, since effective charge sharing is performed, when the liquid crystal display unit displays a special image called a killer pattern in driving in which interlaced scanning is performed for each of the divided areas in the column direction. However, current consumption can be reduced, and heat generation due to this can be reduced.

The liquid crystal display device of the present invention includes a plurality of pixel electrodes arranged in a matrix, a plurality of scanning signal lines for supplying scanning signals to the pixel electrodes in the same row, and a data signal to the pixel electrodes in the same column. A liquid crystal display unit having a plurality of data signal lines for supplying each of the data signals, and the data signal created according to the gradation data to each of the data signal lines of the liquid crystal display unit with opposite outputs at adjacent outputs. And a data signal line driving circuit that outputs the data.

According to the above configuration, since the charge sharing is effectively performed in the data signal line driving circuit, in the driving in which the liquid crystal display unit performs interlaced scanning for each of the divided areas in the column direction, a killer pattern and Even when displaying a special image called, it is possible to realize a liquid crystal display device that reduces current consumption and reduces heat generation.

The liquid crystal display device driving method of the present invention includes a plurality of pixel electrodes arranged in a matrix, a plurality of scanning signal lines for supplying scanning signals to the pixel electrodes in the same row, and the pixel electrodes in the same column. A liquid crystal display unit having a plurality of data signal lines for supplying data signals to the liquid crystal display unit, and each data signal line of the liquid crystal display unit has the polarity of the data signal created according to the gradation data with an adjacent output. A method of driving a liquid crystal display device comprising a data signal line drive circuit that outputs each of them in reverse, wherein the gradation data is divided into an odd row or a row for each area in which the liquid crystal display section is divided into a plurality of columns. Corresponding to the interlaced scanning in which the even-numbered or odd-numbered scanning signal lines are sequentially scanned after the even-numbered scanning signal lines are sequentially scanned, the gradation data is Next, the majority display pattern of the display pattern consisting of a transmission state in which the display at the adjacent output is transparent and a non-transmission state in which it is non-transparent in the gradation data for one line acquired last time, and this time The adjacent output of the data signal line driving circuit based on the display pattern of the majority of the display patterns composed of the transmission state and the non-transmission state in the adjacent output in the acquired gradation data for one row. The first step of determining whether the polarity inversion and the short circuit between the adjacent outputs of the data signal line driving circuit are necessary, and the adjacent output of the data signal line driving circuit when the polarity inversion is determined to be necessary And a third step of performing a short circuit between adjacent outputs of the data signal line drive circuit when it is determined that the short circuit is necessary. It is a symptom.

According to the above configuration, the majority display pattern in one line corresponding to the scanning signal line previously scanned by interlaced scanning, and the majority display pattern in one line corresponding to the scanning signal line currently scanned are Based on the above, whether or not it is effective to perform polarity inversion at adjacent outputs of the data signal line drive circuit and charge sharing between adjacent outputs, and between adjacent outputs without performing the above polarity inversion It is possible to determine whether or not charge sharing is effective. That is, the above determination can be made by recognizing the pattern of the image to be displayed.

If it is determined that it is effective to invert the polarity of the adjacent outputs and perform charge sharing between the adjacent outputs, the polarity of the adjacent outputs of the data signal line drive circuit is reversed and the data signal line drive circuit Short circuit between adjacent outputs. If it is determined that it is effective to perform charge sharing between adjacent outputs without performing polarity inversion, a short circuit between adjacent outputs of the data signal line driving circuit is performed.

Therefore, since effective charge sharing is performed, even when the liquid crystal display unit displays a special image called a killer pattern in driving in which interlaced scanning is performed for each of the divided areas in the column direction. Thus, current consumption can be reduced, and heat generation due to this can be reduced.

As described above, the data signal line driving circuit of the present invention includes a plurality of pixel electrodes arranged in a matrix, a plurality of scanning signal lines for supplying scanning signals to the pixel electrodes in the same row, and the same column. With respect to a liquid crystal display unit having a plurality of data signal lines for supplying data signals to the pixel electrodes, the data signal created according to the gradation data is applied to each data signal line of the liquid crystal display unit. A data signal line drive circuit for outputting the opposite outputs of the adjacent outputs, the polarity inversion means for inverting the polarity of the adjacent outputs, the short-circuit means for short-circuiting the adjacent outputs, and a first control Based on the signal, the first control means for inverting the polarity of the adjacent output with respect to the polarity inverting means, and the short-circuit means with respect to the adjacent output based on the second control signal. A second control unit; and a determination unit that outputs the first control signal to the first control unit and outputs the second control signal to the second control unit. In each area where the display section is divided into a plurality of columns, the odd-numbered or even-numbered scanning signal lines are sequentially scanned, and then the even-numbered or odd-numbered scanning signal lines are scanned sequentially. The determination means sequentially obtains the gradation data corresponding to the scanning, and the transmission at the adjacent output in the gradation data for one line obtained last time becomes transparent. Display of the transmission state and the non-transmission state at the adjacent output in the display pattern of the majority of the display patterns consisting of the non-transmission state and the non-transmission state and the gradation data for one row acquired this time Patter Based on the majority of the display pattern of emission is selectively output to constitute the first control signal and the second control signal.

Further, the driving method of the liquid crystal display device of the present invention includes a plurality of pixel electrodes arranged in a matrix, a plurality of scanning signal lines for supplying scanning signals to the pixel electrodes in the same row, and the above in the same column. A liquid crystal display unit having a plurality of data signal lines for supplying data signals to the pixel electrodes respectively, and the data signal created according to the gradation data to each data signal line of the liquid crystal display unit with adjacent outputs A driving method of a liquid crystal display device comprising a data signal line driving circuit that outputs the signals with opposite polarities, wherein the gradation data is an odd number for each area in which the liquid crystal display section is divided into a plurality of columns. Corresponding to the interlaced scanning in which the scanning signal lines in the even or odd rows are sequentially scanned after the scanning signal lines in the rows or the even rows are sequentially scanned, the gradation data is supplied. The display pattern of the majority of the display pattern consisting of a transmission state in which the display at the adjacent output is transparent and a non-transmission state in which the transmission is non-transparent in the gradation data for one row acquired previously. Based on the display pattern of the majority of the display pattern composed of the transmission state and the non-transmission state in the adjacent outputs in the gradation data for one row acquired this time, the adjacent data signal line driving circuit A first step of determining whether polarity inversion of matching outputs and a short circuit between adjacent outputs of the data signal line driving circuit are necessary, and when determining that polarity inversion is necessary, adjacent to the data signal line driving circuit A second step of performing polarity reversal of matching outputs and a third step of performing a short circuit between adjacent outputs of the data signal line drive circuit when it is determined that the short circuit is necessary. It is the law.

Therefore, since effective charge sharing is performed, the liquid crystal display unit displays a special image called a killer pattern in a drive in which interlaced scanning is performed for each of the divided areas in the column direction. In addition, there is an effect that current consumption can be reduced and heat generation due to this can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an embodiment of a liquid crystal display device according to the present invention, and is a block diagram illustrating a case where a polarity inversion switch circuit is switched to an a side. In the said liquid crystal display device, it is a block diagram which shows when the polarity inversion switch circuit is switched to the b side. It is a block diagram which shows one structural example of the judgment circuit in the said liquid crystal display device. It is a circuit diagram which shows one structural example of the pattern detection circuit in the said determination circuit. It is a block diagram which shows the example of 1 structure of the black collation circuit in the said pattern detection circuit. It is a truth table of the logic circuit in the said black collation circuit. It is a block diagram which shows one structural example of the white collation circuit in the said pattern detection circuit. It is a truth table of a logic circuit in the white matching circuit. It is a circuit diagram which shows one structural example of the pattern collation circuit in the said pattern detection circuit. It is a table | surface which shows the input and output state of the said pattern collation circuit in the display state of the adjacent output pair of the data signal line drive driver of the said liquid crystal display device. It is a truth table of the counter in the pattern detection circuit. It is a circuit diagram which shows one structural example of the polarity inversion and charge share determination circuit in the said judgment circuit. It is a flowchart which shows the processing flow when displaying one screen of the data signal line drive driver in the said liquid crystal display device. It is a flowchart which shows the flowchart 1 performed with the processing flow of FIG. It is a flowchart which shows the flowchart 2 performed with the processing flow of FIG. It is a figure which shows a pattern when the polarity of a killer pattern is reversed, (a) shows the said pattern, (b) shows the pattern of an odd line, (c) shows the pattern of an even line. FIG. 17 is a diagram showing a potential change when charge sharing is performed between output 1 and output 2 of the pattern of FIG. 16, (a) shows a potential change of output 1, and (b) shows a potential change of output 2. Indicates. It is a figure which shows the pattern of 2 rows horizontal stripes, (a) shows the said pattern, (b) shows the pattern of an odd line, (c) shows the pattern of an even line. FIG. 19 is a diagram showing a potential change when charge sharing is performed between the output 1 and the output 2 of the pattern of FIG. 18, (a) shows the potential change of the output 1, and (b) shows the potential change of the output 2. Indicates. It is a figure which shows the output waveform of a source driver at the time of driving a liquid crystal panel by a dot inversion drive system. It is a figure which shows the output waveform of the source driver at the time of performing interlaced scanning. It is a figure which shows the output waveform of a source driver at the time of scanning of both odd-numbered rows and even-numbered rows when interlaced scanning is performed. It is a figure which shows the scanning order at the time of performing a source block inversion drive. It is a figure which shows the pattern called a killer pattern of a source block inversion drive system, (a) shows the said pattern, (b) shows the pattern of odd lines, (c) shows the pattern of even lines. FIG. 25 is a diagram illustrating a potential change when charge sharing is performed between the output 1 and the output 2 of the pattern of FIG. 24, where (a) illustrates a potential change of the output 1 and (b) illustrates a potential change of the output 2. Indicates. It is a figure which shows a specific pattern. 27 is a diagram showing a potential change when charge sharing is performed between the output 1 and the output 2 of the pattern of FIG. 26, (a) shows the potential change of the output 1, and (b) shows the potential change of the output 2. Indicates.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of the configuration of the liquid crystal display device 10, and is a block diagram showing when the polarity

reversal switch circuits

33 and 41 are switched to the a side. FIG. 2 is a block diagram showing a case where the polarity

reversal switch circuits

33 and 41 are switched to the b side in the liquid crystal display device 10 of FIG.

The liquid crystal display device 10 according to the present embodiment is a display device mounted on, for example, an installation device such as a TV or a portable terminal such as a mobile phone. As shown in FIGS. Display section) and a data signal line driver 30 (data signal line driver circuit). The remaining part (not shown) of the liquid crystal display device 10 can be realized by a conventional general configuration (such as a scanning line driver or a timing generator).

The liquid crystal panel 20 includes two transparent substrates (not shown) facing each other. On one transparent substrate, a common electrode 26 to which a common voltage is applied is formed. On the other transparent substrate, gate lines 21 (scanning signal lines), source lines 22 (data signal lines), TFTs 23, and pixel electrodes 24 are formed.

A plurality of gate lines 21 and source lines 22 are arranged so as to be orthogonal to each other, and a TFT 23 and a pixel electrode 24 are arranged corresponding to a portion where each intersects. That is, a plurality of TFTs 23 and pixel electrodes 24 are arranged in a matrix. The gate lines 21 are for supplying selection signals (scanning signals) to the pixel electrodes 24 in the same row, and the source lines 22 are for supplying data signals to the pixel electrodes 24 in the same column. is there.

The pixel electrode 24 is connected to the source line 22 via the TFT 23, and the gate of the TFT 23 is connected to the gate line 21. A selection signal is sequentially output to the gate line 21 from a scanning line driver (not shown), and the TFT 23 is turned on / off accordingly. When the TFT 23 is on, the pixel electrode 24 is electrically connected to the source line 22, and when the TFT 23 is off, the pixel electrode 24 is electrically disconnected from the source line 22.

A liquid crystal layer is formed between the two transparent substrates, and the liquid crystal (liquid crystal cell 25) sandwiched between the common electrode 26 and the pixel electrode 24 positioned opposite to the common electrode 26 is 1 Constitutes a pixel. A difference between a voltage applied to the pixel electrode 24 and a voltage applied to the common electrode 26 is applied to the liquid crystal cell 25. The display is changed by changing the alignment of the liquid crystal depending on the magnitude of the applied voltage.

The data signal line driver 30 is a drive circuit that sequentially outputs data signals (grayscale voltage, drive voltage) corresponding to an image to be displayed to each pixel electrode 24, and is connected to the source line 22. The data signal line driver 30 includes a shift register 31, a data latch 32, a polarity inversion switch circuit 33 (polarity inversion means), a hold latch 34, a level shifter 35, a positive polarity side DAC 36, a negative polarity side DAC 37, a positive polarity operational amplifier 38, Op-amp 39 for negative polarity, short circuit switch circuit 40 (short circuit means), polarity reversal switch circuit 41 (polarity reversal means), output pad 42, determination circuit 43 (determination means), polarity switching control circuit 44 (first control means), An output short-circuit control circuit 45 (second control means) and a setting register 46 are provided.

The data signal line driver 30 is designed as a 414-output data line driver circuit, and the liquid crystal panel 20 is provided with 414 pixels in the horizontal direction. However, unless otherwise specified, a case where six outputs (OUT1 to OUT6) of the data signal line driver 30 are provided will be described below for convenience of explanation.

Further, as will be described in detail later, the data signal line driver 30 performs output polarity reversal and charge sharing between adjacent outputs. Therefore, in the following, for convenience of explanation, components having equivalent functions will be referred to as numbered 1 in order from the left data output line in FIGS.

The data signal line driving driver 30 is an 8-bit (256 gradation) level that is image data (display data) supplied from the outside (for example, a controller provided in the liquid crystal display device 10) via a data bus. Gradation data Data [7: 0] is sequentially acquired, gradation data Data [7: 0] is converted into a data signal, and the data signal is output to the source line 22.

The shift register 31 sequentially creates pulse signals ENB1 to ENB6 according to control from the outside, and outputs each pulse signal to the corresponding data latch 32. The data latch 32 latches the gradation data Data [7: 0] supplied via the data bus in synchronization with the pulse signals ENB1 to ENB6.

The polarity reversing switch circuit 33 is inserted between the data latch 32 and the hold latch 34. The polarity inversion switch circuit 33 switches the connection destination of the corresponding data latch 32 between the a terminal (a side) and the b terminal (b side) based on the polarity inversion signal Opt_REV output from the polarity switching control circuit 44. In the first, third, and fifth polarity reversing switch circuits 33, the terminal a is connected to the first, third, and fifth hold latches 34, and the terminal b is connected to the second, fourth, and sixth hold latches 34. In the second, fourth and sixth polarity reversing switch circuits 33, the a terminal is connected to the second, fourth and sixth hold latches 34, and the b terminal is connected to the first, third and fifth hold latches 34.

In other words, the odd-numbered polarity reversing switch circuit 33 connects the corresponding odd-numbered data latch 32 to the even-numbered number obtained by adding one to the corresponding odd-numbered hold latch 34 (a side). And the hold latch 34 (b side). The even-numbered polarity reversing switch circuit 33 has a corresponding even-numbered data latch 32 connected to the corresponding even-numbered hold latch 34 (a side) and an odd-numbered hold latch obtained by subtracting 1 from the corresponding even-numbered latch. 34 (b side).

The hold latch 34 latches data held by the data latch 32 connected in accordance with the output of the data latch 32, that is, according to switching of the polarity inversion switch circuit 33, in accordance with control from the outside. As a result, the image data corresponding to the pixels of one horizontal line on the screen is held in each hold latch 34.

The level shifter 35 converts the signal level of the input gradation data. The odd level shifter 35 outputs the level-converted gradation data to the positive polarity DAC 36. The even level shifter 35 outputs the level-converted gradation data to the negative polarity side DAC 37.

The positive polarity side DAC 36 selects one voltage from the positive polarity side gradation voltage supplied from the outside according to the gradation data level-converted by the level shifter 35, and outputs it to the positive polarity operational amplifier 38. The negative polarity side DAC 37 selects one voltage from the negative polarity side gradation voltage supplied from the outside according to the gradation data level-converted by the level shifter 35, and outputs it to the negative polarity operational amplifier 39. As a result, the positive polarity operational amplifier 38 and the negative polarity operational amplifier 39 output a positive or negative polarity data signal (gradation voltage) selected (converted) according to the gradation data.

The positive-polarity operational amplifier 38 and the negative-polarity operational amplifier 39 function as output buffers, and their outputs are connected to the output pad 42 via the polarity inversion switch circuit 41. The output pad 42 is connected to the corresponding source line 22 of the liquid crystal panel 20. As a result, a data signal corresponding to the gradation data is output to the source line 22.

The short-circuit switch circuit 40 is provided between the outputs of the adjacent positive polarity operational amplifier 38 and negative polarity operational amplifier 39. The short-circuit switch circuit 40 short-circuits the outputs of the adjacent positive-polarity operational amplifier 38 and negative-polarity operational amplifier 39 based on the short-circuit signal Opt_CS output from the output short-circuit control circuit 45 (short-circuit switch circuit 40: ON).

The polarity reversing switch circuit 41 is inserted between the positive polarity operational amplifier 38 and the negative polarity operational amplifier 39 and the output pad 42. Based on the polarity reversal signal Opt_REV output from the polarity switching control circuit 44, the polarity reversing switch circuit 41 determines the connection destination of the corresponding positive polarity operational amplifier 38 and negative polarity operational amplifier 39 as a terminal (a side) and b terminal. Switch to (b side). In the first, third and fifth polarity reversing switch circuits 41, the terminal a is connected to the first, third and fifth output pads 42, and the terminal b is connected to the second, fourth and sixth output pads 42. In the second, fourth and sixth polarity reversing switch circuits 41, the a terminal is connected to the second, fourth and sixth output pads 42, and the b terminal is connected to the first, third and fifth output pads 42.

In other words, the odd polarity inversion switch circuit 41 connects the corresponding positive polarity operational amplifier 38 to the corresponding odd number output pad 42 (a side) and the even number obtained by adding one to the corresponding odd number. Switch between output pad 42 (b side). The even-numbered polarity reversing switch circuit 41 has a connection destination of the corresponding negative-polarity operational amplifier 39 connected to the corresponding even-numbered output pad 42 (a side) and the odd-numbered output pad 42 obtained by subtracting 1 from the corresponding even-numbered output pad 42. Switch between (b side).

The determination circuit 43 determines the necessity of polarity inversion and charge sharing from the gradation data Data [7: 0] supplied to the data signal line driver 30. The determination circuit 43 performs the above determination at a timing before scanning of the scanning line. If the result of determination is that polarity inversion is necessary, the control circuit Ctrl_REV (first control signal) is output to the polarity switching control circuit 44. If charge sharing is necessary, a control signal Ctrl_CS (second control signal) is output to the output short-circuit control circuit 45. That is, the determination circuit 43 selectively outputs the control signal Ctrl_REV and the control signal Ctrl_CS according to the determination result.

In addition, the determination circuit 43 stores the reference (data Crit_Black [2: 0]) for determining the black display and the reference (data Crit_White [data] stored in the setting register 46 for determining the white display). 2: 0]) and criteria for determining the majority (data Crit_Majority [2: 0]). The setting register 46 can be arbitrarily rewritten by giving a signal from the outside.

The polarity switching control circuit 44 inverts the polarity of the outputs OUT1 to OUT6 from the data signal line driver 30 or the output pad 42 based on the polarity switching command REV from the outside and the control signal Ctrl_REV output from the determination circuit 43. To do. An external polarity switching command REV is input when shifting from odd-numbered line scanning to even-numbered line scanning (or vice versa) within the block, and thus polarity inversion is performed. When Ctrl_REV is output, polarity inversion is performed regardless of the polarity switching command REV. Specifically, the polarity switching control circuit 44 outputs a polarity reversal signal Opt_REV, which is a control signal for performing polarity reversal, to the polarity reversing

switch circuits

33 and 41, thereby causing the polarity reversing

switch circuits

33 and 41 to a. Switch between side and b side. For example, the polarity switching control circuit 44 performs the polarity inversion operation when the polarity switching command REV from the outside becomes “1” or the control signal Ctrl_REV becomes “1”.

The output short-circuit control circuit 45 short-circuits the outputs OUT1 to OUT6 from the data signal line drive driver 30, that is, the output pad 42, based on the external short-circuit command CS and the control signal Ctrl_CS supplied from the determination circuit 43. The short-circuit command CS from the outside is input when scanning is shifted between blocks, and this causes a short-circuit. However, when Ctrl_CS is output from the determination circuit 43, a short-circuit is generated regardless of the short-circuit command CS. Done. Specifically, the output short circuit control circuit 45 outputs a short circuit signal Opt_CS, which is a control signal for performing a short circuit, that is, charge sharing, to the short circuit switch circuit 40, thereby turning on the short circuit switch circuit 40. For example, the output short-circuit control circuit 45 performs the charge sharing operation when the external short-circuit command CS is “1” or the control signal Ctrl_CS is “1”.

In the data signal line driver 30 having the above-described configuration, an operation for display is performed in the same manner as in the prior art. The necessity of charge sharing is determined, and these are performed as necessary.

As shown in FIG. 1, when the polarity

reversal switch circuits

33 and 41 are switched to the a side by the polarity reversal signal Opt_REV from the polarity switching control circuit 44, the gradation data of the odd-numbered data latch 32 corresponds. It is transferred to the odd-numbered hold latch 34. The grayscale data output from the odd-numbered hold latch 34 is level-shifted by the corresponding odd-numbered level shifter 35, converted to a data signal by the positive polarity side DAC 36, and odd-numbered by the positive polarity operational amplifier 38. Are output to the output pad 42.

In this case, the gradation data of the even-numbered data latch 32 is transferred to the corresponding even-numbered hold latch 34. The gradation data output from the even-numbered hold latch 34 is level-shifted by the corresponding even-numbered level shifter 35, converted into a data signal by the negative polarity side DAC 37, and even-numbered by the negative polarity operational amplifier 39. Are output to the output pad 42.

On the other hand, as shown in FIG. 2, when the polarity reversing switch circuit 33 is switched to the b side, the gradation data of the odd-numbered data latch 32 is supplied to the even-numbered hold latch 34, which is one added from the odd-numbered data latch 32. Transferred. The gradation data output from the even-numbered hold latch 34 is level-shifted by the corresponding even-numbered level shifter 35, converted to a data signal by the negative polarity side DAC 37, and odd-numbered by the negative polarity operational amplifier 39. Are output to the output pad 42.

In this case, the gradation data of the even-numbered data latch 32 is transferred to the odd-numbered hold latch 34 obtained by subtracting 1 from the even-numbered data latch 32. The gradation data output from the odd-numbered hold latch 34 is level-shifted by the corresponding odd-numbered level shifter 35, converted into a data signal by the positive polarity side DAC 36, and even-numbered by the positive polarity operational amplifier 38. Are output to the output pad 42.

In this way, by switching the polarity

inversion switch circuits

33 and 41 between the a side and the b side by the polarity inversion signal Opt_REV from the polarity switching control circuit 44, the output OUT1 from the output pad 42, that is, the data signal line driver 30. The polarity of ~ OUT6 is inverted.

Further, the output pad 42, that is, the outputs OUT1 to OUT6 from the data signal line driver 30 are short-circuited by turning on the short-circuit switch circuit 40 by the short-circuit signal Opt_CS from the output short-circuit control circuit 45. On the other hand, when the short circuit switch circuit 40 is switched off, the outputs OUT1 to OUT6 from the output pad 42 are output to the corresponding source line 22.

Therefore, when polarity inversion and charge sharing are required, the determination circuit 43 performs polarity inversion and charge sharing only by outputting the control signal Ctrl_REV and the control signal Ctrl_CS to the polarity switching control circuit 44 and the output short-circuit control circuit 45. It becomes possible.

Here, the data signal line driver 30 determines whether or not polarity inversion and charge sharing are necessary, that is, whether the output of the control signal Ctrl_REV and the control signal Ctrl_CS is valid or invalid, as input image data (gradation data Data [7: 0]) is determined by the determination circuit 43. Next, the detailed configuration and operation of the determination circuit 43 will be described in order.

FIG. 3 shows a configuration example of the determination circuit 43. As shown in FIG. 3, the determination circuit 43 includes a pattern detection circuit 101 and a polarity inversion and charge share determination circuit 102.

The pattern detection circuit 101 compares the reference value set in the setting register 46 with the black / white combination pattern of the adjacent output pairs in the input gradation data Data [7: 0]. This circuit detects the majority (majority). The above criteria include data Crit_Black [2: 0] indicating the number of gradations determined to be black display, data Crit_White [2: 0] indicating the number of gradations determined to be white display, and a set number for determining the majority. The indicated data Crit_Majority [2: 0] is used. Further, control signals SRA, SRB, and LS are also individually input to the pattern detection circuit 101.

More specifically, the adjacent output pairs correspond to the outputs OUT1 and OUT2, the outputs OUT3 and OUT4, and the outputs OUT5 and OUT6 in the data signal line driver 30. There are four black / white combination patterns of adjacent output pairs: “black and black”, “white and white”, “black and white”, and “monochrome”. The pattern detection circuit 101 detects a majority combination pattern from the black / white combination patterns of each output pair in one horizontal line.

The pattern detection circuit 101 has a flag flgMBB indicating that “black and black” is the majority, a flag flgMWW indicating that “white and white” is the majority, and “black and white” are the majority according to the detection result. The flag flgMBW indicating that this is the case and the flag flgMWB indicating that “monochrome” is the majority are output to the polarity inversion and charge share determination circuit 102. The flag flgMBB is set to “1” when black and black are majority, the flag flgMWW is set to “1” when white and white are majority, and the flag flgMBW is set to “1” when black and white is majority. In this case, the flag flgMWB becomes “1”. If there is no majority, all flags are “0”.

The polarity inversion and charge share determination circuit 102 is a circuit that determines the necessity of polarity inversion and charge share based on the majority detection result of the pattern detection circuit 101. The polarity inversion and charge share determination circuit 102 uses the flags flgMBB, flgMWW, flgMBW, and flgMWB output from the pattern detection circuit 101 to compare the majority combination pattern of the previous line with the majority combination pattern of the current line. Thus, the pattern of the image on one screen is identified, and the necessity of polarity inversion and charge sharing is determined. Further, the control signal PS is also input to the polarity inversion and charge share determination circuit 102.

The polarity inversion and charge share determination circuit 102 outputs a control signal Ctrl_REV and a control signal Ctrl_CS to the polarity switching control circuit 44 and the output short-circuit control circuit 45, respectively, according to the determined result. When polarity inversion is performed, the control signal Ctrl_REV is “1”, and when charge sharing is performed, the control signal Ctrl_CS is “1”. If neither is performed, all control signals are “0”.

FIG. 4 shows a configuration example of the pattern detection circuit 101. As shown in FIG. 4, the pattern detection circuit 101 includes a black matching circuit 111 (display state determining means), a white matching circuit 112 (display state determining means), a D-FF 113, a D-FF 114, and a pattern matching circuit 115 (display pattern). Creating means), counters 116 to 119, and majority collating circuits 120 to 123 (majority judging means).

The black collation circuit 111 is a circuit that checks whether or not the gradation data Data [7: 0] is black display compared to the data Crit_Black [2: 0]. The black matching circuit 111 outputs a flag flgB indicating black display to the D-FF 113 and the pattern matching circuit 115 according to the result of the examination. In the case of black display, the flag flgB is “1”, otherwise the flag flgB is “0”.

The white collation circuit 112 is a circuit that checks whether or not the gradation data Data [7: 0] is white display compared to the data Crit_ White [2: 0]. The white matching circuit 112 outputs a flag flgW indicating white display to the D-FF 114 and the pattern matching circuit 115 according to the result of the examination. In the case of white display, the flag flgW is “1”. In other cases, the flag flgB is “0”.

The D-FF 113 and the D-FF 114 latch the outputs of the black matching circuit 111 and the white matching circuit 112 based on the input timing of the control signal SRA. That is, the D-FF 113 latches the value of the flag flgB and holds it as data regB. The D-FF 114 latches the value of the flag flgW and holds it as data regW. The D-FF 113 and the D-FF 114 output the retained data regB and data regW to the pattern matching circuit 115.

The pattern matching circuit 115 compares the flag flgB / flgW indicating black display / white display determined from the current gradation data and the data regB / regW indicating black display / white display determined from the previous gradation data. . In accordance with the result, the pattern matching circuit 115 counts the flags flgBB, flgWW, flgBW, flgWB indicating that the pattern of gradation data corresponding to the output pair is a black-black-white-white-black-white-monochrome pattern. 116 to 119, respectively. The flag flgBB is set to “1” for the black / black pattern, the flag flgWW is set to “1” for the white / white pattern, the flag flgBW is set to “1” for the black / white pattern, and the flag flgWB is set to “1” for the black / white pattern. become. When there is no corresponding combination, all the flags are “0”.

Gradation data Data [7: 0] is data obtained by time-sharing gradation data input serially from the outside, and gradation data corresponding to all output terminals is supplied. After the D-FF 113 and D-FF 114 latch the values of the flags flgB and flgW, respectively, according to the control signal SRA, the next gradation data Data [7: 0] is supplied to the data bus. As a result, the data regB and data regW latched by the D-FF 113 and D-FF 114 can be data indicating black display / white display checked from the previous gradation data, and the D-FF 113 and D-FF 114 The flag flgB and the flag flgW, which are inputs of, can be used as flags indicating black display / white display examined from the current gradation data.

Counters 116 to 119 count up according to the input timing of control signal SRB if flags flgBB, flgWW, flgBW, flgWB indicating the display state of the output pair are “1”. As the counters 116 to 119, CNTs 207 are used. The control signal SRB is output after the values of the flags flgBB, flgWW, flgBW, flgWB are determined. The counters 116 to 119 use 8-bit data cntBB [7: 0], cntWW [7: 0], cntBW [7: 0], and cntWB [7: 0] indicating the count values to the majority collating circuits 120 to 123, respectively. Respectively.

The majority collation circuits 120 to 123 compare with the data Crit_Majority [2: 0] whether the count value output from the counters 116 to 119 is greater than or equal to the number set by the data Crit_Majority [2: 0]. It is a circuit to check. The majority collation circuits 120 to 123 output flags flgMBB, flgMWW, flgMBW, flgMWB indicating the majority to the polarity inversion and charge share determination circuit 102 when the count value exceeds the set number.

The operations of the counters 116 to 119 are performed for the number of output pairs of one horizontal line. The control signal LS input to the RST terminals of the counters 116 to 119 is output when the data signal line driver 30 starts outputting for one line display. When the control signal LS is input, the counters 116 to 119 are reset and the counter value is cleared.

FIG. 5 shows an example of the configuration of the black matching circuit 111. As shown in FIG. 5, the black matching circuit 111 includes a logic circuit 131, OR circuits 132 to 136, an AND circuit 137, and an AND circuit 138.

The logic circuit 131 calculates the number of gradations for determining that the display is black based on the value of the data Crit_Black [2: 0]. The logic circuit 131 outputs the data OPE to the AND circuit 138 according to the result of calculating the data Crit_Black [2: 0] along a predetermined truth value, and outputs the data N_Enable [4: 0] to the OR circuit. Output to 132 to 136, respectively.

OR circuits 132 to 136 output, to AND circuit 137, result data obtained by performing OR operation on gradation data Data [4: 0] and data N_Enable [4: 0]. The AND circuit 137 outputs the result data obtained by performing an AND operation on the data Data [7: 5] and the outputs of the OR circuits 132 to 136 to the AND circuit 138. The AND circuit 138 outputs the result data obtained by ANDing the data OPE from the logic circuit 131 and the output of the AND circuit 137 as a flag flgB.

FIG. 6 shows a truth table of the logic circuit 131. Data Crit_Black [2: 0] is 3-bit data. The output data OPE is “0” when 0 (000H) and 7 (111H), and the output data OPE is “1” when the other 1-6. " The value of the data Crit_Black [2: 0] can be set / changed by inputting data 1 to 6 to the setting register 46.

When the data Crit_Black [2: 0] is 1 (001H), the data N_Enable [4: 0] is (00000H). Therefore, the OR circuits 132 to 136 to which the data N_Enable [4: 0] is input have an output of “1” when the gradation data Data [4] to Data [0] are “1”. Therefore, the output of the AND circuit 137 is “1” only when the gradation data Data [7: 0] is 255 (11111111H). Therefore, since the data OPE is “1”, the output of the AND circuit 138, that is, the flag flgB becomes “1”.

Therefore, when the data Crit_Black [2: 0] is set to 1, when the gradation data Data [7: 0] is 255, the flag flgB becomes “1”. That is, it is determined to be black only in the case of 256 gradation data.

In this manner, the logic circuit 131 returns 1 when the gradation data Data [7: 0] is black or a value close thereto, and returns 0 otherwise. The standard for judging that the gradation is black or close to it is
When Data> 255−X, flgB = 1 (determined as black or close to black)
In other cases, flgB = 0 (determined otherwise)
It has become.

Note that the number of gradations 1 to 32 determined to be black by the setting of the data Crit_Black [2: 0] corresponds to the number of gradations X regarded as black, which is the setting of the flowchart 1 in FIG. In the data signal line driver 30, the set number X can be set to 1, 2, 4, 8, 16, 32.

FIG. 7 shows a configuration example of the white matching circuit 112. As shown in FIG. 7, the white matching circuit 112 includes a logic circuit 141, AND circuits 142 to 146, a NOR circuit 147, and an AND circuit 148.

The logic circuit 141 calculates the number of gradations for determining that the display is white based on the value of the data Crit_White [2: 0]. The logic circuit 141 outputs the data OPE to the AND circuit 148 according to the result of calculating the data Crit_White [2: 0] according to a predetermined truth value, and outputs the data N_Enable [4: 0] to the AND circuit. Output to 142 to 146, respectively.

AND circuits 142 to 146 output the result of AND operation of the gradation data Data [4: 0] and the data N_Enable [4: 0] to the NOR circuit 147. The NOR circuit 147 outputs a result obtained by performing a NOR operation on the gradation data Data [7: 5] and the outputs of the AND circuits 142 to 146 to the AND circuit 148. The AND circuit 148 outputs a result obtained by performing an AND operation on the data OPE from the logic circuit 141 and the output of the NOR circuit 147 as a flag flgW.

FIG. 8 shows a truth table of the logic circuit 141. The data Crit_White [2: 0] is 3-bit data. The output data OPE is “0” when 0 (000H) and 7 (111H), and the output data OPE is “1” when the other 1-6. " The value of the data Crit_White [2: 0] can be set / changed by inputting data 1 to 6 to the setting register 46.

When the data Crit_White [2: 0] is 1 (001H), the data N_Enable [4: 0] is (11111H). Therefore, the AND circuits 142 to 146 to which the data N_Enable [4: 0] is input have an output of “0” when the data [0] is “0” from the gradation data Data [4]. Therefore, the NOR circuit 147 outputs “1” only when the gradation data Data [7: 0] is 0 (00000000H). Therefore, since the data OPE is “1”, the output of the AND circuit 148, that is, the flag flgW becomes “1”.

Therefore, when the data Crit_White [2: 0] is set to 1, when the gradation data Data [7: 0] is 0, the flag flgW becomes “1”. That is, it is determined to be white only when the gradation data is one gradation.

In addition, when 2 (010H) is set in the data Crit_White [2: 0], the data N_Enable [4: 0] becomes (11110H). Therefore, since the data N_Enable [0] is “0”, the AND circuit 146 to which the data N_Enable [0] is input always outputs “0”. Therefore, when the gradation data Data [7: 0] is 0 (00000000H) and 1 (00000001H), the flag flgW becomes “1”. That is, it is determined to be white only in the case of gradation data of 1 gradation and 2 gradations.

Similarly, when 3 (011H) is set in the data Crit_White [2: 0], when the gradation data Data [7: 0] is 0 to 3, four gradations from the first gradation to the fourth gradation are white. Determined. When 4 (100H) is set in the data Crit_White [2: 0], when the gradation data Data [7: 0] is 0 to 7, 8 gradations from 1 gradation to 8 gradations are determined to be white. . When 5 (101H) is set in the data Crit_White [2: 0], when the gradation data Data [7: 0] is 0 to 15, 16 gradations from 1 gradation to 16 gradations are determined to be white. . When 6 (110H) is set in the data Crit_White [2: 0], when the gradation data Data [7: 0] is 0 to 31, 32 gradations from 1 gradation to 32 gradations are determined to be white. .

In this way, the logic circuit 141 returns 1 when the gradation data Data [7: 0] is white or a value close thereto, and returns 0 otherwise. The criterion for judging that the gradation is white or close to it is
When Data <Y, flgW = 1 (determined as white or close to white)
In other cases, flgW = 0 (determined otherwise)
It has become.

Note that the gradation numbers 1 to 32 determined to be white by the setting of the data Crit_White [2: 0] correspond to the gradation number Y regarded as white, which is the setting of the flowchart 1 of FIG. The data signal line driver 30 can set the set number Y to 1, 2, 4, 8, 16, 32.

FIG. 9 shows a configuration example of the pattern matching circuit 115. As shown in FIG. 9, the pattern matching circuit 115 includes AND circuits 151 to 154.

The AND circuit 151 outputs the flag flgBB in accordance with the result of ANDing the flag flgB indicating black display determined from the current gradation data and the data regB indicating black display determined from the previous gradation data. . The AND circuit 152 outputs the flag flgWW according to the result of ANDing the flag flgW indicating white display determined from the current gradation data and the data regW indicating white display determined from the previous gradation data. . The AND circuit 153 outputs the flag flgBW according to the result of ANDing the flag flgB indicating black display determined from the current gradation data and the data regW indicating white display determined from the previous gradation data. . The AND circuit 154 outputs the flag flgWB in accordance with the result of ANDing the flag flgW indicating white display determined from the current gradation data and the data regB indicating black display determined from the previous gradation data. .

FIG. 10 shows the input and output states of the pattern matching circuit 115 in the display state of adjacent output pairs. For example, when the display state of the adjacent output pair is “black and black”, the input flag flgB and data regB are “1”, and the output flag flag flgBB is “1”. If the display state is determined to be neither black nor white (others), the output is “0” for both flags. There is no state other than that shown in FIG.

Here, since the data signal line drive driver 30 is designed as a data line drive circuit with 414 outputs, there are 207 output pairs. Therefore, since the maximum count value of the counters 116 to 119 is 207, the flag flg output from the majority collation circuits 120 to 123 is always “0”. Therefore, the counters 116 to 119 are set to 152 after the count number 103, and the output state is set to (11111111H) by the count of 207.

FIG. 11 shows a truth table of the counters 116 to 119. Up to the count number 103, a normal 8-bit counter is used, but bit inversion is performed at a count of 105, and the output 8-bit state at the count number 104 is set to 152 (10011000H). As a result, at the time of counting 207, the output 8-bit state becomes 255 (11111111H).

Since the counter value is changed in this way, when data Crit_Majority [2: 0] is set to 1, the majority collation circuits 120 to 123 set the flag flg to “1” as the majority when the count number is 207. To. When 2 is set in the data Crit_Majority [2: 0], the majority collation circuits 120 to 123 set the flag flg to “1” as the majority when the count number is 206 or more. When the data Crit_Majority [2: 0] is set to 3, the majority collation circuits 120 to 123 set the flag flg to “1” as the majority when the count number is 204 or more. When the data Crit_Majority [2: 0] is set to 4, the majority collation circuits 120 to 123 set the flag flg to “1” as the majority when the count number is 200 or more. When the data Crit_Majority [2: 0] is set to 5, the majority collation circuits 120 to 123 set the flag flg to “1” as the majority when the count number is 192 or more. When the data Crit_Majority [2: 0] is set to 6, the majority collation circuits 120 to 123 set the flag flg to “1” as the majority when the count number is 176 or more.

The majority collation circuits 120 to 123 can be realized with the same configuration as the black collation circuit 111. That is, in the configuration shown in FIG. 5, instead of the gradation data Data [7: 0], data indicating the count value cntBB [7: 0] · cntWW [7: 0] · cntBW [7: 0] · cntWB [7: 0] is input, and data Crit_Majority [2: 0] may be input instead of the data Crit_Black [2: 0]. As a result, the flag flgMBB / flgMWW / flgMBW / flgMWB indicating the majority is output from the AND circuit 138.

Also, the setting value determined as the majority by setting the data Crit_Majority [2: 0] corresponds to the setting value Z that determines the majority, which is the setting of the flowchart 2 of FIG. In the data signal line driver 30, the set number Z can be set to 1, 2, 4, 8, 16, 32. Further, the value of the data Crit_Majority [2: 0] can be set / changed by inputting data 1 to 6 to the setting register 46.

FIG. 12 shows a configuration example of the polarity inversion and charge share determination circuit 102. As shown in FIG. 12, the polarity inversion and charge share determination circuit 102 includes D-FFs 161 to 163 (holding means), AND circuits 164 to 166 (control signal output means), and OR circuits 167 and 168 (control signal output means). And D-FF 169 and 170 (control signal output means).

The D-FFs 161 to 163 latch the values of the flags flgMBB, flgMBW, and flgMWB, which are the outputs of the pattern detection circuit 101, based on the input timing of the control signal PS. That is, the D-FF 161 latches the value of the flag flgMBB and holds it as data regMBB. The D-FF 162 latches the value of the flag flgMBW and holds it as data regMBW. The D-FF 163 latches the value of the flag flgMWB and holds it as data regMWB. The D-FFs 161 to 163 output the held data regMBB, regMBW, regMWB to the AND circuits 164 to 166, respectively.

The AND circuit 164 ORs the result data obtained by ANDing the flag flgMWB determined from the gradation data for one line acquired this time and the data regMBW determined from the gradation data for one line acquired last time. To 167. The AND circuit 165 ORs the result data obtained by ANDing the flag flgMBW determined from the gradation data for one line acquired this time and the data regMWB determined from the gradation data for one line acquired last time. To 167. The AND circuit 166 ORs the result data obtained by ANDing the flag flgMWW determined from the gradation data for one line acquired this time and the data regMBB determined from the gradation data for one line acquired last time. To 168.

The OR circuit 167 outputs the result data obtained by ORing the output of the AND circuit 164 and the output of the AND circuit 165 to the D-FF 169 and also to the OR circuit 168. The OR circuit 168 outputs the result data obtained by ORing the output of the OR circuit 167 and the output of the AND circuit 166 to the D-FF 170.

The D-FF 169 latches the output of the OR circuit 167 based on the input timing of the control signal PS. Then, the D-FF 169 outputs the held data to the polarity switching control circuit 44 as the control signal Ctrl_REV.

The D-FF 170 latches the output of the OR circuit 168 based on the input timing of the control signal PS. Then, the D-FF 170 outputs the held data to the output short-circuit control circuit 45 as the control signal Ctrl_CS.

The above data regMBB, regMBW, regMWB indicate what the majority combination pattern was in the gradation data in the previous scanning line. If the data regMBB is “1”, the display of the previous line is majority in black and black, if the data regMBW is “1”, the majority is black and white, and if the data regMBB is “1”, black and white is displayed. It shows that it was a majority.

On the other hand, flags flgMBB, flgMWW, flgMBW, and flgMWB indicate a majority combination pattern of gradation data in the current scan line. If the flag flgMBB is “1”, black and black is the majority, if the flag flgMWW is “1”, the white is the majority, and if the flag flgMBW is “1”, the black and white is the majority. If flgMWB is “1”, it indicates that black and white is majority.

Since the data regMBW and the flag flgMWB are input to the AND circuit 164, the output is “1” when the previous line is black and white and the current line is majority. Since the AND circuit 165 receives the data regMWB and the flag flgMBW, the output is “1” when the previous line is black and white and the current line is black and white. Since the data regMBB and the flag flgWW are input to the AND circuit 166, the output is “1” when the front line is black-black and the current line is white-white.

Since the output of the AND circuit 164 and the output of the AND circuit 165 are input to the OR circuit 167, the output is output when either the output of the AND circuit 164 or the output of the AND circuit 165 is “1”. Becomes “1”. That is, the output is “1” when the front line is black and white and the current line is black and white, or the front line is black and white and the current line is black and white. The output state of the OR circuit 167 is latched by the D-FF 169 according to the input timing of the control signal PS and becomes the control signal Ctrl_REV.

Since the output of the OR circuit 167 and the output of the AND circuit 166 are input to the OR circuit 168, the output is output when either the output of the OR circuit 167 or the output of the AND circuit 166 is “1”. Becomes “1”. In other words, when the previous line is black and white, the current line is black and white, the previous line is black and white, the current line is black and white, or the previous line is black and white, and the current line is white and white, the output is “ 1 ”. The output state of the OR circuit 168 is latched by the D-FF 170 according to the input timing of the control signal PS and becomes the control signal Ctrl_CS.

The control signal Ctrl_REV is a signal for operating the polarity switching control circuit 44 so as to invert the polarity. Therefore, when the output of the OR circuit 167 is “1”, that is, when the previous line is black and white and the current line is majority black and white, or the previous line is black and white and the current line is black and white majority, the polarity is inverted. Will do.

The control signal Ctrl_CS is a signal for operating the output short-circuit control circuit 45 so as to perform charge sharing. Therefore, when the OR circuit 168 is “1”, that is, the previous line is black and white, the current line is black and white, the previous line is black and white, the current line is black and white, or the previous line is black and white, When the line is majority white and white, charge sharing is performed.

Further, when the control signal PS is input, the control signal Ctrl_REV and the control signal Ctrl_CS are latched, and the data regMBB / regMBW / regMWB are latched. Thus, this operation changes the data regMBB, regMBW, regMWB to the majority state of the current line, and the preparation for comparison with the majority information of the next line is completed.

Next, the processing operation when the data signal line driver 30 detects the pattern and changes the display method as necessary in the source block inversion driving will be described.

FIG. 13 is a flowchart showing a processing flow of the data signal line driver 30 when one screen is displayed. FIG. 14 shows a flowchart 1 executed in the processing flow shown in FIG. FIG. 15 shows a flowchart 2 executed in the processing flow shown in FIG.

When the display is performed, as shown in FIG. 13, first, the data signal line driver 30 uses the shift register 31 and the data latch 32 to display grayscale data Data of the first line for starting display in one screen image data. [7: 0] are sequentially fetched (step S201). As a result, a data signal is sent to the source line 22 via the output pad 42 by the processing of the hold latch 34, the level shifter 35, the positive polarity side DAC 36, the negative polarity side DAC 37, the positive polarity operational amplifier 38, and the negative polarity operational amplifier 39. Is output. Then, the data signal is applied to the pixel electrode 24 of the first line, and the liquid crystal panel 20 performs display (step S203).

The gradation data Data [7: 0] is sequentially output to the data bus corresponding to the driving method of the liquid crystal panel 20. Here, it is assumed that the liquid crystal panel 20 is driven by source block inversion.

On the other hand, the determination circuit 43 performs the processing shown in the flowchart 1 of FIG. 14 and the flowchart 2 of FIG. 15 from the gradation data Data [7: 0] for the first line, and the gradation data Data [7 of the first line. : 0], the combination pattern of black and white of adjacent output pairs is examined. As a result, data regMBB, regMBW, regMWB indicating the majority of the combination of the first line is obtained (step S202).

The processing in step S202 will be specifically described.

As shown in FIG. 14, first, reference values (number of gradations = n, number of gradations regarded as black = X, number of gradations regarded as white = Y) necessary for the processing of the determination circuit 43 are set in advance. (Step S231). For example, when 256 gradations of 256 gradations are black, assuming that the number of gradations regarded as black is 8 (X = 8), 256 gradations to 256 gradations are determined to be black. Similarly, if the number of gradations regarded as white is 8 (Y = 8), 1 to 8 gradations are determined to be white.

Also, in the determination circuit 43, the number of appearances of the flags flgBB, flgWW, flgBW, flgWB when processing is performed on the previous line is held in the counters 116 to 119 of the pattern detection circuit 101. Therefore, the number of appearances of the flags flgBB, flgWW, flgBW, flgWB is reset by giving a control signal LS to the counters 116 to 119 (step S232).

Subsequently, in the output pair, the gradation data corresponding to the first output is set to K, and the gradation data corresponding to the second output is set to L (step S233). Then, the determination circuit 43, that is, the black collation circuit 111 and the white collation circuit 112 of the pattern detection circuit 101, examines whether the K and L data display black or white.

After examining the data of K and L, the determination circuit 43, that is, the pattern matching circuit 115 determines whether or not “K> n−X” and “L> n−X” (K and L are black) are satisfied (step S1). S234).

When “K> n−X” and “L> n−X” are satisfied (YES in step S234), pattern matching circuit 115 determines that the combination pattern is “black and black” and sets flag flgBB to “1”. In step S235, the count value of the counter 116 is counted up.

Then, the determination circuit 43 checks whether the output pair is the last (step S242). If it is the last (YES in step S242), the process proceeds to the process of the flowchart 2 in FIG. 15, and if not the last (step S242). NO) is moved to the next output pair data (step S243), and the process returns to step S233 to determine the combination pattern of the next output pair.

On the other hand, when “K> n−X” and “L> n−X” are not satisfied (NO in step S234), pattern matching circuit 115 then selects “K <Y” and “L <Y” (K And L satisfies white) (step S236).

If “K <Y” and “L <Y” are satisfied (YES in step S236), pattern matching circuit 115 determines that the combination pattern is “white and white”, sets flag flgWW to “1”, and sets the counter The count value 117 is counted up (step S237). Similarly, the determination circuit 43 checks whether the output pair is the last (step S242), and proceeds to the next process.

On the other hand, when “K <Y” and “L <Y” are not satisfied (NO in step S236), pattern matching circuit 115 then selects “K> n−X” and “L <Y” (K is black). , L is white (step S238).

If “K> n−X” and “L <Y” are satisfied (YES in step S238), pattern matching circuit 115 determines that the combination pattern is “black and white” and sets flag flgBW to “1”. Then, the count value of the counter 118 is counted up (step S239). Similarly, the determination circuit 43 checks whether the output pair is the last (step S242), and proceeds to the next process.

On the other hand, if “K> n−X” and “L <Y” are not satisfied (NO in step S238), pattern matching circuit 115 then selects “K <Y” and “L> n−X” (K Is white and L is black) (step S240).

When “K <Y” and “L> n−X” are satisfied (YES in step S240), pattern matching circuit 115 determines that the combination pattern is “monochrome” and sets flag flgWB to “1”. Then, the count value of the counter 119 is counted up (step S241). Similarly, the determination circuit 43 checks whether the output pair is the last (step S242), and proceeds to the next process.

On the other hand, when “K <Y” and “L> n−X” are not satisfied (NO in step S240), determination circuit 43 determines whether the output pair combination pattern is black / black / white / white / black / white / monochrome. Similarly, it is determined whether the output pair is the last (step S242), and the process proceeds to the next process.

In this way, the determination circuit 43 executes the flowchart 1 of FIG. 14 to determine the combination pattern for all output pairs of one line, and when displaying black and black in one line, display white and white. When displaying black and white, the number of appearances when displaying black and white is counted.

Subsequently, the determination circuit 43 executes the flowchart 2 in FIG. 15 to check which combination pattern appears in large numbers. As shown in FIG. 15, in order to set how many patterns are generated in one line and regarded as the appearance of a large number, a setting value = Z for determining the majority is set in advance (step S261). Therefore, if the total number of output pairs = m, the number that becomes the majority is represented by m−Z. For example, in the data signal line driver 30 with 414 outputs, m = 207, and when Z is 16, the number that becomes the majority is 207-16 = 191.

Subsequently, the determination circuit 43, that is, the majority collation circuit 120 of the pattern detection circuit 101 determines whether or not “flgBB (number of occurrences of black and black pattern)> m−Z” is satisfied (step S262).

If “flgBB> m−Z” is satisfied (YES in step S262), the majority collation circuit 120 determines that the black and black pattern is the majority, and sets the flag flgMBB to “1”. Then, this is latched by the D-FF 131 of the polarity inversion and charge share determination circuit 102, so that the data regMBB becomes “1”. The data regMWW / regMBW / regMWB is “0” (step S263). Obtaining this result, the determination circuit 43 returns to the processing of the flowchart of FIG.

On the other hand, when “flgBB> m−Z” is not satisfied (NO in step S262), majority check circuit 120 then determines whether “flgWW (number of appearances of white and white pattern)> m−Z” is satisfied. (Step S264).

If “flgWW> m−Z” is satisfied (YES in step S264), the majority collation circuit 120 determines that the white / white pattern is the majority, and sets the flag flgMWW to “1”. As a result, the data regMWW becomes “1”. Further, the data regMBB, regMBW, regMWB becomes “0” (step S265). Obtaining this result, the determination circuit 43 returns to the processing of the flowchart of FIG.

On the other hand, when “flgWW> m−Z” is not satisfied (NO in step S264), majority check circuit 120 then determines whether “flgBW (number of appearances of black and white pattern)> m−Z” is satisfied. (Step S266).

If “flgBW> m−Z” is satisfied (YES in step S266), the majority collation circuit 120 determines that the black and white pattern is the majority, and sets the flag flgMBW to “1”. Then, the data regMBW becomes “1” when the D-FF 132 latches this. Further, the data regMBB / regMWW / regMWB becomes “0” (step S267). Obtaining this result, the determination circuit 43 returns to the processing of the flowchart of FIG.

On the other hand, when “flgBW> m−Z” is not satisfied (NO in step S266), majority check circuit 120 then determines whether “flgWB (number of appearances of black and white pattern)> m−Z” is satisfied. (Step S268).

If “flgWB> m−Z” is satisfied (YES in step S268), the majority collation circuit 120 determines that the black and white pattern is the majority, and sets the flag flgMWB to “1”. Then, this is latched by the D-FF 133, so that the data regMWB becomes “1”. Further, the data regMBB / regMWW / regMBW becomes “0” (step S269). Obtaining this result, the determination circuit 43 returns to the processing of the flowchart of FIG.

On the other hand, when “flgWB> m−Z” is not satisfied (NO in step S268), the determination circuit 43 determines that there is no combination pattern occupying a large number. As a result, all the data regMBB, regMWW, regMBW, regMWB become “0” (step S270). Then, after obtaining this result, the determination circuit 43 returns to the processing of the flowchart of FIG.

In this way, the determination circuit 43 obtains the values of the data regMBB, regMBW, and regMWB (step S202 in FIG. 13). Note that the processing in step S202 may be performed every time the gradation data is captured, or may be performed after all the gradation data for one line is captured.

Subsequently, the determination circuit 43 takes in the gradation data Data [7: 0] for displaying the next line (step S204). Then, the determination circuit 43 determines the combination pattern for all output pairs of one line using the fetched gradation data Data [7: 0], and displays black and black in one line. When white and white are displayed, black and white are displayed, and the number of appearances when black and white is displayed is counted. Thereby, the value of the number of appearances of the flags flgBB, flgWW, flgBW, flgWB is obtained (step S205). The appearance count acquisition operation is the same as the operation in the flowchart 1 of FIG.

Subsequently, the determination circuit 43 checks which combination pattern appears in large numbers. This majority decision operation is the same as in the flowchart 2 of FIG. As the setting value for determining the majority = Z and the total number of output pairs = m, those previously set are used (step S206).

Subsequently, the determination circuit 43, that is, the majority collation circuit 120 of the pattern detection circuit 101 determines whether “flgBB (number of appearances of black and black pattern)> m−Z” is satisfied (step S207).

If “flgBB> m−Z” is satisfied (YES in step S207), the majority collation circuit 120 determines that the black and black pattern is the majority, and sets the flag flgMBB to “1”. In this case, that is, when the display of one line to be output is majority black and black, the determination circuit 43 determines that output polarity inversion and charge sharing are not necessary. Accordingly, the liquid crystal panel performs display without changing the display method (step S216).

Then, the flag flgMBB is latched by the D-FF 131 of the polarity inversion and charge share determination circuit 102, so that the data regMBB becomes “1”. Further, the data regMWW / regMBW / regMWB becomes “0” (step S217). That is, the values of the data regMBB, regMWW, regMBW, regMWB are changed with the values of the flags flgMBB, flgMWW, flgMBW, flgMWB obtained from the next line.

After obtaining this result, the determination circuit 43 determines whether the acquired data is for the last line (step S218). In the case of the last line (YES in step S218), determination circuit 43 ends the process. If it is not the last line (NO in step S218), the process returns to step S204, and the determination circuit 43 sequentially obtains the gradation data of the next line and performs the same processing.

On the other hand, when “flgBB> m−Z” is not satisfied (NO in step S207), majority check circuit 120 then determines whether “flgWW (number of appearances of white and white pattern)> m−Z” is satisfied. (Step S208).

If “flgWW> m−Z” is satisfied (YES in step S208), the majority collation circuit 120 determines that the white / white pattern is the majority, and sets the flag flgMWW to “1”. Then, the determination circuit 43, that is, the AND circuit 136 determines whether or not the data regMBB acquired from the previous line is “1” (step S209).

When the data regMBB is “1” (YES in step S209), that is, when the display of one line to be output is white / white majority and the previous line display is black / black majority, the determination circuit 43 Judge that charge sharing is necessary. Therefore, the control signal Ctrl_CS from the D-FF 140 becomes “1”, and charge sharing is performed (step S210). Thus, the display method is changed so as to perform charge sharing, and the liquid crystal panel performs display (step S216).

As a result, the data regMWW becomes “1”. Further, the data regMBB / regMBW / regMWB becomes “0” (step S217). If data regMBB is “0” (NO in step S209), the liquid crystal panel performs display without changing the display method (step S216), and determination circuit 43 acquires the data (step S217). After obtaining this result, the determination circuit 43 similarly determines whether the acquired data is for the last line (step S218), and proceeds to the next process or ends the process.

On the other hand, if “flgWW> m−Z” is not satisfied (NO in step S208), majority collation circuit 120 then determines whether “flgBW (number of occurrences of black and white pattern)> m−Z” is satisfied. (Step S211).

If “flgBW> m−Z” is satisfied (YES in step S211), the majority collation circuit 120 determines that the black and white pattern is the majority, and sets the flag flgMBW to “1”. Then, the determination circuit 43, that is, the AND circuit 135 determines whether or not the data regMWB acquired from the previous line is “1” (step S212).

If the data regMWB is “1” (YES in step S212), that is, if the output of one line is majority in black and white and the display in the previous line is majority in black and white, the determination circuit 43 determines the polarity. Judge that reversal and charge sharing are necessary. Therefore, the control signal Ctrl_REV from the D-FF 139 becomes “1” and the control signal Ctrl_CS from the D-FF 140 becomes “1”, and polarity inversion and charge sharing are performed (step S213). Thereby, the display method is changed so as to perform polarity inversion and charge sharing, and the liquid crystal panel performs display (step S216).

Then, the flag flgMBW is latched by the D-FF 132 of the polarity inversion and charge share determination circuit 102, so that the data regMBW becomes “1”. Further, the data regMBB / regMWW / regMWB becomes “0” (step S217). If data regMWB is “0” (NO in step S212), the liquid crystal panel performs display without changing the display method (step S216), and determination circuit 43 acquires the data (step S217). After obtaining this result, the determination circuit 43 similarly determines whether the acquired data is for the last line (step S218), and proceeds to the next process or ends the process.

On the other hand, if “flgBW> m−Z” is not satisfied (NO in step S211), majority check circuit 120 then determines whether “flgWB (number of appearances of monochrome pattern)> m−Z” is satisfied. (Step S214).

If “flgWB> m−Z” is satisfied (YES in step S214), the majority collation circuit 120 determines that the monochrome pattern is the majority, and sets the flag flgMWB to “1”. Then, the determination circuit 43, that is, the AND circuit 134 determines whether or not the data regMBW acquired from the previous line is “1” (step S215).

If the data regMBW is “1” (YES in step S215), that is, if the output of one line to be displayed is majority in black and white and the display in the previous line is majority in black and white, the determination circuit 43 determines the polarity. Judge that reversal and charge sharing are necessary. Therefore, the control signal Ctrl_REV from the D-FF 139 becomes “1” and the control signal Ctrl_CS from the D-FF 140 becomes “1”, and polarity inversion and charge sharing are performed (step S213). Thereby, the display method is changed so as to perform polarity inversion and charge sharing, and the liquid crystal panel performs display (step S216).

Then, the flag flgMWB is latched by the D-FF 133 of the polarity inversion and charge share determination circuit 102, so that the data regMWB becomes “1”. Further, the data regMBB / regMWW / regMBW becomes “0” (step S217). If data regMBW is “0” (NO in step S215), the liquid crystal panel performs display without changing the display method (step S216), and determination circuit 43 acquires the data (step S217). After obtaining this result, the determination circuit 43 similarly determines whether the acquired data is for the last line (step S218), and proceeds to the next process or ends the process.

In this manner, the data signal line driver 30 outputs a data signal so as to perform display when displaying one screen, and repeatedly determines whether polarity inversion and charge sharing are necessary up to the final line.

Here, in the above processing, the determination circuit 43 determines that the output of one line to be output is majority in black and white, the display of the previous line is majority in black and white, and the output of one line to be output is numerous in black and white. If the display of the previous line is black and white majority, it is judged that polarity reversal and charge sharing are necessary. These two cases may occur in the case of the killer pattern in the source block inversion driving shown in FIG. That is, it is determined that polarity inversion and charge sharing are necessary by extracting a pattern in which the display adjacent in the horizontal direction has many black and white and black and white as a killer pattern.

FIG. 16 shows a pattern obtained by reversing the polarity of the killer pattern shown in FIG. 24A, FIG. 16A shows the pattern, FIG. 16B shows an odd line pattern, and FIG. An even line pattern is shown. Compared to the killer pattern, the polarity is reversed, but the black and white pattern does not change.

17A shows the potential change of output 1 and FIG. 17B shows the potential change of output 2 when charge sharing is performed between output 1 and output 2 of the pattern shown in FIG. . When output 1 and output 2 are short-circuited due to charge sharing between line 1 and line 3, output 1 and output 2 are set to a voltage of “a ′” which is an intermediate voltage between + black and −white. Become. In this change in voltage, since the charge held by the output 1 and the charge held by the output 2 cancel each other, no current flows.

After the short circuit is opened, the output 1 shifts from “a ′” to the −white potential, and the output 2 shifts from “a ′” to the + black potential, so the data signal line driver 30 drives the data lines. At this time, the driving voltage is half that of the case where charge sharing is not performed, and the current for driving the data line can be reduced. As a result, the heat generation of the data signal line driver 30 is also reduced.

When the output 1 and the output 2 are short-circuited due to the charge sharing between the line 3 and the line 5, the output 1 and the output 2 are “b ′” which is an intermediate voltage between −white and + black. Become a voltage. Accordingly, no current flows in the same manner, and a small amount of current is sufficient when shifting to the next potential, so that the data signal line driver 30 generates less heat. Therefore, as a whole, the heat generation of the data signal line driver 30 can be greatly reduced.

Note that the determination circuit 43 recognizes the pattern of the image with the majority combination pattern as described above. Therefore, the determination circuit 43 is not limited to a completely killer pattern display, and is a pattern similar to the killer pattern. Can be recognized. Thereby, substantially the same effect can be produced by performing polarity inversion and charge sharing.

In the above processing, the determination circuit 43 determines that charge sharing is necessary when the output of one line is majority white and white and the previous line is black and black. In this case, it can be considered as a two-row horizontal stripe pattern in which two rows are white or black and the next two rows are black or white.

FIG. 18 shows a two-row horizontal stripe pattern, (a) showing the pattern, (b) showing an odd line pattern, and (c) showing an even line pattern.

When the white driving voltage is a common potential, when displaying white after displaying black as in lines 1 to 3, the voltage displaying black due to charge sharing can be made close to the common voltage. . For example, the adjacent output 1 and output 2 display + black and −black on the line 1. Therefore, when charge sharing is performed, the voltage is “c”, which is a white driving voltage. Therefore, almost no driving power is required for the white display of the next line 3 output.

Thus, since charge sharing is an effective means for reducing current, the determination circuit 43 determines that charge sharing is necessary in the case of a two-row horizontal stripe pattern. Further, the determination circuit 43 is not limited to completely displaying a two-row horizontal stripe pattern, and can recognize a pattern similar to the two-row horizontal stripe pattern.

In addition, as shown in FIG. 19, when displaying black after displaying white, since the positive white voltage and the negative white voltage are the same, there is no charge sharing effect, There is no charge sharing.

In the above processing, the determination circuit 43 determines that the charge share is not valid when the output of one line to be output is majority black and black, and in cases other than the above three cases. For this reason, the display is performed as it is.

As described above, in the data signal line driver 30, the determination circuit 43 applies the majority combination pattern in one line corresponding to the gate line 21 previously scanned by the interlace scanning and the gate line 21 scanned this time. Based on the corresponding majority combination pattern in one line, whether or not it is effective to perform polarity inversion on adjacent outputs and charge sharing between adjacent outputs, and without performing the above polarity inversion It is determined whether it is effective to perform charge sharing between adjacent outputs. That is, the determination circuit 43 can recognize the pattern of the image to be displayed and make the above determination.

If it is determined that it is effective to invert the polarity between adjacent outputs and perform charge sharing between adjacent outputs, the polarity switching control circuit 44 outputs the polarity by outputting both the control signal Ctrl_REV and the control signal Ctrl_CS. The

inversion switch circuits

33 and 41 forcibly invert the polarity of adjacent outputs, and the output short circuit control circuit 45 causes the short circuit switch circuit 40 to short-circuit between adjacent outputs.

In addition, when it is determined that it is effective to perform charge sharing between adjacent outputs without performing polarity inversion, the output short circuit control circuit 45 causes the short circuit switch circuit 40 to switch between adjacent outputs by outputting the control signal Ctrl_CS. Short circuit.

Therefore, since effective charge sharing is performed, current consumption is reduced even when a special image called a killer pattern is displayed when the liquid crystal panel 20 is driven to invert the source block. The resulting heat generation can be reduced.

The liquid crystal display device 10 described above shows a case where one pixel is driven by one output, but when one pixel is composed of three pixels of R, G and B, the data signal line driver 30 Three outputs corresponding to R, G, and B are one output unit. For this reason, the polarity of display is changed for each output unit, and it is necessary to configure the output pair to form a pair in the output unit. Specifically, if the three outputs corresponding to R, G, and B are in units of one output, the polarity is changed every three outputs, and it is necessary to judge the display of output pairs between R, G, and B. is there.

Further, the number of outputs of the data signal line driver 30 is not limited to 414 outputs. The output of the data signal line driver 30 is required according to the number of pixels in the horizontal direction in FIGS. 1 and 2, and can be set to 2 to 2n (n: positive integer).

Further, the above-described liquid crystal display device 10 is a display device including the liquid crystal panel 20 using a liquid crystal element. When the voltage is not applied to the liquid crystal cell 25, the liquid crystal display device 10 is in a transmissive state (white by transmitting backlight light). When the voltage is applied to the liquid crystal cell 25, the liquid crystal cell 25 is in a non-transmissive state (black because it does not transmit light from the backlight) (normally white method). The state where light is most transmitted is one gradation, the gradation is expressed by changing the transmittance by changing the voltage, and the state where the light is least transmitted is 256 gradations.

However, depending on the characteristics of the liquid crystal element, there is a case where the state where no voltage is applied is non-transmissive (normally black method) or the black side is one gradation, and the number of gradations is larger than 256 gradations. There may be fewer cases. The data signal line driver 30 is compatible with both normally white and normally black display type liquid crystal panels, and each condition can be changed as appropriate, so it can be widely used. is there.

In the liquid crystal display device 10 described above, the determination circuit 43 of the data signal line driver 30 determines whether polarity inversion and charge sharing are necessary. This determination process is performed by an external controller or the like. It is also possible to do this.

The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope indicated in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

The data signal line driving circuit of the present invention includes a plurality of pixel electrodes arranged in a matrix, a plurality of scanning signal lines for supplying scanning signals to the pixel electrodes in the same row, and the pixel electrodes in the same column. For a liquid crystal display unit having a plurality of data signal lines for supplying data signals, the polarity of the data signal created in accordance with the gradation data is applied to each data signal line of the liquid crystal display unit with an adjacent output. A signal signal line drive circuit that outputs the signals opposite to each other, the polarity inversion means for inverting the polarity of the adjacent outputs, the short-circuit means for short-circuiting the adjacent outputs, and the first control signal, First control means for inverting the polarity of the adjacent output with respect to the polarity inverting means, and second control means for shorting the adjacent outputs with respect to the short-circuit means based on a second control signal. Determining means for outputting the first control signal to the first control means and outputting the second control signal to the second control means, wherein the liquid crystal display section is arranged in a column direction. Corresponding to the interlaced scanning in which the odd-numbered or even-numbered scanning signal lines are scanned in order after the odd-numbered or even-numbered scanning signal lines are scanned in order for each of the divided areas. Are sequentially supplied, and the determination means sequentially acquires the gradation data, and in the gradation data for one line acquired last time, the display at the adjacent output is transparent and non-transparent. A display pattern of the non-transparent state and a majority of the display patterns of the transparent state and the non-transparent state in the adjacent output in the gradation data for one row acquired this time. Based on the shown pattern has a selectively outputs constituting the first control signal and the second control signal.

In the data signal line driving circuit of the present invention, the determination means sequentially acquires the gradation data and determines whether the gradation data is in the transmissive state and the non-transmissive state. And using the determination result, display pattern creation means for creating a display pattern composed of the transmission state and the non-transmission state in the adjacent outputs, and count each of the created display patterns for one line. A majority determination means for determining a majority display pattern in the gradation data, and a holding means for holding the majority display pattern in the gradation data for one line previously determined by the majority determination means. The display pattern of the majority in the gradation data for one row that has been determined last time, and the number of the gradation data in the gradation data for one row that has been determined this time. Based on the school display pattern, it is desirable that a control signal output means for selectively outputting said first control signal and the second control signal.

In the data signal line driving circuit of the present invention, the display state determination unit of the determination unit is configured so that the acquired gradation data is in the transmission state and the non-transmission state based on a predetermined gradation range. It is preferable to determine whether it exists. Thus, it is possible to determine the transmission state and the non-transmission state within the gradation range indicated by the gradation data.

In the data signal line driving circuit of the present invention, it is preferable that the predetermined gradation range can be changed by a signal supplied from the outside. This makes it possible to adjust the transmissive state and the non-transmissive state to be recognized.

In the data signal line driving circuit according to the present invention, the majority determination means of the determination means is configured to display a display pattern composed of the transmission state and the non-transmission state in the adjacent outputs generated by the display pattern generation means. Among them, it is preferable to determine a display pattern having a predetermined number or more as the display pattern of the majority. This makes it possible to determine the killer pattern by appropriately determining the number.

Further, in the data signal line driving circuit of the present invention, it is preferable that the predetermined number can be changed by a signal given from the outside. Thereby, the recognition pattern can be adjusted.

The liquid crystal display device driving method of the present invention includes a plurality of pixel electrodes arranged in a matrix, a plurality of scanning signal lines for supplying scanning signals to the pixel electrodes in the same row, and the pixel electrodes in the same column. A liquid crystal display unit having a plurality of data signal lines for supplying data signals to the liquid crystal display unit, and each data signal line of the liquid crystal display unit has the polarity of the data signal created according to the gradation data with an adjacent output. A method of driving a liquid crystal display device comprising a data signal line drive circuit that outputs each of them in reverse, wherein the gradation data is divided into an odd row or a row for each area in which the liquid crystal display section is divided into a plurality of columns. Corresponding to the interlaced scanning in which the even-numbered or odd-numbered scanning signal lines are sequentially scanned after the even-numbered scanning signal lines are sequentially scanned, the gradation data is Next, the majority display pattern of the display pattern consisting of a transmission state in which the display at the adjacent output is transparent and a non-transmission state in which it is non-transparent in the gradation data for one line acquired last time, and this time The adjacent output of the data signal line driving circuit based on the display pattern of the majority of the display patterns composed of the transmission state and the non-transmission state in the adjacent output in the acquired gradation data for one row. The first step of determining whether the polarity inversion and the short circuit between the adjacent outputs of the data signal line driving circuit are necessary, and the adjacent output of the data signal line driving circuit when the polarity inversion is determined to be necessary And a third step of performing a short circuit between adjacent outputs of the data signal line driving circuit when it is determined that the short circuit is necessary. To.

Further, in the driving method of the liquid crystal display device of the present invention, the first step is a display state in which the gradation data is sequentially acquired to determine whether the gradation data is in the transmissive state or the non-transmissive state. Using the determination step, the determination result, a display pattern generation step for generating a display pattern composed of the transmission state and the non-transmission state at the adjacent outputs, and each of the generated display patterns is counted. A majority determination step for determining a majority display pattern in the gradation data for a row, and a holding for holding the majority display pattern in the gradation data for one row previously determined in the majority determination step A step, a display pattern of the majority in the gradation data for the previously determined one row, and the upper portion of the currently determined one row Based on the majority of the display pattern in the gradation data, it is desirable to include a control signal output step for selectively outputting the first control signal and the second control signal.

In the driving method of the liquid crystal display device of the present invention, in the display state determination step, based on a predetermined gradation range, whether the acquired gradation data is in the non-transmissive state or the transmissive state. Is preferably determined. Thus, it is possible to determine the transmission state and the non-transmission state within the gradation range indicated by the gradation data.

In the driving method of the liquid crystal display device of the present invention, in the majority determination step, the display pattern composed of the transmission state and the non-transmission state in the adjacent outputs created in the display pattern creation step is selected in advance. It is preferable that a display pattern having a predetermined number or more is determined as the majority display pattern. This makes it possible to determine the killer pattern by appropriately determining the number.

In the driving method of the liquid crystal display device according to the present invention, the liquid crystal display unit is a normally white display type, and in the first step, the majority of the gradation data for one row acquired previously is used. The display pattern is a “non-transparent state / non-transparent state” display pattern, and the majority display pattern in the gradation data for one row acquired this time is the “transparent state / transparent state” display pattern. In this case, it is preferable that the polarity reversal is unnecessary and the short circuit is necessary. Thereby, current consumption can be reduced.

In the driving method of the liquid crystal display device according to the present invention, the liquid crystal display unit is a normally white display type, and in the first step, the majority of the gradation data for one row acquired previously is used. The display pattern is a “transparent state / non-transparent state” display pattern, and the majority display pattern in the gradation data for one line acquired this time is the “non-transparent state / transparent state” display pattern. In this case, it is preferable to determine that the polarity reversal is necessary and the short circuit is necessary. Thereby, current consumption can be reduced.

In the driving method of the liquid crystal display device according to the present invention, the liquid crystal display unit is a normally white display type, and in the first step, the majority of the gradation data for one row acquired previously is used. The display pattern is a “non-transparent state / transparent state” display pattern, and the majority display pattern in the gradation data for one line acquired this time is the “transparent state / non-transparent state” display pattern. In this case, it is preferable to determine that the polarity reversal is necessary and the short circuit is necessary. Thereby, current consumption can be reduced.

In the driving method of the liquid crystal display device according to the present invention, the liquid crystal display unit is a normally black display type. In the first step, the majority of the gradation data for one row acquired last time is used. The display pattern is a “transparent state / transparent state” display pattern, and the majority display pattern in the gradation data for one line acquired this time is the “non-transparent state / non-transparent state” display pattern. In this case, it is preferable that the polarity reversal is unnecessary and the short circuit is necessary. Thereby, current consumption can be reduced.

In the driving method of the liquid crystal display device according to the present invention, the liquid crystal display unit is a normally black display type. In the first step, the majority of the gradation data for one row acquired last time is used. The display pattern is a “non-transparent state / transparent state” display pattern, and the majority display pattern in the gradation data for one line acquired this time is the “transparent state / non-transparent state” display pattern. In this case, it is preferable to determine that the polarity reversal is necessary and the short circuit is necessary. Thereby, current consumption can be reduced.

In the driving method of the liquid crystal display device according to the present invention, the liquid crystal display unit is a normally black display type. In the first step, the majority of the gradation data for one row acquired last time is used. The display pattern is a “transparent state / non-transparent state” display pattern, and the majority display pattern in the gradation data for one line acquired this time is the “non-transparent state / transparent state” display pattern. In this case, it is preferable to determine that the polarity reversal is necessary and the short circuit is necessary. Thereby, current consumption can be reduced.

Further, in the driving method of the liquid crystal display device of the present invention, the polarity inversion of the adjacent outputs of the data signal line driving circuit and the necessity of short circuit between the adjacent outputs of the data signal line driving circuit are determined as described above. It is desirable to carry out in the data signal line driving circuit.

INDUSTRIAL APPLICABILITY The present invention can be suitably used in the field related to a data signal line driving circuit that outputs a data signal to a liquid crystal panel, and is also suitable in the field related to a method for manufacturing a data signal line driving circuit and a method for controlling a data signal line driving circuit. Further, it can be widely used in the field of liquid crystal display devices such as TVs and mobile phones provided with a data signal line driver circuit, and manufacturing methods thereof.

10 Liquid crystal display device 20 Liquid crystal panel (liquid crystal display part)
21 Gate line (scanning signal line)
22 Source line (data signal line)
24 pixel electrode 30 data signal line driver (data signal line driver circuit)
31 Shift register 32 Data latch 33, 41 Polarity inversion switch circuit (polarity inversion means)
34 Hold latch 35 Level shifter 36 Positive side DAC
37 Negative polarity DAC
38 Operational amplifier for positive polarity 39 Operational amplifier for negative polarity 40 Short-circuit switch circuit (short-circuit means)
41 polarity reversing switch circuit 43 determination circuit (determination means)
44 Polarity switching control circuit (first control means)
45 Output short-circuit control circuit (second control means)
46 setting register 101 pattern detection circuit 102 charge share determination circuit 111 black verification circuit (display state determination means)
112 White verification circuit (display state determination means)
113,114 D-FF
115 Pattern matching circuit (display pattern creation means)
116 to 119 Counter 120 to 123 Majority verification circuit (majority determination means)
161-163 D-FF (holding means)
164 to 166 AND circuit (control signal output means)
167,168 OR circuit (control signal output means)
169, 170 D-FF (control signal output means)

Claims

A plurality of pixel electrodes arranged in a matrix, a plurality of scanning signal lines for supplying scanning signals to the pixel electrodes in the same row, and a plurality of data signals for supplying data signals to the pixel electrodes in the same column, respectively. A data signal line for outputting the data signal created in accordance with the gradation data to each data signal line of the liquid crystal display unit with the opposite polarity with adjacent outputs to the liquid crystal display unit having the data signal line A drive circuit,
Polarity inversion means for inverting the polarity of the adjacent outputs;
Short-circuit means for short-circuiting the adjacent outputs;
First control means for inverting the polarity of the adjacent output with respect to the polarity inverting means based on a first control signal;
Second control means for short-circuiting between the adjacent outputs to the short-circuit means based on a second control signal;
Determining means for outputting the first control signal to the first control means and outputting the second control signal to the second control means;
The gradation data is obtained by scanning the odd-numbered or even-numbered scanning signal lines in order for each of the areas in which the liquid crystal display section is divided into a plurality of columns, and then scanning the even-numbered or odd-numbered scanning signals. Corresponding to the interlaced scanning, in which the lines are scanned sequentially,
The determination means sequentially acquires the grayscale data, and in the previously acquired grayscale data for one row, a display comprising a transmissive state in which the display at the adjacent output is transmissive and a non-transmissive state in which it is non-transmissive. Based on the display pattern of the pattern majority and the display pattern of the display pattern consisting of the transmission state and the non-transmission state in the adjacent outputs in the gradation data for one line acquired this time, A data signal line driving circuit which selectively outputs the first control signal and the second control signal.
The above judgment means is
Display state determination means for sequentially acquiring the gradation data and determining whether the gradation data is in the transmission state and the non-transmission state;
Display pattern creating means for creating a display pattern composed of the transmissive state and the non-transmissive state at the adjacent outputs using the determination result;
A majority determination means for counting each of the created display patterns and determining a display pattern of the majority in the gradation data for one line;
Holding means for holding the display pattern of the majority in the gradation data for one row determined last time by the majority determination means;
Based on the held majority display pattern in the gradation data for one row determined last time and the majority display pattern in the gradation data for one row determined this time, 2. The data signal line driving circuit according to claim 1, further comprising control signal output means for selectively outputting the first control signal and the second control signal.
The display state determination unit of the determination unit determines whether the acquired gradation data is the transmission state and the non-transmission state based on a predetermined gradation range. 3. A data signal line drive circuit according to 2.
4. The data signal line driving circuit according to claim 3, wherein the predetermined gradation range can be changed by an externally applied signal.
The majority determination means of the determination means includes display patterns having a predetermined number or more of display patterns composed of the transmission state and the non-transmission state at the adjacent outputs generated by the display pattern generation means. 3. The data signal line drive circuit according to claim 2, wherein the display pattern is determined as the majority display pattern.
6. The data signal line driving circuit according to claim 5, wherein the predetermined number can be changed by a signal given from outside.
A plurality of pixel electrodes arranged in a matrix, a plurality of scanning signal lines for supplying scanning signals to the pixel electrodes in the same row, and a plurality of data signals for supplying data signals to the pixel electrodes in the same column, respectively. A liquid crystal display unit having data signal lines;
A liquid crystal display device comprising, on each data signal line of the liquid crystal display unit, a data signal line driving circuit that outputs the data signal created according to grayscale data with adjacent outputs in opposite polarities,
The liquid crystal display device according to claim 1, wherein the data signal line driving circuit is the data signal line driving circuit according to any one of claims 1 to 6.
A plurality of pixel electrodes arranged in a matrix, a plurality of scanning signal lines for supplying scanning signals to the pixel electrodes in the same row, and a plurality of data signals for supplying data signals to the pixel electrodes in the same column, respectively. A liquid crystal display unit having data signal lines;
According to a driving method of a liquid crystal display device, the data signal line of the liquid crystal display unit is provided with a data signal line driving circuit that outputs the data signal created according to the gradation data in an adjacent output with opposite polarity to each data signal line. There,
The gradation data is scanned evenly or oddly after the scanning signal lines of odd or even rows are sequentially scanned for each of the areas where the liquid crystal display section is divided into a plurality of columns. Corresponding to the interlaced scanning, in which the lines are scanned sequentially,
The gradation data is sequentially acquired, and in the previously acquired gradation data for one row, the majority of display patterns having a transmission state in which the display at the adjacent output is transparent and a non-transmission state in which the transmission is non-transparent The data signal line driving based on the display pattern and the display pattern of the majority of the display pattern composed of the transmission state and the non-transmission state at the adjacent outputs in the gradation data for one row acquired this time. A first step of determining the necessity of a polarity inversion of adjacent outputs of the circuit and a short circuit between adjacent outputs of the data signal line driving circuit;
A second step of performing polarity reversal of adjacent outputs of the data signal line drive circuit when it is determined that the polarity reversal is necessary;
And a third step of performing a short circuit between adjacent outputs of the data signal line drive circuit when it is determined that the short circuit is necessary.
The first step is
A display state determination step of sequentially acquiring the gradation data and determining whether the gradation data is in the transmission state and the non-transmission state;
Using the determination result, a display pattern creating step for creating a display pattern composed of the transmissive state and the non-transmissive state at the adjacent outputs;
A majority determination step of counting each of the created display patterns and determining a display pattern of the majority in the gradation data for one row;
A holding step for holding the display pattern of the majority in the gradation data for one row determined last time in the majority determination step;
Based on the held majority display pattern in the gradation data for one row determined last time and the majority display pattern in the gradation data for one row determined this time, 9. The method of driving a liquid crystal display device according to claim 8, further comprising a control signal output step of selectively outputting the first control signal and the second control signal.
10. The display state determination step of determining whether the acquired gradation data is in the non-transmission state or the transmission state based on a predetermined gradation range. Driving method for liquid crystal display device.
In the majority determination step, a display pattern having a predetermined number or more of the display patterns composed of the transmission state and the non-transmission state in the adjacent outputs generated in the display pattern generation step is selected from the majority. The method for driving a liquid crystal display device according to claim 9, wherein the display pattern is determined.
The liquid crystal display is a normally white display type,
In the first step, the majority display pattern in the gradation data for one line acquired last time is a display pattern of “non-transmission state / non-transmission state”, and the gradation for one line acquired this time 9. The liquid crystal display according to claim 8, wherein when the majority display pattern in the data is a “transmission state / transmission state” display pattern, the polarity inversion is unnecessary and the short circuit is necessary. Device driving method.
The liquid crystal display is a normally white display type,
In the first step, the majority display pattern in the gradation data for one line acquired last time is a display pattern of “transparent state / non-transmission state”, and the gradation data for one line acquired this time is displayed. 9. The liquid crystal display according to claim 8, wherein when the majority display pattern is a display pattern of “non-transmission state / transmission state”, the polarity inversion is necessary and the short circuit is necessary. Device driving method.
The liquid crystal display is a normally white display type,
In the first step, the majority display pattern in the gradation data for one line acquired last time is a display pattern of “non-transmission state / transmission state”, and the gradation data for one line acquired this time is displayed. 9. The liquid crystal display according to claim 8, wherein when the majority display pattern is a display pattern of “transmission state / non-transmission state”, it is determined that the polarity inversion is necessary and the short circuit is necessary. Device driving method.
The liquid crystal display is a normally black display type,
In the first step, the majority display pattern in the gradation data for one line acquired last time is a display pattern of “transmission state / transmission state”, and in the gradation data for one line acquired this time, 9. The liquid crystal display according to claim 8, wherein when the majority display pattern is a display pattern of “non-transmission state / non-transmission state”, it is determined that the polarity inversion is unnecessary and the short circuit is necessary. Device driving method.
The liquid crystal display is a normally black display type,
In the first step, the majority display pattern in the gradation data for one line acquired last time is a display pattern of “non-transmission state / transmission state”, and the gradation data for one line acquired this time is displayed. 9. The liquid crystal display according to claim 8, wherein when the majority display pattern is a display pattern of “transmission state / non-transmission state”, it is determined that the polarity inversion is necessary and the short circuit is necessary. Device driving method.
The liquid crystal display is a normally black display type,
In the first step, the majority display pattern in the gradation data for one line acquired last time is a display pattern of “transparent state / non-transmission state”, and the gradation data for one line acquired this time is displayed. 9. The liquid crystal display according to claim 8, wherein when the majority display pattern is a display pattern of “non-transmission state / transmission state”, the polarity inversion is necessary and the short circuit is necessary. Device driving method.
The polarity inversion of adjacent outputs of the data signal line driving circuit and the necessity of short circuit between adjacent outputs of the data signal line driving circuit are performed in the data signal line driving circuit. The method for driving a liquid crystal display device according to claim 8.