WO2010138415A2 - Semiconductor die attachment method using non-conductive screen print and dispense adhesive - Google Patents

Semiconductor die attachment method using non-conductive screen print and dispense adhesive Download PDF

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Publication number
WO2010138415A2
WO2010138415A2 PCT/US2010/035763 US2010035763W WO2010138415A2 WO 2010138415 A2 WO2010138415 A2 WO 2010138415A2 US 2010035763 W US2010035763 W US 2010035763W WO 2010138415 A2 WO2010138415 A2 WO 2010138415A2
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WO
WIPO (PCT)
Prior art keywords
integrated circuit
die
die attach
conductive material
dice
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Ceased
Application number
PCT/US2010/035763
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French (fr)
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WO2010138415A3 (en
Inventor
Ekgachai Kenganantanon
Surapol Sawatjeen
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Microchip Technology Inc
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Microchip Technology Inc
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Publication date
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Priority to CN201080004725.8A priority Critical patent/CN102282658B/en
Priority to SG2011066701A priority patent/SG174422A1/en
Publication of WO2010138415A2 publication Critical patent/WO2010138415A2/en
Publication of WO2010138415A3 publication Critical patent/WO2010138415A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/098—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H10W70/417—Bonding materials between chips and die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/137—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01331—Manufacture or treatment of die-attach connectors using blanket deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07321—Aligning
    • H10W72/07327—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H10W72/07338—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy hardening the adhesive by curing, e.g. thermosetting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07352—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • the present disclosure relates to attachment of semiconductor integrated circuit dice to leadframes, and more particularly, to attachment of the semiconductor dice to respective die attach paddles of the leadframes by using non-conductive screen print and dispense adhesive that also electrically isolates the semiconductor die from the leadframe die attach paddle.
  • a semiconductor integrated circuit die (backside thereof) is attached to a die attach paddle of a leadframe. Then bond pads of the semiconductor integrated circuit die are attached to conductors of the leadframe with bond wires. Typically, the backside of the semiconductor integrated circuit die is attached to the die attach paddle of the leadframe with an adhesive such as epoxy. Over time, conductive paths may form between the semiconductor integrated circuit die and the die paddle of the leadframe. These conductive paths may be created by migration of silver from the die attach paddle of the leadframe to the backside of the integrated circuit die. Eventually this silver migration creates a connection between the backside of the semiconductor integrated circuit die and the die paddle, thus causing an electrical short therebeween.
  • Silver molecules from the die attach paddle can migrate over time when there is an electrical potential difference between the semiconductor integrated circuit die and the die attach paddle. This electrical potential difference is present when operating and/or standby power is applied to the semiconductor integrated circuit die. Silver migration is particularly active when the semiconductor integrated circuit die is drawing low quiescent current, e.g., during a standby mode of operation (sleep mode). Running the semiconductor integrated circuit die at a low quiescent current is necessary so that the semiconductor integrated circuit die may be brought from the standby (sleep) mode to an operating mode. Silver migration creates electrical paths between the semiconductor integrated circuit die and the die attach paddle and thereby causes high quiescent current in the semiconductor integrated circuit die to the point eventually where the circuits of the semiconductor integrated circuit die fail.
  • the integrated circuit wafer comprises a plurality of semiconductor integrated circuit dice.
  • the screen printed epoxy is partially cured (B-stage) and is thereafter ready for singulation into individual dice.
  • the individual integrated circuit dice are then attached to respective die attach paddles of a plurality of leadframes by heating the die attach paddles then scrubbing the non-conductive B-stage epoxy coated dice onto the heated die attach paddles. After the dice have been attached to the respective die attach paddles, they are heated until the non-conductive B-stage epoxy is hard cured (C-stage).
  • This form of attachment does solve the silver migration problem long term, but the useful storage life of the B-stage epoxy integrated circuit wafer is only about two to four weeks.
  • a uniform layer of non-conductive material e.g., epoxy
  • C-stage a uniform layer of non-conductive material
  • the screen printing may apply the non-conductive material in a pattern onto the backside of the integrated circuit wafer.
  • the integrated circuit wafer, having the hard cured coating thereon, is then sawn apart to separate each individual integrated circuit die from each other in the wafer (singulated) for preparation to be attached to respective die attach paddles of leadframes.
  • the required thickness may be from about one to three milli-inches, preferably from about 1.5 to 2,5 milli-inches, and most preferably about two milli-inches.
  • a non-conductive adhesive e.g., epoxy
  • the face of the die having the hard cured coating is placed into the recently dispensed non- conductive adhesive on the mating face of the die attach paddle.
  • the die and die attach paddle assembly are heated to hard cure the adhesive between the mating faces of the die and die attach paddle.
  • the integrated circuit bond pads may be wire bonded to the leadframe leads (conductive leads used for the finished integrated circuit external circuit connections).
  • a method for attaching semiconductor dice to leadframe die attach paddles comprises the steps of: applying a non-conductive material to a back face of a semiconductor integrated circuit wafer, the semiconductor integrated circuit wafer comprising a plurality of integrated circuit dice; heating the semiconductor integrated circuit wafer and the non-conductive material thereon until the non-conductive material is hard cured; mounting the semiconductor integrated circuit wafer on a wafer carrier; wherein the hard cured non-conductive material is between the semiconductor integrated circuit wafer and the wafer carrier; separating each of the plurality of integrated circuit dice from each other; dispensing non-conductive adhesive on faces of die attach paddles of a plurality of leadframes; placing the plurality of integrated circuit dice into the non-conductive adhesive on the faces of respective ones of the die attach paddles
  • Figure 1 is a schematic process diagram for semiconductor die attachment using non- conductive screen print and dispense adhesive, according to a specific example embodiment of this disclosure.
  • Figure 2 is a schematic flow diagram of the semiconductor die attachment process shown in Figure 1, according to a specific example embodiment of this disclosure. While the present disclosure is susceptible to various modifications and alternative forms, specific example embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific example embodiments is not intended to limit the disclosure to the particular forms disclosed herein, but on the contrary, this disclosure is to cover all modifications and equivalents as defined by the appended claims.
  • FIG. 1 depicted is a schematic process diagram for semiconductor die attachment using non-conductive screen print and dispense adhesive, according to a specific example embodiment of this disclosure.
  • a semiconductor integrated circuit wafer 102 is placed into a screen printing fixture 106, and a non-conductive material 108 is spread over the backside (non-circuit pad side) of the wafer 102 with a screen printing spreader 104.
  • Use of the screen printing fixture 106 is well known in the art of coating surfaces.
  • a desired pattern of non-conductive material 108 may be applied to the backside face of the wafer 102.
  • the non-conductive material 108 may be, for example but is not limited to, epoxy and the like.
  • Hard curing of the non-conductive material 108 may comprise, for example but is not limited to, heating at about 150 degrees Centigrade for about two hours.
  • a leadframe carrier 1 14 comprises a plurality of leadframes 1 16.
  • Each of the plurality of leadframes 1 16 comprises a die attach paddle 1 16a and leadframe conductors 1 16b.
  • Leadframes 1 16 are well known to one having ordinary skill in the art of integrated circuit fabrication.
  • Adhesive 1 18 is dispensed onto a face of each of the die attach paddles 1 16a. Then the singulated (separated) dice 124 are place onto the adhesive 1 18 on each of the respective die attach paddles 1 16a.
  • the assembly of the leadframe carrier 1 14, plurality of leadframes 1 16, adhesive 1 18 and coated dice 124 are placed into a curing oven 120 so that the adhesive 1 18 is thereby hard cured.
  • Hard curing of the non-conductive adhesive 1 18 may comprise, for example but is not limited to, heating at about 175 degrees Centigrade for about one hour.
  • the adhesive material 1 18 is substantially non-conductive and may be, for example but is not limited to, epoxy and the like.
  • the leadframes 1 16 are removed from the curing oven 120 and the bond pads 126 on each of the dice 124 are connected to respective ones of the leadframe conductors 1 16b with bond wires 122. Wire bonding of integrated circuit bond pads 126 to leadframe conductors 1 16b is well known to one having ordinary skill in the art of integrated circuit fabrication.
  • the finished integrated circuit assemblies are separated and may be encapsulated into packaged integrated circuits (not shown).
  • step 202 the backside of a semiconductor integrated circuit wafer ( 102) is coated with non-conductive material (108).
  • step 204 the non-conductive material (108) coated on the backside of a semiconductor integrated circuit wafer (102) is hard cured.
  • step 206 the coated wafer (102) is mounted onto a carrier ( 1 12), and then in step 208 the plurality of integrated circuit dice (124) comprising the wafer ( 102) are separated apart from each other (singulated),
  • step 210 adhesive (1 18) is dispensed onto faces of die attach paddles (1 16a) of leadframes (1 16) on a leadframe carrier (1 14). Then in step 212, the singulated integrated circuit dice (124) are placed into the adhesive (1 18) on the faces of the respective die attach paddles (1 16a). In step 214, the adhesive (1 18) is heated to hard cure it (C-stage). In step 216, bond pads ( 126) of the dice ( 124) are wire bonded to respective ones of the conductors (e.g., leadfingers) (1 16b) of the leadframes (1 16). In step 218 the leadframes (1 16) are separated from the leadframe carrier (1 14) to become finished integrated circuits. These finished integrated circuits may be encapsulated in step 220 to become packaged integrated circuits, as is well know in the electronics arts.

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  • Die Bonding (AREA)

Abstract

A uniform layer of non - conductive material, (108) e.g., epoxy, is screen printed onto the backside of an integrated circuit wafer (102) to a required thickness, and then heated until it is hard cured (C- stage) (110) The integrated circuit wafer having the hard cured coating is then sawn apart to separate the individual integrated circuit dice (124) A non - conductive adhesive is dispensed onto mating faces of die attach paddles (116a) of leadframes (116). The dice are placed into the non - conductive adhesive and then the die and die attach paddle assembly are heated to hard cure the adhesive (118) between the mating faces of the die and die attach paddle. This provides long term electrical isolation of the integrated circuit die from the die attach paddle, and effectively eliminates silver migration from the die attach paddle which causes conductive paths to form that increase unwanted leakage currents in the die and ultimately cause failure during operation thereof.

Description

SEMICONDUCTOE DIE ATTACHMENT METHOD USING NON-CONDUCTIVE SCEEEN PEINT AND DISPENSE ADHESIVE
TECHNICAL FIELD
The present disclosure relates to attachment of semiconductor integrated circuit dice to leadframes, and more particularly, to attachment of the semiconductor dice to respective die attach paddles of the leadframes by using non-conductive screen print and dispense adhesive that also electrically isolates the semiconductor die from the leadframe die attach paddle.
BACKGROUND During fabrication of semiconductor integrated circuits, a semiconductor integrated circuit die (backside thereof) is attached to a die attach paddle of a leadframe. Then bond pads of the semiconductor integrated circuit die are attached to conductors of the leadframe with bond wires. Typically, the backside of the semiconductor integrated circuit die is attached to the die attach paddle of the leadframe with an adhesive such as epoxy. Over time, conductive paths may form between the semiconductor integrated circuit die and the die paddle of the leadframe. These conductive paths may be created by migration of silver from the die attach paddle of the leadframe to the backside of the integrated circuit die. Eventually this silver migration creates a connection between the backside of the semiconductor integrated circuit die and the die paddle, thus causing an electrical short therebeween. Silver molecules from the die attach paddle can migrate over time when there is an electrical potential difference between the semiconductor integrated circuit die and the die attach paddle. This electrical potential difference is present when operating and/or standby power is applied to the semiconductor integrated circuit die. Silver migration is particularly active when the semiconductor integrated circuit die is drawing low quiescent current, e.g., during a standby mode of operation (sleep mode). Running the semiconductor integrated circuit die at a low quiescent current is necessary so that the semiconductor integrated circuit die may be brought from the standby (sleep) mode to an operating mode. Silver migration creates electrical paths between the semiconductor integrated circuit die and the die attach paddle and thereby causes high quiescent current in the semiconductor integrated circuit die to the point eventually where the circuits of the semiconductor integrated circuit die fail. Various physical attachment configurations have been used to electrically isolate the .semiconductor integrated circuit die from the die attach paddle. One such attachment configuration uses non-conductive epoxy to achieve physical attachment and electrical isolation. However, this has proven over time to be ineffective and unreliable in preventing high quiescent currents due to conductive paths between the semiconductor integrated circuit die and the die attach paddle.
Another similar but more effective approach is to screen print one or two layers of non-conductive epoxy onto the backside of an integrated circuit wafer. The integrated circuit wafer comprises a plurality of semiconductor integrated circuit dice. The screen printed epoxy is partially cured (B-stage) and is thereafter ready for singulation into individual dice. The individual integrated circuit dice are then attached to respective die attach paddles of a plurality of leadframes by heating the die attach paddles then scrubbing the non-conductive B-stage epoxy coated dice onto the heated die attach paddles. After the dice have been attached to the respective die attach paddles, they are heated until the non-conductive B-stage epoxy is hard cured (C-stage). This form of attachment does solve the silver migration problem long term, but the useful storage life of the B-stage epoxy integrated circuit wafer is only about two to four weeks.
SUMMARY
Therefore, a need exists for a better way of coating the backside of a semiconductor integrated circuit wafer with a non-conductive material so that the coating has a long storage
(shelf) life, aids in the attachment of singulated semiconductor integrated circuit dice to die attach paddles of leadframes, and prevents or substantially reduces silver migration from the die attach paddle during operation of the semiconductor integrated circuit die.
According to teachings of this disclosure, a uniform layer of non-conductive material, e.g., epoxy, is screen printed onto the backside of an integrated circuit wafer to a required thickness, and then heated until it is hard cured (C-stage). The screen printing may apply the non-conductive material in a pattern onto the backside of the integrated circuit wafer. The integrated circuit wafer, having the hard cured coating thereon, is then sawn apart to separate each individual integrated circuit die from each other in the wafer (singulated) for preparation to be attached to respective die attach paddles of leadframes. The required thickness may be from about one to three milli-inches, preferably from about 1.5 to 2,5 milli-inches, and most preferably about two milli-inches.
During the process of attaching the die to a die attach paddle, a non-conductive adhesive, e.g., epoxy, is dispensed onto the mating face of the die attach paddle. Then the face of the die having the hard cured coating is placed into the recently dispensed non- conductive adhesive on the mating face of the die attach paddle. Next the die and die attach paddle assembly are heated to hard cure the adhesive between the mating faces of the die and die attach paddle. After the adhesive has been hard cured, the integrated circuit bond pads may be wire bonded to the leadframe leads (conductive leads used for the finished integrated circuit external circuit connections). Thereby providing long term electrical isolation of the integrated circuit die from the die attach paddle of the leadframe, and effectively eliminating silver migration from the die attach paddle which causes conductive paths to form that increase unwanted leakage currents in the die and ultimately cause failure during operation thereof. According to a specific example embodiment of this disclosure, a method for attaching semiconductor dice to leadframe die attach paddles comprises the steps of: applying a non-conductive material to a back face of a semiconductor integrated circuit wafer, the semiconductor integrated circuit wafer comprising a plurality of integrated circuit dice; heating the semiconductor integrated circuit wafer and the non-conductive material thereon until the non-conductive material is hard cured; mounting the semiconductor integrated circuit wafer on a wafer carrier; wherein the hard cured non-conductive material is between the semiconductor integrated circuit wafer and the wafer carrier; separating each of the plurality of integrated circuit dice from each other; dispensing non-conductive adhesive on faces of die attach paddles of a plurality of leadframes; placing the plurality of integrated circuit dice into the non-conductive adhesive on the faces of respective ones of the die attach paddles; heating the plurality of integrated circuit dice and die attach paddles until the non- conductive adhesive is hard cured; attaching bond pads of the plurality of integrated circuit dice to respective conductive leads of the plurality of leadframes with bond wires; and separating each of the plurality of leadframes into integrated circuits. Bffilf DESCRJUPTIQN OF THE DRAWINGS
A more complete understanding of the present disclosure may be acquired by referring to the following description taken in conjunction with the accompanying drawings wherein: Figure 1 is a schematic process diagram for semiconductor die attachment using non- conductive screen print and dispense adhesive, according to a specific example embodiment of this disclosure; and
Figure 2 is a schematic flow diagram of the semiconductor die attachment process shown in Figure 1, according to a specific example embodiment of this disclosure. While the present disclosure is susceptible to various modifications and alternative forms, specific example embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific example embodiments is not intended to limit the disclosure to the particular forms disclosed herein, but on the contrary, this disclosure is to cover all modifications and equivalents as defined by the appended claims.
D ETAILED DESCRI PTION
Referring now to the drawing, the details of specific example embodiments are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower case letter suffix.
Referring to Figure 1 , depicted is a schematic process diagram for semiconductor die attachment using non-conductive screen print and dispense adhesive, according to a specific example embodiment of this disclosure. A semiconductor integrated circuit wafer 102 is placed into a screen printing fixture 106, and a non-conductive material 108 is spread over the backside (non-circuit pad side) of the wafer 102 with a screen printing spreader 104. Use of the screen printing fixture 106 is well known in the art of coating surfaces. With the screen printing fixture 106, a desired pattern of non-conductive material 108 may be applied to the backside face of the wafer 102. The non-conductive material 108 may be, for example but is not limited to, epoxy and the like. After screen printing the backside face of the wafer 102 with the non-conductive material 108, the coated wafer 102 is placed into a curing oven 1 10 for hard curing of the non-conductive material 108. Hard curing of the non-conductive material 108 may comprise, for example but is not limited to, heating at about 150 degrees Centigrade for about two hours. After the non-conductive material 108 has been hard cured onto the backside face of the wafer 102, the wafer 102 may be stored for extended periods of time before further processing, or the hard cured coated wafer 102 may be attached to a process substrate 1 12, e.g., mounting tape, so that the wafer 102 can be singulated (separated by cutting) into a plurality of semiconductor integrated circuit dice 124, A leadframe carrier 1 14 comprises a plurality of leadframes 1 16. Each of the plurality of leadframes 1 16 comprises a die attach paddle 1 16a and leadframe conductors 1 16b. Leadframes 1 16 are well known to one having ordinary skill in the art of integrated circuit fabrication. Adhesive 1 18 is dispensed onto a face of each of the die attach paddles 1 16a. Then the singulated (separated) dice 124 are place onto the adhesive 1 18 on each of the respective die attach paddles 1 16a. The assembly of the leadframe carrier 1 14, plurality of leadframes 1 16, adhesive 1 18 and coated dice 124 are placed into a curing oven 120 so that the adhesive 1 18 is thereby hard cured. Hard curing of the non-conductive adhesive 1 18 may comprise, for example but is not limited to, heating at about 175 degrees Centigrade for about one hour. The adhesive material 1 18 is substantially non-conductive and may be, for example but is not limited to, epoxy and the like.
After the adhesive material 1 18 has been hard cured and cooled, the leadframes 1 16 are removed from the curing oven 120 and the bond pads 126 on each of the dice 124 are connected to respective ones of the leadframe conductors 1 16b with bond wires 122. Wire bonding of integrated circuit bond pads 126 to leadframe conductors 1 16b is well known to one having ordinary skill in the art of integrated circuit fabrication.
After wire bonding of each of the die bond pads 126 to respective ones of the leadframe conductors 1 16b, the finished integrated circuit assemblies are separated and may be encapsulated into packaged integrated circuits (not shown).
Referring to Figure 2, depicted is a schematic flow diagram of the semiconductor die attachment process shown in Figure 1, according to a specific example embodiment of this disclosure. In step 202, the backside of a semiconductor integrated circuit wafer ( 102) is coated with non-conductive material (108). In step 204, the non-conductive material (108) coated on the backside of a semiconductor integrated circuit wafer (102) is hard cured. In step 206, the coated wafer (102) is mounted onto a carrier ( 1 12), and then in step 208 the plurality of integrated circuit dice (124) comprising the wafer ( 102) are separated apart from each other (singulated),
In step 210, adhesive (1 18) is dispensed onto faces of die attach paddles (1 16a) of leadframes (1 16) on a leadframe carrier (1 14). Then in step 212, the singulated integrated circuit dice (124) are placed into the adhesive (1 18) on the faces of the respective die attach paddles (1 16a). In step 214, the adhesive (1 18) is heated to hard cure it (C-stage). In step 216, bond pads ( 126) of the dice ( 124) are wire bonded to respective ones of the conductors (e.g., leadfingers) (1 16b) of the leadframes (1 16). In step 218 the leadframes (1 16) are separated from the leadframe carrier (1 14) to become finished integrated circuits. These finished integrated circuits may be encapsulated in step 220 to become packaged integrated circuits, as is well know in the electronics arts.
While embodiments of this disclosure have been depicted, described, and are defined by reference to example embodiments of the disclosure, such references do not imply a limitation on the disclosure, and no such limitation is to be inferred. The subject matter disclosed is capable of considerable modification, alteration, and equivalents in form and function, as will occur to those ordinarily skilled in the pertinent art and having the benefit of this disclosure. The depicted and described embodiments of this disclosure are examples only, and are not exhaustive of the scope of the disclosure.

Claims

CLAIMS What is claimed is:
1 , A method for attaching semiconductor dice to leadframe die attach paddles, said method comprising the steps of: applying a non-conductive material to a back face of a semiconductor integrated circuit wafer, the semiconductor integrated circuit wafer comprising a plurality of integrated circuit dice; heating the semiconductor integrated circuit wafer and the non-conductive material thereon until the non-conductive material is hard cured; mounting the semiconductor integrated circuit wafer on a wafer carrier; wherein the hard cured non-conductive material is between the semiconductor integrated circuit wafer and the wafer carrier; separating each of the plurality of integrated circuit dice from each other; dispensing non-conductive adhesive on faces of die attach paddles of a plurality of leadframes; placing the plurality of integrated circuit dice into the non-conductive adhesive on the faces of respective ones of the die attach paddles; heating the plurality of integrated circuit dice and die attach paddles until the non-conductive adhesive is hard cured; attaching bond pads of the plurality of integrated circuit dice to respective conductive leads of the plurality of leadframes with bond wires; and separating each of the plurality of leadframes into integrated circuits.
2. The method according to claim 1, further comprising the step of encapsulating the integrated circuits to produce packaged integrated circuits.
3. The method according to claim 1, wherein the non-conductive material is applied at a thickness from about one milli-inch to about three milli-inches.
4. The method according to claim 1 , wherein the non-conductive material is applied at a thickness from about 1.5 milli-inches to about 2.5 milli-inches.
5. The method according to claim 1, wherein the non-conductive material is applied at a thickness of about two milli-inches.
6, The method according to claim 1, wherein the non-conductive material is epoxy.
7. The method according to claim 1 , wherein the non-conductive adhesive is epoxy,
8. The method according to claim 1 , wherein the step of applying the non- conductive material is done by screen printing.
9. The method according to claim 8, wherein the screen printed non-conductive material is applied in a pattern.
10. The method according to claim 1 , wherein the step of heating the semiconductor integrated circuit wafer and the non-conductive material comprises the step of heating at about 150 degrees Centigrade for about two hours.
1 1. The method according to claim 1 , wherein the step of heating the plurality of integrated circuit dice and die attach paddles until the non-conductive adhesive is hard cured comprises the step of heating at about 175 degrees Centigrade for about one hour.
PCT/US2010/035763 2009-05-27 2010-05-21 Semiconductor die attachment method using non-conductive screen print and dispense adhesive Ceased WO2010138415A2 (en)

Priority Applications (2)

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CN201080004725.8A CN102282658B (en) 2009-05-27 2010-05-21 Use non-conductive silk-screen printing and the semiconductor bare chip attachment method for applying adhesive
SG2011066701A SG174422A1 (en) 2009-05-27 2010-05-21 Semiconductor die attachment method using non-conductive screen print and dispense adhesive

Applications Claiming Priority (2)

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US12/472,675 US7927921B2 (en) 2009-05-27 2009-05-27 Semiconductor die attachment method using non-conductive screen print and dispense adhesive
US12/472,675 2009-05-27

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WO2010138415A2 true WO2010138415A2 (en) 2010-12-02
WO2010138415A3 WO2010138415A3 (en) 2011-05-26

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CN (1) CN102282658B (en)
MY (1) MY154082A (en)
SG (1) SG174422A1 (en)
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US20120279651A1 (en) * 2011-05-05 2012-11-08 Wei Gu Epoxy coating on substrate for die attach
US10234513B2 (en) 2012-03-20 2019-03-19 Allegro Microsystems, Llc Magnetic field sensor integrated circuit with integral ferromagnetic material
US9812588B2 (en) 2012-03-20 2017-11-07 Allegro Microsystems, Llc Magnetic field sensor integrated circuit with integral ferromagnetic material
US8822274B2 (en) 2012-10-04 2014-09-02 Texas Instruments Incorporated Packaged IC having printed dielectric adhesive on die pad
US10727085B2 (en) * 2015-12-30 2020-07-28 Texas Instruments Incorporated Printed adhesion deposition to mitigate integrated circuit package delamination

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US5208188A (en) * 1989-10-02 1993-05-04 Advanced Micro Devices, Inc. Process for making a multilayer lead frame assembly for an integrated circuit structure and multilayer integrated circuit die package formed by such process
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US6627517B1 (en) * 1999-12-08 2003-09-30 Altera Corporation Semiconductor package with improved thermal cycling performance, and method of forming same
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US7927921B2 (en) 2011-04-19
TW201108337A (en) 2011-03-01
WO2010138415A3 (en) 2011-05-26
US20100304532A1 (en) 2010-12-02
CN102282658B (en) 2018-11-02
MY154082A (en) 2015-04-30
CN102282658A (en) 2011-12-14
SG174422A1 (en) 2011-10-28
TWI462196B (en) 2014-11-21

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