WO2010137092A1 - Multi-operating system control method and processor system - Google Patents

Multi-operating system control method and processor system Download PDF

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Publication number
WO2010137092A1
WO2010137092A1 PCT/JP2009/006778 JP2009006778W WO2010137092A1 WO 2010137092 A1 WO2010137092 A1 WO 2010137092A1 JP 2009006778 W JP2009006778 W JP 2009006778W WO 2010137092 A1 WO2010137092 A1 WO 2010137092A1
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Prior art keywords
operating system
virtual processor
interrupt
virtual
processor
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PCT/JP2009/006778
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French (fr)
Japanese (ja)
Inventor
林邦彦
神田正和
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パナソニック株式会社
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Publication of WO2010137092A1 publication Critical patent/WO2010137092A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors

Definitions

  • the present invention relates to a multi-operating system control method and a processor system, and more particularly to a multi-operating system control method for executing a first operating system and a second operating system in parallel on a plurality of virtual processors.
  • a multi-thread processor is known as a processor realizing high performance.
  • This multi-thread processor can improve processing efficiency by simultaneously executing a plurality of threads by a plurality of virtual processors.
  • the multi-thread processor can share resources in the execution of a plurality of threads, the area efficiency of the processor can be improved as compared with the case where a plurality of processors are provided independently.
  • an object of the present invention is to provide a multi-operating system control method and a processor system that can easily manage virtual processors.
  • a multi-operating system control method includes parallelly executing a first operating system and a second operating system on a plurality of virtual processors that are logically realized by real processors.
  • the virtual processor used by the first operating system is statically generated and the virtual processor used by the second operating system is dynamically generated.
  • the virtual processor used by the first operating system can be fixedly used.
  • the identifiers of the virtual processors used by the first operating system can be matched on the multi-operating system and on the first operating system. Therefore, it is not necessary to convert the virtual processor identifier on the first operating system and the virtual processor identifier on the multi-operating system.
  • the multi-operating system control method according to an aspect of the present invention can reduce the overhead of the first operating system.
  • the operating system uses the identifier of the virtual processor on the first operating system.
  • the identifier can be converted by a simple process such as assigning an identifier for identifying the system.
  • the multi-operating system control method can easily manage the virtual processors used by the first operating system.
  • the virtual processor used by the first operating system is generated only when the first operating system is started, and the virtual processor used by the second operating system is generated and deleted after the second operating system is started. May be.
  • the virtual processor can be used in a fixed manner.
  • the virtual processor used by the second operating system is generated when the second operating system is started, and is generated and deleted after the second operating system is started, so that the first operating system and the second operating system are generated.
  • the virtual processor used by the second operating system may be generated after generating the virtual processor used by the first operating system.
  • the identifiers of the virtual processors used by the first operating system can be matched on the multi-operating system and the first operating system.
  • a first identifier indicating whether the virtual processor is used for the first operating system or the second operating system is assigned to the plurality of virtual processors, and the same first identifier is assigned to the plurality of virtual processors.
  • a plurality of virtual processors may be provided with second identifiers that are serial numbers in the order of generation of the plurality of virtual processors and that are independent among the first identifiers.
  • the identifier on the first operating system of the virtual processor used by the first operating system can be matched with the second identifier.
  • the virtual processor that executes the task may be newly generated.
  • the virtual processor that has executed the task may be deleted.
  • different interrupt vectors may be associated with the virtual processors having different first identifiers, and the same interrupt vector may be associated with a plurality of virtual processors having the same first identifier.
  • an interrupt factor is associated with each set of the first identifier and the second identifier, and when an interrupt request is generated, a virtual processor specified by the set associated with the interrupt factor of the interrupt An interrupt may be issued.
  • each virtual processor can be associated with an interrupt factor.
  • the interrupt may be accepted only when the virtual processor specified by the set associated with the interrupt factor of the interrupt is operating.
  • the interrupt processing based on the interrupt request is started after the operation of the virtual processor is started. May be.
  • the interrupt process may be interrupted.
  • the present invention can be realized not only as such a multi-operating system control method, but also as a processor system using the characteristic steps included in the multi-operating system control method as a means. It can also be realized as a program for causing a computer to execute. Needless to say, such a program can be distributed via a recording medium such as a CD-ROM and a transmission medium such as the Internet.
  • the present invention can provide a multi-operating system control method and a processor system that can easily manage virtual processors.
  • FIG. 1 is a diagram showing a configuration of a processor system according to an embodiment of the present invention.
  • FIG. 2 is a diagram schematically showing a function of executing each OS in the processor system according to the embodiment of the present invention.
  • FIG. 3 is a diagram showing a configuration of the virtual processor according to the embodiment of the present invention.
  • FIG. 4 is a diagram showing a configuration of the virtual processor management unit according to the embodiment of the present invention.
  • FIG. 5 is a diagram showing a configuration of virtual processor information and context according to the embodiment of the present invention.
  • FIG. 6 is a diagram showing an example of a domain number and a virtual processor number in the processor system according to the embodiment of the present invention.
  • FIG. 7 is a diagram showing a configuration of the interrupt factor table according to the embodiment of the present invention.
  • FIG. 8 is a diagram showing a configuration of the TLB according to the embodiment of the present invention.
  • FIG. 9 is a flowchart showing the flow of initialization processing immediately after the start of the processor system according to the embodiment of the present invention.
  • FIG. 10 is a diagram showing virtual processor switching processing in the processor system according to the embodiment of the present invention.
  • FIG. 11 is a flowchart showing the flow of time slot switching processing in the processor system according to the embodiment of the present invention.
  • FIG. 12 is a flowchart showing the flow of interrupt processing in the processor system according to the embodiment of the present invention.
  • FIG. 13 is a diagram showing an example of interrupt processing in the processor system according to the embodiment of the present invention.
  • FIG. 14 is a flowchart showing a flow of virtual processor generation processing in the processor system according to the embodiment of the present invention.
  • FIG. 15 is a flowchart showing the flow of the pause processing of the virtual processor in the processor system according to the embodiment of the present invention.
  • the processor system 100 statically generates the virtual processor 113 used by the first OS 121 only when the first OS 121 is activated, and dynamically generates the virtual processor 113 used by the second OS 122. As a result, the processor system 100 can match the identifier of the virtual processor 113 on the first OS 121 with the identifier of the virtual processor 113 on the multi-OS, so that the virtual processor 113 can be easily managed.
  • FIG. 1 is a diagram schematically showing an overall configuration of a processor system 100 according to an embodiment of the present invention.
  • a processor system 100 shown in FIG. 1 is a multi-thread processor system that realizes a multi-OS that executes a first OS 121 and a second OS 122 on a plurality of virtual processors 113 in parallel.
  • parallel here means that the first OS 121 and the second OS 122 are apparently executed in parallel (simultaneously).
  • a plurality of virtual processors 113 are executed while being switched to time division as described later.
  • the virtual processor 113 is a processor that is logically realized by a real processor. In other words, the virtual processor 113 is a logically defined processor that does not depend on the number of real processors.
  • the processor system 100 includes a processor block 101, an external device 102, and an external memory 103.
  • the processor block 101 includes a CPU 110, an interrupt controller 114, a timer 115, an I / O unit 116, and a virtual processor management unit 120.
  • the CPU 110 includes a cache memory 111, an MMU (Memory Management Unit) 112, and a virtual processor 113.
  • MMU Memory Management Unit
  • first OS 121 and the second OS 122 are realized by the CPU 110 executing the program.
  • a plurality of first programs 123 operate on the first OS 121, and a plurality of second programs 124 operate on the second OS 122.
  • the first OS 121 is a general-purpose OS that is widely used in personal computers.
  • the second OS 122 is an OS suitable for a media control program that ensures real-time performance.
  • FIG. 2 is a diagram schematically showing a function of executing each OS in the processor system 100.
  • FIG. 3 is a diagram illustrating the configuration of the virtual processor 113.
  • one virtual processor 113 includes one logical processor (LP) 133 and one time slot (TS) 134, which are independent of each other.
  • LP logical processor
  • TS time slot
  • a plurality of virtual processors 113 may operate simultaneously, or only one virtual processor 113 may operate.
  • a group of virtual processors 113 on which each OS operates is called a domain.
  • the first domain 131 includes one or more virtual processors 113 that execute the first OS 121
  • the second domain 132 includes one or more virtual processors 113 that execute the second OS 122.
  • This domain is an identifier for identifying a plurality of virtual processors 113 as OS resources.
  • FIG. 4 is a diagram illustrating a configuration of the virtual processor management unit 120.
  • the virtual processor management unit 120 includes a virtual processor control unit 141, a timer control unit 142, an execution control unit 143, a virtual processor information storage unit 144, a context holding unit 145, and an interrupt control unit 148. And a TLB control unit 152.
  • the processor system 100 includes a TLB (Translation Lookaside Buffer) 140 included in the MMU 112.
  • TLB Translation Lookaside Buffer
  • the virtual processor information storage unit 144 stores a plurality of virtual processor information 160 corresponding to each of the plurality of virtual processors 113 on a one-to-one basis.
  • the virtual processor information 160 is information on the corresponding virtual processor 113.
  • the context holding unit 145 holds a plurality of contexts 171 corresponding to the plurality of virtual processors 113 on a one-to-one basis.
  • the context 171 of the process to be interrupted is saved in the context holding unit 145.
  • the context 171 of the process to be started is returned from the context holding unit 145.
  • FIG. 5 is a diagram showing the configuration of the virtual processor information 160 and the context 171.
  • each virtual processor information 160 includes TS information 161 and LP information 162.
  • TS information 161 is information of TS 134 included in the corresponding virtual processor 113, and includes a virtual processor state 163 and an allocation time 164.
  • LP information 162 is information of LP 133 included in the corresponding virtual processor 113, and includes a domain number 165, a virtual processor number 166, and an interrupt vector 167.
  • the virtual processor state 163 indicates what state the corresponding virtual processor 113 is in. Specifically, the virtual processor state 163 indicates one of three states: a valid state, an invalid state, and a dormant state.
  • the valid state is a state in which the corresponding virtual processor 113 is a switching target of the switching unit 147. Further, when the virtual processor information 160 is generated, the virtual processor state 163 is set to a valid state.
  • the invalid state is a state in which the corresponding virtual processor 113 is not a switching target of the switching unit 147.
  • the hibernate state indicates a state waiting for an interrupt to the corresponding virtual processor 113, and when an interrupt occurs, the virtual processor state 163 transitions to a valid state.
  • the allocation time 164 indicates a time during which the corresponding virtual processor 113 can execute processing. When the time when the corresponding virtual processor 113 actually executes the processing reaches the allocation time 164, the virtual processor 113 to be executed is switched to the next virtual processor 113.
  • the allocation time 164 is set simultaneously with the generation of the virtual processor information 160.
  • the domain number 165 indicates to which domain the corresponding virtual processor 113 belongs. That is, the domain number 165 is an identifier indicating whether the corresponding virtual processor 113 is used for the first OS 121 or the second OS 122.
  • the virtual processor number 166 is a serial number in the domain, and is assigned in the order of 1, 2, 3,..., For example.
  • the virtual processor number 166 is an independent number between different domains.
  • the virtual processor number 166 is used as the number of the virtual processor 113 notified from the virtual processor management unit 120 to the first OS 121 and the second OS 122. Therefore, the number of the virtual processor 113 inside the OS does not depend on the actual position of the virtual processor 113.
  • FIG. 6 is a diagram illustrating an example of the domain number 165 and the virtual processor number 166.
  • the domain number 165 of the virtual processor 113 (LP133) belonging to the first OS 121 is set to “1”
  • the domain number 165 of the virtual processor 113 (LP133) belonging to the second OS 122 is set to “2”.
  • the In each domain, the virtual processor number 166 is a serial number.
  • each virtual processor 113 has a number (hereinafter, hardware number) determined by the position of the hardware.
  • the plurality of virtual processor information 160 are arranged in order of this hardware number, for example, from the left.
  • the LP133 number shown in FIG. 6 corresponds to this hardware number.
  • each virtual processor 113 is identified using this hardware number.
  • the virtual processor management unit 120 can uniquely identify a plurality of virtual processors 113 by associating each virtual processor 113 with a domain number 165 and a virtual processor number 166.
  • the virtual processor management unit 120 based on the set of the domain number 165 and the virtual processor number 166, and the position of the virtual processor information 160, the virtual processor number 166 notified from each OS or program, and the hardware number Can be converted to each other. Specifically, when the virtual processor 113 whose virtual processor number 166 is “2” is designated from the second OS 122, in the example illustrated in FIG. 6, the domain number 165 is “2” and the virtual processor number 166 is “ It can be determined that the hardware number of the virtual processor 113 (LP133) that is “2” is “4”.
  • a plurality of virtual processors 113 can be uniquely assigned without changing the function of each OS. Can be identified.
  • the interrupt vector 167 is an address indicating the head of a table in which addresses to handlers for each interrupt type are arranged. Different interrupt vectors 167 are associated with virtual processors 113 belonging to different domains, and the same interrupt vector 167 is associated with a plurality of virtual processors 113 belonging to the same domain.
  • the context 171 includes register information 172 and cache allocation information 173 of the corresponding virtual processor 113.
  • the order of the virtual processor information 160 represents the generation order of the corresponding virtual processor 113.
  • the virtual processor control unit 141 includes a state change unit 146 and a switching unit 147.
  • the virtual processor control unit 141 defines the plurality of domains in the initialization process performed after the processor system 100 is activated, and assigns the required number of virtual processors 113 to each domain.
  • the state changing unit 146 defines a domain and assigns a required number of virtual processors 113 to each domain in an initialization process performed when the processor system 100 is started. Specifically, the state change unit 146 generates the virtual processor 113 belonging to each domain by generating the virtual processor information 160.
  • the plurality of virtual processors 113 belonging to the first OS 121 are not newly generated or deleted after being generated when the processor system 100 is activated.
  • a plurality of virtual processors 113 belonging to the second OS 122 are newly created and deleted in response to a request from the second OS 122 after being created when the processor system 100 is activated.
  • generating the virtual processor 113 means adding a TS 134 that is sequentially switched by the switching unit 147.
  • the state changing unit 146 sets the virtual processor state 163 included in the virtual processor information 160 corresponding to the generated virtual processor 113 to the valid state. Thereby, the virtual processor 113 becomes a switching target of the switching unit 147.
  • to delete the virtual processor 113 is to remove the virtual processor 113 from the switching target of the switching unit 147.
  • the state changing unit 146 deletes the virtual processor by changing the virtual processor state 163 included in the virtual processor information 160 corresponding to the virtual processor 113 to an invalid state.
  • the state change unit 146 changes the virtual processor information 160 in response to a notification from the first OS 121, the second OS 122, the first program 123, or the second program 124.
  • the state change unit 146 prohibits all interrupt requests and switching requests by the timer control unit 142 in order to prevent inconsistency of information.
  • the switching unit 147 performs round robin scheduling for selecting each virtual processor 113 at least once within a predetermined period. Specifically, the switching unit 147 switches the virtual processor 113 when the execution time of the currently executing virtual processor 113 reaches the allocation time 164.
  • the timer control unit 142 starts counting time using the timer 115 every time the allocated time 164 is set from the virtual processor control unit 141.
  • the timer control unit 142 outputs a timeout signal when the counting time reaches the allocation time 164. This timeout signal indicates the switching timing of the time slot 134 and is notified to the virtual processor control unit 141.
  • the switching unit 147 determines whether or not the execution time has reached the allocation time 164 based on a timeout signal output from the timer control unit 142. When the execution time reaches the allocation time 164, the switching unit 147 selects the next virtual processor information 160 in the arrangement order. In addition, the switching unit 147 acquires the allocation time 164 from the newly selected virtual processor information 160 and sets it in the timer control unit 142. As a result, the timer control unit 142 starts counting the allocation time 164 of the next virtual processor 113.
  • the switching unit 147 saves and restores the context 171 before resuming processing that operates on the virtual processor 113.
  • the switching unit 147 interrupts the switching process when the state changing unit 146 performs the process.
  • the execution control unit 143 executes the thread selected by the switching unit 147.
  • the execution control unit 143 corresponds to hardware such as the CPU 110 that executes threads.
  • the interrupt control unit 148 associates the interrupt factor 181 with the virtual processor 113.
  • the interrupt controller 114 issues an interrupt to the virtual processor 113 associated with the interrupt factor 181 of the interrupt.
  • the interrupt control unit 148 includes a setting unit 149, an interrupt receiving unit 150, and an interrupt factor table storage unit 151.
  • the interrupt factor table storage unit 151 stores an interrupt factor table 180 indicating the correspondence between the interrupt factor 181 and the virtual processor 113.
  • FIG. 7 is a diagram showing the configuration of the interrupt factor table 180.
  • the interrupt factor table 180 indicates the interrupt factor 181 associated with each of the plurality of virtual processors 113. Specifically, one interrupt factor 181 is associated with a set of the domain number 165 and the virtual processor number 166.
  • the setting unit 149 registers the domain number 165 and the virtual processor number 166 in the interrupt factor table 180 in response to notifications from the first OS 121, the second OS 122, the first program 123, and the second program 124.
  • the interrupt receiving unit 150 receives an interrupt request requested by the external device 102 or a software factor.
  • the interrupt controller 114 starts an OS interrupt handler that operates on the corresponding virtual processor 113 in accordance with the interrupt factor table 180.
  • the TLB control unit 152 controls the TLB 140.
  • FIG. 8 is a diagram showing the configuration of the TLB 140.
  • the TLB 140 is a kind of cache memory, and holds a part of a page table indicating a correspondence relationship between a logical address and a physical address.
  • the TLB 140 performs conversion between a logical address and a physical address using a held page table.
  • the TLB 140 includes a plurality of entries 190.
  • Each entry 190 includes a tag 191 for identifying a logical address, a domain number 165, a PID 192, and data 193.
  • PID 192 is an ID for identifying a process using the data.
  • Data 193 is a physical address associated with the tag 191.
  • the TLB control unit 152 sets the domain number 165 to which the virtual processor 113 serving as the update source belongs to the tag 191. Further, when the TLB 140 is searched, the TLB control unit 152 searches only the entry 190 that holds the domain number 165 to which the target virtual processor 113 belongs.
  • a plurality of I / O addresses of the I / O unit 116 used for connection with the external device 102 are assigned independently for each domain. Further, as described above, independent interrupt control is performed for each domain. Thereby, since the first OS 121 and the second OS 122 do not access each other, the processor system 100 can ensure independence between the OSs for hardware control.
  • access to the hardware is directly executed by each OS, so that software for managing the OS does not need to emulate access from each OS. This eliminates the need to change the OS kernel and device driver built on the premise of direct access to hardware. Further, overhead when the OS accesses the hardware can be prevented.
  • the first OS 121 and the second OS 122 divide the area of the external memory 103, which is a physical memory used in common, and use the areas obtained by dividing each OS. Further, as described above, the entry 190 of the TLB 140 is identified by the domain number 165. Thereby, a logical space can be divided for each domain.
  • an area where MMU conversion is not performed is arranged. This area has a high protection level and is accessible only from the OS.
  • the processor system 100 can ensure independence between OSs.
  • FIG. 9 is a flowchart showing the flow of initialization processing immediately after the processor system 100 is started.
  • the virtual processor management unit 120 initializes registers and interrupts (S101).
  • the state change unit 146 defines the first domain 131 corresponding to the first OS 121 (S102).
  • the state change unit 146 generates a plurality of virtual processors 113 belonging to the first domain 131 (S103). Specifically, the state change unit 146 generates virtual processor information 160 and stores the generated virtual processor information 160 in the virtual processor information storage unit 144. Further, the number of virtual processors 113 to be generated is a predetermined fixed number required by the first OS 121. Further, the number of the plurality of virtual processors 113 belonging to the first domain 131 is not changed after this process. That is, the plurality of virtual processors 113 belonging to the first domain 131 are not created or deleted after this processing.
  • the state changing unit 146 defines the second domain 132 corresponding to the second OS 122 (S104).
  • the state change unit 146 generates a plurality of virtual processors 113 belonging to the second domain 132 (S105). Specifically, the state change unit 146 generates virtual processor information 160 and stores the generated virtual processor information 160 in the virtual processor information storage unit 144. For example, the state change unit 146 generates only one virtual processor 113. Further, the virtual processor 113 belonging to the second domain 132 is newly created or deleted as necessary after this processing.
  • the state change unit 146 enables the timer control unit 142 and starts the switching operation of the virtual processor 113 (S106).
  • the processor system 100 statically generates the virtual processor 113 used by the first OS 121 and dynamically generates the virtual processor 113 used by the second OS 122. Specifically, the processor system 100 generates the virtual processor 113 used by the first OS 121 only when the first OS 121 is activated. Further, the processor system 100 generates the virtual processor 113 used by the second OS when the second OS 122 is started, and generates and deletes the virtual processor 113 after the second OS 122 is started.
  • the processor system 100 generates the virtual processor 113 of the second OS 122 that is generated and deleted after startup after generating the virtual processor 113 of the first OS 121 that is not generated and deleted after startup.
  • the order of the virtual processor information 160 represents the generation order of the corresponding virtual processors 113.
  • the order of the virtual processor information 160 corresponds to the hardware number of the virtual processor 113. That is, the generation order of the virtual processor 113 is equal to the hardware number.
  • the hardware numbers of the two virtual processors 113 are “1” and “2”, respectively. It becomes equal to the virtual processor number 166 of the processor 113. Furthermore, since the virtual processor 113 of the first OS 121 is not generated or deleted in the subsequent processing, the virtual processor number 166 of the first OS 121 and the hardware number always match in the subsequent processing.
  • the first OS 121 recognizes the virtual processor 113 without using the virtual processor management unit 120, as in the case where a single OS is operating. Can do. Thereby, the processor system 100 can reduce the overhead of the first OS 121.
  • the virtual processor management unit 120 can directly notify the hardware number without converting it. As a result, the processor system 100 can reduce the processing amount of the virtual processor management unit 120, so that the processing speed can be improved.
  • the processor system 100 matches the hardware number with the virtual processor number 166 of the virtual processor 113 of the first OS 121 in which the virtual processor 113 is not generated and deleted after startup. As a result, the virtual processor 113 can be easily controlled.
  • the first OS 121 may recognize the virtual processor 113 via the virtual processor management unit 120. Even in this case, the virtual processor management unit 120 can be used as it is as the virtual processor number 166 without converting the hardware number, so that the processing amount of the virtual processor management unit 120 can be reduced.
  • FIG. 10 is a diagram showing the switching process of the virtual processor 113 in the processor system 100.
  • the LP1 context 171 becomes valid during the TS1 allocation time 164. Also, task A of the first OS 121 operates on LP1.
  • FIG. 11 is a flowchart showing the flow of time slot switching processing by the switching unit 147.
  • the timer control unit 142 sends a timeout notification to the switching unit 147.
  • the switching unit 147 prohibits interruption (S111) and saves the context 171 of the currently executed virtual processor 113 to the context holding unit 145 (S112).
  • the switching unit 147 selects the virtual processor 113 in which the virtual processor state 163 is valid next in accordance with the arrangement order of the virtual processor information 160 stored in the virtual processor information storage unit 144 (S113).
  • the switching unit 147 switches the interrupt vector to be used to the interrupt vector 167 of the selected virtual processor 113 (S114).
  • the switching unit 147 extracts the allocation time 164 of the selected virtual processor 113 from the virtual processor information 160, and sets the extracted allocation time 164 in the timer control unit 142 (S115).
  • the switching unit 147 restores the context 171 of the selected virtual processor 113 from the context holding unit 145 (S116) and permits an interrupt (S117).
  • the switching unit 147 determines whether or not an interrupt designating the selected virtual processor 113 has occurred (S118). If an interrupt has occurred (Yes in S118), the switching unit 147 starts interrupt processing (S119).
  • the processor system 100 accepts the interrupt only when the virtual processor 113 associated with the interrupt factor of the interrupt is operating. In addition, when an interrupt request occurs, the processor system 100 starts interrupt processing based on the interrupt request after the virtual processor 113 starts operating if the virtual processor associated with the interrupt factor of the interrupt is not operating. . Further, when the operation allocation period of the virtual processor 113 ends during execution of the interrupt process based on the interrupt request, the processor system 100 interrupts the interrupt process.
  • FIG. 12 is a flowchart showing the flow of interrupt processing in the processor system 100.
  • the interrupt controller 114 issues an interrupt to the virtual processor 113 corresponding to the interrupt factor 181 of the accepted interrupt according to the interrupt factor table 180 (S121).
  • the switching unit 147 accepts the interrupt (S123). Specifically, the switching unit 147 refers to the interrupt vector 167 of the virtual processor 113 that is the interrupt destination, and sets the address of the interrupt handler specified by the interrupt vector 167 in the program counter. Thereby, the interrupt process is started.
  • FIG. 13 is a diagram illustrating an example of interrupt processing in the processor system 100.
  • the processor system 100 can accept only an interrupt addressed to the operating virtual processor 113.
  • FIG. 14 is a flowchart showing a flow of generation processing of the virtual processor 113.
  • the second OS 122 issues a virtual processor generation instruction to the virtual processor control unit 141.
  • the state changing unit 146 performs initialization by securing a free area in the virtual processor information storage unit 144 (S131).
  • the state change unit 146 reserves virtual processor information 160 that has not been set or a virtual processor state 163 in which the virtual processor state 163 is in an invalid state.
  • the state change unit 146 sets the domain number 165 and the allocation time 164 given from the second OS 122 (S132). Further, the state changing unit 146 sets the virtual processor number 166 so as to be a serial number within the domain number 165 (S133). Further, the state changing unit 146 sets the interrupt vector 167 corresponding to the domain number 165 (S134).
  • state changing unit 146 sets the given execution start address and stack address in the context 171 (S135). Further, the state changing unit 146 sets the virtual processor state 163 to a valid state (S136).
  • the second OS 122 issues a virtual processor release instruction to the virtual processor control unit 141.
  • the state change unit 146 releases the allocated area of the virtual processor information storage unit 144 by changing the virtual processor state 163 of the virtual processor 113 designated by the virtual processor release instruction to an invalid state.
  • the processor system 100 When the second OS 122 starts executing a task, the processor system 100 newly generates a virtual processor 113 that executes the task.
  • the second OS 122 issues a virtual processor generation instruction to the virtual processor control unit 141.
  • the second OS 122 sets the task start address in the context 171 to start execution of the task. Actually, the instruction execution starts when the TS 134 of the virtual processor 113 becomes valid.
  • the processor system 100 deletes the virtual processor 113 that has executed the task.
  • the task is disabled by the scheduler.
  • the second OS 122 issues a virtual processor release instruction to the virtual processor control unit 141.
  • the virtual processor 113 is excluded from the allocation target.
  • one task may be executed on one virtual processor 113, or a plurality of tasks may be executed.
  • the virtual processor 113 is deleted when the second OS 122 finishes executing all the tasks executed on the virtual processor 113.
  • FIG. 15 is a flowchart showing the flow of pause processing of the virtual processor 113.
  • the first OS 121 or the second OS 122 issues a “wait instruction” to the virtual processor control unit 141.
  • the state changing unit 146 changes the virtual processor state 163 of the virtual processor 113 specified by the wait instruction to a dormant state (S141).
  • the virtual processor 113 does not operate until the interrupt to the virtual processor 113 is issued, and the allocated time 164 of the TS 134 is not consumed.
  • the first OS 121 and the second OS 122 are activated at the same time, but the timings at which the first OS 121 and the second OS 122 are activated may be different. For example, only the first OS 121 may be activated when the processor system 100 is activated, and then the first OS 121 may activate the second OS 122.
  • the time when the processor system 100 is started may be when the processor system 100 is turned on, or when the processor system 100 has, for example, a single-thread processor mode and a multi-thread processor mode (virtual processor mode). May be when the single-thread processor mode is shifted to the multi-thread processor mode.
  • the virtual processor 113 of the first OS 121 is statically generated and the virtual processor 113 of the second OS 122 is dynamically generated.
  • both the virtual processors 113 of the first OS 121 and the second OS 122 are statically generated. May be.
  • each processing unit included in the processor system 100 is typically realized as an LSI which is an integrated circuit. These may be individually made into one chip, or may be made into one chip so as to include a part or all of them.
  • part or all of the functions of the processor system 100 according to the embodiment of the present invention may be realized by a processor such as a CPU executing a program.
  • the present invention may be the above program or a recording medium on which the above program is recorded.
  • the present invention can be applied to a multi-operating system control method and a processor system, and in particular, can be applied to a processor system that executes a general-purpose OS and an OS suitable for a media control program.
  • processor system 101 processor block 102 external device 103 external memory 110 CPU 111 Cache memory 112 MMU 113 Virtual Processor 114 Interrupt Controller 115 Timer 116 I / O Unit 120 Virtual Processor Management Unit 121 First OS 122 2nd OS 123 1st program 124 2nd program 131 1st domain 132 2nd domain 133 Logical processor (LP) 134 Time Slot (TS) 140 TLB 141 Virtual processor control unit 142 Timer control unit 143 Execution control unit 144 Virtual processor information storage unit 145 Context holding unit 146 State change unit 147 Switching unit 148 Interrupt control unit 149 Setting unit 150 Interrupt reception unit 151 Interrupt factor table storage unit 152 TLB control Section 160 Virtual processor information 161 TS information 162 LP information 163 Virtual processor state 164 Allocation time 165 Domain number 166 Virtual processor number 167 Interrupt vector 171 Context 172 Register information 173 Cache allocation information 180 Interrupt factor table 181 Interrupt factor 190 Entry 191 Tag 192 PID 193 Data 201, 202 Interrupt request

Abstract

A multi-operating system control method wherein a first OS (121) and a second OS (122) are parallelly executed on a plurality of virtual processors (113) realized logically with real processors. A virtual processor (113) to be used by the first OS (121) is generated statically and a virtual processor (113) to be used by the second OS (122) is generated dynamically.

Description

マルチオペレーティングシステム制御方法及びプロセッサシステムMulti-operating system control method and processor system
　本発明は、マルチオペレーティングシステム制御方法及びプロセッサシステムに関し、特に、第１オペレーティングシステムと第２オペレーティングシステムとを複数の仮想プロセッサ上で並列に実行するマルチオペレーティングシステム制御方法に関する。 The present invention relates to a multi-operating system control method and a processor system, and more particularly to a multi-operating system control method for executing a first operating system and a second operating system in parallel on a plurality of virtual processors.
　近年、一つのプロセッサで、複数のオペレーティングシステム（以下、ＯＳ）を切り替えながら動作させるプロセッサシステムが実現されている（例えば、特許文献１及び特許文献２参照）。 In recent years, a processor system has been realized that allows a single processor to operate while switching a plurality of operating systems (hereinafter referred to as OSs) (see, for example, Patent Document 1 and Patent Document 2).
　一方で、高性能化を実現するプロセッサとしてマルチスレッドプロセッサが知られている。このマルチスレッドプロセッサは、複数の仮想プロセッサで複数のスレッドを同時に実行することにより、処理効率を向上できる。また、マルチスレッドプロセッサは、複数のスレッドの実行において、資源の共有が可能となるので、複数のプロセッサを独立に設ける場合に比べて、プロセッサの面積効率を向上できる。 On the other hand, a multi-thread processor is known as a processor realizing high performance. This multi-thread processor can improve processing efficiency by simultaneously executing a plurality of threads by a plurality of virtual processors. In addition, since the multi-thread processor can share resources in the execution of a plurality of threads, the area efficiency of the processor can be improved as compared with the case where a plurality of processors are provided independently.
特許第３５４６６７８号公報Japanese Patent No. 3546678 特開２０００－７６０８７号公報Japanese Patent Laid-Open No. 2000-76087
　ここで、上述したマルチスレッドプロセッサで複数のＯＳを実行しようとした場合、ＯＳごとに、仮想プロセッサを管理する必要が生じる。しかしながら、特許文献１及び特許文献２に記載のマルチオペレーティングシステムは、マルチスレッドプロセッサを用いたものではなく、このような仮想プロセッサの管理についてはなんら考慮されていない。 Here, when a plurality of OSs are to be executed by the multi-thread processor described above, it is necessary to manage virtual processors for each OS. However, the multi-operating systems described in Patent Document 1 and Patent Document 2 do not use a multi-thread processor, and no consideration is given to management of such virtual processors.
　そこで、本発明は、仮想プロセッサの管理を容易に行うことができるマルチオペレーティングシステム制御方法及びプロセッサシステムを提供することを目的とする。 Therefore, an object of the present invention is to provide a multi-operating system control method and a processor system that can easily manage virtual processors.
　上記目的を達成するために、本発明の一形態に係るマルチオペレーティングシステム制御方法は、第１オペレーティングシステムと第２オペレーティングシステムとを、実プロセッサにより論理的に実現される複数の仮想プロセッサ上で並列に実行するマルチオペレーティングシステム制御方法であって、前記第１オペレーティングシステムが使用する前記仮想プロセッサを静的に生成し、前記第２オペレーティングシステムが使用する前記仮想プロセッサを動的に生成する。 In order to achieve the above object, a multi-operating system control method according to an aspect of the present invention includes parallelly executing a first operating system and a second operating system on a plurality of virtual processors that are logically realized by real processors. The virtual processor used by the first operating system is statically generated and the virtual processor used by the second operating system is dynamically generated.
　これによれば、第１オペレーティングシステムが使用する仮想プロセッサを固定的に使用できる。これにより、例えば、第１オペレーティングシステムが使用する仮想プロセッサの識別子を、マルチオペレーティングシステム上と、第１オペレーティングシステム上とで一致させることができる。よって、第１オペレーティングシステム上の仮想プロセッサの識別子と、マルチオペレーティングシステム上の仮想プロセッサの識別子とを変換する処理が必要なくなる。これにより、本発明の一形態に係るマルチオペレーティングシステム制御方法は、第１オペレーティングシステムのオーバーヘッドを削減できる。 According to this, the virtual processor used by the first operating system can be fixedly used. Thereby, for example, the identifiers of the virtual processors used by the first operating system can be matched on the multi-operating system and on the first operating system. Therefore, it is not necessary to convert the virtual processor identifier on the first operating system and the virtual processor identifier on the multi-operating system. Thereby, the multi-operating system control method according to an aspect of the present invention can reduce the overhead of the first operating system.
　なお、第１オペレーティングシステム上の仮想プロセッサの識別子と、マルチオペレーティングシステム上の仮想プロセッサの識別子とを変換する処理を行う場合であっても、例えば、第１オペレーティングシステム上の仮想プロセッサの識別子にオペレーティングシステムを識別する識別子を付与するというような単純な処理で識別子の変換を行うことができる。 Even when the process of converting the identifier of the virtual processor on the first operating system and the identifier of the virtual processor on the multi-operating system is performed, for example, the operating system uses the identifier of the virtual processor on the first operating system. The identifier can be converted by a simple process such as assigning an identifier for identifying the system.
　このように、本発明の一形態に係るマルチオペレーティングシステム制御方法は、第１オペレーティングシステムが使用する仮想プロセッサの管理を容易に行うことができる。 Thus, the multi-operating system control method according to an aspect of the present invention can easily manage the virtual processors used by the first operating system.
　また、前記第１オペレーティングシステムが使用する前記仮想プロセッサを前記第１オペレーティングシステムの起動時にのみ生成し、前記第２オペレーティングシステムが使用する前記仮想プロセッサを前記第２オペレーティングシステムの起動後に生成及び削除してもよい。 In addition, the virtual processor used by the first operating system is generated only when the first operating system is started, and the virtual processor used by the second operating system is generated and deleted after the second operating system is started. May be.
　これによれば、第１オペレーティングシステムが使用する仮想プロセッサを起動時にのみ生成することにより、当該仮想プロセッサを固定的に使用できる。 According to this, by generating the virtual processor used by the first operating system only at the time of startup, the virtual processor can be used in a fixed manner.
　また、前記第２オペレーティングシステムが使用する前記仮想プロセッサを前記第２オペレーティングシステムの起動時に生成するとともに、前記第２オペレーティングシステムの起動後に生成及び削除し、前記第１オペレーティングシステム及び前記第２オペレーティングシステムの起動時に、前記第１オペレーティングシステムが使用する前記仮想プロセッサを生成した後、前記第２オペレーティングシステムが使用する前記仮想プロセッサを生成してもよい。 Further, the virtual processor used by the second operating system is generated when the second operating system is started, and is generated and deleted after the second operating system is started, so that the first operating system and the second operating system are generated. The virtual processor used by the second operating system may be generated after generating the virtual processor used by the first operating system.
　これによれば、第１オペレーティングシステムが使用する仮想プロセッサの識別子を、マルチオペレーティングシステム上と、第１オペレーティングシステム上とで一致させることができる。 According to this, the identifiers of the virtual processors used by the first operating system can be matched on the multi-operating system and the first operating system.
　また、前記複数の仮想プロセッサに、当該仮想プロセッサが前記第１オペレーティングシステムに使用されるか、前記第２オペレーティングシステムに使用されるかを示す第１識別子を付与し、同一の前記第１識別子を有する複数の仮想プロセッサに当該複数の仮想プロセッサの生成順に連番となり、かつ前記第１識別子間で独立した第２識別子を付与してもよい。 Further, a first identifier indicating whether the virtual processor is used for the first operating system or the second operating system is assigned to the plurality of virtual processors, and the same first identifier is assigned to the plurality of virtual processors. A plurality of virtual processors may be provided with second identifiers that are serial numbers in the order of generation of the plurality of virtual processors and that are independent among the first identifiers.
　これによれば、第１オペレーティングシステムが使用する仮想プロセッサの当該第１オペレーティングシステム上の識別子を、第２識別子と一致させることができる。 According to this, the identifier on the first operating system of the virtual processor used by the first operating system can be matched with the second identifier.
　また、前記第２オペレーティングシステムがタスクの実行を開始する時に、当該タスクを実行する前記仮想プロセッサを新たに生成してもよい。 Further, when the second operating system starts executing a task, the virtual processor that executes the task may be newly generated.
　また、前記第２オペレーティングシステムがタスクの実行を終了した時に、当該タスクを実行していた前記仮想プロセッサを削除してもよい。 Further, when the second operating system finishes executing the task, the virtual processor that has executed the task may be deleted.
　また、異なる前記第１識別子を有する前記仮想プロセッサに異なる割込みベクタを対応付けるとともに、同一の前記第１識別子を有する複数の仮想プロセッサに同一の割込みベクタを対応付けてもよい。 Further, different interrupt vectors may be associated with the virtual processors having different first identifiers, and the same interrupt vector may be associated with a plurality of virtual processors having the same first identifier.
　これによれば、第１オペレーティングシステムと第２オペレーティングシステムとの割込み処理の独立性を維持できる。 According to this, the independence of interrupt processing between the first operating system and the second operating system can be maintained.
　また、前記第１識別子と前記第２識別子との組に対して、それぞれ割込み要因を対応付け、割込み要求が発生した時に、当該割込みの割込み要因に対応付けられた前記組で指定される仮想プロセッサに割込みを発行してもよい。 In addition, an interrupt factor is associated with each set of the first identifier and the second identifier, and when an interrupt request is generated, a virtual processor specified by the set associated with the interrupt factor of the interrupt An interrupt may be issued.
　これによれば、各仮想プロセッサと割込み要因とを対応付けることができる。 According to this, each virtual processor can be associated with an interrupt factor.
　また、前記割込み要求が発生した時に、当該割込みの割込み要因に対応付けられた前記組で指定される仮想プロセッサが動作中の場合にのみ、当該割込みを受理してもよい。 Further, when the interrupt request is generated, the interrupt may be accepted only when the virtual processor specified by the set associated with the interrupt factor of the interrupt is operating.
　これによれば、動作中の仮想プロセッサに対する割込み処理のみを実行することができる。 According to this, it is possible to execute only the interrupt processing for the operating virtual processor.
　また、前記割込み要求が発生した時に、当該割込みの割込み要因に対応付けられた前記組で指定される仮想プロセッサが動作中でない場合、当該仮想プロセッサの動作開始後に当該割込み要求に基づく割込み処理を開始してもよい。 In addition, when the interrupt request is generated, if the virtual processor specified by the group associated with the interrupt factor of the interrupt is not operating, the interrupt processing based on the interrupt request is started after the operation of the virtual processor is started. May be.
　これによれば、動作中の仮想プロセッサに対する割込み処理のみを実行することができる。 According to this, it is possible to execute only the interrupt processing for the operating virtual processor.
　また、前記割込み要求に基づく割込み処理の実行中に、当該仮想プロセッサの動作割当期間が終了した場合、当該割込み処理を中断してもよい。 Further, when the operation allocation period of the virtual processor ends during execution of the interrupt process based on the interrupt request, the interrupt process may be interrupted.
　これによれば、動作中の仮想プロセッサに対する割込み処理のみを実行することができる。 According to this, it is possible to execute only the interrupt processing for the operating virtual processor.
　なお、本発明は、このようなマルチオペレーティングシステム制御方法として実現できるだけでなく、マルチオペレーティングシステム制御方法に含まれる特徴的なステップを手段とするプロセッサシステムとして実現したり、そのような特徴的なステップをコンピュータに実行させるプログラムとして実現したりすることもできる。そして、そのようなプログラムは、ＣＤ－ＲＯＭ等の記録媒体及びインターネット等の伝送媒体を介して流通させることができるのは言うまでもない。 The present invention can be realized not only as such a multi-operating system control method, but also as a processor system using the characteristic steps included in the multi-operating system control method as a means. It can also be realized as a program for causing a computer to execute. Needless to say, such a program can be distributed via a recording medium such as a CD-ROM and a transmission medium such as the Internet.
　以上より、本発明は、仮想プロセッサの管理を容易に行うことができるマルチオペレーティングシステム制御方法及びプロセッサシステムを提供できる。 As described above, the present invention can provide a multi-operating system control method and a processor system that can easily manage virtual processors.
図１は、本発明の実施の形態に係るプロセッサシステムの構成を示す図である。FIG. 1 is a diagram showing a configuration of a processor system according to an embodiment of the present invention. 図２は、本発明の実施の形態に係るプロセッサシステムにおける各ＯＳを実行する機能を模式的に示す図である。FIG. 2 is a diagram schematically showing a function of executing each OS in the processor system according to the embodiment of the present invention. 図３は、本発明の実施の形態に係る仮想プロセッサの構成を示す図である。FIG. 3 is a diagram showing a configuration of the virtual processor according to the embodiment of the present invention. 図４は、本発明の実施の形態に係る仮想プロセッサ管理部の構成を示す図である。FIG. 4 is a diagram showing a configuration of the virtual processor management unit according to the embodiment of the present invention. 図５は、本発明の実施の形態に係る仮想プロセッサ情報及びコンテキストの構成を示す図である。FIG. 5 is a diagram showing a configuration of virtual processor information and context according to the embodiment of the present invention. 図６は、本発明の実施の形態に係るプロセッサシステムにおける、ドメイン番号及び仮想プロセッサ番号の一例を示す図である。FIG. 6 is a diagram showing an example of a domain number and a virtual processor number in the processor system according to the embodiment of the present invention. 図７は、本発明の実施の形態に係る割込み要因テーブルの構成を示す図である。FIG. 7 is a diagram showing a configuration of the interrupt factor table according to the embodiment of the present invention. 図８は、本発明の実施の形態に係るＴＬＢの構成を示す図である。FIG. 8 is a diagram showing a configuration of the TLB according to the embodiment of the present invention. 図９は、本発明の実施の形態に係るプロセッサシステムの起動直後の初期化処理の流れを示すフローチャートである。FIG. 9 is a flowchart showing the flow of initialization processing immediately after the start of the processor system according to the embodiment of the present invention. 図１０は、本発明の実施の形態に係るプロセッサシステムにおける、仮想プロセッサ切替処理を示す図である。FIG. 10 is a diagram showing virtual processor switching processing in the processor system according to the embodiment of the present invention. 図１１は、本発明の実施の形態に係るプロセッサシステムにおける、タイムスロット切替処理の流れを示すフローチャートである。FIG. 11 is a flowchart showing the flow of time slot switching processing in the processor system according to the embodiment of the present invention. 図１２は、本発明の実施の形態に係るプロセッサシステムにおける、割込み処理の流れを示すフローチャートである。FIG. 12 is a flowchart showing the flow of interrupt processing in the processor system according to the embodiment of the present invention. 図１３は、本発明の実施の形態に係るプロセッサシステムにおける、割込み処理の一例を示す図である。FIG. 13 is a diagram showing an example of interrupt processing in the processor system according to the embodiment of the present invention. 図１４は、本発明の実施の形態に係るプロセッサシステムにおける、仮想プロセッサの生成処理の流れを示すフローチャートである。FIG. 14 is a flowchart showing a flow of virtual processor generation processing in the processor system according to the embodiment of the present invention. 図１５は、本発明の実施の形態に係るプロセッサシステムにおける、仮想プロセッサの休止処理の流れを示すフローチャートである。FIG. 15 is a flowchart showing the flow of the pause processing of the virtual processor in the processor system according to the embodiment of the present invention.
　以下、本発明に係るマルチオペレーティングシステム制御方法を実現するプロセッサシステム１００の実施の形態について、図面を参照しながら詳細に説明する。 Hereinafter, an embodiment of a processor system 100 that realizes a multi-operating system control method according to the present invention will be described in detail with reference to the drawings.
　本発明の実施の形態に係るプロセッサシステム１００は、第１ＯＳ１２１が使用する仮想プロセッサ１１３を当該第１ＯＳ１２１の起動時にのみ静的に生成し、第２ＯＳ１２２が使用する仮想プロセッサ１１３を動的に生成する。これにより、プロセッサシステム１００は、第１ＯＳ１２１上の仮想プロセッサ１１３の識別子と、マルチＯＳ上の仮想プロセッサ１１３の識別子とを一致させることができるので、仮想プロセッサ１１３の管理を容易に行うことができる。 The processor system 100 according to the embodiment of the present invention statically generates the virtual processor 113 used by the first OS 121 only when the first OS 121 is activated, and dynamically generates the virtual processor 113 used by the second OS 122. As a result, the processor system 100 can match the identifier of the virtual processor 113 on the first OS 121 with the identifier of the virtual processor 113 on the multi-OS, so that the virtual processor 113 can be easily managed.
　まず、本発明の実施の形態に係るプロセッサシステム１００の構成を説明する。 First, the configuration of the processor system 100 according to the embodiment of the present invention will be described.
　図１は、本発明の実施の形態に係るプロセッサシステム１００の全体構成を模式的に示す図である。 FIG. 1 is a diagram schematically showing an overall configuration of a processor system 100 according to an embodiment of the present invention.
　図１に示すプロセッサシステム１００は、第１ＯＳ１２１と第２ＯＳ１２２とを複数の仮想プロセッサ１１３上で並列に実行するマルチＯＳを実現するマルチスレッドプロセッサシステムである。なお、ここで並列とは、見かけ上並列（同時）に第１ＯＳ１２１と第２ＯＳ１２２とを実行することであり、実際には、後述するように複数の仮想プロセッサ１１３を時分割に切り換えながら実行する。また、仮想プロセッサ１１３とは、実プロセッサにより論理的に実現されるプロセッサである。言い換えると、仮想プロセッサ１１３とは、実プロセッサの数に依存しない論理的に定義されたプロセッサである。 A processor system 100 shown in FIG. 1 is a multi-thread processor system that realizes a multi-OS that executes a first OS 121 and a second OS 122 on a plurality of virtual processors 113 in parallel. Note that “parallel” here means that the first OS 121 and the second OS 122 are apparently executed in parallel (simultaneously). In practice, a plurality of virtual processors 113 are executed while being switched to time division as described later. The virtual processor 113 is a processor that is logically realized by a real processor. In other words, the virtual processor 113 is a logically defined processor that does not depend on the number of real processors.
　このプロセッサシステム１００は、プロセッサブロック１０１と、外部デバイス１０２と、外部メモリ１０３とを備える。また、プロセッサブロック１０１は、ＣＰＵ１１０と、割込みコントローラ１１４と、タイマ１１５と、Ｉ／Ｏ部１１６と、仮想プロセッサ管理部１２０とを備える。また、ＣＰＵ１１０は、キャッシュメモリ１１１と、ＭＭＵ（Ｍｅｍｏｒｙ　Ｍａｎａｇｅｍｅｎｔ　Ｕｎｉｔ）１１２と、仮想プロセッサ１１３とを備える。 The processor system 100 includes a processor block 101, an external device 102, and an external memory 103. The processor block 101 includes a CPU 110, an interrupt controller 114, a timer 115, an I / O unit 116, and a virtual processor management unit 120. In addition, the CPU 110 includes a cache memory 111, an MMU (Memory Management Unit) 112, and a virtual processor 113.
　また、ＣＰＵ１１０がプログラムを実行することにより、第１ＯＳ１２１及び第２ＯＳ１２２の機能を実現する。また、第１ＯＳ１２１上で複数の第１プログラム１２３が動作し、第２ＯＳ１２２上で複数の第２プログラム１２４が動作する。 Further, the functions of the first OS 121 and the second OS 122 are realized by the CPU 110 executing the program. A plurality of first programs 123 operate on the first OS 121, and a plurality of second programs 124 operate on the second OS 122.
　例えば、第１ＯＳ１２１はパーソナルコンピュータで普及している汎用ＯＳである。また、第２ＯＳ１２２はリアルタイム性を確保するメディア制御プログラムに適したＯＳである。 For example, the first OS 121 is a general-purpose OS that is widely used in personal computers. The second OS 122 is an OS suitable for a media control program that ensures real-time performance.
　図２は、プロセッサシステム１００における各ＯＳを実行する機能を模式的に示す図である。また、図３は、仮想プロセッサ１１３の構成を示す図である。 FIG. 2 is a diagram schematically showing a function of executing each OS in the processor system 100. As shown in FIG. FIG. 3 is a diagram illustrating the configuration of the virtual processor 113.
　図３に示すように、一つの仮想プロセッサ１１３は、それぞれ独立した、一つの論理プロセッサ（ＬＰ）１３３と、一つのタイムスロット（ＴＳ）１３４とを含む。 As shown in FIG. 3, one virtual processor 113 includes one logical processor (LP) 133 and one time slot (TS) 134, which are independent of each other.
　また、複数の仮想プロセッサ１１３（ＴＳ１３４）が時分割に切り替りながら動作することにより、複数の仮想プロセッサ１１３が並列に動作しているように見える。 In addition, since the plurality of virtual processors 113 (TS134) operate while being switched in time division, it seems that the plurality of virtual processors 113 are operating in parallel.
　ここで、図２に示すように、複数の仮想プロセッサ１１３（この例では２個の仮想プロセッサ１１３）が同時に動作してもよいし、一つの仮想プロセッサ１１３のみが動作してもよい。 Here, as shown in FIG. 2, a plurality of virtual processors 113 (two virtual processors 113 in this example) may operate simultaneously, or only one virtual processor 113 may operate.
　また、図２に示すように各ＯＳが動作する仮想プロセッサ１１３のグループをドメインと呼ぶ。具体的には、第１ドメイン１３１は、第１ＯＳ１２１を実行する１以上の仮想プロセッサ１１３を含み、第２ドメイン１３２は、第２ＯＳ１２２を実行する１以上の仮想プロセッサ１１３を含む。このドメインは、複数の仮想プロセッサ１１３をＯＳのリソースとして識別するための識別子である。 Also, as shown in FIG. 2, a group of virtual processors 113 on which each OS operates is called a domain. Specifically, the first domain 131 includes one or more virtual processors 113 that execute the first OS 121, and the second domain 132 includes one or more virtual processors 113 that execute the second OS 122. This domain is an identifier for identifying a plurality of virtual processors 113 as OS resources.
　図４は、仮想プロセッサ管理部１２０の構成を示す図である。 FIG. 4 is a diagram illustrating a configuration of the virtual processor management unit 120.
　図４に示すように仮想プロセッサ管理部１２０は、仮想プロセッサ制御部１４１と、タイマ制御部１４２と、実行制御部１４３と、仮想プロセッサ情報記憶部１４４と、コンテキスト保持部１４５と、割込み制御部１４８と、ＴＬＢ制御部１５２とを備える。また、プロセッサシステム１００は、ＭＭＵ１１２に含まれるＴＬＢ（Ｔｒａｎｓｌａｔｉｏｎ　Ｌｏｏｋａｓｉｄｅ　Ｂｕｆｆｅｒ）１４０を備える。 As shown in FIG. 4, the virtual processor management unit 120 includes a virtual processor control unit 141, a timer control unit 142, an execution control unit 143, a virtual processor information storage unit 144, a context holding unit 145, and an interrupt control unit 148. And a TLB control unit 152. The processor system 100 includes a TLB (Translation Lookaside Buffer) 140 included in the MMU 112.
　仮想プロセッサ情報記憶部１４４は、複数の仮想プロセッサ１１３にそれぞれ一対一で対応する複数の仮想プロセッサ情報１６０を記憶する。この仮想プロセッサ情報１６０は、対応する仮想プロセッサ１１３の情報である。 The virtual processor information storage unit 144 stores a plurality of virtual processor information 160 corresponding to each of the plurality of virtual processors 113 on a one-to-one basis. The virtual processor information 160 is information on the corresponding virtual processor 113.
　コンテキスト保持部１４５は、複数の仮想プロセッサ１１３にそれぞれ一対一で対応する複数のコンテキスト１７１を保持する。仮想プロセッサ１１３上で実行している処理を中断し別の仮想プロセッサ１１３の処理の実行を再開する際に、中断する処理のコンテキスト１７１がコンテキスト保持部１４５に退避される。また、開始する処理のコンテキスト１７１がコンテキスト保持部１４５から復帰される。 The context holding unit 145 holds a plurality of contexts 171 corresponding to the plurality of virtual processors 113 on a one-to-one basis. When the process being executed on the virtual processor 113 is interrupted and the execution of another virtual processor 113 is resumed, the context 171 of the process to be interrupted is saved in the context holding unit 145. In addition, the context 171 of the process to be started is returned from the context holding unit 145.
　図５は、仮想プロセッサ情報１６０及びコンテキスト１７１の構成を示す図である。 FIG. 5 is a diagram showing the configuration of the virtual processor information 160 and the context 171.
　図５に示すように各仮想プロセッサ情報１６０は、ＴＳ情報１６１と、ＬＰ情報１６２とを含む。 As shown in FIG. 5, each virtual processor information 160 includes TS information 161 and LP information 162.
　ＴＳ情報１６１は、対応する仮想プロセッサ１１３に含まれるＴＳ１３４の情報であり、仮想プロセッサ状態１６３と、割当時間１６４とを含む。 TS information 161 is information of TS 134 included in the corresponding virtual processor 113, and includes a virtual processor state 163 and an allocation time 164.
　ＬＰ情報１６２は、対応する仮想プロセッサ１１３に含まれるＬＰ１３３の情報であり、ドメイン番号１６５と、仮想プロセッサ番号１６６と、割込みベクタ１６７とを含む。 LP information 162 is information of LP 133 included in the corresponding virtual processor 113, and includes a domain number 165, a virtual processor number 166, and an interrupt vector 167.
　仮想プロセッサ状態１６３は、対応する仮想プロセッサ１１３がどのような状態であるかを示す。具体的には、仮想プロセッサ状態１６３は、有効状態、無効状態、及び休止状態の３つの状態のうちいずれかを示す。 The virtual processor state 163 indicates what state the corresponding virtual processor 113 is in. Specifically, the virtual processor state 163 indicates one of three states: a valid state, an invalid state, and a dormant state.
　有効状態は、対応する仮想プロセッサ１１３が切替部１４７の切替対象となる状態である。また、仮想プロセッサ情報１６０の生成時には、仮想プロセッサ状態１６３は有効状態に設定される。 The valid state is a state in which the corresponding virtual processor 113 is a switching target of the switching unit 147. Further, when the virtual processor information 160 is generated, the virtual processor state 163 is set to a valid state.
　無効状態は、対応する仮想プロセッサ１１３が切替部１４７の切替対象とならない状態である。 The invalid state is a state in which the corresponding virtual processor 113 is not a switching target of the switching unit 147.
　休止状態は、対応する仮想プロセッサ１１３に対して割込みが入るのを待っている状態を示し、割込みが入ると仮想プロセッサ状態１６３は有効状態に遷移する。 The hibernate state indicates a state waiting for an interrupt to the corresponding virtual processor 113, and when an interrupt occurs, the virtual processor state 163 transitions to a valid state.
　割当時間１６４は、対応する仮想プロセッサ１１３が処理を実行することができる時間を示す。対応する仮想プロセッサ１１３が実際に処理を実行した時間が割当時間１６４に達すると、実行される仮想プロセッサ１１３が次の仮想プロセッサ１１３に切り替えられる。また、この割当時間１６４は、仮想プロセッサ情報１６０の生成と同時に設定される。 The allocation time 164 indicates a time during which the corresponding virtual processor 113 can execute processing. When the time when the corresponding virtual processor 113 actually executes the processing reaches the allocation time 164, the virtual processor 113 to be executed is switched to the next virtual processor 113. The allocation time 164 is set simultaneously with the generation of the virtual processor information 160.
　ドメイン番号１６５は、対応する仮想プロセッサ１１３がどのドメインに属しているかを示す。すなわち、ドメイン番号１６５は、対応する仮想プロセッサ１１３が、第１ＯＳ１２１に使用されるか、第２ＯＳ１２２に使用されるかを示す識別子である。 The domain number 165 indicates to which domain the corresponding virtual processor 113 belongs. That is, the domain number 165 is an identifier indicating whether the corresponding virtual processor 113 is used for the first OS 121 or the second OS 122.
　仮想プロセッサ番号１６６は、ドメイン内での連番であり、例えば、１、２、３…の順で振られる。また、仮想プロセッサ番号１６６は、異なるドメイン間で独立した番号である。仮想プロセッサ管理部１２０が第１ＯＳ１２１及び第２ＯＳ１２２に通知する仮想プロセッサ１１３の番号にはこの仮想プロセッサ番号１６６が用いられる。よって、ＯＳ内部での仮想プロセッサ１１３の番号は実際の仮想プロセッサ１１３の位置に依存しない。 The virtual processor number 166 is a serial number in the domain, and is assigned in the order of 1, 2, 3,..., For example. The virtual processor number 166 is an independent number between different domains. The virtual processor number 166 is used as the number of the virtual processor 113 notified from the virtual processor management unit 120 to the first OS 121 and the second OS 122. Therefore, the number of the virtual processor 113 inside the OS does not depend on the actual position of the virtual processor 113.
　図６は、ドメイン番号１６５及び仮想プロセッサ番号１６６の一例を示す図である。図６に示すように、第１ＯＳ１２１に属する仮想プロセッサ１１３（ＬＰ１３３）のドメイン番号１６５は「１」に設定され、第２ＯＳ１２２に属する仮想プロセッサ１１３（ＬＰ１３３）のドメイン番号１６５は「２」に設定される。また、各ドメイン内において、仮想プロセッサ番号１６６は、連番となる。 FIG. 6 is a diagram illustrating an example of the domain number 165 and the virtual processor number 166. As shown in FIG. 6, the domain number 165 of the virtual processor 113 (LP133) belonging to the first OS 121 is set to “1”, and the domain number 165 of the virtual processor 113 (LP133) belonging to the second OS 122 is set to “2”. The In each domain, the virtual processor number 166 is a serial number.
　ここで、各仮想プロセッサ１１３は、ハードウェアの位置により決定される番号（以下、ハードウェア番号）を有している。複数の仮想プロセッサ情報１６０は、このハードウェア番号の順に、例えば左から並べられる。例えば、図６に示すＬＰ１３３の番号がこのハードウェア番号に相当する。 Here, each virtual processor 113 has a number (hereinafter, hardware number) determined by the position of the hardware. The plurality of virtual processor information 160 are arranged in order of this hardware number, for example, from the left. For example, the LP133 number shown in FIG. 6 corresponds to this hardware number.
　また、単一のＯＳのみが動作するマルチスレッドプロセッサでは、このハードウェア番号を用いて各仮想プロセッサ１１３が識別される。しかしながら、各ＯＳの機能変更を行うことなく、複数のＯＳを実行する場合には、各ＯＳが認識する仮想プロセッサ１１３の番号が重複することになる。これに対して、仮想プロセッサ管理部１２０は、各仮想プロセッサ１１３に、ドメイン番号１６５と仮想プロセッサ番号１６６とを対応付けることにより、複数の仮想プロセッサ１１３を一意に識別することができる。 Further, in a multi-thread processor in which only a single OS operates, each virtual processor 113 is identified using this hardware number. However, when a plurality of OSs are executed without changing the function of each OS, the numbers of the virtual processors 113 recognized by each OS overlap. In contrast, the virtual processor management unit 120 can uniquely identify a plurality of virtual processors 113 by associating each virtual processor 113 with a domain number 165 and a virtual processor number 166.
　また、仮想プロセッサ管理部１２０は、このドメイン番号１６５と仮想プロセッサ番号１６６との組と、仮想プロセッサ情報１６０の位置とに基づき、各ＯＳ又はプログラムから通知された仮想プロセッサ番号１６６と、ハードウェア番号とを相互に変換することができる。具体的には、第２ＯＳ１２２から仮想プロセッサ番号１６６が「２」の仮想プロセッサ１１３が指定された場合、図６に示す例では、ドメイン番号１６５が「２」であり、かつ仮想プロセッサ番号１６６が「２」である仮想プロセッサ１１３（ＬＰ１３３）のハードウェア番号は「４」であると判定できる。 Further, the virtual processor management unit 120, based on the set of the domain number 165 and the virtual processor number 166, and the position of the virtual processor information 160, the virtual processor number 166 notified from each OS or program, and the hardware number Can be converted to each other. Specifically, when the virtual processor 113 whose virtual processor number 166 is “2” is designated from the second OS 122, in the example illustrated in FIG. 6, the domain number 165 is “2” and the virtual processor number 166 is “ It can be determined that the hardware number of the virtual processor 113 (LP133) that is “2” is “4”.
　このように、本発明の実施の形態に係るプロセッサシステム１００では、ドメイン番号１６５と仮想プロセッサ番号１６６とを用いることにより、各ＯＳの機能を従来から変更することなく、複数の仮想プロセッサ１１３を一意に識別することができる。 As described above, in the processor system 100 according to the embodiment of the present invention, by using the domain number 165 and the virtual processor number 166, a plurality of virtual processors 113 can be uniquely assigned without changing the function of each OS. Can be identified.
　再び、図５を参照して説明を行う。 Again, a description will be given with reference to FIG.
　割込みベクタ１６７は、割込みの種別ごとのハンドラへのアドレスが並べられたテーブルの先頭を示すアドレスである。異なるドメインに属する仮想プロセッサ１１３には、異なる割込みベクタ１６７が対応付けられるとともに、同一のドメインに属する複数の仮想プロセッサ１１３には同一の割込みベクタ１６７が対応付けられる。 The interrupt vector 167 is an address indicating the head of a table in which addresses to handlers for each interrupt type are arranged. Different interrupt vectors 167 are associated with virtual processors 113 belonging to different domains, and the same interrupt vector 167 is associated with a plurality of virtual processors 113 belonging to the same domain.
　また、コンテキスト１７１は、対応する仮想プロセッサ１１３のレジスタ情報１７２及びキャッシュ割当情報１７３などを含む。 The context 171 includes register information 172 and cache allocation information 173 of the corresponding virtual processor 113.
　また、仮想プロセッサ情報１６０の順序は、対応する仮想プロセッサ１１３の生成順を表す。 Also, the order of the virtual processor information 160 represents the generation order of the corresponding virtual processor 113.
　仮想プロセッサ制御部１４１は、状態変更部１４６と、切替部１４７とを含む。 The virtual processor control unit 141 includes a state change unit 146 and a switching unit 147.
　仮想プロセッサ制御部１４１は、プロセッサシステム１００の起動後に行われる初期化処理において、この複数のドメインを定義し、各ドメインに、各ドメインが必要な数の仮想プロセッサ１１３を割り付ける。 The virtual processor control unit 141 defines the plurality of domains in the initialization process performed after the processor system 100 is activated, and assigns the required number of virtual processors 113 to each domain.
　状態変更部１４６は、プロセッサシステム１００の起動時に行われる初期化処理において、ドメインを定義し、必要な数の仮想プロセッサ１１３を各ドメインに割り付ける。具体的には、状態変更部１４６は、仮想プロセッサ情報１６０を生成することにより、各ドメインに属する仮想プロセッサ１１３を生成する。ここで、第１ＯＳ１２１に属する複数の仮想プロセッサ１１３は、プロセッサシステム１００の起動時に生成された後、新たに生成及び削除されることはない。一方、第２ＯＳ１２２に属する複数の仮想プロセッサ１１３は、プロセッサシステム１００の起動時に生成された後、第２ＯＳ１２２からの要求により新たに生成及び削除される。 The state changing unit 146 defines a domain and assigns a required number of virtual processors 113 to each domain in an initialization process performed when the processor system 100 is started. Specifically, the state change unit 146 generates the virtual processor 113 belonging to each domain by generating the virtual processor information 160. Here, the plurality of virtual processors 113 belonging to the first OS 121 are not newly generated or deleted after being generated when the processor system 100 is activated. On the other hand, a plurality of virtual processors 113 belonging to the second OS 122 are newly created and deleted in response to a request from the second OS 122 after being created when the processor system 100 is activated.
　ここで、仮想プロセッサ１１３を生成するとは、切替部１４７により順次切り替えられるＴＳ１３４を新たに追加することである。具体的には、状態変更部１４６は、生成する仮想プロセッサ１１３に対応する仮想プロセッサ情報１６０に含まれる仮想プロセッサ状態１６３を有効状態にする。これにより、当該仮想プロセッサ１１３が、切替部１４７の切り替え対象となる。 Here, generating the virtual processor 113 means adding a TS 134 that is sequentially switched by the switching unit 147. Specifically, the state changing unit 146 sets the virtual processor state 163 included in the virtual processor information 160 corresponding to the generated virtual processor 113 to the valid state. Thereby, the virtual processor 113 becomes a switching target of the switching unit 147.
　また、仮想プロセッサ１１３を削除するとは、当該仮想プロセッサ１１３を、切替部１４７の切り替え対象から外すことである。具体的には、状態変更部１４６は、仮想プロセッサ１１３に対応する仮想プロセッサ情報１６０に含まれる仮想プロセッサ状態１６３を無効状態に変更することにより、当該仮想プロセッサを削除する。 Further, to delete the virtual processor 113 is to remove the virtual processor 113 from the switching target of the switching unit 147. Specifically, the state changing unit 146 deletes the virtual processor by changing the virtual processor state 163 included in the virtual processor information 160 corresponding to the virtual processor 113 to an invalid state.
　また、状態変更部１４６は、第１ＯＳ１２１、第２ＯＳ１２２、第１プログラム１２３又は第２プログラム１２４からの通知に応じて、仮想プロセッサ情報１６０を変更する。また、状態変更部１４６は、仮想プロセッサ情報１６０を変更する際には、情報の矛盾が起こらないようにするため、全ての割込み要求及びタイマ制御部１４２による切り替え要求を禁止する。 Further, the state change unit 146 changes the virtual processor information 160 in response to a notification from the first OS 121, the second OS 122, the first program 123, or the second program 124. In addition, when changing the virtual processor information 160, the state change unit 146 prohibits all interrupt requests and switching requests by the timer control unit 142 in order to prevent inconsistency of information.
　切替部１４７は、予め定められた周期内において、各仮想プロセッサ１１３を少なくとも１回選択するラウンドロビンスケジューリングを行う。具体的には、切替部１４７は、現在実行中の仮想プロセッサ１１３の実行時間が割当時間１６４に達したときに、仮想プロセッサ１１３の切替を行う。 The switching unit 147 performs round robin scheduling for selecting each virtual processor 113 at least once within a predetermined period. Specifically, the switching unit 147 switches the virtual processor 113 when the execution time of the currently executing virtual processor 113 reaches the allocation time 164.
　タイマ制御部１４２は、仮想プロセッサ制御部１４１から割当時間１６４が設定される毎に、タイマ１１５を用いた時間のカウントを開始する。また、タイマ制御部１４２は、カウントしている時間が割当時間１６４に達したときにタイムアウト信号を出力する。このタイムアウト信号は、タイムスロット１３４の切替タイミングを示し、仮想プロセッサ制御部１４１に通知される。 The timer control unit 142 starts counting time using the timer 115 every time the allocated time 164 is set from the virtual processor control unit 141. The timer control unit 142 outputs a timeout signal when the counting time reaches the allocation time 164. This timeout signal indicates the switching timing of the time slot 134 and is notified to the virtual processor control unit 141.
　切替部１４７は、タイマ制御部１４２により出力されるタイムアウト信号によって、実行時間が割当時間１６４に達したかどうかを判定する。実行時間が割当時間１６４に達した場合、切替部１４７は、並び順で次の仮想プロセッサ情報１６０を選択する。また、切替部１４７は、新たに選択した仮想プロセッサ情報１６０から割当時間１６４を取得してタイマ制御部１４２に設定する。これにより、タイマ制御部１４２は、次の仮想プロセッサ１１３の割当時間１６４のカウントを開始する。 The switching unit 147 determines whether or not the execution time has reached the allocation time 164 based on a timeout signal output from the timer control unit 142. When the execution time reaches the allocation time 164, the switching unit 147 selects the next virtual processor information 160 in the arrangement order. In addition, the switching unit 147 acquires the allocation time 164 from the newly selected virtual processor information 160 and sets it in the timer control unit 142. As a result, the timer control unit 142 starts counting the allocation time 164 of the next virtual processor 113.
　また、切替部１４７は、仮想プロセッサ１１３上で動作する処理を再開する前に、コンテキスト１７１の退避及び復帰を行う。また、切替部１４７は、状態変更部１４６が処理を行う際には、切替処理を中断する。 In addition, the switching unit 147 saves and restores the context 171 before resuming processing that operates on the virtual processor 113. The switching unit 147 interrupts the switching process when the state changing unit 146 performs the process.
　実行制御部１４３は、切替部１４７により選択されたスレッドを実行する。この実行制御部１４３は、スレッドを実行するＣＰＵ１１０等のハードウェアに相当する。 The execution control unit 143 executes the thread selected by the switching unit 147. The execution control unit 143 corresponds to hardware such as the CPU 110 that executes threads.
　割込み制御部１４８は、割込み要因１８１と仮想プロセッサ１１３とを対応付ける。 The interrupt control unit 148 associates the interrupt factor 181 with the virtual processor 113.
　また、割込みコントローラ１１４は、割込み要求が発生したとき、当該割込みの割込み要因１８１に対応付けられた仮想プロセッサ１１３に対して割込みを発行する。 Further, when an interrupt request is generated, the interrupt controller 114 issues an interrupt to the virtual processor 113 associated with the interrupt factor 181 of the interrupt.
　この割込み制御部１４８は、設定部１４９と、割込み受付部１５０と、割込み要因テーブル記憶部１５１とを備える。 The interrupt control unit 148 includes a setting unit 149, an interrupt receiving unit 150, and an interrupt factor table storage unit 151.
　割込み要因テーブル記憶部１５１は、割込み要因１８１と仮想プロセッサ１１３との対応関係を示す割込み要因テーブル１８０を記憶する。 The interrupt factor table storage unit 151 stores an interrupt factor table 180 indicating the correspondence between the interrupt factor 181 and the virtual processor 113.
　図７は、割込み要因テーブル１８０の構成を示す図である。 FIG. 7 is a diagram showing the configuration of the interrupt factor table 180.
　図７に示すように、割込み要因テーブル１８０は、複数の仮想プロセッサ１１３のそれぞれに対応付けられた割込み要因１８１を示す。具体的には、ドメイン番号１６５と仮想プロセッサ番号１６６との組に対して、一つの割込み要因１８１が対応付けられる。 As shown in FIG. 7, the interrupt factor table 180 indicates the interrupt factor 181 associated with each of the plurality of virtual processors 113. Specifically, one interrupt factor 181 is associated with a set of the domain number 165 and the virtual processor number 166.
　設定部１４９は、第１ＯＳ１２１、第２ＯＳ１２２、第１プログラム１２３及び第２プログラム１２４からの通知に応じて、割込み要因テーブル１８０にドメイン番号１６５及び仮想プロセッサ番号１６６を登録する。 The setting unit 149 registers the domain number 165 and the virtual processor number 166 in the interrupt factor table 180 in response to notifications from the first OS 121, the second OS 122, the first program 123, and the second program 124.
　割込み受付部１５０は、外部デバイス１０２、又はソフトウェア要因により要求された割込み要求を受付ける。割込み受付部１５０により割込み要求が受付けられると、割込みコントローラ１１４は、割込み要因テーブル１８０に従って対応する仮想プロセッサ１１３上で動作するＯＳの割込みハンドラを起動する。 The interrupt receiving unit 150 receives an interrupt request requested by the external device 102 or a software factor. When the interrupt request is received by the interrupt receiving unit 150, the interrupt controller 114 starts an OS interrupt handler that operates on the corresponding virtual processor 113 in accordance with the interrupt factor table 180.
　ＴＬＢ制御部１５２は、ＴＬＢ１４０の制御を行う。 The TLB control unit 152 controls the TLB 140.
　図８は、ＴＬＢ１４０の構成を示す図である。 FIG. 8 is a diagram showing the configuration of the TLB 140.
　ＴＬＢ１４０は、一種のキャッシュメモリであり、論理アドレスと物理アドレスとの対応関係を示すページテーブルの一部を保持する。このＴＬＢ１４０は、保持するページテーブルを用いて、論理アドレスと物理アドレスとの間の変換を行う。 The TLB 140 is a kind of cache memory, and holds a part of a page table indicating a correspondence relationship between a logical address and a physical address. The TLB 140 performs conversion between a logical address and a physical address using a held page table.
　図８に示すように、ＴＬＢ１４０は、複数のエントリ１９０を含む。各エントリ１９０は、論理アドレスを識別するためのタグ１９１と、ドメイン番号１６５と、ＰＩＤ１９２と、データ１９３とを含む。 As shown in FIG. 8, the TLB 140 includes a plurality of entries 190. Each entry 190 includes a tag 191 for identifying a logical address, a domain number 165, a PID 192, and data 193.
　ＰＩＤ１９２は、当該データを用いるプロセスを識別するためのＩＤである。データ１９３は、タグ１９１に対応付けられた物理アドレスである。 PID 192 is an ID for identifying a process using the data. Data 193 is a physical address associated with the tag 191.
　ＴＬＢ制御部１５２は、ＴＬＢ１４０の更新が行われる際に、更新元となる仮想プロセッサ１１３が属するドメイン番号１６５をタグ１９１に対して設定する。また、ＴＬＢ制御部１５２は、ＴＬＢ１４０が検索される際には、対象となる仮想プロセッサ１１３が属するドメイン番号１６５を保持するエントリ１９０のみを検索する。 When the TLB 140 is updated, the TLB control unit 152 sets the domain number 165 to which the virtual processor 113 serving as the update source belongs to the tag 191. Further, when the TLB 140 is searched, the TLB control unit 152 searches only the entry 190 that holds the domain number 165 to which the target virtual processor 113 belongs.
　また、本発明の実施の形態に係るプロセッサシステム１００では、外部デバイス１０２との接続に用いられるＩ／Ｏ部１１６の複数のＩ／Ｏアドレスは、ドメインごとに、それぞれ独立に割り当てられる。また、上述したようにドメインごとに独立した割込み制御が行われる。これにより、第１ＯＳ１２１及び第２ＯＳ１２２は互いにアクセスを行わないので、プロセッサシステム１００は、ハードウェア制御に対するＯＳ間の独立性を確保できる。 In the processor system 100 according to the embodiment of the present invention, a plurality of I / O addresses of the I / O unit 116 used for connection with the external device 102 are assigned independently for each domain. Further, as described above, independent interrupt control is performed for each domain. Thereby, since the first OS 121 and the second OS 122 do not access each other, the processor system 100 can ensure independence between the OSs for hardware control.
　このように、プロセッサシステム１００では、ハードウェアに対するアクセスはそれぞれのＯＳが直接実行するため、ＯＳを管理するソフトウェアが各ＯＳからのアクセスをエミュレーションする必要はない。これにより、ハードウェアに対する直接アクセスを前提として構築されたＯＳカーネル及びデバイスドライバを変更する必要がない。また、ＯＳがハードウェアをアクセスする際のオーバーヘッドを防ぐことができる。 As described above, in the processor system 100, access to the hardware is directly executed by each OS, so that software for managing the OS does not need to emulate access from each OS. This eliminates the need to change the OS kernel and device driver built on the premise of direct access to hardware. Further, overhead when the OS accesses the hardware can be prevented.
　また、プロセッサシステム１００では、第１ＯＳ１２１及び第２ＯＳ１２２は、共通で用いられる物理メモリである外部メモリ１０３の領域を分割し、それぞれのＯＳが分割された領域を使用する。また、上述したようにドメイン番号１６５によりＴＬＢ１４０のエントリ１９０が識別される。これにより、ドメインごとに論理空間を分割できる。 In the processor system 100, the first OS 121 and the second OS 122 divide the area of the external memory 103, which is a physical memory used in common, and use the areas obtained by dividing each OS. Further, as described above, the entry 190 of the TLB 140 is identified by the domain number 165. Thereby, a logical space can be divided for each domain.
　また、外部メモリ１０３内には、ＭＭＵ変換を行わない領域を配置する。この領域は、高い保護レベルを有し、ＯＳからのみアクセスが可能である。 In the external memory 103, an area where MMU conversion is not performed is arranged. This area has a high protection level and is accessible only from the OS.
　以上より、本発明の実施の形態に係るプロセッサシステム１００は、ＯＳ間の独立性を確保できる。 As described above, the processor system 100 according to the embodiment of the present invention can ensure independence between OSs.
　次に、プロセッサシステム１００の動作を説明する。 Next, the operation of the processor system 100 will be described.
　まず、プロセッサシステム１００の起動（マルチＯＳの起動）直後の初期化処理について説明する。このプロセッサシステム１００の起動時に、第１ＯＳ１２１及び第２ＯＳ１２２が起動される。 First, the initialization process immediately after the processor system 100 is started (multi-OS startup) will be described. When the processor system 100 is activated, the first OS 121 and the second OS 122 are activated.
　図９は、プロセッサシステム１００の起動直後の初期化処理の流れを示すフローチャートである。 FIG. 9 is a flowchart showing the flow of initialization processing immediately after the processor system 100 is started.
　プロセッサシステム１００が起動すると、まず、仮想プロセッサ管理部１２０は、レジスタ及び割込みの初期化を行う（Ｓ１０１）。 When the processor system 100 is activated, first, the virtual processor management unit 120 initializes registers and interrupts (S101).
　次に、状態変更部１４６は、第１ＯＳ１２１に対応する第１ドメイン１３１を定義する（Ｓ１０２）。 Next, the state change unit 146 defines the first domain 131 corresponding to the first OS 121 (S102).
　次に、状態変更部１４６は、第１ドメイン１３１に属する複数の仮想プロセッサ１１３を生成する（Ｓ１０３）。具体的には、状態変更部１４６は、仮想プロセッサ情報１６０を生成し、生成した仮想プロセッサ情報１６０を仮想プロセッサ情報記憶部１４４に記憶する。また、生成される仮想プロセッサ１１３の数は、第１ＯＳ１２１が必要とする予め定められた固定数である。また、第１ドメイン１３１に属する複数の仮想プロセッサ１１３の数はこの処理の後で変更されない。つまり、第１ドメイン１３１に属する複数の仮想プロセッサ１１３は、この処理の後において生成又は削除されない。 Next, the state change unit 146 generates a plurality of virtual processors 113 belonging to the first domain 131 (S103). Specifically, the state change unit 146 generates virtual processor information 160 and stores the generated virtual processor information 160 in the virtual processor information storage unit 144. Further, the number of virtual processors 113 to be generated is a predetermined fixed number required by the first OS 121. Further, the number of the plurality of virtual processors 113 belonging to the first domain 131 is not changed after this process. That is, the plurality of virtual processors 113 belonging to the first domain 131 are not created or deleted after this processing.
　次に、状態変更部１４６は、第２ＯＳ１２２に対応する第２ドメイン１３２を定義する（Ｓ１０４）。 Next, the state changing unit 146 defines the second domain 132 corresponding to the second OS 122 (S104).
　次に、状態変更部１４６は、第２ドメイン１３２に属する複数の仮想プロセッサ１１３を生成する（Ｓ１０５）。具体的には、状態変更部１４６は、仮想プロセッサ情報１６０を生成し、生成した仮想プロセッサ情報１６０を仮想プロセッサ情報記憶部１４４に記憶する。例えば、状態変更部１４６は、一つの仮想プロセッサ１１３のみを生成する。また、第２ドメイン１３２に属する仮想プロセッサ１１３は、この処理の後に、必要に応じて新たに生成又は削除される。 Next, the state change unit 146 generates a plurality of virtual processors 113 belonging to the second domain 132 (S105). Specifically, the state change unit 146 generates virtual processor information 160 and stores the generated virtual processor information 160 in the virtual processor information storage unit 144. For example, the state change unit 146 generates only one virtual processor 113. Further, the virtual processor 113 belonging to the second domain 132 is newly created or deleted as necessary after this processing.
　次に、状態変更部１４６は、仮想プロセッサ１１３の生成処理が完了した段階で、タイマ制御部１４２を有効にし、仮想プロセッサ１１３の切り替え動作を開始する（Ｓ１０６）。 Next, when the generation process of the virtual processor 113 is completed, the state change unit 146 enables the timer control unit 142 and starts the switching operation of the virtual processor 113 (S106).
　このように本発明の実施の形態に係るプロセッサシステム１００は、第１ＯＳ１２１が使用する仮想プロセッサ１１３を静的に生成し、第２ＯＳ１２２が使用する仮想プロセッサ１１３を動的に生成する。具体的には、プロセッサシステム１００は、第１ＯＳ１２１が使用する仮想プロセッサ１１３を第１ＯＳ１２１の起動時にのみ生成する。また、プロセッサシステム１００は、第２ＯＳが使用する仮想プロセッサ１１３を第２ＯＳ１２２の起動時に生成するとともに、第２ＯＳ１２２の起動後に生成及び削除する。 As described above, the processor system 100 according to the embodiment of the present invention statically generates the virtual processor 113 used by the first OS 121 and dynamically generates the virtual processor 113 used by the second OS 122. Specifically, the processor system 100 generates the virtual processor 113 used by the first OS 121 only when the first OS 121 is activated. Further, the processor system 100 generates the virtual processor 113 used by the second OS when the second OS 122 is started, and generates and deletes the virtual processor 113 after the second OS 122 is started.
　また、プロセッサシステム１００は、起動後に生成及び削除が行われない第１ＯＳ１２１の仮想プロセッサ１１３を生成した後に、起動後に生成及び削除が行われる第２ＯＳ１２２の仮想プロセッサ１１３を生成する。ここで、上述したように、仮想プロセッサ情報１６０の順序は、対応する仮想プロセッサ１１３の生成順を表している。また、仮想プロセッサ情報１６０の順序は、仮想プロセッサ１１３のハードウェア番号に対応している。つまり、仮想プロセッサ１１３の生成順と、ハードウェア番号とは等しくなる。 The processor system 100 generates the virtual processor 113 of the second OS 122 that is generated and deleted after startup after generating the virtual processor 113 of the first OS 121 that is not generated and deleted after startup. Here, as described above, the order of the virtual processor information 160 represents the generation order of the corresponding virtual processors 113. The order of the virtual processor information 160 corresponds to the hardware number of the virtual processor 113. That is, the generation order of the virtual processor 113 is equal to the hardware number.
　例えば、図６に示すように、第１ＯＳ１２１に対する２個の仮想プロセッサ１１３を生成した場合、この２個の仮想プロセッサ１１３のハードウェア番号はそれぞれ「１」及び「２」となり、この２個の仮想プロセッサ１１３の仮想プロセッサ番号１６６と等しくなる。さらに、第１ＯＳ１２１の仮想プロセッサ１１３は、以降の処理において、生成及び削除されないので、以降の処理においても、第１ＯＳ１２１の仮想プロセッサ番号１６６とハードウェア番号とは常に一致する。 For example, as shown in FIG. 6, when two virtual processors 113 for the first OS 121 are generated, the hardware numbers of the two virtual processors 113 are “1” and “2”, respectively. It becomes equal to the virtual processor number 166 of the processor 113. Furthermore, since the virtual processor 113 of the first OS 121 is not generated or deleted in the subsequent processing, the virtual processor number 166 of the first OS 121 and the hardware number always match in the subsequent processing.
　これにより、本発明の実施の形態に係るプロセッサシステム１００では、第１ＯＳ１２１は、単一のＯＳが動作している場合と同様に、仮想プロセッサ管理部１２０を介さず、仮想プロセッサ１１３を認識することができる。これにより、プロセッサシステム１００は、第１ＯＳ１２１のオーバーヘッドを削減できる。 Thus, in the processor system 100 according to the embodiment of the present invention, the first OS 121 recognizes the virtual processor 113 without using the virtual processor management unit 120, as in the case where a single OS is operating. Can do. Thereby, the processor system 100 can reduce the overhead of the first OS 121.
　また、仮想プロセッサ管理部１２０は、第１ＯＳ１２１に仮想プロセッサ１１３の番号を通知する場合において、ハードウェア番号を変換することなくそのまま通知できる。これにより、プロセッサシステム１００は、仮想プロセッサ管理部１２０の処理量を低減できるので処理速度を向上できる。 Further, when notifying the number of the virtual processor 113 to the first OS 121, the virtual processor management unit 120 can directly notify the hardware number without converting it. As a result, the processor system 100 can reduce the processing amount of the virtual processor management unit 120, so that the processing speed can be improved.
　このように、本発明の実施の形態に係るプロセッサシステム１００は、起動後に仮想プロセッサ１１３の生成及び削除が行われない第１ＯＳ１２１の仮想プロセッサ１１３の仮想プロセッサ番号１６６と、ハードウェア番号とを一致させることにより、仮想プロセッサ１１３の制御を容易に行うことができる。 As described above, the processor system 100 according to the embodiment of the present invention matches the hardware number with the virtual processor number 166 of the virtual processor 113 of the first OS 121 in which the virtual processor 113 is not generated and deleted after startup. As a result, the virtual processor 113 can be easily controlled.
　なお、第１ＯＳ１２１は、仮想プロセッサ管理部１２０を介して、仮想プロセッサ１１３を認識してもよい。この場合であっても、仮想プロセッサ管理部１２０は、ハードウェア番号を変換することなくそのまま仮想プロセッサ番号１６６として用いることができるので、仮想プロセッサ管理部１２０の処理量を低減できる。 Note that the first OS 121 may recognize the virtual processor 113 via the virtual processor management unit 120. Even in this case, the virtual processor management unit 120 can be used as it is as the virtual processor number 166 without converting the hardware number, so that the processing amount of the virtual processor management unit 120 can be reduced.
　次に、仮想プロセッサ１１３の切替処理について説明する。 Next, switching processing of the virtual processor 113 will be described.
　図１０は、プロセッサシステム１００における、仮想プロセッサ１１３の切替処理を示す図である。 FIG. 10 is a diagram showing the switching process of the virtual processor 113 in the processor system 100.
　図１０に示すように、ＴＳ１の割当時間１６４の間、ＬＰ１のコンテキスト１７１が有効となる。また、ＬＰ１上で第１ＯＳ１２１のタスクＡが動作する。 As shown in FIG. 10, the LP1 context 171 becomes valid during the TS1 allocation time 164. Also, task A of the first OS 121 operates on LP1.
　また、ＴＳ１の割当時間１６４が経過すると、タスクＡの動作が中断され、動作するＴＳ１３４がＴＳ２（ＬＰ２）に切替えられる。また、ＴＳ２の割当時間１６４の間、ＬＰ２のコンテキスト１７１が有効となり、ＬＰ２上で第１ＯＳ１２１のタスクＢが動作する。 When the allocated time 164 of TS1 elapses, the operation of task A is interrupted, and the operating TS 134 is switched to TS2 (LP2). Further, during the TS2 allocation time 164, the LP2 context 171 becomes valid, and the task B of the first OS 121 operates on the LP2.
　同様に、ＴＳ２の割当時間１６４が経過すると、タスクＢの動作が中断され、動作するＴＳ１３４がＴＳ３（ＬＰ３）に切替えられる。また、ＴＳ３の割当時間１６４の間、ＬＰ３のコンテキスト１７１が有効となり、ＬＰ３上で第２ＯＳ１２２のタスクＣが動作する。 Similarly, when the allocated time 164 of TS2 elapses, the operation of task B is interrupted, and the operating TS134 is switched to TS3 (LP3). Further, during the TS3 allocation time 164, the LP3 context 171 becomes valid, and the task C of the second OS 122 operates on the LP3.
　図１１は、切替部１４７によるタイムスロット切替処理の流れを示すフローチャートである。 FIG. 11 is a flowchart showing the flow of time slot switching processing by the switching unit 147.
　まず、タイマ制御部１４２よりタイムアウト通知が切替部１４７に行われる。これにより、切替部１４７は割込みを禁止するとともに（Ｓ１１１）、現在実行中の仮想プロセッサ１１３のコンテキスト１７１をコンテキスト保持部１４５に退避する（Ｓ１１２）。 First, the timer control unit 142 sends a timeout notification to the switching unit 147. As a result, the switching unit 147 prohibits interruption (S111) and saves the context 171 of the currently executed virtual processor 113 to the context holding unit 145 (S112).
　次に、切替部１４７は、仮想プロセッサ情報記憶部１４４に記憶される仮想プロセッサ情報１６０の配列順に従って、次に仮想プロセッサ状態１６３が有効状態の仮想プロセッサ１１３を選択する（Ｓ１１３）。 Next, the switching unit 147 selects the virtual processor 113 in which the virtual processor state 163 is valid next in accordance with the arrangement order of the virtual processor information 160 stored in the virtual processor information storage unit 144 (S113).
　次に、切替部１４７は、使用する割込みベクタを、選択した仮想プロセッサ１１３の割込みベクタ１６７に切り替える（Ｓ１１４）。 Next, the switching unit 147 switches the interrupt vector to be used to the interrupt vector 167 of the selected virtual processor 113 (S114).
　次に、切替部１４７は、選択した仮想プロセッサ１１３の割当時間１６４を仮想プロセッサ情報１６０から取り出し、取り出した割当時間１６４をタイマ制御部１４２に設定する（Ｓ１１５）。 Next, the switching unit 147 extracts the allocation time 164 of the selected virtual processor 113 from the virtual processor information 160, and sets the extracted allocation time 164 in the timer control unit 142 (S115).
　次に、切替部１４７は、選択した仮想プロセッサ１１３のコンテキスト１７１をコンテキスト保持部１４５から復帰するとともに（Ｓ１１６）、割込みを許可する（Ｓ１１７）。 Next, the switching unit 147 restores the context 171 of the selected virtual processor 113 from the context holding unit 145 (S116) and permits an interrupt (S117).
　次に、切替部１４７は、選択された仮想プロセッサ１１３を指定する割込みが発生しているか否かを判定する（Ｓ１１８）。割込みが発生している場合（Ｓ１１８でＹｅｓ）、切替部１４７は、割込み処理を開始する（Ｓ１１９）。 Next, the switching unit 147 determines whether or not an interrupt designating the selected virtual processor 113 has occurred (S118). If an interrupt has occurred (Yes in S118), the switching unit 147 starts interrupt processing (S119).
　次に、割込み処理について説明する。 Next, interrupt processing will be described.
　プロセッサシステム１００は、割込み要求が発生した時に、当該割込みの割込み要因に対応付けられた仮想プロセッサ１１３が動作中の場合にのみ、当該割込みを受理する。また、プロセッサシステム１００は、割込み要求が発生した時に、当該割込みの割込み要因に対応付けられた仮想プロセッサが動作中でない場合、当該仮想プロセッサ１１３の動作開始後に当該割込み要求に基づく割込み処理を開始する。また、プロセッサシステム１００は、割込み要求に基づく割込み処理の実行中に、当該仮想プロセッサ１１３の動作割当期間が終了した場合、当該割込み処理を中断する。 When an interrupt request is generated, the processor system 100 accepts the interrupt only when the virtual processor 113 associated with the interrupt factor of the interrupt is operating. In addition, when an interrupt request occurs, the processor system 100 starts interrupt processing based on the interrupt request after the virtual processor 113 starts operating if the virtual processor associated with the interrupt factor of the interrupt is not operating. . Further, when the operation allocation period of the virtual processor 113 ends during execution of the interrupt process based on the interrupt request, the processor system 100 interrupts the interrupt process.
　図１２は、プロセッサシステム１００における、割込み処理の流れを示すフローチャートである。 FIG. 12 is a flowchart showing the flow of interrupt processing in the processor system 100.
　まず、割込み受付部１５０が割込み要求を受付けると、割込みコントローラ１１４は、割込み要因テーブル１８０に従って、受付けた割込みの割込み要因１８１に対応する仮想プロセッサ１１３に対して割込みを発行する（Ｓ１２１）。 First, when the interrupt receiving unit 150 receives an interrupt request, the interrupt controller 114 issues an interrupt to the virtual processor 113 corresponding to the interrupt factor 181 of the accepted interrupt according to the interrupt factor table 180 (S121).
　ここで、現在動作中の仮想プロセッサ１１３への割込みの場合（Ｓ１２２でＹｅｓ）、切替部１４７は当該割込みを受理する（Ｓ１２３）。具体的には、切替部１４７は、割込み先の仮想プロセッサ１１３の割込みベクタ１６７を参照し、割込みベクタ１６７で指定される割込みハンドラのアドレスをプログラムカウンタに設定する。これにより、割込み処理が開始される。 Here, in the case of an interrupt to the currently operating virtual processor 113 (Yes in S122), the switching unit 147 accepts the interrupt (S123). Specifically, the switching unit 147 refers to the interrupt vector 167 of the virtual processor 113 that is the interrupt destination, and sets the address of the interrupt handler specified by the interrupt vector 167 in the program counter. Thereby, the interrupt process is started.
　一方、動作していない仮想プロセッサ１１３への割込みの場合（Ｓ１２２でＮｏ）、かつ、割込み先の仮想プロセッサ１１３の仮想プロセッサ状態１６３が休止状態の場合（Ｓ１２４でＹｅｓ）、切替部１４７は当該仮想プロセッサ状態１６３を有効状態に変更する（Ｓ１２５）。 On the other hand, in the case of an interrupt to the virtual processor 113 that is not operating (No in S122), and when the virtual processor state 163 of the virtual processor 113 that is the interrupt destination is in the dormant state (Yes in S124), the switching unit 147 The processor state 163 is changed to a valid state (S125).
　以下、具体例を示す。図１３は、プロセッサシステム１００における、割込み処理の一例を示す図である。 Specific examples are shown below. FIG. 13 is a diagram illustrating an example of interrupt processing in the processor system 100.
　図１３に示すように、ＴＳ１を含む仮想プロセッサ１１３の動作中に、当該仮想プロセッサ１１３宛の割込み要求２０１が発生した場合、当該仮想プロセッサ１１３の割込みベクタ１６７に従って割込みハンドラが起動されることにより、割込み処理が開始される。 As shown in FIG. 13, when an interrupt request 201 addressed to the virtual processor 113 is generated during the operation of the virtual processor 113 including TS1, an interrupt handler is started according to the interrupt vector 167 of the virtual processor 113, Interrupt processing starts.
　また、当該割込み処理が、ＴＳ１の割当時間１６４中に終了しなかった場合、当該割込み処理は、一時中断される。その後、再度、ＴＳ１に切替えられた際に、当該割込み処理が引き続き行われる。 Further, when the interrupt process is not completed during the allocation time 164 of TS1, the interrupt process is temporarily suspended. After that, when switching to TS1 again, the interrupt processing is continued.
　また、図１３に示すように、ＴＳ２を含む仮想プロセッサ１１３の動作中に、現在動作していないＴＳ１を含む仮想プロセッサ１１３宛の割込み要求２０２が発生した場合、動作中のＴＳ２を含む仮想プロセッサ１１３は、当該割込み要求２０２を受理しない。また、次に、ＴＳ１に切替えられた際に、この割込み要求２０２に対する割込み処理が開始される。 As shown in FIG. 13, when an interrupt request 202 addressed to the virtual processor 113 including TS1 that is not currently operating occurs during operation of the virtual processor 113 including TS2, the virtual processor 113 including TS2 that is currently operating. Does not accept the interrupt request 202. Next, when switching to TS1, interrupt processing for this interrupt request 202 is started.
　以上により、プロセッサシステム１００は、動作中の仮想プロセッサ１１３宛の割込みのみを受理できる。 As described above, the processor system 100 can accept only an interrupt addressed to the operating virtual processor 113.
　次に、仮想プロセッサ１１３の生成処理について説明する。 Next, the generation process of the virtual processor 113 will be described.
　図１４は、仮想プロセッサ１１３の生成処理の流れを示すフローチャートである。 FIG. 14 is a flowchart showing a flow of generation processing of the virtual processor 113.
　まず、第２ＯＳ１２２は、仮想プロセッサ制御部１４１に対して仮想プロセッサ生成指示を発行する。これにより、状態変更部１４６は、仮想プロセッサ情報記憶部１４４の空き領域を確保することにより、初期化を行う（Ｓ１３１）。具体的には、状態変更部１４６は、設定されていない仮想プロセッサ情報１６０、又は、仮想プロセッサ状態１６３が無効状態の仮想プロセッサ状態１６３を確保する。 First, the second OS 122 issues a virtual processor generation instruction to the virtual processor control unit 141. As a result, the state changing unit 146 performs initialization by securing a free area in the virtual processor information storage unit 144 (S131). Specifically, the state change unit 146 reserves virtual processor information 160 that has not been set or a virtual processor state 163 in which the virtual processor state 163 is in an invalid state.
　次に、状態変更部１４６は、第２ＯＳ１２２から与えられたドメイン番号１６５、及び割当時間１６４を設定する（Ｓ１３２）。また、状態変更部１４６は、ドメイン番号１６５内で連番になるように仮想プロセッサ番号１６６を設定する（Ｓ１３３）。また、状態変更部１４６は、ドメイン番号１６５に対応する割込みベクタ１６７を設定する（Ｓ１３４）。 Next, the state change unit 146 sets the domain number 165 and the allocation time 164 given from the second OS 122 (S132). Further, the state changing unit 146 sets the virtual processor number 166 so as to be a serial number within the domain number 165 (S133). Further, the state changing unit 146 sets the interrupt vector 167 corresponding to the domain number 165 (S134).
　また、状態変更部１４６は、与えられた実行開始アドレス及びスタックアドレスをコンテキスト１７１に設定する（Ｓ１３５）。さらに、状態変更部１４６は、仮想プロセッサ状態１６３を有効状態に設定する（Ｓ１３６）。 Further, the state changing unit 146 sets the given execution start address and stack address in the context 171 (S135). Further, the state changing unit 146 sets the virtual processor state 163 to a valid state (S136).
　以上により、仮想プロセッサ１１３が新たに生成される。 Thus, a new virtual processor 113 is generated.
　次に、仮想プロセッサ１１３の解放処理（削除処理）について説明する。 Next, the release process (deletion process) of the virtual processor 113 will be described.
　まず、第２ＯＳ１２２は、仮想プロセッサ制御部１４１に対して仮想プロセッサ解放指示を発行する。これにより、状態変更部１４６は、当該仮想プロセッサ解放指示により指定された仮想プロセッサ１１３の仮想プロセッサ状態１６３を無効状態に変更することにより、仮想プロセッサ情報記憶部１４４の割り当てられた領域を解放する。 First, the second OS 122 issues a virtual processor release instruction to the virtual processor control unit 141. As a result, the state change unit 146 releases the allocated area of the virtual processor information storage unit 144 by changing the virtual processor state 163 of the virtual processor 113 designated by the virtual processor release instruction to an invalid state.
　次に、第２ＯＳ１２２のスケジューラに従った仮想プロセッサ操作について説明する。 Next, the virtual processor operation according to the scheduler of the second OS 122 will be described.
　プロセッサシステム１００は、第２ＯＳ１２２がタスクの実行を開始する時に、当該タスクを実行する仮想プロセッサ１１３を新たに生成する。 When the second OS 122 starts executing a task, the processor system 100 newly generates a virtual processor 113 that executes the task.
　具体的には、第２ＯＳ１２２上でタスクが起動された場合、スケジューラによりタスクが実行可能状態となる。このとき第２ＯＳ１２２は、仮想プロセッサ制御部１４１に対して仮想プロセッサ生成指示を発行する。 More specifically, when a task is activated on the second OS 122, the task is ready to be executed by the scheduler. At this time, the second OS 122 issues a virtual processor generation instruction to the virtual processor control unit 141.
　仮想プロセッサ１１３が生成されると、第２ＯＳ１２２は、タスクの開始アドレスをコンテキスト１７１に設定することにより、タスクの実行を開始する。実際には、仮想プロセッサ１１３のＴＳ１３４が有効になった時に命令実行が開始される。 When the virtual processor 113 is generated, the second OS 122 sets the task start address in the context 171 to start execution of the task. Actually, the instruction execution starts when the TS 134 of the virtual processor 113 becomes valid.
　また、プロセッサシステム１００は、第２ＯＳ１２２がタスクの実行を終了した時に、当該タスクを実行していた仮想プロセッサ１１３を削除する。 Further, when the second OS 122 finishes executing the task, the processor system 100 deletes the virtual processor 113 that has executed the task.
　具体的には、第２ＯＳ１２２上でタスクが終了された場合、スケジューラによりタスクが無効状態となる。このとき、第２ＯＳ１２２は、仮想プロセッサ制御部１４１に対して仮想プロセッサ解放指示を発行する。 Specifically, when the task is terminated on the second OS 122, the task is disabled by the scheduler. At this time, the second OS 122 issues a virtual processor release instruction to the virtual processor control unit 141.
　解放処理が行われると仮想プロセッサ１１３は割当対象外となる。 When the release process is performed, the virtual processor 113 is excluded from the allocation target.
　なお、一つの仮想プロセッサ１１３上で一つのタスクが実行されてもよいし、複数のタスクが実行されてもよい。複数のタスクが一つの仮想プロセッサ１１３上で実行される場合には、第２ＯＳ１２２が当該仮想プロセッサ１１３上で実行される全てのタスクの実行を終了した時点で、当該仮想プロセッサ１１３を削除する。 Note that one task may be executed on one virtual processor 113, or a plurality of tasks may be executed. When a plurality of tasks are executed on one virtual processor 113, the virtual processor 113 is deleted when the second OS 122 finishes executing all the tasks executed on the virtual processor 113.
　次に、ＯＳが実行しないときの動作について説明する。 Next, the operation when the OS is not executed will be described.
　図１５は、仮想プロセッサ１１３の休止処理の流れを示すフローチャートである。 FIG. 15 is a flowchart showing the flow of pause processing of the virtual processor 113.
　第１ＯＳ１２１及び第２ＯＳ１２２は実行可能なタスクがないアイドル状態の場合、「ｗａｉｔ命令」により実行権を放棄する。これにより、他の実行可能な仮想プロセッサ１１３が実行される。 When the first OS 121 and the second OS 122 are in an idle state with no executable task, the execution right is abandoned by a “wait instruction”. As a result, another executable virtual processor 113 is executed.
　まず、第１ＯＳ１２１又は第２ＯＳ１２２は、仮想プロセッサ制御部１４１に対して「ｗａｉｔ命令」を発行する。これにより、状態変更部１４６は、ｗａｉｔ命令で指定された仮想プロセッサ１１３の仮想プロセッサ状態１６３を休止状態に変更する（Ｓ１４１）。 First, the first OS 121 or the second OS 122 issues a “wait instruction” to the virtual processor control unit 141. As a result, the state changing unit 146 changes the virtual processor state 163 of the virtual processor 113 specified by the wait instruction to a dormant state (S141).
　これにより、当該仮想プロセッサ１１３に対する割込みが発行されるまで、当該仮想プロセッサ１１３は動作せず、ＴＳ１３４の割当時間１６４も消費されない。 Thus, the virtual processor 113 does not operate until the interrupt to the virtual processor 113 is issued, and the allocated time 164 of the TS 134 is not consumed.
　ステップＳ１４１の仮想プロセッサ状態１６３の変更により、第１ＯＳ１２１及び第２ＯＳ１２２の全ての仮想プロセッサ１１３の仮想プロセッサ状態１６３が休止状態になった場合（Ｓ１４２でＹｅｓ）、ＴＳ１３４の割当時間１６４が消費されないため、ＣＰＵ１１０は省電力モードに移行する（Ｓ１４３）。 When the virtual processor state 163 of all the virtual processors 113 of the first OS 121 and the second OS 122 is in a dormant state due to the change of the virtual processor state 163 in step S141 (Yes in S142), the allocated time 164 of the TS 134 is not consumed. The CPU 110 shifts to the power saving mode (S143).
　一方、仮想プロセッサ状態１６３が有効状態の仮想プロセッサ１１３が存在する場合（Ｓ１４２でＮｏ）、ＣＰＵ１１０は通常モードで動作する（Ｓ１４４）。 On the other hand, when there is a virtual processor 113 in which the virtual processor state 163 is valid (No in S142), the CPU 110 operates in the normal mode (S144).
　以上、本発明の実施の形態に係るプロセッサシステムについて説明したが、本発明は、この実施の形態に限定されるものではない。 Although the processor system according to the embodiment of the present invention has been described above, the present invention is not limited to this embodiment.
　例えば、上記説明では、プロセッサシステム１００の起動時に、第１ＯＳ１２１及び第２ＯＳ１２２を同時に起動しているが、第１ＯＳ１２１と第２ＯＳ１２２とを起動するタイミングは異なってもよい。例えば、プロセッサシステム１００の起動時に第１ＯＳ１２１のみを起動し、その後、第１ＯＳ１２１が第２ＯＳ１２２を起動してもよい。 For example, in the above description, when the processor system 100 is activated, the first OS 121 and the second OS 122 are activated at the same time, but the timings at which the first OS 121 and the second OS 122 are activated may be different. For example, only the first OS 121 may be activated when the processor system 100 is activated, and then the first OS 121 may activate the second OS 122.
　また、プロセッサシステム１００の起動時とは、プロセッサシステム１００の電源が投入された際でもよいし、プロセッサシステム１００が、例えば、シングルスレッドプロセッサモードとマルチスレッドプロセッサモード（仮想プロセッサモード）とを有する場合には、シングルスレッドプロセッサモードからマルチスレッドプロセッサモードに移行した際でもよい。 The time when the processor system 100 is started may be when the processor system 100 is turned on, or when the processor system 100 has, for example, a single-thread processor mode and a multi-thread processor mode (virtual processor mode). May be when the single-thread processor mode is shifted to the multi-thread processor mode.
　また、上記説明では、第１ＯＳ１２１の仮想プロセッサ１１３を静的に生成し、第２ＯＳ１２２の仮想プロセッサ１１３を動的に生成するとしたが、第１ＯＳ１２１及び第２ＯＳ１２２の仮想プロセッサ１１３を共に静的に生成してもよい。 In the above description, the virtual processor 113 of the first OS 121 is statically generated and the virtual processor 113 of the second OS 122 is dynamically generated. However, both the virtual processors 113 of the first OS 121 and the second OS 122 are statically generated. May be.
　また、上記実施の形態に係るプロセッサシステム１００に含まれる各処理部は典型的には集積回路であるＬＳＩとして実現される。これらは個別に１チップ化されてもよいし、一部又はすべてを含むように１チップ化されてもよい。 Further, each processing unit included in the processor system 100 according to the above embodiment is typically realized as an LSI which is an integrated circuit. These may be individually made into one chip, or may be made into one chip so as to include a part or all of them.
　また、本発明の実施の形態に係るプロセッサシステム１００の機能の一部又は全てを、ＣＰＵ等のプロセッサがプログラムを実行することにより実現してもよい。 Further, part or all of the functions of the processor system 100 according to the embodiment of the present invention may be realized by a processor such as a CPU executing a program.
　さらに、本発明は上記プログラムであってもよいし、上記プログラムが記録された記録媒体であってもよい。 Furthermore, the present invention may be the above program or a recording medium on which the above program is recorded.
　本発明は、マルチオペレーティングシステム制御方法及びプロセッサシステムに適用でき、特に、汎用ＯＳと、メディア制御プログラム等に適したＯＳとを実行するプロセッサシステムに適用できる。 The present invention can be applied to a multi-operating system control method and a processor system, and in particular, can be applied to a processor system that executes a general-purpose OS and an OS suitable for a media control program.
　１００　プロセッサシステム
　１０１　プロセッサブロック
　１０２　外部デバイス
　１０３　外部メモリ
　１１０　ＣＰＵ
　１１１　キャッシュメモリ
　１１２　ＭＭＵ
　１１３　仮想プロセッサ
　１１４　割込みコントローラ
　１１５　タイマ
　１１６　Ｉ／Ｏ部
　１２０　仮想プロセッサ管理部
　１２１　第１ＯＳ
　１２２　第２ＯＳ
　１２３　第１プログラム
　１２４　第２プログラム
　１３１　第１ドメイン
　１３２　第２ドメイン
　１３３　論理プロセッサ（ＬＰ）
　１３４　タイムスロット（ＴＳ）
　１４０　ＴＬＢ
　１４１　仮想プロセッサ制御部
　１４２　タイマ制御部
　１４３　実行制御部
　１４４　仮想プロセッサ情報記憶部
　１４５　コンテキスト保持部
　１４６　状態変更部
　１４７　切替部
　１４８　割込み制御部
　１４９　設定部
　１５０　割込み受付部
　１５１　割込み要因テーブル記憶部
　１５２　ＴＬＢ制御部
　１６０　仮想プロセッサ情報
　１６１　ＴＳ情報
　１６２　ＬＰ情報
　１６３　仮想プロセッサ状態
　１６４　割当時間
　１６５　ドメイン番号
　１６６　仮想プロセッサ番号
　１６７　割込みベクタ
　１７１　コンテキスト
　１７２　レジスタ情報
　１７３　キャッシュ割当情報
　１８０　割込み要因テーブル
　１８１　割込み要因
　１９０　エントリ
　１９１　タグ
　１９２　ＰＩＤ
　１９３　データ
　２０１、２０２　割込み要求 100 processor system 101 processor block 102 external device 103 external memory 110 CPU
111 Cache memory 112 MMU
113 Virtual Processor 114 Interrupt Controller 115 Timer 116 I / O Unit 120 Virtual Processor Management Unit 121 First OS
122 2nd OS
123 1st program 124 2nd program 131 1st domain 132 2nd domain 133 Logical processor (LP)
134 Time Slot (TS)
140 TLB
141 Virtual processor control unit 142 Timer control unit 143 Execution control unit 144 Virtual processor information storage unit 145 Context holding unit 146 State change unit 147 Switching unit 148 Interrupt control unit 149 Setting unit 150 Interrupt reception unit 151 Interrupt factor table storage unit 152 TLB control Section 160 Virtual processor information 161 TS information 162 LP information 163 Virtual processor state 164 Allocation time 165 Domain number 166 Virtual processor number 167 Interrupt vector 171 Context 172 Register information 173 Cache allocation information 180 Interrupt factor table 181 Interrupt factor 190 Entry 191 Tag 192 PID
193 Data 201, 202 Interrupt request

Claims (13)

  1. 　第１オペレーティングシステムと第２オペレーティングシステムとを、実プロセッサにより論理的に実現される複数の仮想プロセッサ上で並列に実行するマルチオペレーティングシステム制御方法であって、
    　前記第１オペレーティングシステムが使用する前記仮想プロセッサを静的に生成し、
    　前記第２オペレーティングシステムが使用する前記仮想プロセッサを動的に生成する
    　マルチオペレーティングシステム制御方法。     A multi-operating system control method for executing a first operating system and a second operating system in parallel on a plurality of virtual processors logically realized by a real processor,
    Statically generating the virtual processor used by the first operating system;
    A multi-operating system control method for dynamically generating the virtual processor used by the second operating system.
  2. 　前記第１オペレーティングシステムが使用する前記仮想プロセッサを前記第１オペレーティングシステムの起動時にのみ生成し、
    　前記第２オペレーティングシステムが使用する前記仮想プロセッサを前記第２オペレーティングシステムの起動後に生成及び削除する
    　請求項１記載のマルチオペレーティングシステム制御方法。     Generating the virtual processor used by the first operating system only when the first operating system is started;
    The multi-operating system control method according to claim 1, wherein the virtual processor used by the second operating system is generated and deleted after the second operating system is started.
  3. 　前記第２オペレーティングシステムが使用する前記仮想プロセッサを前記第２オペレーティングシステムの起動時に生成するとともに、前記第２オペレーティングシステムの起動後に生成及び削除し、
    　前記第１オペレーティングシステム及び前記第２オペレーティングシステムの起動時に、前記第１オペレーティングシステムが使用する前記仮想プロセッサを生成した後、前記第２オペレーティングシステムが使用する前記仮想プロセッサを生成する
    　請求項２記載のマルチオペレーティングシステム制御方法。     Generating the virtual processor used by the second operating system when the second operating system is started, and generating and deleting the virtual processor after starting the second operating system;
    The virtual processor used by the second operating system is generated after the virtual processor used by the first operating system is generated when the first operating system and the second operating system are started. Multi-operating system control method.
  4. 　前記複数の仮想プロセッサに、当該仮想プロセッサが前記第１オペレーティングシステムに使用されるか、前記第２オペレーティングシステムに使用されるかを示す第１識別子を付与し、
    　同一の前記第１識別子を有する複数の仮想プロセッサに当該複数の仮想プロセッサの生成順に連番となり、かつ前記第１識別子間で独立した第２識別子を付与する
    　請求項３記載のマルチオペレーティングシステム制御方法。     Giving the plurality of virtual processors a first identifier indicating whether the virtual processor is used for the first operating system or the second operating system;
    4. The multi-operating system control method according to claim 3, wherein a plurality of virtual processors having the same first identifier are assigned sequential second numbers in the generation order of the plurality of virtual processors and independent among the first identifiers. .
  5. 　前記第２オペレーティングシステムがタスクの実行を開始する時に、当該タスクを実行する前記仮想プロセッサを新たに生成する
    　請求項２記載のマルチオペレーティングシステム制御方法。     The multi-operating system control method according to claim 2, wherein when the second operating system starts executing a task, the virtual processor that newly executes the task is newly generated.
  6. 　前記第２オペレーティングシステムがタスクの実行を終了した時に、当該タスクを実行していた前記仮想プロセッサを削除する
    　請求項２記載のマルチオペレーティングシステム制御方法。     The multi-operating system control method according to claim 2, wherein when the second operating system finishes executing a task, the virtual processor that has executed the task is deleted.
  7. 　異なる前記第１識別子を有する前記仮想プロセッサに異なる割込みベクタを対応付けるとともに、同一の前記第１識別子を有する複数の仮想プロセッサに同一の割込みベクタを対応付ける
    　請求項４記載のマルチオペレーティングシステム制御方法。     The multi-operating system control method according to claim 4, wherein different interrupt vectors are associated with the virtual processors having different first identifiers, and the same interrupt vector is associated with a plurality of virtual processors having the same first identifier.
  8. 　前記第１識別子と前記第２識別子との組に対して、それぞれ割込み要因を対応付け、
    　割込み要求が発生した時に、当該割込みの割込み要因に対応付けられた前記組で指定される仮想プロセッサに割込みを発行する
    　請求項４記載のマルチオペレーティングシステム制御方法。     An interrupt factor is associated with each set of the first identifier and the second identifier,
    The multi-operating system control method according to claim 4, wherein when an interrupt request is generated, an interrupt is issued to a virtual processor designated by the set associated with the interrupt factor of the interrupt.
  9. 　前記割込み要求が発生した時に、当該割込みの割込み要因に対応付けられた前記組で指定される仮想プロセッサが動作中の場合にのみ、当該割込みを受理する
    　請求項８記載のマルチオペレーティングシステム制御方法。     The multi-operating system control method according to claim 8, wherein when the interrupt request is generated, the interrupt is accepted only when the virtual processor specified by the set associated with the interrupt factor of the interrupt is operating.
  10. 　前記割込み要求が発生した時に、当該割込みの割込み要因に対応付けられた前記組で指定される仮想プロセッサが動作中でない場合、当該仮想プロセッサの動作開始後に当該割込み要求に基づく割込み処理を開始する
    　請求項９記載のマルチオペレーティングシステム制御方法。     When the interrupt request is generated, if the virtual processor specified by the set associated with the interrupt factor of the interrupt is not operating, the interrupt processing based on the interrupt request is started after the operation of the virtual processor is started. Item 10. The multi-operating system control method according to Item 9.
  11. 　前記割込み要求に基づく割込み処理の実行中に、当該仮想プロセッサの動作割当期間が終了した場合、当該割込み処理を中断する
    　請求項９記載のマルチオペレーティングシステム制御方法。     10. The multi-operating system control method according to claim 9, wherein the interrupt process is interrupted when the operation allocation period of the virtual processor ends during execution of the interrupt process based on the interrupt request.
  12. 　第１オペレーティングシステムと第２オペレーティングシステムとを複数の仮想プロセッサ上で並列に実行するプロセッサシステムであって、
    　前記第１オペレーティングシステムが使用する前記仮想プロセッサを静的に生成し、
    　前記第２オペレーティングシステムが使用する前記仮想プロセッサを動的に生成する
    　プロセッサシステム。     A processor system for executing a first operating system and a second operating system in parallel on a plurality of virtual processors,
    Statically generating the virtual processor used by the first operating system;
    A processor system that dynamically generates the virtual processor used by the second operating system.
  13. 　請求項１記載の前記マルチオペレーティングシステム制御方法をコンピュータに実行させる
    　プログラム。     A program causing a computer to execute the multi-operating system control method according to claim 1.
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